nic0_qm_arc_aux0_regs.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2016-2020 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8/************************************
  9 ** This is an auto-generated file **
 10 **       DO NOT EDIT BELOW        **
 11 ************************************/
 12
 13#ifndef ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_
 14#define ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_
 15
 16/*
 17 *****************************************
 18 *   NIC0_QM_ARC_AUX0
 19 *   (Prototype: QMAN_ARC_AUX)
 20 *****************************************
 21 */
 22
 23#define mmNIC0_QM_ARC_AUX0_RUN_HALT_REQ 0x5418100
 24
 25#define mmNIC0_QM_ARC_AUX0_RUN_HALT_ACK 0x5418104
 26
 27#define mmNIC0_QM_ARC_AUX0_RST_VEC_ADDR 0x5418108
 28
 29#define mmNIC0_QM_ARC_AUX0_DBG_MODE 0x541810C
 30
 31#define mmNIC0_QM_ARC_AUX0_CLUSTER_NUM 0x5418110
 32
 33#define mmNIC0_QM_ARC_AUX0_ARC_NUM 0x5418114
 34
 35#define mmNIC0_QM_ARC_AUX0_WAKE_UP_EVENT 0x5418118
 36
 37#define mmNIC0_QM_ARC_AUX0_DCCM_SYS_ADDR_BASE 0x541811C
 38
 39#define mmNIC0_QM_ARC_AUX0_CTI_AP_STS 0x5418120
 40
 41#define mmNIC0_QM_ARC_AUX0_CTI_CFG_MUX_SEL 0x5418124
 42
 43#define mmNIC0_QM_ARC_AUX0_ARC_RST 0x5418128
 44
 45#define mmNIC0_QM_ARC_AUX0_ARC_RST_REQ 0x541812C
 46
 47#define mmNIC0_QM_ARC_AUX0_SRAM_LSB_ADDR 0x5418130
 48
 49#define mmNIC0_QM_ARC_AUX0_SRAM_MSB_ADDR 0x5418134
 50
 51#define mmNIC0_QM_ARC_AUX0_PCIE_LSB_ADDR 0x5418138
 52
 53#define mmNIC0_QM_ARC_AUX0_PCIE_MSB_ADDR 0x541813C
 54
 55#define mmNIC0_QM_ARC_AUX0_CFG_LSB_ADDR 0x5418140
 56
 57#define mmNIC0_QM_ARC_AUX0_CFG_MSB_ADDR 0x5418144
 58
 59#define mmNIC0_QM_ARC_AUX0_HBM0_LSB_ADDR 0x5418150
 60
 61#define mmNIC0_QM_ARC_AUX0_HBM0_MSB_ADDR 0x5418154
 62
 63#define mmNIC0_QM_ARC_AUX0_HBM1_LSB_ADDR 0x5418158
 64
 65#define mmNIC0_QM_ARC_AUX0_HBM1_MSB_ADDR 0x541815C
 66
 67#define mmNIC0_QM_ARC_AUX0_HBM2_LSB_ADDR 0x5418160
 68
 69#define mmNIC0_QM_ARC_AUX0_HBM2_MSB_ADDR 0x5418164
 70
 71#define mmNIC0_QM_ARC_AUX0_HBM3_LSB_ADDR 0x5418168
 72
 73#define mmNIC0_QM_ARC_AUX0_HBM3_MSB_ADDR 0x541816C
 74
 75#define mmNIC0_QM_ARC_AUX0_HBM0_OFFSET 0x5418170
 76
 77#define mmNIC0_QM_ARC_AUX0_HBM1_OFFSET 0x5418174
 78
 79#define mmNIC0_QM_ARC_AUX0_HBM2_OFFSET 0x5418178
 80
 81#define mmNIC0_QM_ARC_AUX0_HBM3_OFFSET 0x541817C
 82
 83#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_0 0x5418180
 84
 85#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_1 0x5418184
 86
 87#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_2 0x5418188
 88
 89#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_3 0x541818C
 90
 91#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_4 0x5418190
 92
 93#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_5 0x5418194
 94
 95#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_6 0x5418198
 96
 97#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_0 0x541819C
 98
 99#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_1 0x54181A0
100
101#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_2 0x54181A4
102
103#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_3 0x54181A8
104
105#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_4 0x54181AC
106
107#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_5 0x54181B0
108
109#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_6 0x54181B4
110
111#define mmNIC0_QM_ARC_AUX0_ARC_CBU_AWCACHE_OVR 0x54181B8
112
113#define mmNIC0_QM_ARC_AUX0_ARC_LBU_AWCACHE_OVR 0x54181BC
114
115#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_0 0x54181C0
116
117#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_1 0x54181C4
118
119#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_2 0x54181C8
120
121#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_3 0x54181CC
122
123#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_4 0x54181D0
124
125#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_5 0x54181D4
126
127#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_6 0x54181D8
128
129#define mmNIC0_QM_ARC_AUX0_CONTEXT_ID_7 0x54181DC
130
131#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_0 0x54181E0
132
133#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_1 0x54181E4
134
135#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_2 0x54181E8
136
137#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_3 0x54181EC
138
139#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_4 0x54181F0
140
141#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_5 0x54181F4
142
143#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_6 0x54181F8
144
145#define mmNIC0_QM_ARC_AUX0_CID_OFFSET_7 0x54181FC
146
147#define mmNIC0_QM_ARC_AUX0_SW_INTR_0 0x5418200
148
149#define mmNIC0_QM_ARC_AUX0_SW_INTR_1 0x5418204
150
151#define mmNIC0_QM_ARC_AUX0_SW_INTR_2 0x5418208
152
153#define mmNIC0_QM_ARC_AUX0_SW_INTR_3 0x541820C
154
155#define mmNIC0_QM_ARC_AUX0_SW_INTR_4 0x5418210
156
157#define mmNIC0_QM_ARC_AUX0_SW_INTR_5 0x5418214
158
159#define mmNIC0_QM_ARC_AUX0_SW_INTR_6 0x5418218
160
161#define mmNIC0_QM_ARC_AUX0_SW_INTR_7 0x541821C
162
163#define mmNIC0_QM_ARC_AUX0_SW_INTR_8 0x5418220
164
165#define mmNIC0_QM_ARC_AUX0_SW_INTR_9 0x5418224
166
167#define mmNIC0_QM_ARC_AUX0_SW_INTR_10 0x5418228
168
169#define mmNIC0_QM_ARC_AUX0_SW_INTR_11 0x541822C
170
171#define mmNIC0_QM_ARC_AUX0_SW_INTR_12 0x5418230
172
173#define mmNIC0_QM_ARC_AUX0_SW_INTR_13 0x5418234
174
175#define mmNIC0_QM_ARC_AUX0_SW_INTR_14 0x5418238
176
177#define mmNIC0_QM_ARC_AUX0_SW_INTR_15 0x541823C
178
179#define mmNIC0_QM_ARC_AUX0_IRQ_INTR_MASK_0 0x5418280
180
181#define mmNIC0_QM_ARC_AUX0_IRQ_INTR_MASK_1 0x5418284
182
183#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_STS 0x5418290
184
185#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_CLR 0x5418294
186
187#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_MASK 0x5418298
188
189#define mmNIC0_QM_ARC_AUX0_ARC_EXCPTN_CAUSE 0x541829C
190
191#define mmNIC0_QM_ARC_AUX0_SEI_INTR_HALT_EN 0x54182A0
192
193#define mmNIC0_QM_ARC_AUX0_ARC_SEI_INTR_HALT_MASK 0x54182A4
194
195#define mmNIC0_QM_ARC_AUX0_QMAN_SEI_INTR_HALT_MASK 0x54182A8
196
197#define mmNIC0_QM_ARC_AUX0_ARC_REI_INTR_STS 0x54182B0
198
199#define mmNIC0_QM_ARC_AUX0_ARC_REI_INTR_CLR 0x54182B4
200
201#define mmNIC0_QM_ARC_AUX0_ARC_REI_INTR_MASK 0x54182B8
202
203#define mmNIC0_QM_ARC_AUX0_DCCM_ECC_ERR_ADDR 0x54182BC
204
205#define mmNIC0_QM_ARC_AUX0_DCCM_ECC_SYNDROME 0x54182C0
206
207#define mmNIC0_QM_ARC_AUX0_I_CACHE_ECC_ERR_ADDR 0x54182C4
208
209#define mmNIC0_QM_ARC_AUX0_I_CACHE_ECC_SYNDROME 0x54182C8
210
211#define mmNIC0_QM_ARC_AUX0_D_CACHE_ECC_ERR_ADDR 0x54182CC
212
213#define mmNIC0_QM_ARC_AUX0_D_CACHE_ECC_SYNDROME 0x54182D0
214
215#define mmNIC0_QM_ARC_AUX0_LBW_TRMINATE_AWADDR_ERR 0x54182E0
216
217#define mmNIC0_QM_ARC_AUX0_LBW_TRMINATE_ARADDR_ERR 0x54182E4
218
219#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_BRESP 0x54182E8
220
221#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_RRESP 0x54182EC
222
223#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_AXLEN 0x54182F0
224
225#define mmNIC0_QM_ARC_AUX0_CFG_LBW_TERMINATE_AXSIZE 0x54182F4
226
227#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_0 0x5418300
228
229#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_1 0x5418304
230
231#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_2 0x5418308
232
233#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_3 0x541830C
234
235#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_4 0x5418310
236
237#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_5 0x5418314
238
239#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_6 0x5418318
240
241#define mmNIC0_QM_ARC_AUX0_SCRATCHPAD_7 0x541831C
242
243#define mmNIC0_QM_ARC_AUX0_TOTAL_CBU_WR_CNT 0x5418320
244
245#define mmNIC0_QM_ARC_AUX0_INFLIGHT_CBU_WR_CNT 0x5418324
246
247#define mmNIC0_QM_ARC_AUX0_TOTAL_CBU_RD_CNT 0x5418328
248
249#define mmNIC0_QM_ARC_AUX0_INFLIGHT_CBU_RD_CNT 0x541832C
250
251#define mmNIC0_QM_ARC_AUX0_TOTAL_LBU_WR_CNT 0x5418330
252
253#define mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_WR_CNT 0x5418334
254
255#define mmNIC0_QM_ARC_AUX0_TOTAL_LBU_RD_CNT 0x5418338
256
257#define mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_RD_CNT 0x541833C
258
259#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_OVR 0x5418350
260
261#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_OVR_EN 0x5418354
262
263#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_OVR 0x5418358
264
265#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_OVR_EN 0x541835C
266
267#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_MSB_OVR 0x5418360
268
269#define mmNIC0_QM_ARC_AUX0_CBU_ARUSER_MSB_OVR_EN 0x5418364
270
271#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_MSB_OVR 0x5418368
272
273#define mmNIC0_QM_ARC_AUX0_CBU_AWUSER_MSB_OVR_EN 0x541836C
274
275#define mmNIC0_QM_ARC_AUX0_CBU_AXCACHE_OVR 0x5418370
276
277#define mmNIC0_QM_ARC_AUX0_CBU_LOCK_OVR 0x5418374
278
279#define mmNIC0_QM_ARC_AUX0_CBU_PROT_OVR 0x5418378
280
281#define mmNIC0_QM_ARC_AUX0_CBU_MAX_OUTSTANDING 0x541837C
282
283#define mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN 0x5418380
284
285#define mmNIC0_QM_ARC_AUX0_CBU_FORCE_RSP_OK 0x5418384
286
287#define mmNIC0_QM_ARC_AUX0_CBU_NO_WR_INFLIGHT 0x541838C
288
289#define mmNIC0_QM_ARC_AUX0_CBU_SEI_INTR_ID 0x5418390
290
291#define mmNIC0_QM_ARC_AUX0_LBU_ARUSER_OVR 0x5418400
292
293#define mmNIC0_QM_ARC_AUX0_LBU_ARUSER_OVR_EN 0x5418404
294
295#define mmNIC0_QM_ARC_AUX0_LBU_AWUSER_OVR 0x5418408
296
297#define mmNIC0_QM_ARC_AUX0_LBU_AWUSER_OVR_EN 0x541840C
298
299#define mmNIC0_QM_ARC_AUX0_LBU_AXCACHE_OVR 0x5418420
300
301#define mmNIC0_QM_ARC_AUX0_LBU_LOCK_OVR 0x5418424
302
303#define mmNIC0_QM_ARC_AUX0_LBU_PROT_OVR 0x5418428
304
305#define mmNIC0_QM_ARC_AUX0_LBU_MAX_OUTSTANDING 0x541842C
306
307#define mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN 0x5418430
308
309#define mmNIC0_QM_ARC_AUX0_LBU_FORCE_RSP_OK 0x5418434
310
311#define mmNIC0_QM_ARC_AUX0_LBU_NO_WR_INFLIGHT 0x541843C
312
313#define mmNIC0_QM_ARC_AUX0_LBU_SEI_INTR_ID 0x5418440
314
315#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_0 0x5418500
316
317#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_1 0x5418504
318
319#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_2 0x5418508
320
321#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_3 0x541850C
322
323#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_4 0x5418510
324
325#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_5 0x5418514
326
327#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_6 0x5418518
328
329#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_7 0x541851C
330
331#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_0 0x5418520
332
333#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_1 0x5418524
334
335#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_2 0x5418528
336
337#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_3 0x541852C
338
339#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_4 0x5418530
340
341#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_5 0x5418534
342
343#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_6 0x5418538
344
345#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_SIZE_7 0x541853C
346
347#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_0 0x5418540
348
349#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_1 0x5418544
350
351#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_2 0x5418548
352
353#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_3 0x541854C
354
355#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_4 0x5418550
356
357#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_5 0x5418554
358
359#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_6 0x5418558
360
361#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PI_7 0x541855C
362
363#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_0 0x5418560
364
365#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_1 0x5418564
366
367#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_2 0x5418568
368
369#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_3 0x541856C
370
371#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_4 0x5418570
372
373#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_5 0x5418574
374
375#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_6 0x5418578
376
377#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_CI_7 0x541857C
378
379#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_0 0x5418580
380
381#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_1 0x5418584
382
383#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_2 0x5418588
384
385#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_3 0x541858C
386
387#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_4 0x5418590
388
389#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_5 0x5418594
390
391#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_6 0x5418598
392
393#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_PUSH_REG_7 0x541859C
394
395#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_0 0x54185A0
396
397#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_1 0x54185A4
398
399#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_2 0x54185A8
400
401#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_3 0x54185AC
402
403#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_4 0x54185B0
404
405#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_5 0x54185B4
406
407#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_6 0x54185B8
408
409#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_MAX_OCCUPANCY_7 0x54185BC
410
411#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_0 0x54185C0
412
413#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_1 0x54185C4
414
415#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_2 0x54185C8
416
417#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_3 0x54185CC
418
419#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_4 0x54185D0
420
421#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_5 0x54185D4
422
423#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_6 0x54185D8
424
425#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_VALID_ENTRIES_7 0x54185DC
426
427#define mmNIC0_QM_ARC_AUX0_GENERAL_Q_VLD_ENTRY_MASK 0x54185E0
428
429#define mmNIC0_QM_ARC_AUX0_NIC_Q_VLD_ENTRY_MASK 0x54185E4
430
431#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_DROP_EN 0x5418620
432
433#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_WARN_MSG 0x5418624
434
435#define mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_ALERT_MSG 0x5418628
436
437#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWPROT 0x5418630
438
439#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWUSER 0x5418634
440
441#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWBURST 0x5418638
442
443#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWLOCK 0x541863C
444
445#define mmNIC0_QM_ARC_AUX0_DCCM_GEN_AXI_AWCACHE 0x5418640
446
447#define mmNIC0_QM_ARC_AUX0_DCCM_WRR_ARB_WEIGHT 0x5418644
448
449#define mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_FULL_CFG 0x5418648
450
451#define mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_CNT 0x541864C
452
453#define mmNIC0_QM_ARC_AUX0_QMAN_CQ_IFIFO_SHADOW_CI 0x5418650
454
455#define mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x5418654
456
457#define mmNIC0_QM_ARC_AUX0_QMAN_CQ_SHADOW_CI 0x5418658
458
459#define mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_SHADOW_CI 0x541865C
460
461#define mmNIC0_QM_ARC_AUX0_AUX2APB_PROT 0x5418700
462
463#define mmNIC0_QM_ARC_AUX0_LBW_FORK_WIN_EN 0x5418704
464
465#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_BASE_ADDR0 0x5418708
466
467#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_ADDR_MASK0 0x541870C
468
469#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_BASE_ADDR1 0x5418710
470
471#define mmNIC0_QM_ARC_AUX0_QMAN_LBW_FORK_ADDR_MASK1 0x5418714
472
473#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_BASE_ADDR0 0x5418718
474
475#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_ADDR_MASK0 0x541871C
476
477#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_BASE_ADDR1 0x5418720
478
479#define mmNIC0_QM_ARC_AUX0_FARM_LBW_FORK_ADDR_MASK1 0x5418724
480
481#define mmNIC0_QM_ARC_AUX0_LBW_APB_FORK_MAX_ADDR0 0x5418728
482
483#define mmNIC0_QM_ARC_AUX0_LBW_APB_FORK_MAX_ADDR1 0x541872C
484
485#define mmNIC0_QM_ARC_AUX0_ARC_ACC_ENGS_LBW_FORK_MASK 0x5418730
486
487#define mmNIC0_QM_ARC_AUX0_ARC_DUP_ENG_LBW_FORK_ADDR 0x5418734
488
489#define mmNIC0_QM_ARC_AUX0_ARC_ACP_ENG_LBW_FORK_ADDR 0x5418738
490
491#define mmNIC0_QM_ARC_AUX0_ARC_ACC_ENGS_VIRTUAL_ADDR 0x541873C
492
493#define mmNIC0_QM_ARC_AUX0_CBU_FORK_WIN_EN 0x5418740
494
495#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR0_LSB 0x5418750
496
497#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR0_MSB 0x5418754
498
499#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK0_LSB 0x5418758
500
501#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK0_MSB 0x541875C
502
503#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR1_LSB 0x5418760
504
505#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR1_MSB 0x5418764
506
507#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK1_LSB 0x5418768
508
509#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK1_MSB 0x541876C
510
511#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR2_LSB 0x5418770
512
513#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR2_MSB 0x5418774
514
515#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK2_LSB 0x5418778
516
517#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK2_MSB 0x541877C
518
519#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR3_LSB 0x5418780
520
521#define mmNIC0_QM_ARC_AUX0_CBU_FORK_BASE_ADDR3_MSB 0x5418784
522
523#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK3_LSB 0x5418788
524
525#define mmNIC0_QM_ARC_AUX0_CBU_FORK_ADDR_MASK3_MSB 0x541878C
526
527#define mmNIC0_QM_ARC_AUX0_CBU_TRMINATE_ARADDR_LSB 0x5418790
528
529#define mmNIC0_QM_ARC_AUX0_CBU_TRMINATE_ARADDR_MSB 0x5418794
530
531#define mmNIC0_QM_ARC_AUX0_CFG_CBU_TERMINATE_BRESP 0x5418798
532
533#define mmNIC0_QM_ARC_AUX0_CFG_CBU_TERMINATE_RRESP 0x541879C
534
535#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_0 0x5418800
536
537#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_1 0x5418804
538
539#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_2 0x5418808
540
541#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_3 0x541880C
542
543#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_4 0x5418810
544
545#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_5 0x5418814
546
547#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_6 0x5418818
548
549#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_7 0x541881C
550
551#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_8 0x5418820
552
553#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_9 0x5418824
554
555#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_10 0x5418828
556
557#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_11 0x541882C
558
559#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_12 0x5418830
560
561#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_13 0x5418834
562
563#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_14 0x5418838
564
565#define mmNIC0_QM_ARC_AUX0_ARC_REGION_CFG_15 0x541883C
566
567#define mmNIC0_QM_ARC_AUX0_DCCM_TRMINATE_AWADDR_ERR 0x5418840
568
569#define mmNIC0_QM_ARC_AUX0_DCCM_TRMINATE_ARADDR_ERR 0x5418844
570
571#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_TERMINATE_BRESP 0x5418848
572
573#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_TERMINATE_RRESP 0x541884C
574
575#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_TERMINATE_EN 0x5418850
576
577#define mmNIC0_QM_ARC_AUX0_CFG_DCCM_SECURE_REGION 0x5418854
578
579#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_WR_IF_CNT 0x5418900
580
581#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_CTL 0x5418904
582
583#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_ADDR_MSK 0x5418908
584
585#define mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_ADDR 0x541890C
586
587#define mmNIC0_QM_ARC_AUX0_ARC_ACC_ENGS_BUSER 0x5418910
588
589#define mmNIC0_QM_ARC_AUX0_MME_ARC_UPPER_DCCM_EN 0x5418920
590
591#endif /* ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_ */