FILE
nic0_qm0_regs.h
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linux-6.19.14/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_NIC0_QM0_REGS_H_ 14#define ASIC_REG_NIC0_QM0_REGS_H_ 15 16/* 17 ***************************************** 18 * NIC0_QM0 19 * (Prototype: QMAN) 20 ***************************************** 21 */ 22 23#define mmNIC0_QM0_GLBL_CFG0 0x541A000 24 25#define mmNIC0_QM0_GLBL_CFG1 0x541A004 26 27#define mmNIC0_QM0_GLBL_CFG2 0x541A008 28 29#define mmNIC0_QM0_GLBL_ERR_CFG 0x541A00C 30 31#define mmNIC0_QM0_GLBL_ERR_CFG1 0x541A010 32 33#define mmNIC0_QM0_GLBL_ERR_ARC_HALT_EN 0x541A014 34 35#define mmNIC0_QM0_GLBL_AXCACHE 0x541A018 36 37#define mmNIC0_QM0_GLBL_STS0 0x541A01C 38 39#define mmNIC0_QM0_GLBL_STS1 0x541A020 40 41#define mmNIC0_QM0_GLBL_ERR_STS_0 0x541A024 42 43#define mmNIC0_QM0_GLBL_ERR_STS_1 0x541A028 44 45#define mmNIC0_QM0_GLBL_ERR_STS_2 0x541A02C 46 47#define mmNIC0_QM0_GLBL_ERR_STS_3 0x541A030 48 49#define mmNIC0_QM0_GLBL_ERR_STS_4 0x541A034 50 51#define mmNIC0_QM0_GLBL_ERR_MSG_EN_0 0x541A038 52 53#define mmNIC0_QM0_GLBL_ERR_MSG_EN_1 0x541A03C 54 55#define mmNIC0_QM0_GLBL_ERR_MSG_EN_2 0x541A040 56 57#define mmNIC0_QM0_GLBL_ERR_MSG_EN_3 0x541A044 58 59#define mmNIC0_QM0_GLBL_ERR_MSG_EN_4 0x541A048 60 61#define mmNIC0_QM0_GLBL_PROT 0x541A04C 62 63#define mmNIC0_QM0_PQ_BASE_LO_0 0x541A050 64 65#define mmNIC0_QM0_PQ_BASE_LO_1 0x541A054 66 67#define mmNIC0_QM0_PQ_BASE_LO_2 0x541A058 68 69#define mmNIC0_QM0_PQ_BASE_LO_3 0x541A05C 70 71#define mmNIC0_QM0_PQ_BASE_HI_0 0x541A060 72 73#define mmNIC0_QM0_PQ_BASE_HI_1 0x541A064 74 75#define mmNIC0_QM0_PQ_BASE_HI_2 0x541A068 76 77#define mmNIC0_QM0_PQ_BASE_HI_3 0x541A06C 78 79#define mmNIC0_QM0_PQ_SIZE_0 0x541A070 80 81#define mmNIC0_QM0_PQ_SIZE_1 0x541A074 82 83#define mmNIC0_QM0_PQ_SIZE_2 0x541A078 84 85#define mmNIC0_QM0_PQ_SIZE_3 0x541A07C 86 87#define mmNIC0_QM0_PQ_PI_0 0x541A080 88 89#define mmNIC0_QM0_PQ_PI_1 0x541A084 90 91#define mmNIC0_QM0_PQ_PI_2 0x541A088 92 93#define mmNIC0_QM0_PQ_PI_3 0x541A08C 94 95#define mmNIC0_QM0_PQ_CI_0 0x541A090 96 97#define mmNIC0_QM0_PQ_CI_1 0x541A094 98 99#define mmNIC0_QM0_PQ_CI_2 0x541A098 100 101#define mmNIC0_QM0_PQ_CI_3 0x541A09C 102 103#define mmNIC0_QM0_PQ_CFG0_0 0x541A0A0 104 105#define mmNIC0_QM0_PQ_CFG0_1 0x541A0A4 106 107#define mmNIC0_QM0_PQ_CFG0_2 0x541A0A8 108 109#define mmNIC0_QM0_PQ_CFG0_3 0x541A0AC 110 111#define mmNIC0_QM0_PQ_CFG1_0 0x541A0B0 112 113#define mmNIC0_QM0_PQ_CFG1_1 0x541A0B4 114 115#define mmNIC0_QM0_PQ_CFG1_2 0x541A0B8 116 117#define mmNIC0_QM0_PQ_CFG1_3 0x541A0BC 118 119#define mmNIC0_QM0_PQ_STS0_0 0x541A0C0 120 121#define mmNIC0_QM0_PQ_STS0_1 0x541A0C4 122 123#define mmNIC0_QM0_PQ_STS0_2 0x541A0C8 124 125#define mmNIC0_QM0_PQ_STS0_3 0x541A0CC 126 127#define mmNIC0_QM0_PQ_STS1_0 0x541A0D0 128 129#define mmNIC0_QM0_PQ_STS1_1 0x541A0D4 130 131#define mmNIC0_QM0_PQ_STS1_2 0x541A0D8 132 133#define mmNIC0_QM0_PQ_STS1_3 0x541A0DC 134 135#define mmNIC0_QM0_CQ_CFG0_0 0x541A0E0 136 137#define mmNIC0_QM0_CQ_CFG0_1 0x541A0E4 138 139#define mmNIC0_QM0_CQ_CFG0_2 0x541A0E8 140 141#define mmNIC0_QM0_CQ_CFG0_3 0x541A0EC 142 143#define mmNIC0_QM0_CQ_CFG0_4 0x541A0F0 144 145#define mmNIC0_QM0_CQ_STS0_0 0x541A0F4 146 147#define mmNIC0_QM0_CQ_STS0_1 0x541A0F8 148 149#define mmNIC0_QM0_CQ_STS0_2 0x541A0FC 150 151#define mmNIC0_QM0_CQ_STS0_3 0x541A100 152 153#define mmNIC0_QM0_CQ_STS0_4 0x541A104 154 155#define mmNIC0_QM0_CQ_CFG1_0 0x541A108 156 157#define mmNIC0_QM0_CQ_CFG1_1 0x541A10C 158 159#define mmNIC0_QM0_CQ_CFG1_2 0x541A110 160 161#define mmNIC0_QM0_CQ_CFG1_3 0x541A114 162 163#define mmNIC0_QM0_CQ_CFG1_4 0x541A118 164 165#define mmNIC0_QM0_CQ_STS1_0 0x541A11C 166 167#define mmNIC0_QM0_CQ_STS1_1 0x541A120 168 169#define mmNIC0_QM0_CQ_STS1_2 0x541A124 170 171#define mmNIC0_QM0_CQ_STS1_3 0x541A128 172 173#define mmNIC0_QM0_CQ_STS1_4 0x541A12C 174 175#define mmNIC0_QM0_CQ_PTR_LO_0 0x541A150 176 177#define mmNIC0_QM0_CQ_PTR_HI_0 0x541A154 178 179#define mmNIC0_QM0_CQ_TSIZE_0 0x541A158 180 181#define mmNIC0_QM0_CQ_CTL_0 0x541A15C 182 183#define mmNIC0_QM0_CQ_PTR_LO_1 0x541A160 184 185#define mmNIC0_QM0_CQ_PTR_HI_1 0x541A164 186 187#define mmNIC0_QM0_CQ_TSIZE_1 0x541A168 188 189#define mmNIC0_QM0_CQ_CTL_1 0x541A16C 190 191#define mmNIC0_QM0_CQ_PTR_LO_2 0x541A170 192 193#define mmNIC0_QM0_CQ_PTR_HI_2 0x541A174 194 195#define mmNIC0_QM0_CQ_TSIZE_2 0x541A178 196 197#define mmNIC0_QM0_CQ_CTL_2 0x541A17C 198 199#define mmNIC0_QM0_CQ_PTR_LO_3 0x541A180 200 201#define mmNIC0_QM0_CQ_PTR_HI_3 0x541A184 202 203#define mmNIC0_QM0_CQ_TSIZE_3 0x541A188 204 205#define mmNIC0_QM0_CQ_CTL_3 0x541A18C 206 207#define mmNIC0_QM0_CQ_PTR_LO_4 0x541A190 208 209#define mmNIC0_QM0_CQ_PTR_HI_4 0x541A194 210 211#define mmNIC0_QM0_CQ_TSIZE_4 0x541A198 212 213#define mmNIC0_QM0_CQ_CTL_4 0x541A19C 214 215#define mmNIC0_QM0_CQ_TSIZE_STS_0 0x541A1A0 216 217#define mmNIC0_QM0_CQ_TSIZE_STS_1 0x541A1A4 218 219#define mmNIC0_QM0_CQ_TSIZE_STS_2 0x541A1A8 220 221#define mmNIC0_QM0_CQ_TSIZE_STS_3 0x541A1AC 222 223#define mmNIC0_QM0_CQ_TSIZE_STS_4 0x541A1B0 224 225#define mmNIC0_QM0_CQ_PTR_LO_STS_0 0x541A1B4 226 227#define mmNIC0_QM0_CQ_PTR_LO_STS_1 0x541A1B8 228 229#define mmNIC0_QM0_CQ_PTR_LO_STS_2 0x541A1BC 230 231#define mmNIC0_QM0_CQ_PTR_LO_STS_3 0x541A1C0 232 233#define mmNIC0_QM0_CQ_PTR_LO_STS_4 0x541A1C4 234 235#define mmNIC0_QM0_CQ_PTR_HI_STS_0 0x541A1C8 236 237#define mmNIC0_QM0_CQ_PTR_HI_STS_1 0x541A1CC 238 239#define mmNIC0_QM0_CQ_PTR_HI_STS_2 0x541A1D0 240 241#define mmNIC0_QM0_CQ_PTR_HI_STS_3 0x541A1D4 242 243#define mmNIC0_QM0_CQ_PTR_HI_STS_4 0x541A1D8 244 245#define mmNIC0_QM0_CQ_IFIFO_STS_0 0x541A1DC 246 247#define mmNIC0_QM0_CQ_IFIFO_STS_1 0x541A1E0 248 249#define mmNIC0_QM0_CQ_IFIFO_STS_2 0x541A1E4 250 251#define mmNIC0_QM0_CQ_IFIFO_STS_3 0x541A1E8 252 253#define mmNIC0_QM0_CQ_IFIFO_STS_4 0x541A1EC 254 255#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 0x541A1F0 256 257#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1 0x541A1F4 258 259#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2 0x541A1F8 260 261#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3 0x541A1FC 262 263#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4 0x541A200 264 265#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 0x541A204 266 267#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1 0x541A208 268 269#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2 0x541A20C 270 271#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3 0x541A210 272 273#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4 0x541A214 274 275#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 0x541A218 276 277#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1 0x541A21C 278 279#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2 0x541A220 280 281#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3 0x541A224 282 283#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4 0x541A228 284 285#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 0x541A22C 286 287#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1 0x541A230 288 289#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2 0x541A234 290 291#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3 0x541A238 292 293#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4 0x541A23C 294 295#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 0x541A240 296 297#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1 0x541A244 298 299#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2 0x541A248 300 301#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3 0x541A24C 302 303#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4 0x541A250 304 305#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 0x541A254 306 307#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1 0x541A258 308 309#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2 0x541A25C 310 311#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3 0x541A260 312 313#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4 0x541A264 314 315#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 0x541A268 316 317#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1 0x541A26C 318 319#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2 0x541A270 320 321#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3 0x541A274 322 323#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4 0x541A278 324 325#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 0x541A27C 326 327#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1 0x541A280 328 329#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2 0x541A284 330 331#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3 0x541A288 332 333#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4 0x541A28C 334 335#define mmNIC0_QM0_CP_FENCE0_RDATA_0 0x541A290 336 337#define mmNIC0_QM0_CP_FENCE0_RDATA_1 0x541A294 338 339#define mmNIC0_QM0_CP_FENCE0_RDATA_2 0x541A298 340 341#define mmNIC0_QM0_CP_FENCE0_RDATA_3 0x541A29C 342 343#define mmNIC0_QM0_CP_FENCE0_RDATA_4 0x541A2A0 344 345#define mmNIC0_QM0_CP_FENCE1_RDATA_0 0x541A2A4 346 347#define mmNIC0_QM0_CP_FENCE1_RDATA_1 0x541A2A8 348 349#define mmNIC0_QM0_CP_FENCE1_RDATA_2 0x541A2AC 350 351#define mmNIC0_QM0_CP_FENCE1_RDATA_3 0x541A2B0 352 353#define mmNIC0_QM0_CP_FENCE1_RDATA_4 0x541A2B4 354 355#define mmNIC0_QM0_CP_FENCE2_RDATA_0 0x541A2B8 356 357#define mmNIC0_QM0_CP_FENCE2_RDATA_1 0x541A2BC 358 359#define mmNIC0_QM0_CP_FENCE2_RDATA_2 0x541A2C0 360 361#define mmNIC0_QM0_CP_FENCE2_RDATA_3 0x541A2C4 362 363#define mmNIC0_QM0_CP_FENCE2_RDATA_4 0x541A2C8 364 365#define mmNIC0_QM0_CP_FENCE3_RDATA_0 0x541A2CC 366 367#define mmNIC0_QM0_CP_FENCE3_RDATA_1 0x541A2D0 368 369#define mmNIC0_QM0_CP_FENCE3_RDATA_2 0x541A2D4 370 371#define mmNIC0_QM0_CP_FENCE3_RDATA_3 0x541A2D8 372 373#define mmNIC0_QM0_CP_FENCE3_RDATA_4 0x541A2DC 374 375#define mmNIC0_QM0_CP_FENCE0_CNT_0 0x541A2E0 376 377#define mmNIC0_QM0_CP_FENCE0_CNT_1 0x541A2E4 378 379#define mmNIC0_QM0_CP_FENCE0_CNT_2 0x541A2E8 380 381#define mmNIC0_QM0_CP_FENCE0_CNT_3 0x541A2EC 382 383#define mmNIC0_QM0_CP_FENCE0_CNT_4 0x541A2F0 384 385#define mmNIC0_QM0_CP_FENCE1_CNT_0 0x541A2F4 386 387#define mmNIC0_QM0_CP_FENCE1_CNT_1 0x541A2F8 388 389#define mmNIC0_QM0_CP_FENCE1_CNT_2 0x541A2FC 390 391#define mmNIC0_QM0_CP_FENCE1_CNT_3 0x541A300 392 393#define mmNIC0_QM0_CP_FENCE1_CNT_4 0x541A304 394 395#define mmNIC0_QM0_CP_FENCE2_CNT_0 0x541A308 396 397#define mmNIC0_QM0_CP_FENCE2_CNT_1 0x541A30C 398 399#define mmNIC0_QM0_CP_FENCE2_CNT_2 0x541A310 400 401#define mmNIC0_QM0_CP_FENCE2_CNT_3 0x541A314 402 403#define mmNIC0_QM0_CP_FENCE2_CNT_4 0x541A318 404 405#define mmNIC0_QM0_CP_FENCE3_CNT_0 0x541A31C 406 407#define mmNIC0_QM0_CP_FENCE3_CNT_1 0x541A320 408 409#define mmNIC0_QM0_CP_FENCE3_CNT_2 0x541A324 410 411#define mmNIC0_QM0_CP_FENCE3_CNT_3 0x541A328 412 413#define mmNIC0_QM0_CP_FENCE3_CNT_4 0x541A32C 414 415#define mmNIC0_QM0_CP_BARRIER_CFG 0x541A330 416 417#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET 0x541A334 418 419#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET 0x541A338 420 421#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET 0x541A33C 422 423#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_0 0x541A340 424 425#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_1 0x541A344 426 427#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_2 0x541A348 428 429#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_3 0x541A34C 430 431#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_4 0x541A350 432 433#define mmNIC0_QM0_CP_STS_0 0x541A368 434 435#define mmNIC0_QM0_CP_STS_1 0x541A36C 436 437#define mmNIC0_QM0_CP_STS_2 0x541A370 438 439#define mmNIC0_QM0_CP_STS_3 0x541A374 440 441#define mmNIC0_QM0_CP_STS_4 0x541A378 442 443#define mmNIC0_QM0_CP_CURRENT_INST_LO_0 0x541A37C 444 445#define mmNIC0_QM0_CP_CURRENT_INST_LO_1 0x541A380 446 447#define mmNIC0_QM0_CP_CURRENT_INST_LO_2 0x541A384 448 449#define mmNIC0_QM0_CP_CURRENT_INST_LO_3 0x541A388 450 451#define mmNIC0_QM0_CP_CURRENT_INST_LO_4 0x541A38C 452 453#define mmNIC0_QM0_CP_CURRENT_INST_HI_0 0x541A390 454 455#define mmNIC0_QM0_CP_CURRENT_INST_HI_1 0x541A394 456 457#define mmNIC0_QM0_CP_CURRENT_INST_HI_2 0x541A398 458 459#define mmNIC0_QM0_CP_CURRENT_INST_HI_3 0x541A39C 460 461#define mmNIC0_QM0_CP_CURRENT_INST_HI_4 0x541A3A0 462 463#define mmNIC0_QM0_CP_PRED_0 0x541A3A4 464 465#define mmNIC0_QM0_CP_PRED_1 0x541A3A8 466 467#define mmNIC0_QM0_CP_PRED_2 0x541A3AC 468 469#define mmNIC0_QM0_CP_PRED_3 0x541A3B0 470 471#define mmNIC0_QM0_CP_PRED_4 0x541A3B4 472 473#define mmNIC0_QM0_CP_PRED_UPEN_0 0x541A3B8 474 475#define mmNIC0_QM0_CP_PRED_UPEN_1 0x541A3BC 476 477#define mmNIC0_QM0_CP_PRED_UPEN_2 0x541A3C0 478 479#define mmNIC0_QM0_CP_PRED_UPEN_3 0x541A3C4 480 481#define mmNIC0_QM0_CP_PRED_UPEN_4 0x541A3C8 482 483#define mmNIC0_QM0_CP_DBG_0_0 0x541A3CC 484 485#define mmNIC0_QM0_CP_DBG_0_1 0x541A3D0 486 487#define mmNIC0_QM0_CP_DBG_0_2 0x541A3D4 488 489#define mmNIC0_QM0_CP_DBG_0_3 0x541A3D8 490 491#define mmNIC0_QM0_CP_DBG_0_4 0x541A3DC 492 493#define mmNIC0_QM0_CP_CPDMA_UP_CRED_0 0x541A3E0 494 495#define mmNIC0_QM0_CP_CPDMA_UP_CRED_1 0x541A3E4 496 497#define mmNIC0_QM0_CP_CPDMA_UP_CRED_2 0x541A3E8 498 499#define mmNIC0_QM0_CP_CPDMA_UP_CRED_3 0x541A3EC 500 501#define mmNIC0_QM0_CP_CPDMA_UP_CRED_4 0x541A3F0 502 503#define mmNIC0_QM0_CP_IN_DATA_LO_0 0x541A3F4 504 505#define mmNIC0_QM0_CP_IN_DATA_LO_1 0x541A3F8 506 507#define mmNIC0_QM0_CP_IN_DATA_LO_2 0x541A3FC 508 509#define mmNIC0_QM0_CP_IN_DATA_LO_3 0x541A400 510 511#define mmNIC0_QM0_CP_IN_DATA_LO_4 0x541A404 512 513#define mmNIC0_QM0_CP_IN_DATA_HI_0 0x541A408 514 515#define mmNIC0_QM0_CP_IN_DATA_HI_1 0x541A40C 516 517#define mmNIC0_QM0_CP_IN_DATA_HI_2 0x541A410 518 519#define mmNIC0_QM0_CP_IN_DATA_HI_3 0x541A414 520 521#define mmNIC0_QM0_CP_IN_DATA_HI_4 0x541A418 522 523#define mmNIC0_QM0_PQC_HBW_BASE_LO_0 0x541A41C 524 525#define mmNIC0_QM0_PQC_HBW_BASE_LO_1 0x541A420 526 527#define mmNIC0_QM0_PQC_HBW_BASE_LO_2 0x541A424 528 529#define mmNIC0_QM0_PQC_HBW_BASE_LO_3 0x541A428 530 531#define mmNIC0_QM0_PQC_HBW_BASE_HI_0 0x541A42C 532 533#define mmNIC0_QM0_PQC_HBW_BASE_HI_1 0x541A430 534 535#define mmNIC0_QM0_PQC_HBW_BASE_HI_2 0x541A434 536 537#define mmNIC0_QM0_PQC_HBW_BASE_HI_3 0x541A438 538 539#define mmNIC0_QM0_PQC_SIZE_0 0x541A43C 540 541#define mmNIC0_QM0_PQC_SIZE_1 0x541A440 542 543#define mmNIC0_QM0_PQC_SIZE_2 0x541A444 544 545#define mmNIC0_QM0_PQC_SIZE_3 0x541A448 546 547#define mmNIC0_QM0_PQC_PI_0 0x541A44C 548 549#define mmNIC0_QM0_PQC_PI_1 0x541A450 550 551#define mmNIC0_QM0_PQC_PI_2 0x541A454 552 553#define mmNIC0_QM0_PQC_PI_3 0x541A458 554 555#define mmNIC0_QM0_PQC_LBW_WDATA_0 0x541A45C 556 557#define mmNIC0_QM0_PQC_LBW_WDATA_1 0x541A460 558 559#define mmNIC0_QM0_PQC_LBW_WDATA_2 0x541A464 560 561#define mmNIC0_QM0_PQC_LBW_WDATA_3 0x541A468 562 563#define mmNIC0_QM0_PQC_LBW_BASE_LO_0 0x541A46C 564 565#define mmNIC0_QM0_PQC_LBW_BASE_LO_1 0x541A470 566 567#define mmNIC0_QM0_PQC_LBW_BASE_LO_2 0x541A474 568 569#define mmNIC0_QM0_PQC_LBW_BASE_LO_3 0x541A478 570 571#define mmNIC0_QM0_PQC_LBW_BASE_HI_0 0x541A47C 572 573#define mmNIC0_QM0_PQC_LBW_BASE_HI_1 0x541A480 574 575#define mmNIC0_QM0_PQC_LBW_BASE_HI_2 0x541A484 576 577#define mmNIC0_QM0_PQC_LBW_BASE_HI_3 0x541A488 578 579#define mmNIC0_QM0_PQC_CFG 0x541A48C 580 581#define mmNIC0_QM0_PQC_SECURE_PUSH_IND 0x541A490 582 583#define mmNIC0_QM0_ARB_MASK 0x541A4A0 584 585#define mmNIC0_QM0_ARB_CFG_0 0x541A4A4 586 587#define mmNIC0_QM0_ARB_CHOICE_Q_PUSH 0x541A4A8 588 589#define mmNIC0_QM0_ARB_WRR_WEIGHT_0 0x541A4AC 590 591#define mmNIC0_QM0_ARB_WRR_WEIGHT_1 0x541A4B0 592 593#define mmNIC0_QM0_ARB_WRR_WEIGHT_2 0x541A4B4 594 595#define mmNIC0_QM0_ARB_WRR_WEIGHT_3 0x541A4B8 596 597#define mmNIC0_QM0_ARB_CFG_1 0x541A4BC 598 599#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_0 0x541A4C0 600 601#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_1 0x541A4C4 602 603#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_2 0x541A4C8 604 605#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_3 0x541A4CC 606 607#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_4 0x541A4D0 608 609#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_5 0x541A4D4 610 611#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_6 0x541A4D8 612 613#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_7 0x541A4DC 614 615#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_8 0x541A4E0 616 617#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_9 0x541A4E4 618 619#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_10 0x541A4E8 620 621#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_11 0x541A4EC 622 623#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_12 0x541A4F0 624 625#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_13 0x541A4F4 626 627#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_14 0x541A4F8 628 629#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_15 0x541A4FC 630 631#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_16 0x541A500 632 633#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_17 0x541A504 634 635#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_18 0x541A508 636 637#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_19 0x541A50C 638 639#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_20 0x541A510 640 641#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_21 0x541A514 642 643#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_22 0x541A518 644 645#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_23 0x541A51C 646 647#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_24 0x541A520 648 649#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_25 0x541A524 650 651#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_26 0x541A528 652 653#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_27 0x541A52C 654 655#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_28 0x541A530 656 657#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_29 0x541A534 658 659#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_30 0x541A538 660 661#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_31 0x541A53C 662 663#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_32 0x541A540 664 665#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_33 0x541A544 666 667#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_34 0x541A548 668 669#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_35 0x541A54C 670 671#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_36 0x541A550 672 673#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_37 0x541A554 674 675#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_38 0x541A558 676 677#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_39 0x541A55C 678 679#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_40 0x541A560 680 681#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_41 0x541A564 682 683#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_42 0x541A568 684 685#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_43 0x541A56C 686 687#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_44 0x541A570 688 689#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_45 0x541A574 690 691#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_46 0x541A578 692 693#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_47 0x541A57C 694 695#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_48 0x541A580 696 697#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_49 0x541A584 698 699#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_50 0x541A588 700 701#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_51 0x541A58C 702 703#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_52 0x541A590 704 705#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_53 0x541A594 706 707#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_54 0x541A598 708 709#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_55 0x541A59C 710 711#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_56 0x541A5A0 712 713#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_57 0x541A5A4 714 715#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_58 0x541A5A8 716 717#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_59 0x541A5AC 718 719#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_60 0x541A5B0 720 721#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_61 0x541A5B4 722 723#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_62 0x541A5B8 724 725#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_63 0x541A5BC 726 727#define mmNIC0_QM0_ARB_MST_CRED_INC 0x541A5E0 728 729#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_0 0x541A5E4 730 731#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_1 0x541A5E8 732 733#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_2 0x541A5EC 734 735#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_3 0x541A5F0 736 737#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_4 0x541A5F4 738 739#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_5 0x541A5F8 740 741#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_6 0x541A5FC 742 743#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_7 0x541A600 744 745#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_8 0x541A604 746 747#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_9 0x541A608 748 749#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_10 0x541A60C 750 751#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_11 0x541A610 752 753#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_12 0x541A614 754 755#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_13 0x541A618 756 757#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_14 0x541A61C 758 759#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_15 0x541A620 760 761#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_16 0x541A624 762 763#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_17 0x541A628 764 765#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_18 0x541A62C 766 767#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_19 0x541A630 768 769#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_20 0x541A634 770 771#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_21 0x541A638 772 773#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_22 0x541A63C 774 775#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_23 0x541A640 776 777#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_24 0x541A644 778 779#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_25 0x541A648 780 781#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_26 0x541A64C 782 783#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_27 0x541A650 784 785#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_28 0x541A654 786 787#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_29 0x541A658 788 789#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_30 0x541A65C 790 791#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_31 0x541A660 792 793#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_32 0x541A664 794 795#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_33 0x541A668 796 797#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_34 0x541A66C 798 799#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_35 0x541A670 800 801#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_36 0x541A674 802 803#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_37 0x541A678 804 805#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_38 0x541A67C 806 807#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_39 0x541A680 808 809#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_40 0x541A684 810 811#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_41 0x541A688 812 813#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_42 0x541A68C 814 815#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_43 0x541A690 816 817#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_44 0x541A694 818 819#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_45 0x541A698 820 821#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_46 0x541A69C 822 823#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_47 0x541A6A0 824 825#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_48 0x541A6A4 826 827#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_49 0x541A6A8 828 829#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_50 0x541A6AC 830 831#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_51 0x541A6B0 832 833#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_52 0x541A6B4 834 835#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_53 0x541A6B8 836 837#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_54 0x541A6BC 838 839#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_55 0x541A6C0 840 841#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_56 0x541A6C4 842 843#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_57 0x541A6C8 844 845#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_58 0x541A6CC 846 847#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_59 0x541A6D0 848 849#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_60 0x541A6D4 850 851#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_61 0x541A6D8 852 853#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_62 0x541A6DC 854 855#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_63 0x541A6E0 856 857#define mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0x541A704 858 859#define mmNIC0_QM0_ARB_MST_SLAVE_EN 0x541A708 860 861#define mmNIC0_QM0_ARB_MST_SLAVE_EN_1 0x541A70C 862 863#define mmNIC0_QM0_ARB_SLV_CHOICE_WDT 0x541A710 864 865#define mmNIC0_QM0_ARB_SLV_ID 0x541A714 866 867#define mmNIC0_QM0_ARB_MST_QUIET_PER 0x541A718 868 869#define mmNIC0_QM0_ARB_MSG_MAX_INFLIGHT 0x541A744 870 871#define mmNIC0_QM0_ARB_BASE_LO 0x541A754 872 873#define mmNIC0_QM0_ARB_BASE_HI 0x541A758 874 875#define mmNIC0_QM0_ARB_STATE_STS 0x541A780 876 877#define mmNIC0_QM0_ARB_CHOICE_FULLNESS_STS 0x541A784 878 879#define mmNIC0_QM0_ARB_MSG_STS 0x541A788 880 881#define mmNIC0_QM0_ARB_SLV_CHOICE_Q_HEAD 0x541A78C 882 883#define mmNIC0_QM0_ARB_ERR_CAUSE 0x541A79C 884 885#define mmNIC0_QM0_ARB_ERR_MSG_EN 0x541A7A0 886 887#define mmNIC0_QM0_ARB_ERR_STS_DRP 0x541A7A8 888 889#define mmNIC0_QM0_ARB_MST_CRED_STS 0x541A7B0 890 891#define mmNIC0_QM0_ARB_MST_CRED_STS_1 0x541A7B4 892 893#define mmNIC0_QM0_CSMR_STRICT_PRIO_CFG 0x541A7FC 894 895#define mmNIC0_QM0_ARC_CQ_CFG0 0x541A800 896 897#define mmNIC0_QM0_ARC_CQ_CFG1 0x541A804 898 899#define mmNIC0_QM0_ARC_CQ_PTR_LO 0x541A808 900 901#define mmNIC0_QM0_ARC_CQ_PTR_HI 0x541A80C 902 903#define mmNIC0_QM0_ARC_CQ_TSIZE 0x541A810 904 905#define mmNIC0_QM0_ARC_CQ_CTL 0x541A814 906 907#define mmNIC0_QM0_ARC_CQ_IFIFO_STS 0x541A81C 908 909#define mmNIC0_QM0_ARC_CQ_STS0 0x541A820 910 911#define mmNIC0_QM0_ARC_CQ_STS1 0x541A824 912 913#define mmNIC0_QM0_ARC_CQ_TSIZE_STS 0x541A828 914 915#define mmNIC0_QM0_ARC_CQ_PTR_LO_STS 0x541A82C 916 917#define mmNIC0_QM0_ARC_CQ_PTR_HI_STS 0x541A830 918 919#define mmNIC0_QM0_CP_WR_ARC_ADDR_HI 0x541A834 920 921#define mmNIC0_QM0_CP_WR_ARC_ADDR_LO 0x541A838 922 923#define mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_HI 0x541A83C 924 925#define mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_LO 0x541A840 926 927#define mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_HI 0x541A844 928 929#define mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_LO 0x541A848 930 931#define mmNIC0_QM0_CQ_IFIFO_MSG_BASE_HI 0x541A84C 932 933#define mmNIC0_QM0_CQ_IFIFO_MSG_BASE_LO 0x541A850 934 935#define mmNIC0_QM0_CQ_CTL_MSG_BASE_HI 0x541A854 936 937#define mmNIC0_QM0_CQ_CTL_MSG_BASE_LO 0x541A858 938 939#define mmNIC0_QM0_ADDR_OVRD 0x541A85C 940 941#define mmNIC0_QM0_CQ_IFIFO_CI_0 0x541A860 942 943#define mmNIC0_QM0_CQ_IFIFO_CI_1 0x541A864 944 945#define mmNIC0_QM0_CQ_IFIFO_CI_2 0x541A868 946 947#define mmNIC0_QM0_CQ_IFIFO_CI_3 0x541A86C 948 949#define mmNIC0_QM0_CQ_IFIFO_CI_4 0x541A870 950 951#define mmNIC0_QM0_ARC_CQ_IFIFO_CI 0x541A874 952 953#define mmNIC0_QM0_CQ_CTL_CI_0 0x541A878 954 955#define mmNIC0_QM0_CQ_CTL_CI_1 0x541A87C 956 957#define mmNIC0_QM0_CQ_CTL_CI_2 0x541A880 958 959#define mmNIC0_QM0_CQ_CTL_CI_3 0x541A884 960 961#define mmNIC0_QM0_CQ_CTL_CI_4 0x541A888 962 963#define mmNIC0_QM0_ARC_CQ_CTL_CI 0x541A88C 964 965#define mmNIC0_QM0_CP_CFG 0x541A890 966 967#define mmNIC0_QM0_CP_EXT_SWITCH 0x541A894 968 969#define mmNIC0_QM0_CP_SWITCH_WD_SET 0x541A898 970 971#define mmNIC0_QM0_CP_SWITCH_WD 0x541A89C 972 973#define mmNIC0_QM0_ARC_LB_ADDR_BASE_LO 0x541A8A4 974 975#define mmNIC0_QM0_ARC_LB_ADDR_BASE_HI 0x541A8A8 976 977#define mmNIC0_QM0_ENGINE_BASE_ADDR_HI 0x541A8AC 978 979#define mmNIC0_QM0_ENGINE_BASE_ADDR_LO 0x541A8B0 980 981#define mmNIC0_QM0_ENGINE_ADDR_RANGE_SIZE 0x541A8B4 982 983#define mmNIC0_QM0_QM_ARC_AUX_BASE_ADDR_HI 0x541A8B8 984 985#define mmNIC0_QM0_QM_ARC_AUX_BASE_ADDR_LO 0x541A8BC 986 987#define mmNIC0_QM0_QM_BASE_ADDR_HI 0x541A8C0 988 989#define mmNIC0_QM0_QM_BASE_ADDR_LO 0x541A8C4 990 991#define mmNIC0_QM0_ARC_PQC_SECURE_PUSH_IND 0x541A8C8 992 993#define mmNIC0_QM0_PQC_STS_0_0 0x541A8D0 994 995#define mmNIC0_QM0_PQC_STS_0_1 0x541A8D4 996 997#define mmNIC0_QM0_PQC_STS_0_2 0x541A8D8 998 999#define mmNIC0_QM0_PQC_STS_0_3 0x541A8DC 1000 1001#define mmNIC0_QM0_PQC_STS_1_0 0x541A8E0 1002 1003#define mmNIC0_QM0_PQC_STS_1_1 0x541A8E4 1004 1005#define mmNIC0_QM0_PQC_STS_1_2 0x541A8E8 1006 1007#define mmNIC0_QM0_PQC_STS_1_3 0x541A8EC 1008 1009#define mmNIC0_QM0_SEI_STATUS 0x541A8F0 1010 1011#define mmNIC0_QM0_SEI_MASK 0x541A8F4 1012 1013#define mmNIC0_QM0_GLBL_ERR_ADDR_LO 0x541AD00 1014 1015#define mmNIC0_QM0_GLBL_ERR_ADDR_HI 0x541AD04 1016 1017#define mmNIC0_QM0_GLBL_ERR_WDATA 0x541AD08 1018 1019#define mmNIC0_QM0_L2H_MASK_LO 0x541AD14 1020 1021#define mmNIC0_QM0_L2H_MASK_HI 0x541AD18 1022 1023#define mmNIC0_QM0_L2H_CMPR_LO 0x541AD1C 1024 1025#define mmNIC0_QM0_L2H_CMPR_HI 0x541AD20 1026 1027#define mmNIC0_QM0_LOCAL_RANGE_BASE 0x541AD24 1028 1029#define mmNIC0_QM0_LOCAL_RANGE_SIZE 0x541AD28 1030 1031#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_1 0x541AD30 1032 1033#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_0 0x541AD34 1034 1035#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_1 0x541AD38 1036 1037#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_0 0x541AD3C 1038 1039#define mmNIC0_QM0_IND_GW_APB_CFG 0x541AD40 1040 1041#define mmNIC0_QM0_IND_GW_APB_WDATA 0x541AD44 1042 1043#define mmNIC0_QM0_IND_GW_APB_RDATA 0x541AD48 1044 1045#define mmNIC0_QM0_IND_GW_APB_STATUS 0x541AD4C 1046 1047#define mmNIC0_QM0_PERF_CNT_FREE_LO 0x541AD60 1048 1049#define mmNIC0_QM0_PERF_CNT_FREE_HI 0x541AD64 1050 1051#define mmNIC0_QM0_PERF_CNT_IDLE_LO 0x541AD68 1052 1053#define mmNIC0_QM0_PERF_CNT_IDLE_HI 0x541AD6C 1054 1055#define mmNIC0_QM0_PERF_CNT_CFG 0x541AD70 1056 1057#endif /* ASIC_REG_NIC0_QM0_REGS_H_ */
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