File Index
Files and directories
Sign in
FILE

gaudi2_regs.h

File preview with syntax highlighting.

linux-6.19.14/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h C 
  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2020-2023 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8#ifndef ASIC_REG_GAUDI2_REGS_H_
  9#define ASIC_REG_GAUDI2_REGS_H_
 10
 11#include "gaudi2_blocks_linux_driver.h"
 12#include "psoc_reset_conf_regs.h"
 13#include "psoc_global_conf_regs.h"
 14#include "cpu_if_regs.h"
 15#include "pcie_aux_regs.h"
 16#include "pcie_dbi_regs.h"
 17#include "pcie_wrap_regs.h"
 18#include "pmmu_hbw_stlb_regs.h"
 19#include "psoc_timestamp_regs.h"
 20#include "psoc_etr_regs.h"
 21#include "xbar_edge_0_regs.h"
 22#include "xbar_mid_0_regs.h"
 23#include "arc_farm_kdma_regs.h"
 24#include "arc_farm_kdma_ctx_regs.h"
 25#include "arc_farm_kdma_kdma_cgm_regs.h"
 26#include "arc_farm_arc0_aux_regs.h"
 27#include "arc_farm_arc0_acp_eng_regs.h"
 28#include "arc_farm_kdma_ctx_axuser_regs.h"
 29#include "arc_farm_arc0_dup_eng_axuser_regs.h"
 30#include "arc_farm_arc0_dup_eng_regs.h"
 31#include "dcore0_sync_mngr_objs_regs.h"
 32#include "dcore0_sync_mngr_glbl_regs.h"
 33#include "dcore0_sync_mngr_mstr_if_axuser_regs.h"
 34#include "dcore1_sync_mngr_glbl_regs.h"
 35#include "pdma0_qm_arc_aux_regs.h"
 36#include "pdma0_core_ctx_regs.h"
 37#include "pdma0_core_regs.h"
 38#include "pdma0_qm_axuser_secured_regs.h"
 39#include "pdma0_qm_regs.h"
 40#include "pdma0_qm_cgm_regs.h"
 41#include "pdma0_core_ctx_axuser_regs.h"
 42#include "pdma1_core_ctx_axuser_regs.h"
 43#include "pdma0_qm_axuser_nonsecured_regs.h"
 44#include "pdma1_qm_axuser_nonsecured_regs.h"
 45#include "dcore0_tpc0_qm_regs.h"
 46#include "dcore0_tpc0_qm_cgm_regs.h"
 47#include "dcore0_tpc0_qm_axuser_nonsecured_regs.h"
 48#include "dcore0_tpc0_qm_arc_aux_regs.h"
 49#include "dcore0_tpc0_cfg_regs.h"
 50#include "dcore0_tpc0_cfg_qm_regs.h"
 51#include "dcore0_tpc0_cfg_axuser_regs.h"
 52#include "dcore0_tpc0_cfg_qm_sync_object_regs.h"
 53#include "dcore0_tpc0_cfg_kernel_regs.h"
 54#include "dcore0_tpc0_cfg_kernel_tensor_0_regs.h"
 55#include "dcore0_tpc0_cfg_qm_tensor_0_regs.h"
 56#include "dcore0_tpc0_cfg_special_regs.h"
 57#include "dcore0_tpc0_eml_funnel_regs.h"
 58#include "dcore0_tpc0_eml_etf_regs.h"
 59#include "dcore0_tpc0_eml_stm_regs.h"
 60#include "dcore0_tpc0_eml_busmon_0_regs.h"
 61#include "dcore0_tpc0_eml_spmu_regs.h"
 62#include "pmmu_pif_regs.h"
 63#include "dcore0_edma0_qm_cgm_regs.h"
 64#include "dcore0_edma0_core_regs.h"
 65#include "dcore0_edma0_qm_regs.h"
 66#include "dcore0_edma0_qm_arc_aux_regs.h"
 67#include "dcore0_edma0_core_ctx_regs.h"
 68#include "dcore0_edma0_core_ctx_axuser_regs.h"
 69#include "dcore0_edma0_qm_axuser_nonsecured_regs.h"
 70#include "dcore0_edma1_core_ctx_axuser_regs.h"
 71#include "dcore0_edma1_qm_axuser_nonsecured_regs.h"
 72#include "dcore0_hmmu0_stlb_regs.h"
 73#include "dcore0_hmmu0_mmu_regs.h"
 74#include "rot0_qm_regs.h"
 75#include "rot0_qm_cgm_regs.h"
 76#include "rot0_qm_arc_aux_regs.h"
 77#include "rot0_regs.h"
 78#include "rot0_desc_regs.h"
 79#include "rot0_qm_axuser_nonsecured_regs.h"
 80#include "dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h"
 81#include "dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h"
 82#include "dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h"
 83#include "dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h"
 84#include "dcore0_rtr0_ctrl_regs.h"
 85#include "dcore0_dec0_cmd_regs.h"
 86#include "dcore0_vdec0_brdg_ctrl_regs.h"
 87#include "dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h"
 88#include "dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h"
 89#include "dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h"
 90#include "dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h"
 91#include "dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h"
 92#include "dcore0_vdec0_ctrl_special_regs.h"
 93#include "pcie_vdec0_brdg_ctrl_axuser_dec_regs.h"
 94#include "pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h"
 95#include "pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h"
 96#include "pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h"
 97#include "pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h"
 98#include "pcie_dec0_cmd_regs.h"
 99#include "pcie_vdec0_brdg_ctrl_regs.h"
100#include "pcie_vdec0_ctrl_special_regs.h"
101#include "dcore0_mme_qm_regs.h"
102#include "dcore0_mme_qm_arc_aux_regs.h"
103#include "dcore0_mme_qm_axuser_secured_regs.h"
104#include "dcore0_mme_qm_cgm_regs.h"
105#include "dcore0_mme_qm_arc_acp_eng_regs.h"
106#include "dcore0_mme_qm_axuser_nonsecured_regs.h"
107#include "dcore0_mme_qm_arc_dup_eng_regs.h"
108#include "dcore0_mme_qm_arc_dup_eng_axuser_regs.h"
109#include "dcore0_mme_sbte0_mstr_if_axuser_regs.h"
110#include "dcore0_mme_wb0_mstr_if_axuser_regs.h"
111#include "dcore0_mme_acc_regs.h"
112#include "dcore0_mme_ctrl_lo_regs.h"
113#include "dcore1_mme_ctrl_lo_regs.h"
114#include "dcore3_mme_ctrl_lo_regs.h"
115#include "dcore0_mme_ctrl_lo_mme_axuser_regs.h"
116#include "dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h"
117#include "dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h"
118#include "dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h"
119#include "dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h"
120#include "dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h"
121#include "dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h"
122#include "dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h"
123#include "dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h"
124#include "dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h"
125#include "dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h"
126#include "dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h"
127#include "dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h"
128#include "dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h"
129#include "dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h"
130#include "dcore0_mme_ctrl_lo_arch_base_addr_regs.h"
131#include "dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h"
132#include "dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h"
133#include "dcore0_mme_ctrl_lo_arch_tensor_a_regs.h"
134#include "dcore0_mme_ctrl_lo_arch_tensor_b_regs.h"
135#include "dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h"
136#include "pcie_wrap_special_regs.h"
137
138#include "pdma0_qm_masks.h"
139#include "pdma0_core_masks.h"
140#include "pdma0_core_special_masks.h"
141#include "psoc_global_conf_masks.h"
142#include "psoc_reset_conf_masks.h"
143#include "arc_farm_kdma_masks.h"
144#include "arc_farm_kdma_ctx_masks.h"
145#include "arc_farm_arc0_aux_masks.h"
146#include "arc_farm_kdma_ctx_axuser_masks.h"
147#include "dcore0_sync_mngr_objs_masks.h"
148#include "dcore0_sync_mngr_glbl_masks.h"
149#include "dcore0_sync_mngr_mstr_if_axuser_masks.h"
150#include "dcore0_tpc0_cfg_masks.h"
151#include "dcore0_mme_ctrl_lo_masks.h"
152#include "dcore0_mme_sbte0_masks.h"
153#include "dcore0_edma0_qm_masks.h"
154#include "dcore0_edma0_core_masks.h"
155#include "dcore0_hmmu0_stlb_masks.h"
156#include "dcore0_hmmu0_mmu_masks.h"
157#include "dcore0_dec0_cmd_masks.h"
158#include "dcore0_vdec0_brdg_ctrl_masks.h"
159#include "pcie_dec0_cmd_masks.h"
160#include "pcie_vdec0_brdg_ctrl_masks.h"
161#include "rot0_masks.h"
162#include "pmmu_hbw_stlb_masks.h"
163#include "psoc_etr_masks.h"
164
165#define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR	0x4800040
166
167#define mmDCORE0_TPC0_EML_CFG_DBG_CNT		0x40000
168
169#define SM_OBJS_PROT_BITS_OFFS			0x14000
170
171#define DCORE_OFFSET			(mmDCORE1_TPC0_QM_BASE - mmDCORE0_TPC0_QM_BASE)
172#define DCORE_EDMA_OFFSET		(mmDCORE0_EDMA1_QM_BASE - mmDCORE0_EDMA0_QM_BASE)
173#define DCORE_TPC_OFFSET		(mmDCORE0_TPC1_QM_BASE - mmDCORE0_TPC0_QM_BASE)
174#define DCORE_DEC_OFFSET		(mmDCORE0_DEC1_VSI_BASE - mmDCORE0_DEC0_VSI_BASE)
175#define DCORE_HMMU_OFFSET		(mmDCORE0_HMMU1_MMU_BASE - mmDCORE0_HMMU0_MMU_BASE)
176#define NIC_QM_OFFSET			(mmNIC0_QM1_BASE - mmNIC0_QM0_BASE)
177#define PDMA_OFFSET			(mmPDMA1_QM_BASE - mmPDMA0_QM_BASE)
178#define ROT_OFFSET			(mmROT1_BASE - mmROT0_BASE)
179
180#define TPC_CFG_BASE_ADDRESS_HIGH_OFFSET \
181			(mmDCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH - mmDCORE0_TPC0_CFG_BASE)
182
183#define TPC_CFG_SM_BASE_ADDRESS_HIGH_OFFSET \
184			(mmDCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH - mmDCORE0_TPC0_CFG_BASE)
185
186#define TPC_CFG_STALL_OFFSET		(mmDCORE0_TPC0_CFG_TPC_STALL - mmDCORE0_TPC0_CFG_BASE)
187#define TPC_CFG_STALL_ON_ERR_OFFSET	(mmDCORE0_TPC0_CFG_STALL_ON_ERR - mmDCORE0_TPC0_CFG_BASE)
188#define TPC_CFG_TPC_INTR_MASK_OFFSET	(mmDCORE0_TPC0_CFG_TPC_INTR_MASK - mmDCORE0_TPC0_CFG_BASE)
189#define TPC_CFG_MSS_CONFIG_OFFSET	(mmDCORE0_TPC0_CFG_MSS_CONFIG - mmDCORE0_TPC0_CFG_BASE)
190#define TPC_EML_CFG_DBG_CNT_OFFSET	(mmDCORE0_TPC0_EML_CFG_DBG_CNT - mmDCORE0_TPC0_EML_CFG_BASE)
191
192#define EDMA_CORE_CFG_STALL_OFFSET	(mmDCORE0_EDMA0_CORE_CFG_1 - mmDCORE0_EDMA0_CORE_BASE)
193#define MME_CTRL_LO_QM_STALL_OFFSET	(mmDCORE0_MME_CTRL_LO_QM_STALL - mmDCORE0_MME_CTRL_LO_BASE)
194#define MME_ACC_INTR_MASK_OFFSET	(mmDCORE0_MME_ACC_INTR_MASK - mmDCORE0_MME_ACC_BASE)
195#define MME_ACC_WR_AXI_AGG_COUT0_OFFSET	(mmDCORE0_MME_ACC_WR_AXI_AGG_COUT0 - mmDCORE0_MME_ACC_BASE)
196#define MME_ACC_WR_AXI_AGG_COUT1_OFFSET	(mmDCORE0_MME_ACC_WR_AXI_AGG_COUT1 - mmDCORE0_MME_ACC_BASE)
197#define MME_ACC_AP_LFSR_POLY_OFFSET	(mmDCORE0_MME_ACC_AP_LFSR_POLY - mmDCORE0_MME_ACC_BASE)
198#define MME_ACC_AP_LFSR_SEED_SEL_OFFSET	(mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL - mmDCORE0_MME_ACC_BASE)
199#define MME_ACC_AP_LFSR_SEED_WDATA_OFFSET \
200	(mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA - mmDCORE0_MME_ACC_BASE)
201
202#define DMA_CORE_CFG_0_OFFSET		(mmARC_FARM_KDMA_CFG_0 - mmARC_FARM_KDMA_BASE)
203#define DMA_CORE_CFG_1_OFFSET		(mmARC_FARM_KDMA_CFG_1 - mmARC_FARM_KDMA_BASE)
204#define DMA_CORE_PROT_OFFSET		(mmARC_FARM_KDMA_PROT - mmARC_FARM_KDMA_BASE)
205#define DMA_CORE_ERRMSG_ADDR_LO_OFFSET	(mmARC_FARM_KDMA_ERRMSG_ADDR_LO - mmARC_FARM_KDMA_BASE)
206#define DMA_CORE_ERRMSG_ADDR_HI_OFFSET	(mmARC_FARM_KDMA_ERRMSG_ADDR_HI - mmARC_FARM_KDMA_BASE)
207#define DMA_CORE_ERRMSG_WDATA_OFFSET	(mmARC_FARM_KDMA_ERRMSG_WDATA - mmARC_FARM_KDMA_BASE)
208
209#define QM_PQ_BASE_LO_0_OFFSET		(mmPDMA0_QM_PQ_BASE_LO_0 - mmPDMA0_QM_BASE)
210#define QM_PQ_BASE_HI_0_OFFSET		(mmPDMA0_QM_PQ_BASE_HI_0 - mmPDMA0_QM_BASE)
211#define QM_PQ_SIZE_0_OFFSET		(mmPDMA0_QM_PQ_SIZE_0 - mmPDMA0_QM_BASE)
212#define QM_PQ_PI_0_OFFSET		(mmPDMA0_QM_PQ_PI_0 - mmPDMA0_QM_BASE)
213#define QM_PQ_CI_0_OFFSET		(mmPDMA0_QM_PQ_CI_0 - mmPDMA0_QM_BASE)
214#define QM_CP_FENCE0_CNT_0_OFFSET	(mmPDMA0_QM_CP_FENCE0_CNT_0 - mmPDMA0_QM_BASE)
215
216#define QM_CP_MSG_BASE0_ADDR_LO_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 - mmPDMA0_QM_BASE)
217#define QM_CP_MSG_BASE0_ADDR_HI_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 - mmPDMA0_QM_BASE)
218#define QM_CP_MSG_BASE1_ADDR_LO_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 - mmPDMA0_QM_BASE)
219#define QM_CP_MSG_BASE1_ADDR_HI_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 - mmPDMA0_QM_BASE)
220
221#define QM_CP_CFG_OFFSET		(mmPDMA0_QM_CP_CFG - mmPDMA0_QM_BASE)
222#define QM_PQC_HBW_BASE_LO_0_OFFSET	(mmPDMA0_QM_PQC_HBW_BASE_LO_0 - mmPDMA0_QM_BASE)
223#define QM_PQC_HBW_BASE_HI_0_OFFSET	(mmPDMA0_QM_PQC_HBW_BASE_HI_0 - mmPDMA0_QM_BASE)
224#define QM_PQC_SIZE_0_OFFSET		(mmPDMA0_QM_PQC_SIZE_0 - mmPDMA0_QM_BASE)
225#define QM_PQC_PI_0_OFFSET		(mmPDMA0_QM_PQC_PI_0 - mmPDMA0_QM_BASE)
226#define QM_PQC_LBW_WDATA_0_OFFSET	(mmPDMA0_QM_PQC_LBW_WDATA_0 - mmPDMA0_QM_BASE)
227#define QM_PQC_LBW_BASE_LO_0_OFFSET	(mmPDMA0_QM_PQC_LBW_BASE_LO_0 - mmPDMA0_QM_BASE)
228#define QM_PQC_LBW_BASE_HI_0_OFFSET	(mmPDMA0_QM_PQC_LBW_BASE_HI_0 - mmPDMA0_QM_BASE)
229#define QM_GLBL_ERR_ADDR_LO_OFFSET	(mmPDMA0_QM_GLBL_ERR_ADDR_LO - mmPDMA0_QM_BASE)
230#define QM_PQC_CFG_OFFSET		(mmPDMA0_QM_PQC_CFG - mmPDMA0_QM_BASE)
231#define QM_ARB_CFG_0_OFFSET		(mmPDMA0_QM_ARB_CFG_0 - mmPDMA0_QM_BASE)
232#define QM_GLBL_CFG0_OFFSET		(mmPDMA0_QM_GLBL_CFG0 -	mmPDMA0_QM_BASE)
233#define QM_GLBL_CFG1_OFFSET		(mmPDMA0_QM_GLBL_CFG1 - mmPDMA0_QM_BASE)
234#define QM_GLBL_CFG2_OFFSET		(mmPDMA0_QM_GLBL_CFG2 - mmPDMA0_QM_BASE)
235#define QM_GLBL_PROT_OFFSET		(mmPDMA0_QM_GLBL_PROT -	mmPDMA0_QM_BASE)
236#define QM_GLBL_ERR_CFG_OFFSET		(mmPDMA0_QM_GLBL_ERR_CFG - mmPDMA0_QM_BASE)
237#define QM_GLBL_ERR_CFG1_OFFSET		(mmPDMA0_QM_GLBL_ERR_CFG1 - mmPDMA0_QM_BASE)
238#define QM_GLBL_ERR_ADDR_HI_OFFSET	(mmPDMA0_QM_GLBL_ERR_ADDR_HI - mmPDMA0_QM_BASE)
239#define QM_GLBL_ERR_WDATA_OFFSET	(mmPDMA0_QM_GLBL_ERR_WDATA - mmPDMA0_QM_BASE)
240#define QM_ARB_ERR_MSG_EN_OFFSET	(mmPDMA0_QM_ARB_ERR_MSG_EN - mmPDMA0_QM_BASE)
241#define QM_ARB_SLV_CHOISE_WDT_OFFSET	(mmPDMA0_QM_ARB_SLV_CHOICE_WDT - mmPDMA0_QM_BASE)
242#define QM_FENCE2_OFFSET		(mmPDMA0_QM_CP_FENCE2_RDATA_0 - mmPDMA0_QM_BASE)
243#define QM_SEI_STATUS_OFFSET		(mmPDMA0_QM_SEI_STATUS - mmPDMA0_QM_BASE)
244
245#define QM_CQ_TSIZE_STS_4_OFFSET	(mmPDMA0_QM_CQ_TSIZE_STS_4 - mmPDMA0_QM_BASE)
246#define QM_CQ_PTR_LO_STS_4_OFFSET	(mmPDMA0_QM_CQ_PTR_LO_STS_4 - mmPDMA0_QM_BASE)
247#define QM_CQ_PTR_HI_STS_4_OFFSET	(mmPDMA0_QM_CQ_PTR_HI_STS_4 - mmPDMA0_QM_BASE)
248
249#define QM_ARC_CQ_TSIZE_STS_OFFSET	(mmPDMA0_QM_ARC_CQ_TSIZE_STS - mmPDMA0_QM_BASE)
250#define QM_ARC_CQ_PTR_LO_STS_OFFSET	(mmPDMA0_QM_ARC_CQ_PTR_LO_STS - mmPDMA0_QM_BASE)
251#define QM_ARC_CQ_PTR_HI_STS_OFFSET	(mmPDMA0_QM_ARC_CQ_PTR_HI_STS - mmPDMA0_QM_BASE)
252
253#define QM_CP_STS_4_OFFSET		(mmPDMA0_QM_CP_STS_4 - mmPDMA0_QM_BASE)
254#define QM_CP_CURRENT_INST_LO_4_OFFSET	(mmPDMA0_QM_CP_CURRENT_INST_LO_4 - mmPDMA0_QM_BASE)
255#define QM_CP_CURRENT_INST_HI_4_OFFSET	(mmPDMA0_QM_CP_CURRENT_INST_HI_4 - mmPDMA0_QM_BASE)
256
257#define SFT_OFFSET		(mmSFT1_HBW_RTR_IF0_RTR_H3_BASE - mmSFT0_HBW_RTR_IF0_RTR_H3_BASE)
258#define SFT_IF_RTR_OFFSET	(mmSFT0_HBW_RTR_IF1_RTR_H3_BASE - mmSFT0_HBW_RTR_IF0_RTR_H3_BASE)
259
260#define ARC_HALT_REQ_OFFSET	(mmARC_FARM_ARC0_AUX_RUN_HALT_REQ - mmARC_FARM_ARC0_AUX_BASE)
261#define ARC_HALT_ACK_OFFSET	(mmARC_FARM_ARC0_AUX_RUN_HALT_ACK - mmARC_FARM_ARC0_AUX_BASE)
262
263#define ARC_REGION_CFG_OFFSET(region) \
264	(mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_0 + (region * 4) - mmARC_FARM_ARC0_AUX_BASE)
265
266#define ARC_DCCM_UPPER_EN_OFFSET \
267	(mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN - mmARC_FARM_ARC0_AUX_BASE)
268
269#define PCIE_VDEC_OFFSET	\
270	(mmPCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE - mmPCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE)
271
272#define DCORE_MME_SBTE_OFFSET	\
273	(mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE)
274
275#define DCORE_MME_WB_OFFSET	\
276	(mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE)
277
278#define DCORE_RTR_OFFSET	\
279	(mmDCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
280
281#define DCORE_VDEC_OFFSET	\
282	(mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE)
283
284#define MMU_OFFSET(REG)			(REG - mmDCORE0_HMMU0_MMU_BASE)
285#define MMU_BYPASS_OFFSET		MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_BYPASS)
286#define MMU_SPI_SEI_MASK_OFFSET		MMU_OFFSET(mmDCORE0_HMMU0_MMU_SPI_SEI_MASK)
287#define MMU_SPI_SEI_CAUSE_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_SPI_SEI_CAUSE)
288#define MMU_ENABLE_OFFSET		MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_ENABLE)
289#define MMU_DDR_RANGE_REG_ENABLE	MMU_OFFSET(mmDCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE)
290#define MMU_RR_SEC_MIN_63_32_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_0)
291#define MMU_RR_SEC_MIN_31_0_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_0)
292#define MMU_RR_SEC_MAX_63_32_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_0)
293#define MMU_RR_SEC_MAX_31_0_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_0)
294#define MMU_RR_PRIV_MIN_63_32_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_0)
295#define MMU_RR_PRIV_MIN_31_0_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_0)
296#define MMU_RR_PRIV_MAX_63_32_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_0)
297#define MMU_RR_PRIV_MAX_31_0_0_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_0)
298#define MMU_INTERRUPT_CLR_OFFSET	MMU_OFFSET(mmDCORE0_HMMU0_MMU_INTERRUPT_CLR)
299
300#define STLB_OFFSET(REG)		(REG - mmDCORE0_HMMU0_STLB_BASE)
301#define STLB_BUSY_OFFSET		STLB_OFFSET(mmDCORE0_HMMU0_STLB_BUSY)
302#define STLB_ASID_OFFSET		STLB_OFFSET(mmDCORE0_HMMU0_STLB_ASID)
303#define STLB_HOP0_PA43_12_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP0_PA43_12)
304#define STLB_HOP0_PA63_44_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP0_PA63_44)
305#define STLB_HOP_CONFIGURATION_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP_CONFIGURATION)
306#define STLB_INV_ALL_START_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_INV_ALL_START)
307#define STLB_SRAM_INIT_OFFSET		STLB_OFFSET(mmDCORE0_HMMU0_STLB_SRAM_INIT)
308#define STLB_SET_THRESHOLD_HOP3_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3)
309#define STLB_SET_THRESHOLD_HOP2_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2)
310#define STLB_SET_THRESHOLD_HOP1_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1)
311#define STLB_SET_THRESHOLD_HOP0_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0)
312#define STLB_RANGE_INV_START_LSB_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_START_LSB)
313#define STLB_RANGE_INV_START_MSB_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_START_MSB)
314#define STLB_RANGE_INV_END_LSB_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_END_LSB)
315#define STLB_RANGE_INV_END_MSB_OFFSET	STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_END_MSB)
316
317#define STLB_LL_LOOKUP_MASK_63_32_OFFSET	\
318			STLB_OFFSET(mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32)
319
320#define STLB_RANGE_CACHE_INVALIDATION_OFFSET	\
321			STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION)
322
323/* RTR CTR RAZWI related offsets */
324#define RTR_MSTR_IF_OFFSET	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_CTRL_BASE)
325
326#define RTR_LBW_MSTR_IF_OFFSET	\
327			(mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_CTRL_BASE)
328
329/* RAZWI captured hbw aw addr high */
330#define DEC_RAZWI_HBW_AW_ADDR_HI	\
331			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_HI_ADDR - mmDCORE0_RTR0_CTRL_BASE)
332
333/* RAZWI captured hbw aw addr low */
334#define DEC_RAZWI_HBW_AW_ADDR_LO	\
335			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_LO_ADDR - mmDCORE0_RTR0_CTRL_BASE)
336
337/* RAZWI captured hbw aw set */
338#define DEC_RAZWI_HBW_AW_SET		\
339			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET - mmDCORE0_RTR0_CTRL_BASE)
340
341/* RAZWI captured hbw ar addr high */
342#define DEC_RAZWI_HBW_AR_ADDR_HI \
343			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_HI_ADDR - mmDCORE0_RTR0_CTRL_BASE)
344
345/* RAZWI captured hbw ar addr low */
346#define DEC_RAZWI_HBW_AR_ADDR_LO	\
347			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_LO_ADDR - mmDCORE0_RTR0_CTRL_BASE)
348
349/* RAZWI captured hbw ar set */
350#define DEC_RAZWI_HBW_AR_SET		\
351			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_SET - mmDCORE0_RTR0_CTRL_BASE)
352
353/* RAZWI captured lbw aw addr */
354#define DEC_RAZWI_LBW_AW_ADDR		\
355			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_ADDR - mmDCORE0_RTR0_CTRL_BASE)
356
357/* RAZWI captured lbw aw set */
358#define DEC_RAZWI_LBW_AW_SET		\
359			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET - mmDCORE0_RTR0_CTRL_BASE)
360
361/* RAZWI captured lbw ar addr */
362#define DEC_RAZWI_LBW_AR_ADDR		\
363			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_ADDR - mmDCORE0_RTR0_CTRL_BASE)
364
365/* RAZWI captured lbw ar set */
366#define DEC_RAZWI_LBW_AR_SET		\
367			(mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_SET - mmDCORE0_RTR0_CTRL_BASE)
368
369/* RAZWI captured shared hbw aw addr high */
370#define RR_SHRD_HBW_AW_RAZWI_HI		\
371	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HI - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
372
373/* RAZWI captured shared hbw aw addr low */
374#define RR_SHRD_HBW_AW_RAZWI_LO		\
375	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_LO - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
376
377/* RAZWI captured shared hbw ar addr high */
378#define RR_SHRD_HBW_AR_RAZWI_HI		\
379	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HI - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
380
381/* RAZWI captured shared hbw ar addr low */
382#define RR_SHRD_HBW_AR_RAZWI_LO		\
383	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_LO - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
384
385/* RAZWI captured shared aw XY coordinates */
386#define RR_SHRD_HBW_AW_RAZWI_XY		\
387	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_XY - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
388
389/* RAZWI captured shared ar XY coordinates */
390#define RR_SHRD_HBW_AR_RAZWI_XY		\
391	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_XY - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
392
393/* RAZWI hbw shared occurred due to write access */
394#define RR_SHRD_HBW_AW_RAZWI_HAPPENED	\
395			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HAPPENED - \
396				mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
397
398/* RAZWI hbw shared occurred due to read access */
399#define RR_SHRD_HBW_AR_RAZWI_HAPPENED	\
400			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HAPPENED - \
401				mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
402
403/* RAZWI captured shared lbw aw addr */
404#define RR_SHRD_LBW_AW_RAZWI		\
405			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI - \
406					mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
407
408/* RAZWI captured shared lbw ar addr */
409#define RR_SHRD_LBW_AR_RAZWI		\
410			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI - \
411					mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
412
413/* RAZWI captured shared lbw aw XY coordinates */
414#define RR_SHRD_LBW_AW_RAZWI_XY		\
415			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_XY - \
416					mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
417
418/* RAZWI captured shared lbw ar XY coordinates */
419#define RR_SHRD_LBW_AR_RAZWI_XY		\
420			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_XY - \
421					mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
422
423/* RAZWI lbw shared occurred due to write access */
424#define RR_SHRD_LBW_AW_RAZWI_HAPPENED	\
425			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_HAPPENED - \
426					mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
427
428/* RAZWI lbw shared occurred due to read access */
429#define RR_SHRD_LBW_AR_RAZWI_HAPPENED	\
430			(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_HAPPENED - \
431				mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
432
433#define BRDG_CTRL_BLOCK_OFFSET (mmDCORE0_VDEC0_BRDG_CTRL_BASE - mmDCORE0_DEC0_CMD_BASE)
434#define SPECIAL_BLOCK_OFFSET (mmDCORE0_VDEC0_BRDG_CTRL_SPECIAL_BASE - mmDCORE0_DEC0_CMD_BASE)
435#define SFT_DCORE_OFFSET (mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE)
436#define SFT_IF_OFFSET (mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE)
437
438#define BRDG_CTRL_NRM_MSIX_LBW_AWADDR	\
439	(mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
440
441#define BRDG_CTRL_NRM_MSIX_LBW_WDATA	\
442	(mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
443
444#define BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR	\
445	(mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
446
447#define BRDG_CTRL_ABNRM_MSIX_LBW_WDATA	\
448	(mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
449
450#define RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET	\
451	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0 - \
452			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
453
454#define RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET	\
455	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0 - \
456			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
457
458#define RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET	\
459	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0 - \
460			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
461
462#define RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET	\
463	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0 - \
464			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
465
466#define RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET	\
467	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0 - \
468			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
469
470#define RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET	\
471	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0 - \
472			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
473
474#define RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET	\
475	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0 - \
476			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
477
478#define RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET	\
479	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0 - \
480			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
481
482#define RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET	\
483	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_0 - \
484			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
485
486#define RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET	\
487	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_0 - \
488			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
489
490#define RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET	\
491	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_0 - \
492			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
493
494#define RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET	\
495	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_0 - \
496			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
497
498#define RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET	\
499	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0 - \
500			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
501
502#define RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET	\
503	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0 - \
504			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
505
506#define RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET	\
507	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0 - \
508			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
509
510#define RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET	\
511	(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0 - \
512			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
513
514#define RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET	\
515		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_0 - \
516			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
517
518#define RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET	\
519		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_0 - \
520			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
521
522#define RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET	\
523		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_0 - \
524			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
525
526#define RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET	\
527		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_0 - \
528			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
529
530#define RR_LBW_SEC_RANGE_MIN_0_OFFSET	\
531		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_0 - \
532			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
533
534#define RR_LBW_SEC_RANGE_MAX_0_OFFSET	\
535		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_0 - \
536			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
537
538#define RR_LBW_PRIV_RANGE_MIN_0_OFFSET	\
539		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_0 - \
540			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
541
542#define RR_LBW_PRIV_RANGE_MAX_0_OFFSET	\
543		(mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_0 - \
544			mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
545
546#define ARC_AUX_DCCM_QUEUE_PUSH_REG_0_OFFSET	\
547		(mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_0 - mmARC_FARM_ARC0_AUX_BASE)
548
549#define MMU_STATIC_MULTI_PAGE_SIZE_OFFSET	\
550	(mmDCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE - mmDCORE0_HMMU0_MMU_BASE)
551
552#define HBM_MC_SPI_TEMP_PIN_CHG_MASK		BIT(0)
553#define HBM_MC_SPI_THR_ENG_MASK			BIT(1)
554#define HBM_MC_SPI_THR_DIS_ENG_MASK		BIT(2)
555#define HBM_MC_SPI_IEEE1500_COMP_MASK		BIT(3)
556#define HBM_MC_SPI_IEEE1500_PAUSED_MASK		BIT(4)
557
558#define ARC_FARM_OFFSET (mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE)
559
560#include "nic0_qpc0_regs.h"
561#include "nic0_qm0_regs.h"
562#include "nic0_qm_arc_aux0_regs.h"
563#include "nic0_qm0_cgm_regs.h"
564#include "nic0_umr0_0_completion_queue_ci_1_regs.h"
565#include "nic0_umr0_0_unsecure_doorbell0_regs.h"
566
567#define NIC_OFFSET		(mmNIC1_MSTR_IF_RR_SHRD_HBW_BASE - mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE)
568
569#define NIC_UMR_OFFSET \
570	(mmNIC0_UMR0_1_UNSECURE_DOORBELL0_BASE - mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE)
571
572#endif /* ASIC_REG_GAUDI2_REGS_H_ */
~/ Read-only file preview.