cpu_if_regs.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2016-2020 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8/************************************
  9 ** This is an auto-generated file **
 10 **       DO NOT EDIT BELOW        **
 11 ************************************/
 12
 13#ifndef ASIC_REG_CPU_IF_REGS_H_
 14#define ASIC_REG_CPU_IF_REGS_H_
 15
 16/*
 17 *****************************************
 18 *   CPU_IF
 19 *   (Prototype: CPU_IF)
 20 *****************************************
 21 */
 22
 23#define mmCPU_IF_ARUSER_OVR 0x4CC1104
 24
 25#define mmCPU_IF_ARUSER_OVR_EN 0x4CC1108
 26
 27#define mmCPU_IF_AWUSER_OVR 0x4CC110C
 28
 29#define mmCPU_IF_AWUSER_OVR_EN 0x4CC1110
 30
 31#define mmCPU_IF_ARUSER_MSB_OVR 0x4CC1114
 32
 33#define mmCPU_IF_AWUSER_MSB_OVR 0x4CC1120
 34
 35#define mmCPU_IF_AXCACHE_OVR 0x4CC1128
 36
 37#define mmCPU_IF_LOCK_OVR 0x4CC112C
 38
 39#define mmCPU_IF_PROT_OVR 0x4CC1130
 40
 41#define mmCPU_IF_MAX_OUTSTANDING 0x4CC1134
 42
 43#define mmCPU_IF_EARLY_BRESP_EN 0x4CC1138
 44
 45#define mmCPU_IF_FORCE_RSP_OK 0x4CC113C
 46
 47#define mmCPU_IF_CPU_SEI_INTR_STS 0x4CC1140
 48
 49#define mmCPU_IF_CPU_SEI_INTR_CLR 0x4CC1144
 50
 51#define mmCPU_IF_CPU_SEI_INTR_MASK 0x4CC1148
 52
 53#define mmCPU_IF_AXI_SPLIT_NO_WR_INFLIGHT 0x4CC114C
 54
 55#define mmCPU_IF_AXI_SPLIT_SEI_INTR_ID 0x4CC1150
 56
 57#define mmCPU_IF_TOTAL_WR_CNT 0x4CC1154
 58
 59#define mmCPU_IF_INFLIGHT_WR_CNT 0x4CC1158
 60
 61#define mmCPU_IF_TOTAL_RD_CNT 0x4CC115C
 62
 63#define mmCPU_IF_INFLIGHT_RD_CNT 0x4CC1160
 64
 65#define mmCPU_IF_SRAM_MSB_ADDR 0x4CC1164
 66
 67#define mmCPU_IF_CFG_MSB_ADDR 0x4CC1168
 68
 69#define mmCPU_IF_HBM_MSB_ADDR 0x4CC116C
 70
 71#define mmCPU_IF_PCIE_MSB_ADDR 0x4CC1170
 72
 73#define mmCPU_IF_KMD_HW_DIRTY_STATUS 0x4CC1174
 74
 75#define mmCPU_IF_MSTR_IF_E2E_FORCE_BP 0x4CC1188
 76
 77#define mmCPU_IF_MSTR_IF_E2E_GRCFL_CLR 0x4CC118C
 78
 79#define mmCPU_IF_LBW_TERMINATE_AWADDR_ERR 0x4CC11A0
 80
 81#define mmCPU_IF_LBW_TERMINATE_ARADDR_ERR 0x4CC11A4
 82
 83#define mmCPU_IF_CFG_LBW_TERMINATE_BRESP 0x4CC11A8
 84
 85#define mmCPU_IF_CFG_LBW_TERMINATE_RRESP 0x4CC11AC
 86
 87#define mmCPU_IF_PF_PQ_PI 0x4CC1200
 88
 89#define mmCPU_IF_PQ_BASE_ADDR_LOW 0x4CC1204
 90
 91#define mmCPU_IF_PQ_BASE_ADDR_HIGH 0x4CC1208
 92
 93#define mmCPU_IF_PQ_LENGTH 0x4CC120C
 94
 95#define mmCPU_IF_CQ_BASE_ADDR_LOW 0x4CC1210
 96
 97#define mmCPU_IF_CQ_BASE_ADDR_HIGH 0x4CC1214
 98
 99#define mmCPU_IF_CQ_LENGTH 0x4CC1218
100
101#define mmCPU_IF_EQ_BASE_ADDR_LOW 0x4CC1220
102
103#define mmCPU_IF_EQ_BASE_ADDR_HIGH 0x4CC1224
104
105#define mmCPU_IF_EQ_LENGTH 0x4CC1228
106
107#define mmCPU_IF_EQ_RD_OFFS 0x4CC122C
108
109#define mmCPU_IF_QUEUE_INIT 0x4CC1230
110
111#define mmCPU_IF_TPC_SERR_INTR_STS 0x4CC1300
112
113#define mmCPU_IF_TPC_SERR_INTR_CLR 0x4CC1304
114
115#define mmCPU_IF_TPC_SERR_INTR_MASK 0x4CC1308
116
117#define mmCPU_IF_TPC_DERR_INTR_STS 0x4CC1310
118
119#define mmCPU_IF_TPC_DERR_INTR_CLR 0x4CC1314
120
121#define mmCPU_IF_TPC_DERR_INTR_MASK 0x4CC1318
122
123#define mmCPU_IF_MME_SERR_INTR_STS_0 0x4CC1320
124
125#define mmCPU_IF_MME_SERR_INTR_STS_1 0x4CC1324
126
127#define mmCPU_IF_MME_SERR_INTR_STS_2 0x4CC1328
128
129#define mmCPU_IF_MME_SERR_INTR_STS_3 0x4CC132C
130
131#define mmCPU_IF_MME_SERR_INTR_CLR_0 0x4CC1330
132
133#define mmCPU_IF_MME_SERR_INTR_CLR_1 0x4CC1334
134
135#define mmCPU_IF_MME_SERR_INTR_CLR_2 0x4CC1338
136
137#define mmCPU_IF_MME_SERR_INTR_CLR_3 0x4CC133C
138
139#define mmCPU_IF_MME_SERR_INTR_MASK_0 0x4CC1340
140
141#define mmCPU_IF_MME_SERR_INTR_MASK_1 0x4CC1344
142
143#define mmCPU_IF_MME_SERR_INTR_MASK_2 0x4CC1348
144
145#define mmCPU_IF_MME_SERR_INTR_MASK_3 0x4CC134C
146
147#define mmCPU_IF_MME_DERR_INTR_STS_0 0x4CC1350
148
149#define mmCPU_IF_MME_DERR_INTR_STS_1 0x4CC1354
150
151#define mmCPU_IF_MME_DERR_INTR_STS_2 0x4CC1358
152
153#define mmCPU_IF_MME_DERR_INTR_STS_3 0x4CC135C
154
155#define mmCPU_IF_MME_DERR_INTR_CLR_0 0x4CC1360
156
157#define mmCPU_IF_MME_DERR_INTR_CLR_1 0x4CC1364
158
159#define mmCPU_IF_MME_DERR_INTR_CLR_2 0x4CC1368
160
161#define mmCPU_IF_MME_DERR_INTR_CLR_3 0x4CC136C
162
163#define mmCPU_IF_MME_DERR_INTR_MASK_0 0x4CC1370
164
165#define mmCPU_IF_MME_DERR_INTR_MASK_1 0x4CC1374
166
167#define mmCPU_IF_MME_DERR_INTR_MASK_2 0x4CC1378
168
169#define mmCPU_IF_MME_DERR_INTR_MASK_3 0x4CC137C
170
171#define mmCPU_IF_HDMA_SERR_INTR_STS 0x4CC1380
172
173#define mmCPU_IF_HDMA_SERR_INTR_CLR 0x4CC1384
174
175#define mmCPU_IF_HDMA_SERR_INTR_MASK 0x4CC1388
176
177#define mmCPU_IF_HDMA_DERR_INTR_STS 0x4CC1390
178
179#define mmCPU_IF_HDMA_DERR_INTR_CLR 0x4CC1394
180
181#define mmCPU_IF_HDMA_DERR_INTR_MASK 0x4CC1398
182
183#define mmCPU_IF_PDMA_SERR_INTR_STS 0x4CC13A0
184
185#define mmCPU_IF_PDMA_SERR_INTR_CLR 0x4CC13A4
186
187#define mmCPU_IF_PDMA_SERR_INTR_MASK 0x4CC13A8
188
189#define mmCPU_IF_PDMA_DERR_INTR_STS 0x4CC13B0
190
191#define mmCPU_IF_PDMA_DERR_INTR_CLR 0x4CC13B4
192
193#define mmCPU_IF_PDMA_DERR_INTR_MASK 0x4CC13B8
194
195#define mmCPU_IF_SRAM_SERR_INTR_STS 0x4CC13C0
196
197#define mmCPU_IF_SRAM_SERR_INTR_CLR 0x4CC13C4
198
199#define mmCPU_IF_SRAM_SERR_INTR_MASK 0x4CC13C8
200
201#define mmCPU_IF_SRAM_DERR_INTR_STS 0x4CC13D0
202
203#define mmCPU_IF_SRAM_DERR_INTR_CLR 0x4CC13D4
204
205#define mmCPU_IF_SRAM_DERR_INTR_MASK 0x4CC13D8
206
207#define mmCPU_IF_HBM_SERR_INTR_STS 0x4CC13E0
208
209#define mmCPU_IF_HBM_SERR_INTR_CLR 0x4CC13E4
210
211#define mmCPU_IF_HBM_SERR_INTR_MASK 0x4CC13E8
212
213#define mmCPU_IF_HBM_DERR_INTR_STS 0x4CC13F0
214
215#define mmCPU_IF_HBM_DERR_INTR_CLR 0x4CC13F4
216
217#define mmCPU_IF_HBM_DERR_INTR_MASK 0x4CC13F8
218
219#define mmCPU_IF_HMMU_SERR_INTR_STS 0x4CC1400
220
221#define mmCPU_IF_HMMU_SERR_INTR_CLR 0x4CC1404
222
223#define mmCPU_IF_HMMU_SERR_INTR_MASK 0x4CC1408
224
225#define mmCPU_IF_HMMU_DERR_INTR_STS 0x4CC1410
226
227#define mmCPU_IF_HMMU_DERR_INTR_CLR 0x4CC1414
228
229#define mmCPU_IF_HMMU_DERR_INTR_MASK 0x4CC1418
230
231#define mmCPU_IF_DEC_SERR_INTR_STS 0x4CC1420
232
233#define mmCPU_IF_DEC_SERR_INTR_CLR 0x4CC1424
234
235#define mmCPU_IF_DEC_SERR_INTR_MASK 0x4CC1428
236
237#define mmCPU_IF_DEC_DERR_INTR_STS 0x4CC1430
238
239#define mmCPU_IF_DEC_DERR_INTR_CLR 0x4CC1434
240
241#define mmCPU_IF_DEC_DERR_INTR_MASK 0x4CC1438
242
243#define mmCPU_IF_NIC_SERR_INTR_STS 0x4CC1440
244
245#define mmCPU_IF_NIC_SERR_INTR_CLR 0x4CC1444
246
247#define mmCPU_IF_NIC_SERR_INTR_MASK 0x4CC1448
248
249#define mmCPU_IF_NIC_DERR_INTR_STS 0x4CC1450
250
251#define mmCPU_IF_NIC_DERR_INTR_CLR 0x4CC1454
252
253#define mmCPU_IF_NIC_DERR_INTR_MASK 0x4CC1458
254
255#define mmCPU_IF_SYNC_MNGR_SERR_INTR_STS 0x4CC1460
256
257#define mmCPU_IF_SYNC_MNGR_SERR_INTR_CLR 0x4CC1464
258
259#define mmCPU_IF_SYNC_MNGR_SERR_INTR_MASK 0x4CC1468
260
261#define mmCPU_IF_SYNC_MNGR_DERR_INTR_STS 0x4CC1470
262
263#define mmCPU_IF_SYNC_MNGR_DERR_INTR_CLR 0x4CC1474
264
265#define mmCPU_IF_SYNC_MNGR_DERR_INTR_MASK 0x4CC1478
266
267#define mmCPU_IF_HIF_SERR_INTR_STS 0x4CC1480
268
269#define mmCPU_IF_HIF_SERR_INTR_CLR 0x4CC1484
270
271#define mmCPU_IF_HIF_SERR_INTR_MASK 0x4CC1488
272
273#define mmCPU_IF_HIF_DERR_INTR_STS 0x4CC1490
274
275#define mmCPU_IF_HIF_DERR_INTR_CLR 0x4CC1494
276
277#define mmCPU_IF_HIF_DERR_INTR_MASK 0x4CC1498
278
279#define mmCPU_IF_XBAR_SERR_INTR_STS 0x4CC14A0
280
281#define mmCPU_IF_XBAR_SERR_INTR_CLR 0x4CC14A4
282
283#define mmCPU_IF_XBAR_SERR_INTR_MASK 0x4CC14A8
284
285#define mmCPU_IF_XBAR_DERR_INTR_STS 0x4CC14B0
286
287#define mmCPU_IF_XBAR_DERR_INTR_CLR 0x4CC14B4
288
289#define mmCPU_IF_XBAR_DERR_INTR_MASK 0x4CC14B8
290
291#define mmCPU_IF_TPC_SEI_INTR_STS 0x4CC14C0
292
293#define mmCPU_IF_TPC_SEI_INTR_CLR 0x4CC14C4
294
295#define mmCPU_IF_TPC_SEI_INTR_MASK 0x4CC14C8
296
297#define mmCPU_IF_MME_SEI_INTR_STS_0 0x4CC14D0
298
299#define mmCPU_IF_MME_SEI_INTR_STS_1 0x4CC14D4
300
301#define mmCPU_IF_MME_SEI_INTR_STS_2 0x4CC14D8
302
303#define mmCPU_IF_MME_SEI_INTR_STS_3 0x4CC14DC
304
305#define mmCPU_IF_MME_SEI_INTR_CLR_0 0x4CC14E0
306
307#define mmCPU_IF_MME_SEI_INTR_CLR_1 0x4CC14E4
308
309#define mmCPU_IF_MME_SEI_INTR_CLR_2 0x4CC14E8
310
311#define mmCPU_IF_MME_SEI_INTR_CLR_3 0x4CC14EC
312
313#define mmCPU_IF_MME_SEI_INTR_MASK_0 0x4CC14F0
314
315#define mmCPU_IF_MME_SEI_INTR_MASK_1 0x4CC14F4
316
317#define mmCPU_IF_MME_SEI_INTR_MASK_2 0x4CC14F8
318
319#define mmCPU_IF_MME_SEI_INTR_MASK_3 0x4CC14FC
320
321#define mmCPU_IF_PLL_LSB_SEI_INTR_STS 0x4CC1500
322
323#define mmCPU_IF_PLL_LSB_SEI_INTR_CLR 0x4CC1504
324
325#define mmCPU_IF_PLL_LSB_SEI_INTR_MASK 0x4CC1508
326
327#define mmCPU_IF_PLL_MSB_SEI_INTR_STS 0x4CC1510
328
329#define mmCPU_IF_PLL_MSB_SEI_INTR_CLR 0x4CC1514
330
331#define mmCPU_IF_PLL_MSB_SEI_INTR_MASK 0x4CC1518
332
333#define mmCPU_IF_HMMU_SEI_INTR_STS 0x4CC1520
334
335#define mmCPU_IF_HMMU_SEI_INTR_CLR 0x4CC1524
336
337#define mmCPU_IF_HMMU_SEI_INTR_MASK 0x4CC1528
338
339#define mmCPU_IF_HDMA_SEI_INTR_STS 0x4CC1530
340
341#define mmCPU_IF_HDMA_SEI_INTR_CLR 0x4CC1534
342
343#define mmCPU_IF_HDMA_SEI_INTR_MASK 0x4CC1538
344
345#define mmCPU_IF_PDMA_SEI_INTR_STS 0x4CC1540
346
347#define mmCPU_IF_PDMA_SEI_INTR_CLR 0x4CC1544
348
349#define mmCPU_IF_PDMA_SEI_INTR_MASK 0x4CC1548
350
351#define mmCPU_IF_HBM_SEI_INTR_STS 0x4CC1550
352
353#define mmCPU_IF_HBM_SEI_INTR_CLR 0x4CC1554
354
355#define mmCPU_IF_HBM_SEI_INTR_MASK 0x4CC1558
356
357#define mmCPU_IF_DEC_SEI_INTR_STS 0x4CC1560
358
359#define mmCPU_IF_DEC_SEI_INTR_CLR 0x4CC1564
360
361#define mmCPU_IF_DEC_SEI_INTR_MASK 0x4CC1568
362
363#define mmCPU_IF_HIF_SEI_INTR_STS 0x4CC1570
364
365#define mmCPU_IF_HIF_SEI_INTR_CLR 0x4CC1574
366
367#define mmCPU_IF_HIF_SEI_INTR_MASK 0x4CC1578
368
369#define mmCPU_IF_SYNC_MNGR_SEI_INTR_STS 0x4CC1580
370
371#define mmCPU_IF_SYNC_MNGR_SEI_INTR_CLR 0x4CC1584
372
373#define mmCPU_IF_SYNC_MNGR_SEI_INTR_MASK 0x4CC1588
374
375#define mmCPU_IF_NIC_SEI_INTR_STS 0x4CC1590
376
377#define mmCPU_IF_NIC_SEI_INTR_CLR 0x4CC1594
378
379#define mmCPU_IF_NIC_SEI_INTR_MASK 0x4CC1598
380
381#define mmCPU_IF_PCIE_SPI_INTR_STS 0x4CC1600
382
383#define mmCPU_IF_PCIE_SPI_INTR_CLR 0x4CC1604
384
385#define mmCPU_IF_PCIE_SPI_INTR_MASK 0x4CC1608
386
387#define mmCPU_IF_MME_SPI_INTR_STS_0 0x4CC1610
388
389#define mmCPU_IF_MME_SPI_INTR_STS_1 0x4CC1614
390
391#define mmCPU_IF_MME_SPI_INTR_STS_2 0x4CC1618
392
393#define mmCPU_IF_MME_SPI_INTR_STS_3 0x4CC161C
394
395#define mmCPU_IF_MME_SPI_INTR_CLR_0 0x4CC1620
396
397#define mmCPU_IF_MME_SPI_INTR_CLR_1 0x4CC1624
398
399#define mmCPU_IF_MME_SPI_INTR_CLR_2 0x4CC1628
400
401#define mmCPU_IF_MME_SPI_INTR_CLR_3 0x4CC162C
402
403#define mmCPU_IF_MME_SPI_INTR_MASK_0 0x4CC1630
404
405#define mmCPU_IF_MME_SPI_INTR_MASK_1 0x4CC1634
406
407#define mmCPU_IF_MME_SPI_INTR_MASK_2 0x4CC1638
408
409#define mmCPU_IF_MME_SPI_INTR_MASK_3 0x4CC163C
410
411#define mmCPU_IF_HMMU_SPI_INTR_STS_0 0x4CC1640
412
413#define mmCPU_IF_HMMU_SPI_INTR_STS_1 0x4CC1644
414
415#define mmCPU_IF_HMMU_SPI_INTR_STS_2 0x4CC1648
416
417#define mmCPU_IF_HMMU_SPI_INTR_STS_3 0x4CC164C
418
419#define mmCPU_IF_HMMU_SPI_INTR_STS_4 0x4CC1650
420
421#define mmCPU_IF_HMMU_SPI_INTR_STS_5 0x4CC1654
422
423#define mmCPU_IF_HMMU_SPI_INTR_STS_6 0x4CC1658
424
425#define mmCPU_IF_HMMU_SPI_INTR_STS_7 0x4CC165C
426
427#define mmCPU_IF_HMMU_SPI_INTR_STS_8 0x4CC1660
428
429#define mmCPU_IF_HMMU_SPI_INTR_STS_9 0x4CC1664
430
431#define mmCPU_IF_HMMU_SPI_INTR_STS_10 0x4CC1668
432
433#define mmCPU_IF_HMMU_SPI_INTR_STS_11 0x4CC166C
434
435#define mmCPU_IF_HMMU_SPI_INTR_STS_12 0x4CC1670
436
437#define mmCPU_IF_HMMU_SPI_INTR_STS_13 0x4CC1674
438
439#define mmCPU_IF_HMMU_SPI_INTR_STS_14 0x4CC1678
440
441#define mmCPU_IF_HMMU_SPI_INTR_STS_15 0x4CC167C
442
443#define mmCPU_IF_HMMU_SPI_INTR_CLR_0 0x4CC1680
444
445#define mmCPU_IF_HMMU_SPI_INTR_CLR_1 0x4CC1684
446
447#define mmCPU_IF_HMMU_SPI_INTR_CLR_2 0x4CC1688
448
449#define mmCPU_IF_HMMU_SPI_INTR_CLR_3 0x4CC168C
450
451#define mmCPU_IF_HMMU_SPI_INTR_CLR_4 0x4CC1690
452
453#define mmCPU_IF_HMMU_SPI_INTR_CLR_5 0x4CC1694
454
455#define mmCPU_IF_HMMU_SPI_INTR_CLR_6 0x4CC1698
456
457#define mmCPU_IF_HMMU_SPI_INTR_CLR_7 0x4CC169C
458
459#define mmCPU_IF_HMMU_SPI_INTR_CLR_8 0x4CC16A0
460
461#define mmCPU_IF_HMMU_SPI_INTR_CLR_9 0x4CC16A4
462
463#define mmCPU_IF_HMMU_SPI_INTR_CLR_10 0x4CC16A8
464
465#define mmCPU_IF_HMMU_SPI_INTR_CLR_11 0x4CC16AC
466
467#define mmCPU_IF_HMMU_SPI_INTR_CLR_12 0x4CC16B0
468
469#define mmCPU_IF_HMMU_SPI_INTR_CLR_13 0x4CC16B4
470
471#define mmCPU_IF_HMMU_SPI_INTR_CLR_14 0x4CC16B8
472
473#define mmCPU_IF_HMMU_SPI_INTR_CLR_15 0x4CC16BC
474
475#define mmCPU_IF_HMMU_SPI_INTR_MASK_0 0x4CC16C0
476
477#define mmCPU_IF_HMMU_SPI_INTR_MASK_1 0x4CC16C4
478
479#define mmCPU_IF_HMMU_SPI_INTR_MASK_2 0x4CC16C8
480
481#define mmCPU_IF_HMMU_SPI_INTR_MASK_3 0x4CC16CC
482
483#define mmCPU_IF_HMMU_SPI_INTR_MASK_4 0x4CC16D0
484
485#define mmCPU_IF_HMMU_SPI_INTR_MASK_5 0x4CC16D4
486
487#define mmCPU_IF_HMMU_SPI_INTR_MASK_6 0x4CC16D8
488
489#define mmCPU_IF_HMMU_SPI_INTR_MASK_7 0x4CC16DC
490
491#define mmCPU_IF_HMMU_SPI_INTR_MASK_8 0x4CC16E0
492
493#define mmCPU_IF_HMMU_SPI_INTR_MASK_9 0x4CC16E4
494
495#define mmCPU_IF_HMMU_SPI_INTR_MASK_10 0x4CC16E8
496
497#define mmCPU_IF_HMMU_SPI_INTR_MASK_11 0x4CC16EC
498
499#define mmCPU_IF_HMMU_SPI_INTR_MASK_12 0x4CC16F0
500
501#define mmCPU_IF_HMMU_SPI_INTR_MASK_13 0x4CC16F4
502
503#define mmCPU_IF_HMMU_SPI_INTR_MASK_14 0x4CC16F8
504
505#define mmCPU_IF_HMMU_SPI_INTR_MASK_15 0x4CC16FC
506
507#define mmCPU_IF_DEC_SPI_INTR_STS_0 0x4CC1700
508
509#define mmCPU_IF_DEC_SPI_INTR_STS_1 0x4CC1704
510
511#define mmCPU_IF_DEC_SPI_INTR_STS_2 0x4CC1708
512
513#define mmCPU_IF_DEC_SPI_INTR_STS_3 0x4CC170C
514
515#define mmCPU_IF_DEC_SPI_INTR_STS_4 0x4CC1710
516
517#define mmCPU_IF_DEC_SPI_INTR_STS_5 0x4CC1714
518
519#define mmCPU_IF_DEC_SPI_INTR_STS_6 0x4CC1718
520
521#define mmCPU_IF_DEC_SPI_INTR_STS_7 0x4CC171C
522
523#define mmCPU_IF_DEC_SPI_INTR_STS_8 0x4CC1720
524
525#define mmCPU_IF_DEC_SPI_INTR_STS_9 0x4CC1724
526
527#define mmCPU_IF_DEC_SPI_INTR_CLR_0 0x4CC1730
528
529#define mmCPU_IF_DEC_SPI_INTR_CLR_1 0x4CC1734
530
531#define mmCPU_IF_DEC_SPI_INTR_CLR_2 0x4CC1738
532
533#define mmCPU_IF_DEC_SPI_INTR_CLR_3 0x4CC173C
534
535#define mmCPU_IF_DEC_SPI_INTR_CLR_4 0x4CC1740
536
537#define mmCPU_IF_DEC_SPI_INTR_CLR_5 0x4CC1744
538
539#define mmCPU_IF_DEC_SPI_INTR_CLR_6 0x4CC1748
540
541#define mmCPU_IF_DEC_SPI_INTR_CLR_7 0x4CC174C
542
543#define mmCPU_IF_DEC_SPI_INTR_CLR_8 0x4CC1750
544
545#define mmCPU_IF_DEC_SPI_INTR_CLR_9 0x4CC1754
546
547#define mmCPU_IF_DEC_SPI_INTR_MASK_0 0x4CC1760
548
549#define mmCPU_IF_DEC_SPI_INTR_MASK_1 0x4CC1764
550
551#define mmCPU_IF_DEC_SPI_INTR_MASK_2 0x4CC1768
552
553#define mmCPU_IF_DEC_SPI_INTR_MASK_3 0x4CC176C
554
555#define mmCPU_IF_DEC_SPI_INTR_MASK_4 0x4CC1770
556
557#define mmCPU_IF_DEC_SPI_INTR_MASK_5 0x4CC1774
558
559#define mmCPU_IF_DEC_SPI_INTR_MASK_6 0x4CC1778
560
561#define mmCPU_IF_DEC_SPI_INTR_MASK_7 0x4CC177C
562
563#define mmCPU_IF_DEC_SPI_INTR_MASK_8 0x4CC1780
564
565#define mmCPU_IF_DEC_SPI_INTR_MASK_9 0x4CC1784
566
567#define mmCPU_IF_HIF_SPI_INTR_STS 0x4CC17A0
568
569#define mmCPU_IF_HIF_SPI_INTR_CLR 0x4CC17A4
570
571#define mmCPU_IF_HIF_SPI_INTR_MASK 0x4CC17A8
572
573#define mmCPU_IF_NIC_SPI_INTR_STS_0 0x4CC17B0
574
575#define mmCPU_IF_NIC_SPI_INTR_STS_1 0x4CC17B4
576
577#define mmCPU_IF_NIC_SPI_INTR_STS_2 0x4CC17B8
578
579#define mmCPU_IF_NIC_SPI_INTR_STS_3 0x4CC17BC
580
581#define mmCPU_IF_NIC_SPI_INTR_STS_4 0x4CC17C0
582
583#define mmCPU_IF_NIC_SPI_INTR_STS_5 0x4CC17C4
584
585#define mmCPU_IF_NIC_SPI_INTR_STS_6 0x4CC17C8
586
587#define mmCPU_IF_NIC_SPI_INTR_STS_7 0x4CC17CC
588
589#define mmCPU_IF_NIC_SPI_INTR_STS_8 0x4CC17D0
590
591#define mmCPU_IF_NIC_SPI_INTR_STS_9 0x4CC17D4
592
593#define mmCPU_IF_NIC_SPI_INTR_STS_10 0x4CC17D8
594
595#define mmCPU_IF_NIC_SPI_INTR_STS_11 0x4CC17DC
596
597#define mmCPU_IF_NIC_SPI_INTR_CLR_0 0x4CC17E0
598
599#define mmCPU_IF_NIC_SPI_INTR_CLR_1 0x4CC17E4
600
601#define mmCPU_IF_NIC_SPI_INTR_CLR_2 0x4CC17E8
602
603#define mmCPU_IF_NIC_SPI_INTR_CLR_3 0x4CC17EC
604
605#define mmCPU_IF_NIC_SPI_INTR_CLR_4 0x4CC17F0
606
607#define mmCPU_IF_NIC_SPI_INTR_CLR_5 0x4CC17F4
608
609#define mmCPU_IF_NIC_SPI_INTR_CLR_6 0x4CC17F8
610
611#define mmCPU_IF_NIC_SPI_INTR_CLR_7 0x4CC17FC
612
613#define mmCPU_IF_NIC_SPI_INTR_CLR_8 0x4CC1800
614
615#define mmCPU_IF_NIC_SPI_INTR_CLR_9 0x4CC1804
616
617#define mmCPU_IF_NIC_SPI_INTR_CLR_10 0x4CC1808
618
619#define mmCPU_IF_NIC_SPI_INTR_CLR_11 0x4CC180C
620
621#define mmCPU_IF_NIC_SPI_INTR_MASK_0 0x4CC1810
622
623#define mmCPU_IF_NIC_SPI_INTR_MASK_1 0x4CC1814
624
625#define mmCPU_IF_NIC_SPI_INTR_MASK_2 0x4CC1818
626
627#define mmCPU_IF_NIC_SPI_INTR_MASK_3 0x4CC181C
628
629#define mmCPU_IF_NIC_SPI_INTR_MASK_4 0x4CC1820
630
631#define mmCPU_IF_NIC_SPI_INTR_MASK_5 0x4CC1824
632
633#define mmCPU_IF_NIC_SPI_INTR_MASK_6 0x4CC1828
634
635#define mmCPU_IF_NIC_SPI_INTR_MASK_7 0x4CC182C
636
637#define mmCPU_IF_NIC_SPI_INTR_MASK_8 0x4CC1830
638
639#define mmCPU_IF_NIC_SPI_INTR_MASK_9 0x4CC1834
640
641#define mmCPU_IF_NIC_SPI_INTR_MASK_10 0x4CC1838
642
643#define mmCPU_IF_NIC_SPI_INTR_MASK_11 0x4CC183C
644
645#define mmCPU_IF_DEC_ECO_INTR_STS 0x4CC1840
646
647#define mmCPU_IF_DEC_ECO_INTR_CLR 0x4CC1844
648
649#define mmCPU_IF_DEC_ECO_INTR_MASK 0x4CC1848
650
651#define mmCPU_IF_HIF_ECO_INTR_STS 0x4CC1850
652
653#define mmCPU_IF_HIF_ECO_INTR_CLR 0x4CC1854
654
655#define mmCPU_IF_HIF_ECO_INTR_MASK 0x4CC1858
656
657#define mmCPU_IF_HMMU_ECO_INTR_STS 0x4CC1860
658
659#define mmCPU_IF_HMMU_ECO_INTR_CLR 0x4CC1864
660
661#define mmCPU_IF_HMMU_ECO_INTR_MASK 0x4CC1868
662
663#define mmCPU_IF_NIC_ECO_INTR_STS 0x4CC1870
664
665#define mmCPU_IF_NIC_ECO_INTR_CLR 0x4CC1874
666
667#define mmCPU_IF_NIC_ECO_INTR_MASK 0x4CC1878
668
669#define mmCPU_IF_MSI_X_INTR_STS_0 0x4CC1900
670
671#define mmCPU_IF_MSI_X_INTR_STS_1 0x4CC1904
672
673#define mmCPU_IF_MSI_X_INTR_STS_2 0x4CC1908
674
675#define mmCPU_IF_MSI_X_INTR_STS_3 0x4CC190C
676
677#define mmCPU_IF_MSI_X_INTR_STS_4 0x4CC1910
678
679#define mmCPU_IF_MSI_X_INTR_STS_5 0x4CC1914
680
681#define mmCPU_IF_MSI_X_INTR_STS_6 0x4CC1918
682
683#define mmCPU_IF_MSI_X_INTR_STS_7 0x4CC191C
684
685#define mmCPU_IF_MSI_X_INTR_STS_8 0x4CC1920
686
687#define mmCPU_IF_MSI_X_INTR_STS_9 0x4CC1924
688
689#define mmCPU_IF_MSI_X_INTR_STS_10 0x4CC1928
690
691#define mmCPU_IF_MSI_X_INTR_STS_11 0x4CC192C
692
693#define mmCPU_IF_MSI_X_INTR_STS_12 0x4CC1930
694
695#define mmCPU_IF_MSI_X_INTR_STS_13 0x4CC1934
696
697#define mmCPU_IF_MSI_X_INTR_STS_14 0x4CC1938
698
699#define mmCPU_IF_MSI_X_INTR_STS_15 0x4CC193C
700
701#define mmCPU_IF_MSI_X_INTR_CLR_0 0x4CC1940
702
703#define mmCPU_IF_MSI_X_INTR_CLR_1 0x4CC1944
704
705#define mmCPU_IF_MSI_X_INTR_CLR_2 0x4CC1948
706
707#define mmCPU_IF_MSI_X_INTR_CLR_3 0x4CC194C
708
709#define mmCPU_IF_MSI_X_INTR_CLR_4 0x4CC1950
710
711#define mmCPU_IF_MSI_X_INTR_CLR_5 0x4CC1954
712
713#define mmCPU_IF_MSI_X_INTR_CLR_6 0x4CC1958
714
715#define mmCPU_IF_MSI_X_INTR_CLR_7 0x4CC195C
716
717#define mmCPU_IF_MSI_X_INTR_CLR_8 0x4CC1960
718
719#define mmCPU_IF_MSI_X_INTR_CLR_9 0x4CC1964
720
721#define mmCPU_IF_MSI_X_INTR_CLR_10 0x4CC1968
722
723#define mmCPU_IF_MSI_X_INTR_CLR_11 0x4CC196C
724
725#define mmCPU_IF_MSI_X_INTR_CLR_12 0x4CC1970
726
727#define mmCPU_IF_MSI_X_INTR_CLR_13 0x4CC1974
728
729#define mmCPU_IF_MSI_X_INTR_CLR_14 0x4CC1978
730
731#define mmCPU_IF_MSI_X_INTR_CLR_15 0x4CC197C
732
733#define mmCPU_IF_MSI_X_INTR_MASK_0 0x4CC1980
734
735#define mmCPU_IF_MSI_X_INTR_MASK_1 0x4CC1984
736
737#define mmCPU_IF_MSI_X_INTR_MASK_2 0x4CC1988
738
739#define mmCPU_IF_MSI_X_INTR_MASK_3 0x4CC198C
740
741#define mmCPU_IF_MSI_X_INTR_MASK_4 0x4CC1990
742
743#define mmCPU_IF_MSI_X_INTR_MASK_5 0x4CC1994
744
745#define mmCPU_IF_MSI_X_INTR_MASK_6 0x4CC1998
746
747#define mmCPU_IF_MSI_X_INTR_MASK_7 0x4CC199C
748
749#define mmCPU_IF_MSI_X_INTR_MASK_8 0x4CC19A0
750
751#define mmCPU_IF_MSI_X_INTR_MASK_9 0x4CC19A4
752
753#define mmCPU_IF_MSI_X_INTR_MASK_10 0x4CC19A8
754
755#define mmCPU_IF_MSI_X_INTR_MASK_11 0x4CC19AC
756
757#define mmCPU_IF_MSI_X_INTR_MASK_12 0x4CC19B0
758
759#define mmCPU_IF_MSI_X_INTR_MASK_13 0x4CC19B4
760
761#define mmCPU_IF_MSI_X_INTR_MASK_14 0x4CC19B8
762
763#define mmCPU_IF_MSI_X_INTR_MASK_15 0x4CC19BC
764
765#define mmCPU_IF_MSI_X_BUSY_INTR_STS 0x4CC19C0
766
767#define mmCPU_IF_MSI_X_BUSY_INTR_CLR 0x4CC19C4
768
769#define mmCPU_IF_MSI_X_BUSY_INTR_MASK 0x4CC19C8
770
771#define mmCPU_IF_MSI_X_GEN_ADDR 0x4CC19D0
772
773#define mmCPU_IF_MSI_X_GEN_DATA 0x4CC19D4
774
775#define mmCPU_IF_MSI_X_GEN_AWPROT 0x4CC19D8
776
777#endif /* ASIC_REG_CPU_IF_REGS_H_ */