arc_farm_kdma_ctx_masks.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2016-2020 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8/************************************
  9 ** This is an auto-generated file **
 10 **       DO NOT EDIT BELOW        **
 11 ************************************/
 12
 13#ifndef ASIC_REG_ARC_FARM_KDMA_CTX_MASKS_H_
 14#define ASIC_REG_ARC_FARM_KDMA_CTX_MASKS_H_
 15
 16/*
 17 *****************************************
 18 *   ARC_FARM_KDMA_CTX
 19 *   (Prototype: DMA_CORE_CTX)
 20 *****************************************
 21 */
 22
 23/* ARC_FARM_KDMA_CTX_RATE_LIM_TKN */
 24#define ARC_FARM_KDMA_CTX_RATE_LIM_TKN_RD_SHIFT 0
 25#define ARC_FARM_KDMA_CTX_RATE_LIM_TKN_RD_MASK 0xFF
 26#define ARC_FARM_KDMA_CTX_RATE_LIM_TKN_WR_SHIFT 16
 27#define ARC_FARM_KDMA_CTX_RATE_LIM_TKN_WR_MASK 0xFF0000
 28
 29/* ARC_FARM_KDMA_CTX_PWRLP */
 30#define ARC_FARM_KDMA_CTX_PWRLP_DATA_SHIFT 0
 31#define ARC_FARM_KDMA_CTX_PWRLP_DATA_MASK 0xFF
 32#define ARC_FARM_KDMA_CTX_PWRLP_EN_SHIFT 8
 33#define ARC_FARM_KDMA_CTX_PWRLP_EN_MASK 0x100
 34
 35/* ARC_FARM_KDMA_CTX_TE_NUMROWS */
 36#define ARC_FARM_KDMA_CTX_TE_NUMROWS_VAL_SHIFT 0
 37#define ARC_FARM_KDMA_CTX_TE_NUMROWS_VAL_MASK 0xFFFFFFFF
 38
 39/* ARC_FARM_KDMA_CTX_IDX */
 40#define ARC_FARM_KDMA_CTX_IDX_VAL_SHIFT 0
 41#define ARC_FARM_KDMA_CTX_IDX_VAL_MASK 0xFFFF
 42
 43/* ARC_FARM_KDMA_CTX_IDX_INC */
 44#define ARC_FARM_KDMA_CTX_IDX_INC_VAL_SHIFT 0
 45#define ARC_FARM_KDMA_CTX_IDX_INC_VAL_MASK 0xFF
 46
 47/* ARC_FARM_KDMA_CTX_CTRL */
 48#define ARC_FARM_KDMA_CTX_CTRL_TRANSPOSE_SHIFT 0
 49#define ARC_FARM_KDMA_CTX_CTRL_TRANSPOSE_MASK 0x1
 50#define ARC_FARM_KDMA_CTX_CTRL_DTYPE_SHIFT 4
 51#define ARC_FARM_KDMA_CTX_CTRL_DTYPE_MASK 0x30
 52#define ARC_FARM_KDMA_CTX_CTRL_COMPRESS_SHIFT 8
 53#define ARC_FARM_KDMA_CTX_CTRL_COMPRESS_MASK 0x100
 54#define ARC_FARM_KDMA_CTX_CTRL_DECOMPRESS_SHIFT 9
 55#define ARC_FARM_KDMA_CTX_CTRL_DECOMPRESS_MASK 0x200
 56#define ARC_FARM_KDMA_CTX_CTRL_RD_UNCACHEABLE_SHIFT 12
 57#define ARC_FARM_KDMA_CTX_CTRL_RD_UNCACHEABLE_MASK 0x1000
 58
 59/* ARC_FARM_KDMA_CTX_SRC_TSIZE_0 */
 60#define ARC_FARM_KDMA_CTX_SRC_TSIZE_0_VAL_SHIFT 0
 61#define ARC_FARM_KDMA_CTX_SRC_TSIZE_0_VAL_MASK 0xFFFFFFFF
 62
 63/* ARC_FARM_KDMA_CTX_SRC_TSIZE_1 */
 64#define ARC_FARM_KDMA_CTX_SRC_TSIZE_1_VAL_SHIFT 0
 65#define ARC_FARM_KDMA_CTX_SRC_TSIZE_1_VAL_MASK 0xFFFFFFFF
 66
 67/* ARC_FARM_KDMA_CTX_SRC_STRIDE_1 */
 68#define ARC_FARM_KDMA_CTX_SRC_STRIDE_1_VAL_SHIFT 0
 69#define ARC_FARM_KDMA_CTX_SRC_STRIDE_1_VAL_MASK 0xFFFFFFFF
 70
 71/* ARC_FARM_KDMA_CTX_SRC_TSIZE_2 */
 72#define ARC_FARM_KDMA_CTX_SRC_TSIZE_2_VAL_SHIFT 0
 73#define ARC_FARM_KDMA_CTX_SRC_TSIZE_2_VAL_MASK 0xFFFFFFFF
 74
 75/* ARC_FARM_KDMA_CTX_SRC_STRIDE_2 */
 76#define ARC_FARM_KDMA_CTX_SRC_STRIDE_2_VAL_SHIFT 0
 77#define ARC_FARM_KDMA_CTX_SRC_STRIDE_2_VAL_MASK 0xFFFFFFFF
 78
 79/* ARC_FARM_KDMA_CTX_SRC_TSIZE_3 */
 80#define ARC_FARM_KDMA_CTX_SRC_TSIZE_3_VAL_SHIFT 0
 81#define ARC_FARM_KDMA_CTX_SRC_TSIZE_3_VAL_MASK 0xFFFFFFFF
 82
 83/* ARC_FARM_KDMA_CTX_SRC_STRIDE_3 */
 84#define ARC_FARM_KDMA_CTX_SRC_STRIDE_3_VAL_SHIFT 0
 85#define ARC_FARM_KDMA_CTX_SRC_STRIDE_3_VAL_MASK 0xFFFFFFFF
 86
 87/* ARC_FARM_KDMA_CTX_SRC_TSIZE_4 */
 88#define ARC_FARM_KDMA_CTX_SRC_TSIZE_4_VAL_SHIFT 0
 89#define ARC_FARM_KDMA_CTX_SRC_TSIZE_4_VAL_MASK 0xFFFFFFFF
 90
 91/* ARC_FARM_KDMA_CTX_SRC_STRIDE_4 */
 92#define ARC_FARM_KDMA_CTX_SRC_STRIDE_4_VAL_SHIFT 0
 93#define ARC_FARM_KDMA_CTX_SRC_STRIDE_4_VAL_MASK 0xFFFFFFFF
 94
 95/* ARC_FARM_KDMA_CTX_DST_TSIZE_1 */
 96#define ARC_FARM_KDMA_CTX_DST_TSIZE_1_VAL_SHIFT 0
 97#define ARC_FARM_KDMA_CTX_DST_TSIZE_1_VAL_MASK 0xFFFFFFFF
 98
 99/* ARC_FARM_KDMA_CTX_DST_STRIDE_1 */
100#define ARC_FARM_KDMA_CTX_DST_STRIDE_1_VAL_SHIFT 0
101#define ARC_FARM_KDMA_CTX_DST_STRIDE_1_VAL_MASK 0xFFFFFFFF
102
103/* ARC_FARM_KDMA_CTX_DST_TSIZE_2 */
104#define ARC_FARM_KDMA_CTX_DST_TSIZE_2_VAL_SHIFT 0
105#define ARC_FARM_KDMA_CTX_DST_TSIZE_2_VAL_MASK 0xFFFFFFFF
106
107/* ARC_FARM_KDMA_CTX_DST_STRIDE_2 */
108#define ARC_FARM_KDMA_CTX_DST_STRIDE_2_VAL_SHIFT 0
109#define ARC_FARM_KDMA_CTX_DST_STRIDE_2_VAL_MASK 0xFFFFFFFF
110
111/* ARC_FARM_KDMA_CTX_DST_TSIZE_3 */
112#define ARC_FARM_KDMA_CTX_DST_TSIZE_3_VAL_SHIFT 0
113#define ARC_FARM_KDMA_CTX_DST_TSIZE_3_VAL_MASK 0xFFFFFFFF
114
115/* ARC_FARM_KDMA_CTX_DST_STRIDE_3 */
116#define ARC_FARM_KDMA_CTX_DST_STRIDE_3_VAL_SHIFT 0
117#define ARC_FARM_KDMA_CTX_DST_STRIDE_3_VAL_MASK 0xFFFFFFFF
118
119/* ARC_FARM_KDMA_CTX_DST_TSIZE_4 */
120#define ARC_FARM_KDMA_CTX_DST_TSIZE_4_VAL_SHIFT 0
121#define ARC_FARM_KDMA_CTX_DST_TSIZE_4_VAL_MASK 0xFFFFFFFF
122
123/* ARC_FARM_KDMA_CTX_DST_STRIDE_4 */
124#define ARC_FARM_KDMA_CTX_DST_STRIDE_4_VAL_SHIFT 0
125#define ARC_FARM_KDMA_CTX_DST_STRIDE_4_VAL_MASK 0xFFFFFFFF
126
127/* ARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI */
128#define ARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI_VAL_SHIFT 0
129#define ARC_FARM_KDMA_CTX_WR_COMP_ADDR_HI_VAL_MASK 0xFFFFFFFF
130
131/* ARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO */
132#define ARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO_VAL_SHIFT 0
133#define ARC_FARM_KDMA_CTX_WR_COMP_ADDR_LO_VAL_MASK 0xFFFFFFFF
134
135/* ARC_FARM_KDMA_CTX_WR_COMP_WDATA */
136#define ARC_FARM_KDMA_CTX_WR_COMP_WDATA_VAL_SHIFT 0
137#define ARC_FARM_KDMA_CTX_WR_COMP_WDATA_VAL_MASK 0xFFFFFFFF
138
139/* ARC_FARM_KDMA_CTX_SRC_OFFSET_LO */
140#define ARC_FARM_KDMA_CTX_SRC_OFFSET_LO_VAL_SHIFT 0
141#define ARC_FARM_KDMA_CTX_SRC_OFFSET_LO_VAL_MASK 0xFFFFFFFF
142
143/* ARC_FARM_KDMA_CTX_SRC_OFFSET_HI */
144#define ARC_FARM_KDMA_CTX_SRC_OFFSET_HI_VAL_SHIFT 0
145#define ARC_FARM_KDMA_CTX_SRC_OFFSET_HI_VAL_MASK 0xFFFFFFFF
146
147/* ARC_FARM_KDMA_CTX_DST_OFFSET_LO */
148#define ARC_FARM_KDMA_CTX_DST_OFFSET_LO_VAL_SHIFT 0
149#define ARC_FARM_KDMA_CTX_DST_OFFSET_LO_VAL_MASK 0xFFFFFFFF
150
151/* ARC_FARM_KDMA_CTX_DST_OFFSET_HI */
152#define ARC_FARM_KDMA_CTX_DST_OFFSET_HI_VAL_SHIFT 0
153#define ARC_FARM_KDMA_CTX_DST_OFFSET_HI_VAL_MASK 0xFFFFFFFF
154
155/* ARC_FARM_KDMA_CTX_SRC_BASE_LO */
156#define ARC_FARM_KDMA_CTX_SRC_BASE_LO_VAL_SHIFT 0
157#define ARC_FARM_KDMA_CTX_SRC_BASE_LO_VAL_MASK 0xFFFFFFFF
158
159/* ARC_FARM_KDMA_CTX_SRC_BASE_HI */
160#define ARC_FARM_KDMA_CTX_SRC_BASE_HI_VAL_SHIFT 0
161#define ARC_FARM_KDMA_CTX_SRC_BASE_HI_VAL_MASK 0xFFFFFFFF
162
163/* ARC_FARM_KDMA_CTX_DST_BASE_LO */
164#define ARC_FARM_KDMA_CTX_DST_BASE_LO_VAL_SHIFT 0
165#define ARC_FARM_KDMA_CTX_DST_BASE_LO_VAL_MASK 0xFFFFFFFF
166
167/* ARC_FARM_KDMA_CTX_DST_BASE_HI */
168#define ARC_FARM_KDMA_CTX_DST_BASE_HI_VAL_SHIFT 0
169#define ARC_FARM_KDMA_CTX_DST_BASE_HI_VAL_MASK 0xFFFFFFFF
170
171/* ARC_FARM_KDMA_CTX_DST_TSIZE_0 */
172#define ARC_FARM_KDMA_CTX_DST_TSIZE_0_VAL_SHIFT 0
173#define ARC_FARM_KDMA_CTX_DST_TSIZE_0_VAL_MASK 0xFFFFFFFF
174
175/* ARC_FARM_KDMA_CTX_COMMIT */
176#define ARC_FARM_KDMA_CTX_COMMIT_WR_COMP_EN_SHIFT 0
177#define ARC_FARM_KDMA_CTX_COMMIT_WR_COMP_EN_MASK 0x1
178#define ARC_FARM_KDMA_CTX_COMMIT_ENDIAN_SWAP_SHIFT 1
179#define ARC_FARM_KDMA_CTX_COMMIT_ENDIAN_SWAP_MASK 0x6
180#define ARC_FARM_KDMA_CTX_COMMIT_MEM_SET_SHIFT 4
181#define ARC_FARM_KDMA_CTX_COMMIT_MEM_SET_MASK 0x10
182#define ARC_FARM_KDMA_CTX_COMMIT_BF16_SHIFT 6
183#define ARC_FARM_KDMA_CTX_COMMIT_BF16_MASK 0x40
184#define ARC_FARM_KDMA_CTX_COMMIT_FP16_SHIFT 7
185#define ARC_FARM_KDMA_CTX_COMMIT_FP16_MASK 0x80
186#define ARC_FARM_KDMA_CTX_COMMIT_CTX_ID_INC_SHIFT 8
187#define ARC_FARM_KDMA_CTX_COMMIT_CTX_ID_INC_MASK 0x100
188#define ARC_FARM_KDMA_CTX_COMMIT_ADD_OFFSET_0_SHIFT 9
189#define ARC_FARM_KDMA_CTX_COMMIT_ADD_OFFSET_0_MASK 0x200
190#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE0_FROM_DST_SIZE0_SHIFT 10
191#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE0_FROM_DST_SIZE0_MASK 0x400
192#define ARC_FARM_KDMA_CTX_COMMIT_SRC_OFST_FROM_DST_OFST_SHIFT 11
193#define ARC_FARM_KDMA_CTX_COMMIT_SRC_OFST_FROM_DST_OFST_MASK 0x800
194#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM1_SHIFT 12
195#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM1_MASK 0x1000
196#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM2_SHIFT 13
197#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM2_MASK 0x2000
198#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM3_SHIFT 14
199#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM3_MASK 0x4000
200#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM4_SHIFT 15
201#define ARC_FARM_KDMA_CTX_COMMIT_DISABLE_DIM4_MASK 0x8000
202#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE1_FROM_DST_SIZE1_SHIFT 16
203#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE1_FROM_DST_SIZE1_MASK 0x10000
204#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE2_FROM_DST_SIZE2_SHIFT 17
205#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE2_FROM_DST_SIZE2_MASK 0x20000
206#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE3_FROM_DST_SIZE3_SHIFT 18
207#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE3_FROM_DST_SIZE3_MASK 0x40000
208#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE4_FROM_DST_SIZE4_SHIFT 19
209#define ARC_FARM_KDMA_CTX_COMMIT_SRC_SIZE4_FROM_DST_SIZE4_MASK 0x80000
210#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD1_FROM_DST_STRD1_SHIFT 20
211#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD1_FROM_DST_STRD1_MASK 0x100000
212#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD2_FROM_DST_STRD2_SHIFT 21
213#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD2_FROM_DST_STRD2_MASK 0x200000
214#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD3_FROM_DST_STRD3_SHIFT 22
215#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD3_FROM_DST_STRD3_MASK 0x400000
216#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD4_FROM_DST_STRD4_SHIFT 23
217#define ARC_FARM_KDMA_CTX_COMMIT_SRC_STRD4_FROM_DST_STRD4_MASK 0x800000
218#define ARC_FARM_KDMA_CTX_COMMIT_LIN_SHIFT 31
219#define ARC_FARM_KDMA_CTX_COMMIT_LIN_MASK 0x80000000
220
221#endif /* ASIC_REG_ARC_FARM_KDMA_CTX_MASKS_H_ */