FILE
tpc4_cfg_regs.h
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linux-6.19.14/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_TPC4_CFG_REGS_H_ 14#define ASIC_REG_TPC4_CFG_REGS_H_ 15 16/* 17 ***************************************** 18 * TPC4_CFG (Prototype: TPC) 19 ***************************************** 20 */ 21 22#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF06400 23 24#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF06404 25 26#define mmTPC4_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF06408 27 28#define mmTPC4_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF0640C 29 30#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF06410 31 32#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF06414 33 34#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF06418 35 36#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF0641C 37 38#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF06420 39 40#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF06424 41 42#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF06428 43 44#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF0642C 45 46#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF06430 47 48#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF06434 49 50#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF06438 51 52#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF0643C 53 54#define mmTPC4_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF06440 55 56#define mmTPC4_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF06444 57 58#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF06448 59 60#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF0644C 61 62#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF06450 63 64#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF06454 65 66#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF06458 67 68#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF0645C 69 70#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF06460 71 72#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF06464 73 74#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF06468 75 76#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF0646C 77 78#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF06470 79 80#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF06474 81 82#define mmTPC4_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF06478 83 84#define mmTPC4_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF0647C 85 86#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF06480 87 88#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF06484 89 90#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF06488 91 92#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF0648C 93 94#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF06490 95 96#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF06494 97 98#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF06498 99 100#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF0649C 101 102#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF064A0 103 104#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF064A4 105 106#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF064A8 107 108#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF064AC 109 110#define mmTPC4_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF064B0 111 112#define mmTPC4_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF064B4 113 114#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF064B8 115 116#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF064BC 117 118#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF064C0 119 120#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF064C4 121 122#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF064C8 123 124#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF064CC 125 126#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF064D0 127 128#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF064D4 129 130#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF064D8 131 132#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF064DC 133 134#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF064E0 135 136#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF064E4 137 138#define mmTPC4_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF064E8 139 140#define mmTPC4_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF064EC 141 142#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF064F0 143 144#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF064F4 145 146#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF064F8 147 148#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF064FC 149 150#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF06500 151 152#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF06504 153 154#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF06508 155 156#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF0650C 157 158#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF06510 159 160#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF06514 161 162#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF06518 163 164#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF0651C 165 166#define mmTPC4_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF06520 167 168#define mmTPC4_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF06524 169 170#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF06528 171 172#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF0652C 173 174#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF06530 175 176#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF06534 177 178#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF06538 179 180#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF0653C 181 182#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF06540 183 184#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF06544 185 186#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF06548 187 188#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF0654C 189 190#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF06550 191 192#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF06554 193 194#define mmTPC4_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF06558 195 196#define mmTPC4_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF0655C 197 198#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF06560 199 200#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF06564 201 202#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF06568 203 204#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF0656C 205 206#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF06570 207 208#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF06574 209 210#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF06578 211 212#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF0657C 213 214#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF06580 215 216#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF06584 217 218#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF06588 219 220#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF0658C 221 222#define mmTPC4_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF06590 223 224#define mmTPC4_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF06594 225 226#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF06598 227 228#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF0659C 229 230#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF065A0 231 232#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF065A4 233 234#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF065A8 235 236#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF065AC 237 238#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF065B0 239 240#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF065B4 241 242#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF065B8 243 244#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF065BC 245 246#define mmTPC4_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF065C0 247 248#define mmTPC4_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF065C4 249 250#define mmTPC4_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF065C8 251 252#define mmTPC4_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF065CC 253 254#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF065D0 255 256#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF065D4 257 258#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF065D8 259 260#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF065DC 261 262#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF065E0 263 264#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF065E4 265 266#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF065E8 267 268#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF065EC 269 270#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF065F0 271 272#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF065F4 273 274#define mmTPC4_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF065F8 275 276#define mmTPC4_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF065FC 277 278#define mmTPC4_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF06600 279 280#define mmTPC4_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF06604 281 282#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF06608 283 284#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF0660C 285 286#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF06610 287 288#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF06614 289 290#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF06618 291 292#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF0661C 293 294#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF06620 295 296#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF06624 297 298#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF06628 299 300#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF0662C 301 302#define mmTPC4_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF06630 303 304#define mmTPC4_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF06634 305 306#define mmTPC4_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF06638 307 308#define mmTPC4_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF0663C 309 310#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF06640 311 312#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF06644 313 314#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF06648 315 316#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF0664C 317 318#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF06650 319 320#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF06654 321 322#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF06658 323 324#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF0665C 325 326#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF06660 327 328#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF06664 329 330#define mmTPC4_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF06668 331 332#define mmTPC4_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF0666C 333 334#define mmTPC4_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF06670 335 336#define mmTPC4_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF06674 337 338#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF06678 339 340#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF0667C 341 342#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF06680 343 344#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF06684 345 346#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF06688 347 348#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF0668C 349 350#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF06690 351 352#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF06694 353 354#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF06698 355 356#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF0669C 357 358#define mmTPC4_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF066A0 359 360#define mmTPC4_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF066A4 361 362#define mmTPC4_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF066A8 363 364#define mmTPC4_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF066AC 365 366#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF066B0 367 368#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF066B4 369 370#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF066B8 371 372#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF066BC 373 374#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF066C0 375 376#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF066C4 377 378#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF066C8 379 380#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF066CC 381 382#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF066D0 383 384#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF066D4 385 386#define mmTPC4_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF066D8 387 388#define mmTPC4_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF066DC 389 390#define mmTPC4_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF066E0 391 392#define mmTPC4_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF066E4 393 394#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF066E8 395 396#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF066EC 397 398#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF066F0 399 400#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF066F4 401 402#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF066F8 403 404#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF066FC 405 406#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF06700 407 408#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF06704 409 410#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF06708 411 412#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF0670C 413 414#define mmTPC4_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF06710 415 416#define mmTPC4_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF06714 417 418#define mmTPC4_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF06718 419 420#define mmTPC4_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF0671C 421 422#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF06720 423 424#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF06724 425 426#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF06728 427 428#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF0672C 429 430#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF06730 431 432#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF06734 433 434#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF06738 435 436#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF0673C 437 438#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF06740 439 440#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF06744 441 442#define mmTPC4_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF06748 443 444#define mmTPC4_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF0674C 445 446#define mmTPC4_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF06750 447 448#define mmTPC4_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF06754 449 450#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF06758 451 452#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF0675C 453 454#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF06760 455 456#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF06764 457 458#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF06768 459 460#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF0676C 461 462#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF06770 463 464#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF06774 465 466#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF06778 467 468#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF0677C 469 470#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF06780 471 472#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF06784 473 474#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF06788 475 476#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF0678C 477 478#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_0 0xF06790 479 480#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_0 0xF06794 481 482#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_1 0xF06798 483 484#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_1 0xF0679C 485 486#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_2 0xF067A0 487 488#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_2 0xF067A4 489 490#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_3 0xF067A8 491 492#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_3 0xF067AC 493 494#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_4 0xF067B0 495 496#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_4 0xF067B4 497 498#define mmTPC4_CFG_KERNEL_KERNEL_CONFIG 0xF067B8 499 500#define mmTPC4_CFG_KERNEL_KERNEL_ID 0xF067BC 501 502#define mmTPC4_CFG_KERNEL_SRF_0 0xF067C0 503 504#define mmTPC4_CFG_KERNEL_SRF_1 0xF067C4 505 506#define mmTPC4_CFG_KERNEL_SRF_2 0xF067C8 507 508#define mmTPC4_CFG_KERNEL_SRF_3 0xF067CC 509 510#define mmTPC4_CFG_KERNEL_SRF_4 0xF067D0 511 512#define mmTPC4_CFG_KERNEL_SRF_5 0xF067D4 513 514#define mmTPC4_CFG_KERNEL_SRF_6 0xF067D8 515 516#define mmTPC4_CFG_KERNEL_SRF_7 0xF067DC 517 518#define mmTPC4_CFG_KERNEL_SRF_8 0xF067E0 519 520#define mmTPC4_CFG_KERNEL_SRF_9 0xF067E4 521 522#define mmTPC4_CFG_KERNEL_SRF_10 0xF067E8 523 524#define mmTPC4_CFG_KERNEL_SRF_11 0xF067EC 525 526#define mmTPC4_CFG_KERNEL_SRF_12 0xF067F0 527 528#define mmTPC4_CFG_KERNEL_SRF_13 0xF067F4 529 530#define mmTPC4_CFG_KERNEL_SRF_14 0xF067F8 531 532#define mmTPC4_CFG_KERNEL_SRF_15 0xF067FC 533 534#define mmTPC4_CFG_KERNEL_SRF_16 0xF06800 535 536#define mmTPC4_CFG_KERNEL_SRF_17 0xF06804 537 538#define mmTPC4_CFG_KERNEL_SRF_18 0xF06808 539 540#define mmTPC4_CFG_KERNEL_SRF_19 0xF0680C 541 542#define mmTPC4_CFG_KERNEL_SRF_20 0xF06810 543 544#define mmTPC4_CFG_KERNEL_SRF_21 0xF06814 545 546#define mmTPC4_CFG_KERNEL_SRF_22 0xF06818 547 548#define mmTPC4_CFG_KERNEL_SRF_23 0xF0681C 549 550#define mmTPC4_CFG_KERNEL_SRF_24 0xF06820 551 552#define mmTPC4_CFG_KERNEL_SRF_25 0xF06824 553 554#define mmTPC4_CFG_KERNEL_SRF_26 0xF06828 555 556#define mmTPC4_CFG_KERNEL_SRF_27 0xF0682C 557 558#define mmTPC4_CFG_KERNEL_SRF_28 0xF06830 559 560#define mmTPC4_CFG_KERNEL_SRF_29 0xF06834 561 562#define mmTPC4_CFG_KERNEL_SRF_30 0xF06838 563 564#define mmTPC4_CFG_KERNEL_SRF_31 0xF0683C 565 566#define mmTPC4_CFG_ROUND_CSR 0xF068FC 567 568#define mmTPC4_CFG_PROT 0xF06900 569 570#define mmTPC4_CFG_SEMAPHORE 0xF06908 571 572#define mmTPC4_CFG_VFLAGS 0xF0690C 573 574#define mmTPC4_CFG_SFLAGS 0xF06910 575 576#define mmTPC4_CFG_LFSR_POLYNOM 0xF06918 577 578#define mmTPC4_CFG_STATUS 0xF0691C 579 580#define mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH 0xF06920 581 582#define mmTPC4_CFG_CFG_SUBTRACT_VALUE 0xF06924 583 584#define mmTPC4_CFG_SM_BASE_ADDRESS_HIGH 0xF0692C 585 586#define mmTPC4_CFG_TPC_CMD 0xF06930 587 588#define mmTPC4_CFG_TPC_EXECUTE 0xF06938 589 590#define mmTPC4_CFG_TPC_STALL 0xF0693C 591 592#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_LOW 0xF06940 593 594#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF06944 595 596#define mmTPC4_CFG_RD_RATE_LIMIT 0xF06948 597 598#define mmTPC4_CFG_WR_RATE_LIMIT 0xF06950 599 600#define mmTPC4_CFG_MSS_CONFIG 0xF06954 601 602#define mmTPC4_CFG_TPC_INTR_CAUSE 0xF06958 603 604#define mmTPC4_CFG_TPC_INTR_MASK 0xF0695C 605 606#define mmTPC4_CFG_WQ_CREDITS 0xF06960 607 608#define mmTPC4_CFG_ARUSER_LO 0xF06964 609 610#define mmTPC4_CFG_ARUSER_HI 0xF06968 611 612#define mmTPC4_CFG_AWUSER_LO 0xF0696C 613 614#define mmTPC4_CFG_AWUSER_HI 0xF06970 615 616#define mmTPC4_CFG_OPCODE_EXEC 0xF06974 617 618#define mmTPC4_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF06978 619 620#define mmTPC4_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF0697C 621 622#define mmTPC4_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF06980 623 624#define mmTPC4_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF06984 625 626#define mmTPC4_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF06988 627 628#define mmTPC4_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF0698C 629 630#define mmTPC4_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF06990 631 632#define mmTPC4_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF06994 633 634#define mmTPC4_CFG_TSB_CFG_MAX_SIZE 0xF06998 635 636#define mmTPC4_CFG_TSB_CFG 0xF0699C 637 638#define mmTPC4_CFG_DBGMEM_ADD 0xF069A0 639 640#define mmTPC4_CFG_DBGMEM_DATA_WR 0xF069A4 641 642#define mmTPC4_CFG_DBGMEM_DATA_RD 0xF069A8 643 644#define mmTPC4_CFG_DBGMEM_CTRL 0xF069AC 645 646#define mmTPC4_CFG_DBGMEM_RC 0xF069B0 647 648#define mmTPC4_CFG_TSB_INFLIGHT_CNTR 0xF069B4 649 650#define mmTPC4_CFG_WQ_INFLIGHT_CNTR 0xF069B8 651 652#define mmTPC4_CFG_WQ_LBW_TOTAL_CNTR 0xF069BC 653 654#define mmTPC4_CFG_WQ_HBW_TOTAL_CNTR 0xF069C0 655 656#define mmTPC4_CFG_IRQ_OCCOUPY_CNTR 0xF069C4 657 658#define mmTPC4_CFG_FUNC_MBIST_CNTRL 0xF069D0 659 660#define mmTPC4_CFG_FUNC_MBIST_PAT 0xF069D4 661 662#define mmTPC4_CFG_FUNC_MBIST_MEM_0 0xF069D8 663 664#define mmTPC4_CFG_FUNC_MBIST_MEM_1 0xF069DC 665 666#define mmTPC4_CFG_FUNC_MBIST_MEM_2 0xF069E0 667 668#define mmTPC4_CFG_FUNC_MBIST_MEM_3 0xF069E4 669 670#define mmTPC4_CFG_FUNC_MBIST_MEM_4 0xF069E8 671 672#define mmTPC4_CFG_FUNC_MBIST_MEM_5 0xF069EC 673 674#define mmTPC4_CFG_FUNC_MBIST_MEM_6 0xF069F0 675 676#define mmTPC4_CFG_FUNC_MBIST_MEM_7 0xF069F4 677 678#define mmTPC4_CFG_FUNC_MBIST_MEM_8 0xF069F8 679 680#define mmTPC4_CFG_FUNC_MBIST_MEM_9 0xF069FC 681 682#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF06A00 683 684#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF06A04 685 686#define mmTPC4_CFG_QM_TENSOR_0_PADDING_VALUE 0xF06A08 687 688#define mmTPC4_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF06A0C 689 690#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF06A10 691 692#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF06A14 693 694#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF06A18 695 696#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF06A1C 697 698#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF06A20 699 700#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF06A24 701 702#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF06A28 703 704#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF06A2C 705 706#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF06A30 707 708#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF06A34 709 710#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF06A38 711 712#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF06A3C 713 714#define mmTPC4_CFG_QM_TENSOR_1_PADDING_VALUE 0xF06A40 715 716#define mmTPC4_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF06A44 717 718#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF06A48 719 720#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF06A4C 721 722#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF06A50 723 724#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF06A54 725 726#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF06A58 727 728#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF06A5C 729 730#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF06A60 731 732#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF06A64 733 734#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF06A68 735 736#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF06A6C 737 738#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF06A70 739 740#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF06A74 741 742#define mmTPC4_CFG_QM_TENSOR_2_PADDING_VALUE 0xF06A78 743 744#define mmTPC4_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF06A7C 745 746#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF06A80 747 748#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF06A84 749 750#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF06A88 751 752#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF06A8C 753 754#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF06A90 755 756#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF06A94 757 758#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF06A98 759 760#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF06A9C 761 762#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF06AA0 763 764#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF06AA4 765 766#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF06AA8 767 768#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF06AAC 769 770#define mmTPC4_CFG_QM_TENSOR_3_PADDING_VALUE 0xF06AB0 771 772#define mmTPC4_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF06AB4 773 774#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF06AB8 775 776#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF06ABC 777 778#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF06AC0 779 780#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF06AC4 781 782#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF06AC8 783 784#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF06ACC 785 786#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF06AD0 787 788#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF06AD4 789 790#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF06AD8 791 792#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF06ADC 793 794#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF06AE0 795 796#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF06AE4 797 798#define mmTPC4_CFG_QM_TENSOR_4_PADDING_VALUE 0xF06AE8 799 800#define mmTPC4_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF06AEC 801 802#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF06AF0 803 804#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF06AF4 805 806#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF06AF8 807 808#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF06AFC 809 810#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF06B00 811 812#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF06B04 813 814#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF06B08 815 816#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF06B0C 817 818#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF06B10 819 820#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF06B14 821 822#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF06B18 823 824#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF06B1C 825 826#define mmTPC4_CFG_QM_TENSOR_5_PADDING_VALUE 0xF06B20 827 828#define mmTPC4_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF06B24 829 830#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF06B28 831 832#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF06B2C 833 834#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF06B30 835 836#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF06B34 837 838#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF06B38 839 840#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF06B3C 841 842#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF06B40 843 844#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF06B44 845 846#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF06B48 847 848#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF06B4C 849 850#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF06B50 851 852#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF06B54 853 854#define mmTPC4_CFG_QM_TENSOR_6_PADDING_VALUE 0xF06B58 855 856#define mmTPC4_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF06B5C 857 858#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF06B60 859 860#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF06B64 861 862#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF06B68 863 864#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF06B6C 865 866#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF06B70 867 868#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF06B74 869 870#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF06B78 871 872#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF06B7C 873 874#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF06B80 875 876#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF06B84 877 878#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF06B88 879 880#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF06B8C 881 882#define mmTPC4_CFG_QM_TENSOR_7_PADDING_VALUE 0xF06B90 883 884#define mmTPC4_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF06B94 885 886#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF06B98 887 888#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF06B9C 889 890#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF06BA0 891 892#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF06BA4 893 894#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF06BA8 895 896#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF06BAC 897 898#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF06BB0 899 900#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF06BB4 901 902#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF06BB8 903 904#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF06BBC 905 906#define mmTPC4_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF06BC0 907 908#define mmTPC4_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF06BC4 909 910#define mmTPC4_CFG_QM_TENSOR_8_PADDING_VALUE 0xF06BC8 911 912#define mmTPC4_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF06BCC 913 914#define mmTPC4_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF06BD0 915 916#define mmTPC4_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF06BD4 917 918#define mmTPC4_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF06BD8 919 920#define mmTPC4_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF06BDC 921 922#define mmTPC4_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF06BE0 923 924#define mmTPC4_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF06BE4 925 926#define mmTPC4_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF06BE8 927 928#define mmTPC4_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF06BEC 929 930#define mmTPC4_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF06BF0 931 932#define mmTPC4_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF06BF4 933 934#define mmTPC4_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF06BF8 935 936#define mmTPC4_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF06BFC 937 938#define mmTPC4_CFG_QM_TENSOR_9_PADDING_VALUE 0xF06C00 939 940#define mmTPC4_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF06C04 941 942#define mmTPC4_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF06C08 943 944#define mmTPC4_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF06C0C 945 946#define mmTPC4_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF06C10 947 948#define mmTPC4_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF06C14 949 950#define mmTPC4_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF06C18 951 952#define mmTPC4_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF06C1C 953 954#define mmTPC4_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF06C20 955 956#define mmTPC4_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF06C24 957 958#define mmTPC4_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF06C28 959 960#define mmTPC4_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF06C2C 961 962#define mmTPC4_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF06C30 963 964#define mmTPC4_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF06C34 965 966#define mmTPC4_CFG_QM_TENSOR_10_PADDING_VALUE 0xF06C38 967 968#define mmTPC4_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF06C3C 969 970#define mmTPC4_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF06C40 971 972#define mmTPC4_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF06C44 973 974#define mmTPC4_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF06C48 975 976#define mmTPC4_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF06C4C 977 978#define mmTPC4_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF06C50 979 980#define mmTPC4_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF06C54 981 982#define mmTPC4_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF06C58 983 984#define mmTPC4_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF06C5C 985 986#define mmTPC4_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF06C60 987 988#define mmTPC4_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF06C64 989 990#define mmTPC4_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF06C68 991 992#define mmTPC4_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF06C6C 993 994#define mmTPC4_CFG_QM_TENSOR_11_PADDING_VALUE 0xF06C70 995 996#define mmTPC4_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF06C74 997 998#define mmTPC4_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF06C78 999 1000#define mmTPC4_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF06C7C 1001 1002#define mmTPC4_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF06C80 1003 1004#define mmTPC4_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF06C84 1005 1006#define mmTPC4_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF06C88 1007 1008#define mmTPC4_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF06C8C 1009 1010#define mmTPC4_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF06C90 1011 1012#define mmTPC4_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF06C94 1013 1014#define mmTPC4_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF06C98 1015 1016#define mmTPC4_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF06C9C 1017 1018#define mmTPC4_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF06CA0 1019 1020#define mmTPC4_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF06CA4 1021 1022#define mmTPC4_CFG_QM_TENSOR_12_PADDING_VALUE 0xF06CA8 1023 1024#define mmTPC4_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF06CAC 1025 1026#define mmTPC4_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF06CB0 1027 1028#define mmTPC4_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF06CB4 1029 1030#define mmTPC4_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF06CB8 1031 1032#define mmTPC4_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF06CBC 1033 1034#define mmTPC4_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF06CC0 1035 1036#define mmTPC4_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF06CC4 1037 1038#define mmTPC4_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF06CC8 1039 1040#define mmTPC4_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF06CCC 1041 1042#define mmTPC4_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF06CD0 1043 1044#define mmTPC4_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF06CD4 1045 1046#define mmTPC4_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF06CD8 1047 1048#define mmTPC4_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF06CDC 1049 1050#define mmTPC4_CFG_QM_TENSOR_13_PADDING_VALUE 0xF06CE0 1051 1052#define mmTPC4_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF06CE4 1053 1054#define mmTPC4_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF06CE8 1055 1056#define mmTPC4_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF06CEC 1057 1058#define mmTPC4_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF06CF0 1059 1060#define mmTPC4_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF06CF4 1061 1062#define mmTPC4_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF06CF8 1063 1064#define mmTPC4_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF06CFC 1065 1066#define mmTPC4_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF06D00 1067 1068#define mmTPC4_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF06D04 1069 1070#define mmTPC4_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF06D08 1071 1072#define mmTPC4_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF06D0C 1073 1074#define mmTPC4_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF06D10 1075 1076#define mmTPC4_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF06D14 1077 1078#define mmTPC4_CFG_QM_TENSOR_14_PADDING_VALUE 0xF06D18 1079 1080#define mmTPC4_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF06D1C 1081 1082#define mmTPC4_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF06D20 1083 1084#define mmTPC4_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF06D24 1085 1086#define mmTPC4_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF06D28 1087 1088#define mmTPC4_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF06D2C 1089 1090#define mmTPC4_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF06D30 1091 1092#define mmTPC4_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF06D34 1093 1094#define mmTPC4_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF06D38 1095 1096#define mmTPC4_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF06D3C 1097 1098#define mmTPC4_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF06D40 1099 1100#define mmTPC4_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF06D44 1101 1102#define mmTPC4_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF06D48 1103 1104#define mmTPC4_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF06D4C 1105 1106#define mmTPC4_CFG_QM_TENSOR_15_PADDING_VALUE 0xF06D50 1107 1108#define mmTPC4_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF06D54 1109 1110#define mmTPC4_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF06D58 1111 1112#define mmTPC4_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF06D5C 1113 1114#define mmTPC4_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF06D60 1115 1116#define mmTPC4_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF06D64 1117 1118#define mmTPC4_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF06D68 1119 1120#define mmTPC4_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF06D6C 1121 1122#define mmTPC4_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF06D70 1123 1124#define mmTPC4_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF06D74 1125 1126#define mmTPC4_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF06D78 1127 1128#define mmTPC4_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF06D7C 1129 1130#define mmTPC4_CFG_QM_SYNC_OBJECT_MESSAGE 0xF06D80 1131 1132#define mmTPC4_CFG_QM_SYNC_OBJECT_ADDR 0xF06D84 1133 1134#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF06D88 1135 1136#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF06D8C 1137 1138#define mmTPC4_CFG_QM_TID_BASE_DIM_0 0xF06D90 1139 1140#define mmTPC4_CFG_QM_TID_SIZE_DIM_0 0xF06D94 1141 1142#define mmTPC4_CFG_QM_TID_BASE_DIM_1 0xF06D98 1143 1144#define mmTPC4_CFG_QM_TID_SIZE_DIM_1 0xF06D9C 1145 1146#define mmTPC4_CFG_QM_TID_BASE_DIM_2 0xF06DA0 1147 1148#define mmTPC4_CFG_QM_TID_SIZE_DIM_2 0xF06DA4 1149 1150#define mmTPC4_CFG_QM_TID_BASE_DIM_3 0xF06DA8 1151 1152#define mmTPC4_CFG_QM_TID_SIZE_DIM_3 0xF06DAC 1153 1154#define mmTPC4_CFG_QM_TID_BASE_DIM_4 0xF06DB0 1155 1156#define mmTPC4_CFG_QM_TID_SIZE_DIM_4 0xF06DB4 1157 1158#define mmTPC4_CFG_QM_KERNEL_CONFIG 0xF06DB8 1159 1160#define mmTPC4_CFG_QM_KERNEL_ID 0xF06DBC 1161 1162#define mmTPC4_CFG_QM_SRF_0 0xF06DC0 1163 1164#define mmTPC4_CFG_QM_SRF_1 0xF06DC4 1165 1166#define mmTPC4_CFG_QM_SRF_2 0xF06DC8 1167 1168#define mmTPC4_CFG_QM_SRF_3 0xF06DCC 1169 1170#define mmTPC4_CFG_QM_SRF_4 0xF06DD0 1171 1172#define mmTPC4_CFG_QM_SRF_5 0xF06DD4 1173 1174#define mmTPC4_CFG_QM_SRF_6 0xF06DD8 1175 1176#define mmTPC4_CFG_QM_SRF_7 0xF06DDC 1177 1178#define mmTPC4_CFG_QM_SRF_8 0xF06DE0 1179 1180#define mmTPC4_CFG_QM_SRF_9 0xF06DE4 1181 1182#define mmTPC4_CFG_QM_SRF_10 0xF06DE8 1183 1184#define mmTPC4_CFG_QM_SRF_11 0xF06DEC 1185 1186#define mmTPC4_CFG_QM_SRF_12 0xF06DF0 1187 1188#define mmTPC4_CFG_QM_SRF_13 0xF06DF4 1189 1190#define mmTPC4_CFG_QM_SRF_14 0xF06DF8 1191 1192#define mmTPC4_CFG_QM_SRF_15 0xF06DFC 1193 1194#define mmTPC4_CFG_QM_SRF_16 0xF06E00 1195 1196#define mmTPC4_CFG_QM_SRF_17 0xF06E04 1197 1198#define mmTPC4_CFG_QM_SRF_18 0xF06E08 1199 1200#define mmTPC4_CFG_QM_SRF_19 0xF06E0C 1201 1202#define mmTPC4_CFG_QM_SRF_20 0xF06E10 1203 1204#define mmTPC4_CFG_QM_SRF_21 0xF06E14 1205 1206#define mmTPC4_CFG_QM_SRF_22 0xF06E18 1207 1208#define mmTPC4_CFG_QM_SRF_23 0xF06E1C 1209 1210#define mmTPC4_CFG_QM_SRF_24 0xF06E20 1211 1212#define mmTPC4_CFG_QM_SRF_25 0xF06E24 1213 1214#define mmTPC4_CFG_QM_SRF_26 0xF06E28 1215 1216#define mmTPC4_CFG_QM_SRF_27 0xF06E2C 1217 1218#define mmTPC4_CFG_QM_SRF_28 0xF06E30 1219 1220#define mmTPC4_CFG_QM_SRF_29 0xF06E34 1221 1222#define mmTPC4_CFG_QM_SRF_30 0xF06E38 1223 1224#define mmTPC4_CFG_QM_SRF_31 0xF06E3C 1225 1226#endif /* ASIC_REG_TPC4_CFG_REGS_H_ */
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