FILE
tpc2_qm_regs.h
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linux-6.19.14/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_TPC2_QM_REGS_H_ 14#define ASIC_REG_TPC2_QM_REGS_H_ 15 16/* 17 ***************************************** 18 * TPC2_QM (Prototype: QMAN) 19 ***************************************** 20 */ 21 22#define mmTPC2_QM_GLBL_CFG0 0xE88000 23 24#define mmTPC2_QM_GLBL_CFG1 0xE88004 25 26#define mmTPC2_QM_GLBL_PROT 0xE88008 27 28#define mmTPC2_QM_GLBL_ERR_CFG 0xE8800C 29 30#define mmTPC2_QM_GLBL_SECURE_PROPS_0 0xE88010 31 32#define mmTPC2_QM_GLBL_SECURE_PROPS_1 0xE88014 33 34#define mmTPC2_QM_GLBL_SECURE_PROPS_2 0xE88018 35 36#define mmTPC2_QM_GLBL_SECURE_PROPS_3 0xE8801C 37 38#define mmTPC2_QM_GLBL_SECURE_PROPS_4 0xE88020 39 40#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_0 0xE88024 41 42#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_1 0xE88028 43 44#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_2 0xE8802C 45 46#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_3 0xE88030 47 48#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_4 0xE88034 49 50#define mmTPC2_QM_GLBL_STS0 0xE88038 51 52#define mmTPC2_QM_GLBL_STS1_0 0xE88040 53 54#define mmTPC2_QM_GLBL_STS1_1 0xE88044 55 56#define mmTPC2_QM_GLBL_STS1_2 0xE88048 57 58#define mmTPC2_QM_GLBL_STS1_3 0xE8804C 59 60#define mmTPC2_QM_GLBL_STS1_4 0xE88050 61 62#define mmTPC2_QM_GLBL_MSG_EN_0 0xE88054 63 64#define mmTPC2_QM_GLBL_MSG_EN_1 0xE88058 65 66#define mmTPC2_QM_GLBL_MSG_EN_2 0xE8805C 67 68#define mmTPC2_QM_GLBL_MSG_EN_3 0xE88060 69 70#define mmTPC2_QM_GLBL_MSG_EN_4 0xE88068 71 72#define mmTPC2_QM_PQ_BASE_LO_0 0xE88070 73 74#define mmTPC2_QM_PQ_BASE_LO_1 0xE88074 75 76#define mmTPC2_QM_PQ_BASE_LO_2 0xE88078 77 78#define mmTPC2_QM_PQ_BASE_LO_3 0xE8807C 79 80#define mmTPC2_QM_PQ_BASE_HI_0 0xE88080 81 82#define mmTPC2_QM_PQ_BASE_HI_1 0xE88084 83 84#define mmTPC2_QM_PQ_BASE_HI_2 0xE88088 85 86#define mmTPC2_QM_PQ_BASE_HI_3 0xE8808C 87 88#define mmTPC2_QM_PQ_SIZE_0 0xE88090 89 90#define mmTPC2_QM_PQ_SIZE_1 0xE88094 91 92#define mmTPC2_QM_PQ_SIZE_2 0xE88098 93 94#define mmTPC2_QM_PQ_SIZE_3 0xE8809C 95 96#define mmTPC2_QM_PQ_PI_0 0xE880A0 97 98#define mmTPC2_QM_PQ_PI_1 0xE880A4 99 100#define mmTPC2_QM_PQ_PI_2 0xE880A8 101 102#define mmTPC2_QM_PQ_PI_3 0xE880AC 103 104#define mmTPC2_QM_PQ_CI_0 0xE880B0 105 106#define mmTPC2_QM_PQ_CI_1 0xE880B4 107 108#define mmTPC2_QM_PQ_CI_2 0xE880B8 109 110#define mmTPC2_QM_PQ_CI_3 0xE880BC 111 112#define mmTPC2_QM_PQ_CFG0_0 0xE880C0 113 114#define mmTPC2_QM_PQ_CFG0_1 0xE880C4 115 116#define mmTPC2_QM_PQ_CFG0_2 0xE880C8 117 118#define mmTPC2_QM_PQ_CFG0_3 0xE880CC 119 120#define mmTPC2_QM_PQ_CFG1_0 0xE880D0 121 122#define mmTPC2_QM_PQ_CFG1_1 0xE880D4 123 124#define mmTPC2_QM_PQ_CFG1_2 0xE880D8 125 126#define mmTPC2_QM_PQ_CFG1_3 0xE880DC 127 128#define mmTPC2_QM_PQ_ARUSER_31_11_0 0xE880E0 129 130#define mmTPC2_QM_PQ_ARUSER_31_11_1 0xE880E4 131 132#define mmTPC2_QM_PQ_ARUSER_31_11_2 0xE880E8 133 134#define mmTPC2_QM_PQ_ARUSER_31_11_3 0xE880EC 135 136#define mmTPC2_QM_PQ_STS0_0 0xE880F0 137 138#define mmTPC2_QM_PQ_STS0_1 0xE880F4 139 140#define mmTPC2_QM_PQ_STS0_2 0xE880F8 141 142#define mmTPC2_QM_PQ_STS0_3 0xE880FC 143 144#define mmTPC2_QM_PQ_STS1_0 0xE88100 145 146#define mmTPC2_QM_PQ_STS1_1 0xE88104 147 148#define mmTPC2_QM_PQ_STS1_2 0xE88108 149 150#define mmTPC2_QM_PQ_STS1_3 0xE8810C 151 152#define mmTPC2_QM_CQ_CFG0_0 0xE88110 153 154#define mmTPC2_QM_CQ_CFG0_1 0xE88114 155 156#define mmTPC2_QM_CQ_CFG0_2 0xE88118 157 158#define mmTPC2_QM_CQ_CFG0_3 0xE8811C 159 160#define mmTPC2_QM_CQ_CFG0_4 0xE88120 161 162#define mmTPC2_QM_CQ_CFG1_0 0xE88124 163 164#define mmTPC2_QM_CQ_CFG1_1 0xE88128 165 166#define mmTPC2_QM_CQ_CFG1_2 0xE8812C 167 168#define mmTPC2_QM_CQ_CFG1_3 0xE88130 169 170#define mmTPC2_QM_CQ_CFG1_4 0xE88134 171 172#define mmTPC2_QM_CQ_ARUSER_31_11_0 0xE88138 173 174#define mmTPC2_QM_CQ_ARUSER_31_11_1 0xE8813C 175 176#define mmTPC2_QM_CQ_ARUSER_31_11_2 0xE88140 177 178#define mmTPC2_QM_CQ_ARUSER_31_11_3 0xE88144 179 180#define mmTPC2_QM_CQ_ARUSER_31_11_4 0xE88148 181 182#define mmTPC2_QM_CQ_STS0_0 0xE8814C 183 184#define mmTPC2_QM_CQ_STS0_1 0xE88150 185 186#define mmTPC2_QM_CQ_STS0_2 0xE88154 187 188#define mmTPC2_QM_CQ_STS0_3 0xE88158 189 190#define mmTPC2_QM_CQ_STS0_4 0xE8815C 191 192#define mmTPC2_QM_CQ_STS1_0 0xE88160 193 194#define mmTPC2_QM_CQ_STS1_1 0xE88164 195 196#define mmTPC2_QM_CQ_STS1_2 0xE88168 197 198#define mmTPC2_QM_CQ_STS1_3 0xE8816C 199 200#define mmTPC2_QM_CQ_STS1_4 0xE88170 201 202#define mmTPC2_QM_CQ_PTR_LO_0 0xE88174 203 204#define mmTPC2_QM_CQ_PTR_HI_0 0xE88178 205 206#define mmTPC2_QM_CQ_TSIZE_0 0xE8817C 207 208#define mmTPC2_QM_CQ_CTL_0 0xE88180 209 210#define mmTPC2_QM_CQ_PTR_LO_1 0xE88184 211 212#define mmTPC2_QM_CQ_PTR_HI_1 0xE88188 213 214#define mmTPC2_QM_CQ_TSIZE_1 0xE8818C 215 216#define mmTPC2_QM_CQ_CTL_1 0xE88190 217 218#define mmTPC2_QM_CQ_PTR_LO_2 0xE88194 219 220#define mmTPC2_QM_CQ_PTR_HI_2 0xE88198 221 222#define mmTPC2_QM_CQ_TSIZE_2 0xE8819C 223 224#define mmTPC2_QM_CQ_CTL_2 0xE881A0 225 226#define mmTPC2_QM_CQ_PTR_LO_3 0xE881A4 227 228#define mmTPC2_QM_CQ_PTR_HI_3 0xE881A8 229 230#define mmTPC2_QM_CQ_TSIZE_3 0xE881AC 231 232#define mmTPC2_QM_CQ_CTL_3 0xE881B0 233 234#define mmTPC2_QM_CQ_PTR_LO_4 0xE881B4 235 236#define mmTPC2_QM_CQ_PTR_HI_4 0xE881B8 237 238#define mmTPC2_QM_CQ_TSIZE_4 0xE881BC 239 240#define mmTPC2_QM_CQ_CTL_4 0xE881C0 241 242#define mmTPC2_QM_CQ_PTR_LO_STS_0 0xE881C4 243 244#define mmTPC2_QM_CQ_PTR_LO_STS_1 0xE881C8 245 246#define mmTPC2_QM_CQ_PTR_LO_STS_2 0xE881CC 247 248#define mmTPC2_QM_CQ_PTR_LO_STS_3 0xE881D0 249 250#define mmTPC2_QM_CQ_PTR_LO_STS_4 0xE881D4 251 252#define mmTPC2_QM_CQ_PTR_HI_STS_0 0xE881D8 253 254#define mmTPC2_QM_CQ_PTR_HI_STS_1 0xE881DC 255 256#define mmTPC2_QM_CQ_PTR_HI_STS_2 0xE881E0 257 258#define mmTPC2_QM_CQ_PTR_HI_STS_3 0xE881E4 259 260#define mmTPC2_QM_CQ_PTR_HI_STS_4 0xE881E8 261 262#define mmTPC2_QM_CQ_TSIZE_STS_0 0xE881EC 263 264#define mmTPC2_QM_CQ_TSIZE_STS_1 0xE881F0 265 266#define mmTPC2_QM_CQ_TSIZE_STS_2 0xE881F4 267 268#define mmTPC2_QM_CQ_TSIZE_STS_3 0xE881F8 269 270#define mmTPC2_QM_CQ_TSIZE_STS_4 0xE881FC 271 272#define mmTPC2_QM_CQ_CTL_STS_0 0xE88200 273 274#define mmTPC2_QM_CQ_CTL_STS_1 0xE88204 275 276#define mmTPC2_QM_CQ_CTL_STS_2 0xE88208 277 278#define mmTPC2_QM_CQ_CTL_STS_3 0xE8820C 279 280#define mmTPC2_QM_CQ_CTL_STS_4 0xE88210 281 282#define mmTPC2_QM_CQ_IFIFO_CNT_0 0xE88214 283 284#define mmTPC2_QM_CQ_IFIFO_CNT_1 0xE88218 285 286#define mmTPC2_QM_CQ_IFIFO_CNT_2 0xE8821C 287 288#define mmTPC2_QM_CQ_IFIFO_CNT_3 0xE88220 289 290#define mmTPC2_QM_CQ_IFIFO_CNT_4 0xE88224 291 292#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_0 0xE88228 293 294#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_1 0xE8822C 295 296#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_2 0xE88230 297 298#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_3 0xE88234 299 300#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_4 0xE88238 301 302#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_0 0xE8823C 303 304#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_1 0xE88240 305 306#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_2 0xE88244 307 308#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_3 0xE88248 309 310#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_4 0xE8824C 311 312#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_0 0xE88250 313 314#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_1 0xE88254 315 316#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_2 0xE88258 317 318#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_3 0xE8825C 319 320#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_4 0xE88260 321 322#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_0 0xE88264 323 324#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_1 0xE88268 325 326#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_2 0xE8826C 327 328#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_3 0xE88270 329 330#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_4 0xE88274 331 332#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_0 0xE88278 333 334#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_1 0xE8827C 335 336#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 0xE88280 337 338#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_3 0xE88284 339 340#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_4 0xE88288 341 342#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_0 0xE8828C 343 344#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_1 0xE88290 345 346#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_2 0xE88294 347 348#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_3 0xE88298 349 350#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_4 0xE8829C 351 352#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_0 0xE882A0 353 354#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_1 0xE882A4 355 356#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_2 0xE882A8 357 358#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_3 0xE882AC 359 360#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_4 0xE882B0 361 362#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_0 0xE882B4 363 364#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_1 0xE882B8 365 366#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_2 0xE882BC 367 368#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_3 0xE882C0 369 370#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_4 0xE882C4 371 372#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_0 0xE882C8 373 374#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_1 0xE882CC 375 376#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_2 0xE882D0 377 378#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_3 0xE882D4 379 380#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_4 0xE882D8 381 382#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE882E0 383 384#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE882E4 385 386#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE882E8 387 388#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE882EC 389 390#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE882F0 391 392#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE882F4 393 394#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE882F8 395 396#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE882FC 397 398#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE88300 399 400#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE88304 401 402#define mmTPC2_QM_CP_FENCE0_RDATA_0 0xE88308 403 404#define mmTPC2_QM_CP_FENCE0_RDATA_1 0xE8830C 405 406#define mmTPC2_QM_CP_FENCE0_RDATA_2 0xE88310 407 408#define mmTPC2_QM_CP_FENCE0_RDATA_3 0xE88314 409 410#define mmTPC2_QM_CP_FENCE0_RDATA_4 0xE88318 411 412#define mmTPC2_QM_CP_FENCE1_RDATA_0 0xE8831C 413 414#define mmTPC2_QM_CP_FENCE1_RDATA_1 0xE88320 415 416#define mmTPC2_QM_CP_FENCE1_RDATA_2 0xE88324 417 418#define mmTPC2_QM_CP_FENCE1_RDATA_3 0xE88328 419 420#define mmTPC2_QM_CP_FENCE1_RDATA_4 0xE8832C 421 422#define mmTPC2_QM_CP_FENCE2_RDATA_0 0xE88330 423 424#define mmTPC2_QM_CP_FENCE2_RDATA_1 0xE88334 425 426#define mmTPC2_QM_CP_FENCE2_RDATA_2 0xE88338 427 428#define mmTPC2_QM_CP_FENCE2_RDATA_3 0xE8833C 429 430#define mmTPC2_QM_CP_FENCE2_RDATA_4 0xE88340 431 432#define mmTPC2_QM_CP_FENCE3_RDATA_0 0xE88344 433 434#define mmTPC2_QM_CP_FENCE3_RDATA_1 0xE88348 435 436#define mmTPC2_QM_CP_FENCE3_RDATA_2 0xE8834C 437 438#define mmTPC2_QM_CP_FENCE3_RDATA_3 0xE88350 439 440#define mmTPC2_QM_CP_FENCE3_RDATA_4 0xE88354 441 442#define mmTPC2_QM_CP_FENCE0_CNT_0 0xE88358 443 444#define mmTPC2_QM_CP_FENCE0_CNT_1 0xE8835C 445 446#define mmTPC2_QM_CP_FENCE0_CNT_2 0xE88360 447 448#define mmTPC2_QM_CP_FENCE0_CNT_3 0xE88364 449 450#define mmTPC2_QM_CP_FENCE0_CNT_4 0xE88368 451 452#define mmTPC2_QM_CP_FENCE1_CNT_0 0xE8836C 453 454#define mmTPC2_QM_CP_FENCE1_CNT_1 0xE88370 455 456#define mmTPC2_QM_CP_FENCE1_CNT_2 0xE88374 457 458#define mmTPC2_QM_CP_FENCE1_CNT_3 0xE88378 459 460#define mmTPC2_QM_CP_FENCE1_CNT_4 0xE8837C 461 462#define mmTPC2_QM_CP_FENCE2_CNT_0 0xE88380 463 464#define mmTPC2_QM_CP_FENCE2_CNT_1 0xE88384 465 466#define mmTPC2_QM_CP_FENCE2_CNT_2 0xE88388 467 468#define mmTPC2_QM_CP_FENCE2_CNT_3 0xE8838C 469 470#define mmTPC2_QM_CP_FENCE2_CNT_4 0xE88390 471 472#define mmTPC2_QM_CP_FENCE3_CNT_0 0xE88394 473 474#define mmTPC2_QM_CP_FENCE3_CNT_1 0xE88398 475 476#define mmTPC2_QM_CP_FENCE3_CNT_2 0xE8839C 477 478#define mmTPC2_QM_CP_FENCE3_CNT_3 0xE883A0 479 480#define mmTPC2_QM_CP_FENCE3_CNT_4 0xE883A4 481 482#define mmTPC2_QM_CP_STS_0 0xE883A8 483 484#define mmTPC2_QM_CP_STS_1 0xE883AC 485 486#define mmTPC2_QM_CP_STS_2 0xE883B0 487 488#define mmTPC2_QM_CP_STS_3 0xE883B4 489 490#define mmTPC2_QM_CP_STS_4 0xE883B8 491 492#define mmTPC2_QM_CP_CURRENT_INST_LO_0 0xE883BC 493 494#define mmTPC2_QM_CP_CURRENT_INST_LO_1 0xE883C0 495 496#define mmTPC2_QM_CP_CURRENT_INST_LO_2 0xE883C4 497 498#define mmTPC2_QM_CP_CURRENT_INST_LO_3 0xE883C8 499 500#define mmTPC2_QM_CP_CURRENT_INST_LO_4 0xE883CC 501 502#define mmTPC2_QM_CP_CURRENT_INST_HI_0 0xE883D0 503 504#define mmTPC2_QM_CP_CURRENT_INST_HI_1 0xE883D4 505 506#define mmTPC2_QM_CP_CURRENT_INST_HI_2 0xE883D8 507 508#define mmTPC2_QM_CP_CURRENT_INST_HI_3 0xE883DC 509 510#define mmTPC2_QM_CP_CURRENT_INST_HI_4 0xE883E0 511 512#define mmTPC2_QM_CP_BARRIER_CFG_0 0xE883F4 513 514#define mmTPC2_QM_CP_BARRIER_CFG_1 0xE883F8 515 516#define mmTPC2_QM_CP_BARRIER_CFG_2 0xE883FC 517 518#define mmTPC2_QM_CP_BARRIER_CFG_3 0xE88400 519 520#define mmTPC2_QM_CP_BARRIER_CFG_4 0xE88404 521 522#define mmTPC2_QM_CP_DBG_0_0 0xE88408 523 524#define mmTPC2_QM_CP_DBG_0_1 0xE8840C 525 526#define mmTPC2_QM_CP_DBG_0_2 0xE88410 527 528#define mmTPC2_QM_CP_DBG_0_3 0xE88414 529 530#define mmTPC2_QM_CP_DBG_0_4 0xE88418 531 532#define mmTPC2_QM_CP_ARUSER_31_11_0 0xE8841C 533 534#define mmTPC2_QM_CP_ARUSER_31_11_1 0xE88420 535 536#define mmTPC2_QM_CP_ARUSER_31_11_2 0xE88424 537 538#define mmTPC2_QM_CP_ARUSER_31_11_3 0xE88428 539 540#define mmTPC2_QM_CP_ARUSER_31_11_4 0xE8842C 541 542#define mmTPC2_QM_CP_AWUSER_31_11_0 0xE88430 543 544#define mmTPC2_QM_CP_AWUSER_31_11_1 0xE88434 545 546#define mmTPC2_QM_CP_AWUSER_31_11_2 0xE88438 547 548#define mmTPC2_QM_CP_AWUSER_31_11_3 0xE8843C 549 550#define mmTPC2_QM_CP_AWUSER_31_11_4 0xE88440 551 552#define mmTPC2_QM_ARB_CFG_0 0xE88A00 553 554#define mmTPC2_QM_ARB_CHOISE_Q_PUSH 0xE88A04 555 556#define mmTPC2_QM_ARB_WRR_WEIGHT_0 0xE88A08 557 558#define mmTPC2_QM_ARB_WRR_WEIGHT_1 0xE88A0C 559 560#define mmTPC2_QM_ARB_WRR_WEIGHT_2 0xE88A10 561 562#define mmTPC2_QM_ARB_WRR_WEIGHT_3 0xE88A14 563 564#define mmTPC2_QM_ARB_CFG_1 0xE88A18 565 566#define mmTPC2_QM_ARB_MST_AVAIL_CRED_0 0xE88A20 567 568#define mmTPC2_QM_ARB_MST_AVAIL_CRED_1 0xE88A24 569 570#define mmTPC2_QM_ARB_MST_AVAIL_CRED_2 0xE88A28 571 572#define mmTPC2_QM_ARB_MST_AVAIL_CRED_3 0xE88A2C 573 574#define mmTPC2_QM_ARB_MST_AVAIL_CRED_4 0xE88A30 575 576#define mmTPC2_QM_ARB_MST_AVAIL_CRED_5 0xE88A34 577 578#define mmTPC2_QM_ARB_MST_AVAIL_CRED_6 0xE88A38 579 580#define mmTPC2_QM_ARB_MST_AVAIL_CRED_7 0xE88A3C 581 582#define mmTPC2_QM_ARB_MST_AVAIL_CRED_8 0xE88A40 583 584#define mmTPC2_QM_ARB_MST_AVAIL_CRED_9 0xE88A44 585 586#define mmTPC2_QM_ARB_MST_AVAIL_CRED_10 0xE88A48 587 588#define mmTPC2_QM_ARB_MST_AVAIL_CRED_11 0xE88A4C 589 590#define mmTPC2_QM_ARB_MST_AVAIL_CRED_12 0xE88A50 591 592#define mmTPC2_QM_ARB_MST_AVAIL_CRED_13 0xE88A54 593 594#define mmTPC2_QM_ARB_MST_AVAIL_CRED_14 0xE88A58 595 596#define mmTPC2_QM_ARB_MST_AVAIL_CRED_15 0xE88A5C 597 598#define mmTPC2_QM_ARB_MST_AVAIL_CRED_16 0xE88A60 599 600#define mmTPC2_QM_ARB_MST_AVAIL_CRED_17 0xE88A64 601 602#define mmTPC2_QM_ARB_MST_AVAIL_CRED_18 0xE88A68 603 604#define mmTPC2_QM_ARB_MST_AVAIL_CRED_19 0xE88A6C 605 606#define mmTPC2_QM_ARB_MST_AVAIL_CRED_20 0xE88A70 607 608#define mmTPC2_QM_ARB_MST_AVAIL_CRED_21 0xE88A74 609 610#define mmTPC2_QM_ARB_MST_AVAIL_CRED_22 0xE88A78 611 612#define mmTPC2_QM_ARB_MST_AVAIL_CRED_23 0xE88A7C 613 614#define mmTPC2_QM_ARB_MST_AVAIL_CRED_24 0xE88A80 615 616#define mmTPC2_QM_ARB_MST_AVAIL_CRED_25 0xE88A84 617 618#define mmTPC2_QM_ARB_MST_AVAIL_CRED_26 0xE88A88 619 620#define mmTPC2_QM_ARB_MST_AVAIL_CRED_27 0xE88A8C 621 622#define mmTPC2_QM_ARB_MST_AVAIL_CRED_28 0xE88A90 623 624#define mmTPC2_QM_ARB_MST_AVAIL_CRED_29 0xE88A94 625 626#define mmTPC2_QM_ARB_MST_AVAIL_CRED_30 0xE88A98 627 628#define mmTPC2_QM_ARB_MST_AVAIL_CRED_31 0xE88A9C 629 630#define mmTPC2_QM_ARB_MST_CRED_INC 0xE88AA0 631 632#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE88AA4 633 634#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE88AA8 635 636#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE88AAC 637 638#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE88AB0 639 640#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE88AB4 641 642#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE88AB8 643 644#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE88ABC 645 646#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE88AC0 647 648#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE88AC4 649 650#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE88AC8 651 652#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE88ACC 653 654#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE88AD0 655 656#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE88AD4 657 658#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE88AD8 659 660#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE88ADC 661 662#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE88AE0 663 664#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE88AE4 665 666#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE88AE8 667 668#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE88AEC 669 670#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE88AF0 671 672#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE88AF4 673 674#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE88AF8 675 676#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE88AFC 677 678#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE88B00 679 680#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE88B04 681 682#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE88B08 683 684#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE88B0C 685 686#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE88B10 687 688#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE88B14 689 690#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE88B18 691 692#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE88B1C 693 694#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE88B20 695 696#define mmTPC2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE88B28 697 698#define mmTPC2_QM_ARB_MST_SLAVE_EN 0xE88B2C 699 700#define mmTPC2_QM_ARB_MST_QUIET_PER 0xE88B34 701 702#define mmTPC2_QM_ARB_SLV_CHOISE_WDT 0xE88B38 703 704#define mmTPC2_QM_ARB_SLV_ID 0xE88B3C 705 706#define mmTPC2_QM_ARB_MSG_MAX_INFLIGHT 0xE88B44 707 708#define mmTPC2_QM_ARB_MSG_AWUSER_31_11 0xE88B48 709 710#define mmTPC2_QM_ARB_MSG_AWUSER_SEC_PROP 0xE88B4C 711 712#define mmTPC2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE88B50 713 714#define mmTPC2_QM_ARB_BASE_LO 0xE88B54 715 716#define mmTPC2_QM_ARB_BASE_HI 0xE88B58 717 718#define mmTPC2_QM_ARB_STATE_STS 0xE88B80 719 720#define mmTPC2_QM_ARB_CHOISE_FULLNESS_STS 0xE88B84 721 722#define mmTPC2_QM_ARB_MSG_STS 0xE88B88 723 724#define mmTPC2_QM_ARB_SLV_CHOISE_Q_HEAD 0xE88B8C 725 726#define mmTPC2_QM_ARB_ERR_CAUSE 0xE88B9C 727 728#define mmTPC2_QM_ARB_ERR_MSG_EN 0xE88BA0 729 730#define mmTPC2_QM_ARB_ERR_STS_DRP 0xE88BA8 731 732#define mmTPC2_QM_ARB_MST_CRED_STS_0 0xE88BB0 733 734#define mmTPC2_QM_ARB_MST_CRED_STS_1 0xE88BB4 735 736#define mmTPC2_QM_ARB_MST_CRED_STS_2 0xE88BB8 737 738#define mmTPC2_QM_ARB_MST_CRED_STS_3 0xE88BBC 739 740#define mmTPC2_QM_ARB_MST_CRED_STS_4 0xE88BC0 741 742#define mmTPC2_QM_ARB_MST_CRED_STS_5 0xE88BC4 743 744#define mmTPC2_QM_ARB_MST_CRED_STS_6 0xE88BC8 745 746#define mmTPC2_QM_ARB_MST_CRED_STS_7 0xE88BCC 747 748#define mmTPC2_QM_ARB_MST_CRED_STS_8 0xE88BD0 749 750#define mmTPC2_QM_ARB_MST_CRED_STS_9 0xE88BD4 751 752#define mmTPC2_QM_ARB_MST_CRED_STS_10 0xE88BD8 753 754#define mmTPC2_QM_ARB_MST_CRED_STS_11 0xE88BDC 755 756#define mmTPC2_QM_ARB_MST_CRED_STS_12 0xE88BE0 757 758#define mmTPC2_QM_ARB_MST_CRED_STS_13 0xE88BE4 759 760#define mmTPC2_QM_ARB_MST_CRED_STS_14 0xE88BE8 761 762#define mmTPC2_QM_ARB_MST_CRED_STS_15 0xE88BEC 763 764#define mmTPC2_QM_ARB_MST_CRED_STS_16 0xE88BF0 765 766#define mmTPC2_QM_ARB_MST_CRED_STS_17 0xE88BF4 767 768#define mmTPC2_QM_ARB_MST_CRED_STS_18 0xE88BF8 769 770#define mmTPC2_QM_ARB_MST_CRED_STS_19 0xE88BFC 771 772#define mmTPC2_QM_ARB_MST_CRED_STS_20 0xE88C00 773 774#define mmTPC2_QM_ARB_MST_CRED_STS_21 0xE88C04 775 776#define mmTPC2_QM_ARB_MST_CRED_STS_22 0xE88C08 777 778#define mmTPC2_QM_ARB_MST_CRED_STS_23 0xE88C0C 779 780#define mmTPC2_QM_ARB_MST_CRED_STS_24 0xE88C10 781 782#define mmTPC2_QM_ARB_MST_CRED_STS_25 0xE88C14 783 784#define mmTPC2_QM_ARB_MST_CRED_STS_26 0xE88C18 785 786#define mmTPC2_QM_ARB_MST_CRED_STS_27 0xE88C1C 787 788#define mmTPC2_QM_ARB_MST_CRED_STS_28 0xE88C20 789 790#define mmTPC2_QM_ARB_MST_CRED_STS_29 0xE88C24 791 792#define mmTPC2_QM_ARB_MST_CRED_STS_30 0xE88C28 793 794#define mmTPC2_QM_ARB_MST_CRED_STS_31 0xE88C2C 795 796#define mmTPC2_QM_CGM_CFG 0xE88C70 797 798#define mmTPC2_QM_CGM_STS 0xE88C74 799 800#define mmTPC2_QM_CGM_CFG1 0xE88C78 801 802#define mmTPC2_QM_LOCAL_RANGE_BASE 0xE88C80 803 804#define mmTPC2_QM_LOCAL_RANGE_SIZE 0xE88C84 805 806#define mmTPC2_QM_CSMR_STRICT_PRIO_CFG 0xE88C90 807 808#define mmTPC2_QM_HBW_RD_RATE_LIM_CFG_1 0xE88C94 809 810#define mmTPC2_QM_LBW_WR_RATE_LIM_CFG_0 0xE88C98 811 812#define mmTPC2_QM_LBW_WR_RATE_LIM_CFG_1 0xE88C9C 813 814#define mmTPC2_QM_HBW_RD_RATE_LIM_CFG_0 0xE88CA0 815 816#define mmTPC2_QM_GLBL_AXCACHE 0xE88CA4 817 818#define mmTPC2_QM_IND_GW_APB_CFG 0xE88CB0 819 820#define mmTPC2_QM_IND_GW_APB_WDATA 0xE88CB4 821 822#define mmTPC2_QM_IND_GW_APB_RDATA 0xE88CB8 823 824#define mmTPC2_QM_IND_GW_APB_STATUS 0xE88CBC 825 826#define mmTPC2_QM_GLBL_ERR_ADDR_LO 0xE88CD0 827 828#define mmTPC2_QM_GLBL_ERR_ADDR_HI 0xE88CD4 829 830#define mmTPC2_QM_GLBL_ERR_WDATA 0xE88CD8 831 832#define mmTPC2_QM_GLBL_MEM_INIT_BUSY 0xE88D00 833 834#endif /* ASIC_REG_TPC2_QM_REGS_H_ */
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