FILE
tpc2_cfg_regs.h
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linux-6.19.14/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_TPC2_CFG_REGS_H_ 14#define ASIC_REG_TPC2_CFG_REGS_H_ 15 16/* 17 ***************************************** 18 * TPC2_CFG (Prototype: TPC) 19 ***************************************** 20 */ 21 22#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE86400 23 24#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE86404 25 26#define mmTPC2_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE86408 27 28#define mmTPC2_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE8640C 29 30#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE86410 31 32#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE86414 33 34#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE86418 35 36#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE8641C 37 38#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE86420 39 40#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE86424 41 42#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE86428 43 44#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE8642C 45 46#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE86430 47 48#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE86434 49 50#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE86438 51 52#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE8643C 53 54#define mmTPC2_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE86440 55 56#define mmTPC2_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE86444 57 58#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE86448 59 60#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE8644C 61 62#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE86450 63 64#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE86454 65 66#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE86458 67 68#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE8645C 69 70#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE86460 71 72#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE86464 73 74#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE86468 75 76#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE8646C 77 78#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE86470 79 80#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE86474 81 82#define mmTPC2_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE86478 83 84#define mmTPC2_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE8647C 85 86#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE86480 87 88#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE86484 89 90#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE86488 91 92#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE8648C 93 94#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE86490 95 96#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE86494 97 98#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE86498 99 100#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE8649C 101 102#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE864A0 103 104#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE864A4 105 106#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE864A8 107 108#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE864AC 109 110#define mmTPC2_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE864B0 111 112#define mmTPC2_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE864B4 113 114#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE864B8 115 116#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE864BC 117 118#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE864C0 119 120#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE864C4 121 122#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE864C8 123 124#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE864CC 125 126#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE864D0 127 128#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE864D4 129 130#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE864D8 131 132#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE864DC 133 134#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE864E0 135 136#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE864E4 137 138#define mmTPC2_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE864E8 139 140#define mmTPC2_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE864EC 141 142#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE864F0 143 144#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE864F4 145 146#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE864F8 147 148#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE864FC 149 150#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE86500 151 152#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE86504 153 154#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE86508 155 156#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE8650C 157 158#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE86510 159 160#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE86514 161 162#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE86518 163 164#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE8651C 165 166#define mmTPC2_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE86520 167 168#define mmTPC2_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE86524 169 170#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE86528 171 172#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE8652C 173 174#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE86530 175 176#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE86534 177 178#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE86538 179 180#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE8653C 181 182#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE86540 183 184#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE86544 185 186#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE86548 187 188#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE8654C 189 190#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE86550 191 192#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE86554 193 194#define mmTPC2_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE86558 195 196#define mmTPC2_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE8655C 197 198#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE86560 199 200#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE86564 201 202#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE86568 203 204#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE8656C 205 206#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE86570 207 208#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE86574 209 210#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE86578 211 212#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE8657C 213 214#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE86580 215 216#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE86584 217 218#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE86588 219 220#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE8658C 221 222#define mmTPC2_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE86590 223 224#define mmTPC2_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE86594 225 226#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE86598 227 228#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE8659C 229 230#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE865A0 231 232#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE865A4 233 234#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE865A8 235 236#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE865AC 237 238#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE865B0 239 240#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE865B4 241 242#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE865B8 243 244#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE865BC 245 246#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE865C0 247 248#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE865C4 249 250#define mmTPC2_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE865C8 251 252#define mmTPC2_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE865CC 253 254#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE865D0 255 256#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE865D4 257 258#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE865D8 259 260#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE865DC 261 262#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE865E0 263 264#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE865E4 265 266#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE865E8 267 268#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE865EC 269 270#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE865F0 271 272#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE865F4 273 274#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE865F8 275 276#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE865FC 277 278#define mmTPC2_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE86600 279 280#define mmTPC2_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE86604 281 282#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE86608 283 284#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE8660C 285 286#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE86610 287 288#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE86614 289 290#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE86618 291 292#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE8661C 293 294#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE86620 295 296#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE86624 297 298#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE86628 299 300#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE8662C 301 302#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE86630 303 304#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE86634 305 306#define mmTPC2_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE86638 307 308#define mmTPC2_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE8663C 309 310#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE86640 311 312#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE86644 313 314#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE86648 315 316#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE8664C 317 318#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE86650 319 320#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE86654 321 322#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE86658 323 324#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE8665C 325 326#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE86660 327 328#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE86664 329 330#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE86668 331 332#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE8666C 333 334#define mmTPC2_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE86670 335 336#define mmTPC2_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE86674 337 338#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE86678 339 340#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE8667C 341 342#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE86680 343 344#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE86684 345 346#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE86688 347 348#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE8668C 349 350#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE86690 351 352#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE86694 353 354#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE86698 355 356#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE8669C 357 358#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE866A0 359 360#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE866A4 361 362#define mmTPC2_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE866A8 363 364#define mmTPC2_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE866AC 365 366#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE866B0 367 368#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE866B4 369 370#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE866B8 371 372#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE866BC 373 374#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE866C0 375 376#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE866C4 377 378#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE866C8 379 380#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE866CC 381 382#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE866D0 383 384#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE866D4 385 386#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE866D8 387 388#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE866DC 389 390#define mmTPC2_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE866E0 391 392#define mmTPC2_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE866E4 393 394#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE866E8 395 396#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE866EC 397 398#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE866F0 399 400#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE866F4 401 402#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE866F8 403 404#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE866FC 405 406#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE86700 407 408#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE86704 409 410#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE86708 411 412#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE8670C 413 414#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE86710 415 416#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE86714 417 418#define mmTPC2_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE86718 419 420#define mmTPC2_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE8671C 421 422#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE86720 423 424#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE86724 425 426#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE86728 427 428#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE8672C 429 430#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE86730 431 432#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE86734 433 434#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE86738 435 436#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE8673C 437 438#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE86740 439 440#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE86744 441 442#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE86748 443 444#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE8674C 445 446#define mmTPC2_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE86750 447 448#define mmTPC2_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE86754 449 450#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE86758 451 452#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE8675C 453 454#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE86760 455 456#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE86764 457 458#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE86768 459 460#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE8676C 461 462#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE86770 463 464#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE86774 465 466#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE86778 467 468#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE8677C 469 470#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE86780 471 472#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE86784 473 474#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE86788 475 476#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE8678C 477 478#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_0 0xE86790 479 480#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_0 0xE86794 481 482#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_1 0xE86798 483 484#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_1 0xE8679C 485 486#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_2 0xE867A0 487 488#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_2 0xE867A4 489 490#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_3 0xE867A8 491 492#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_3 0xE867AC 493 494#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_4 0xE867B0 495 496#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_4 0xE867B4 497 498#define mmTPC2_CFG_KERNEL_KERNEL_CONFIG 0xE867B8 499 500#define mmTPC2_CFG_KERNEL_KERNEL_ID 0xE867BC 501 502#define mmTPC2_CFG_KERNEL_SRF_0 0xE867C0 503 504#define mmTPC2_CFG_KERNEL_SRF_1 0xE867C4 505 506#define mmTPC2_CFG_KERNEL_SRF_2 0xE867C8 507 508#define mmTPC2_CFG_KERNEL_SRF_3 0xE867CC 509 510#define mmTPC2_CFG_KERNEL_SRF_4 0xE867D0 511 512#define mmTPC2_CFG_KERNEL_SRF_5 0xE867D4 513 514#define mmTPC2_CFG_KERNEL_SRF_6 0xE867D8 515 516#define mmTPC2_CFG_KERNEL_SRF_7 0xE867DC 517 518#define mmTPC2_CFG_KERNEL_SRF_8 0xE867E0 519 520#define mmTPC2_CFG_KERNEL_SRF_9 0xE867E4 521 522#define mmTPC2_CFG_KERNEL_SRF_10 0xE867E8 523 524#define mmTPC2_CFG_KERNEL_SRF_11 0xE867EC 525 526#define mmTPC2_CFG_KERNEL_SRF_12 0xE867F0 527 528#define mmTPC2_CFG_KERNEL_SRF_13 0xE867F4 529 530#define mmTPC2_CFG_KERNEL_SRF_14 0xE867F8 531 532#define mmTPC2_CFG_KERNEL_SRF_15 0xE867FC 533 534#define mmTPC2_CFG_KERNEL_SRF_16 0xE86800 535 536#define mmTPC2_CFG_KERNEL_SRF_17 0xE86804 537 538#define mmTPC2_CFG_KERNEL_SRF_18 0xE86808 539 540#define mmTPC2_CFG_KERNEL_SRF_19 0xE8680C 541 542#define mmTPC2_CFG_KERNEL_SRF_20 0xE86810 543 544#define mmTPC2_CFG_KERNEL_SRF_21 0xE86814 545 546#define mmTPC2_CFG_KERNEL_SRF_22 0xE86818 547 548#define mmTPC2_CFG_KERNEL_SRF_23 0xE8681C 549 550#define mmTPC2_CFG_KERNEL_SRF_24 0xE86820 551 552#define mmTPC2_CFG_KERNEL_SRF_25 0xE86824 553 554#define mmTPC2_CFG_KERNEL_SRF_26 0xE86828 555 556#define mmTPC2_CFG_KERNEL_SRF_27 0xE8682C 557 558#define mmTPC2_CFG_KERNEL_SRF_28 0xE86830 559 560#define mmTPC2_CFG_KERNEL_SRF_29 0xE86834 561 562#define mmTPC2_CFG_KERNEL_SRF_30 0xE86838 563 564#define mmTPC2_CFG_KERNEL_SRF_31 0xE8683C 565 566#define mmTPC2_CFG_ROUND_CSR 0xE868FC 567 568#define mmTPC2_CFG_PROT 0xE86900 569 570#define mmTPC2_CFG_SEMAPHORE 0xE86908 571 572#define mmTPC2_CFG_VFLAGS 0xE8690C 573 574#define mmTPC2_CFG_SFLAGS 0xE86910 575 576#define mmTPC2_CFG_LFSR_POLYNOM 0xE86918 577 578#define mmTPC2_CFG_STATUS 0xE8691C 579 580#define mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH 0xE86920 581 582#define mmTPC2_CFG_CFG_SUBTRACT_VALUE 0xE86924 583 584#define mmTPC2_CFG_SM_BASE_ADDRESS_HIGH 0xE8692C 585 586#define mmTPC2_CFG_TPC_CMD 0xE86930 587 588#define mmTPC2_CFG_TPC_EXECUTE 0xE86938 589 590#define mmTPC2_CFG_TPC_STALL 0xE8693C 591 592#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_LOW 0xE86940 593 594#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE86944 595 596#define mmTPC2_CFG_RD_RATE_LIMIT 0xE86948 597 598#define mmTPC2_CFG_WR_RATE_LIMIT 0xE86950 599 600#define mmTPC2_CFG_MSS_CONFIG 0xE86954 601 602#define mmTPC2_CFG_TPC_INTR_CAUSE 0xE86958 603 604#define mmTPC2_CFG_TPC_INTR_MASK 0xE8695C 605 606#define mmTPC2_CFG_WQ_CREDITS 0xE86960 607 608#define mmTPC2_CFG_ARUSER_LO 0xE86964 609 610#define mmTPC2_CFG_ARUSER_HI 0xE86968 611 612#define mmTPC2_CFG_AWUSER_LO 0xE8696C 613 614#define mmTPC2_CFG_AWUSER_HI 0xE86970 615 616#define mmTPC2_CFG_OPCODE_EXEC 0xE86974 617 618#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE86978 619 620#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE8697C 621 622#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE86980 623 624#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE86984 625 626#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE86988 627 628#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE8698C 629 630#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE86990 631 632#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE86994 633 634#define mmTPC2_CFG_TSB_CFG_MAX_SIZE 0xE86998 635 636#define mmTPC2_CFG_TSB_CFG 0xE8699C 637 638#define mmTPC2_CFG_DBGMEM_ADD 0xE869A0 639 640#define mmTPC2_CFG_DBGMEM_DATA_WR 0xE869A4 641 642#define mmTPC2_CFG_DBGMEM_DATA_RD 0xE869A8 643 644#define mmTPC2_CFG_DBGMEM_CTRL 0xE869AC 645 646#define mmTPC2_CFG_DBGMEM_RC 0xE869B0 647 648#define mmTPC2_CFG_TSB_INFLIGHT_CNTR 0xE869B4 649 650#define mmTPC2_CFG_WQ_INFLIGHT_CNTR 0xE869B8 651 652#define mmTPC2_CFG_WQ_LBW_TOTAL_CNTR 0xE869BC 653 654#define mmTPC2_CFG_WQ_HBW_TOTAL_CNTR 0xE869C0 655 656#define mmTPC2_CFG_IRQ_OCCOUPY_CNTR 0xE869C4 657 658#define mmTPC2_CFG_FUNC_MBIST_CNTRL 0xE869D0 659 660#define mmTPC2_CFG_FUNC_MBIST_PAT 0xE869D4 661 662#define mmTPC2_CFG_FUNC_MBIST_MEM_0 0xE869D8 663 664#define mmTPC2_CFG_FUNC_MBIST_MEM_1 0xE869DC 665 666#define mmTPC2_CFG_FUNC_MBIST_MEM_2 0xE869E0 667 668#define mmTPC2_CFG_FUNC_MBIST_MEM_3 0xE869E4 669 670#define mmTPC2_CFG_FUNC_MBIST_MEM_4 0xE869E8 671 672#define mmTPC2_CFG_FUNC_MBIST_MEM_5 0xE869EC 673 674#define mmTPC2_CFG_FUNC_MBIST_MEM_6 0xE869F0 675 676#define mmTPC2_CFG_FUNC_MBIST_MEM_7 0xE869F4 677 678#define mmTPC2_CFG_FUNC_MBIST_MEM_8 0xE869F8 679 680#define mmTPC2_CFG_FUNC_MBIST_MEM_9 0xE869FC 681 682#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE86A00 683 684#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE86A04 685 686#define mmTPC2_CFG_QM_TENSOR_0_PADDING_VALUE 0xE86A08 687 688#define mmTPC2_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE86A0C 689 690#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE86A10 691 692#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE86A14 693 694#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE86A18 695 696#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE86A1C 697 698#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE86A20 699 700#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE86A24 701 702#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE86A28 703 704#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE86A2C 705 706#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE86A30 707 708#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE86A34 709 710#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE86A38 711 712#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE86A3C 713 714#define mmTPC2_CFG_QM_TENSOR_1_PADDING_VALUE 0xE86A40 715 716#define mmTPC2_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE86A44 717 718#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE86A48 719 720#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE86A4C 721 722#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE86A50 723 724#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE86A54 725 726#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE86A58 727 728#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE86A5C 729 730#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE86A60 731 732#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE86A64 733 734#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE86A68 735 736#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE86A6C 737 738#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE86A70 739 740#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE86A74 741 742#define mmTPC2_CFG_QM_TENSOR_2_PADDING_VALUE 0xE86A78 743 744#define mmTPC2_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE86A7C 745 746#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE86A80 747 748#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE86A84 749 750#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE86A88 751 752#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE86A8C 753 754#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE86A90 755 756#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE86A94 757 758#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE86A98 759 760#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE86A9C 761 762#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE86AA0 763 764#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE86AA4 765 766#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE86AA8 767 768#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE86AAC 769 770#define mmTPC2_CFG_QM_TENSOR_3_PADDING_VALUE 0xE86AB0 771 772#define mmTPC2_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE86AB4 773 774#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE86AB8 775 776#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE86ABC 777 778#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE86AC0 779 780#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE86AC4 781 782#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE86AC8 783 784#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE86ACC 785 786#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE86AD0 787 788#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE86AD4 789 790#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE86AD8 791 792#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE86ADC 793 794#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE86AE0 795 796#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE86AE4 797 798#define mmTPC2_CFG_QM_TENSOR_4_PADDING_VALUE 0xE86AE8 799 800#define mmTPC2_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE86AEC 801 802#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE86AF0 803 804#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE86AF4 805 806#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE86AF8 807 808#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE86AFC 809 810#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE86B00 811 812#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE86B04 813 814#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE86B08 815 816#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE86B0C 817 818#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE86B10 819 820#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE86B14 821 822#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE86B18 823 824#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE86B1C 825 826#define mmTPC2_CFG_QM_TENSOR_5_PADDING_VALUE 0xE86B20 827 828#define mmTPC2_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE86B24 829 830#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE86B28 831 832#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE86B2C 833 834#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE86B30 835 836#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE86B34 837 838#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE86B38 839 840#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE86B3C 841 842#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE86B40 843 844#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE86B44 845 846#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE86B48 847 848#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE86B4C 849 850#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE86B50 851 852#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE86B54 853 854#define mmTPC2_CFG_QM_TENSOR_6_PADDING_VALUE 0xE86B58 855 856#define mmTPC2_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE86B5C 857 858#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE86B60 859 860#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE86B64 861 862#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE86B68 863 864#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE86B6C 865 866#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE86B70 867 868#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE86B74 869 870#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE86B78 871 872#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE86B7C 873 874#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE86B80 875 876#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE86B84 877 878#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE86B88 879 880#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE86B8C 881 882#define mmTPC2_CFG_QM_TENSOR_7_PADDING_VALUE 0xE86B90 883 884#define mmTPC2_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE86B94 885 886#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE86B98 887 888#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE86B9C 889 890#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE86BA0 891 892#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE86BA4 893 894#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE86BA8 895 896#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE86BAC 897 898#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE86BB0 899 900#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE86BB4 901 902#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE86BB8 903 904#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE86BBC 905 906#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE86BC0 907 908#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE86BC4 909 910#define mmTPC2_CFG_QM_TENSOR_8_PADDING_VALUE 0xE86BC8 911 912#define mmTPC2_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE86BCC 913 914#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE86BD0 915 916#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE86BD4 917 918#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE86BD8 919 920#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE86BDC 921 922#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE86BE0 923 924#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE86BE4 925 926#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE86BE8 927 928#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE86BEC 929 930#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE86BF0 931 932#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE86BF4 933 934#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE86BF8 935 936#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE86BFC 937 938#define mmTPC2_CFG_QM_TENSOR_9_PADDING_VALUE 0xE86C00 939 940#define mmTPC2_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE86C04 941 942#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE86C08 943 944#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE86C0C 945 946#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE86C10 947 948#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE86C14 949 950#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE86C18 951 952#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE86C1C 953 954#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE86C20 955 956#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE86C24 957 958#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE86C28 959 960#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE86C2C 961 962#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE86C30 963 964#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE86C34 965 966#define mmTPC2_CFG_QM_TENSOR_10_PADDING_VALUE 0xE86C38 967 968#define mmTPC2_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE86C3C 969 970#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE86C40 971 972#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE86C44 973 974#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE86C48 975 976#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE86C4C 977 978#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE86C50 979 980#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE86C54 981 982#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE86C58 983 984#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE86C5C 985 986#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE86C60 987 988#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE86C64 989 990#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE86C68 991 992#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE86C6C 993 994#define mmTPC2_CFG_QM_TENSOR_11_PADDING_VALUE 0xE86C70 995 996#define mmTPC2_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE86C74 997 998#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE86C78 999 1000#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE86C7C 1001 1002#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE86C80 1003 1004#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE86C84 1005 1006#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE86C88 1007 1008#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE86C8C 1009 1010#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE86C90 1011 1012#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE86C94 1013 1014#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE86C98 1015 1016#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE86C9C 1017 1018#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE86CA0 1019 1020#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE86CA4 1021 1022#define mmTPC2_CFG_QM_TENSOR_12_PADDING_VALUE 0xE86CA8 1023 1024#define mmTPC2_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE86CAC 1025 1026#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE86CB0 1027 1028#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE86CB4 1029 1030#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE86CB8 1031 1032#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE86CBC 1033 1034#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE86CC0 1035 1036#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE86CC4 1037 1038#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE86CC8 1039 1040#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE86CCC 1041 1042#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE86CD0 1043 1044#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE86CD4 1045 1046#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE86CD8 1047 1048#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE86CDC 1049 1050#define mmTPC2_CFG_QM_TENSOR_13_PADDING_VALUE 0xE86CE0 1051 1052#define mmTPC2_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE86CE4 1053 1054#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE86CE8 1055 1056#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE86CEC 1057 1058#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE86CF0 1059 1060#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE86CF4 1061 1062#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE86CF8 1063 1064#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE86CFC 1065 1066#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE86D00 1067 1068#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE86D04 1069 1070#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE86D08 1071 1072#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE86D0C 1073 1074#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE86D10 1075 1076#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE86D14 1077 1078#define mmTPC2_CFG_QM_TENSOR_14_PADDING_VALUE 0xE86D18 1079 1080#define mmTPC2_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE86D1C 1081 1082#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE86D20 1083 1084#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE86D24 1085 1086#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE86D28 1087 1088#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE86D2C 1089 1090#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE86D30 1091 1092#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE86D34 1093 1094#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE86D38 1095 1096#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE86D3C 1097 1098#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE86D40 1099 1100#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE86D44 1101 1102#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE86D48 1103 1104#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE86D4C 1105 1106#define mmTPC2_CFG_QM_TENSOR_15_PADDING_VALUE 0xE86D50 1107 1108#define mmTPC2_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE86D54 1109 1110#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE86D58 1111 1112#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE86D5C 1113 1114#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE86D60 1115 1116#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE86D64 1117 1118#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE86D68 1119 1120#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE86D6C 1121 1122#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE86D70 1123 1124#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE86D74 1125 1126#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE86D78 1127 1128#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE86D7C 1129 1130#define mmTPC2_CFG_QM_SYNC_OBJECT_MESSAGE 0xE86D80 1131 1132#define mmTPC2_CFG_QM_SYNC_OBJECT_ADDR 0xE86D84 1133 1134#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE86D88 1135 1136#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE86D8C 1137 1138#define mmTPC2_CFG_QM_TID_BASE_DIM_0 0xE86D90 1139 1140#define mmTPC2_CFG_QM_TID_SIZE_DIM_0 0xE86D94 1141 1142#define mmTPC2_CFG_QM_TID_BASE_DIM_1 0xE86D98 1143 1144#define mmTPC2_CFG_QM_TID_SIZE_DIM_1 0xE86D9C 1145 1146#define mmTPC2_CFG_QM_TID_BASE_DIM_2 0xE86DA0 1147 1148#define mmTPC2_CFG_QM_TID_SIZE_DIM_2 0xE86DA4 1149 1150#define mmTPC2_CFG_QM_TID_BASE_DIM_3 0xE86DA8 1151 1152#define mmTPC2_CFG_QM_TID_SIZE_DIM_3 0xE86DAC 1153 1154#define mmTPC2_CFG_QM_TID_BASE_DIM_4 0xE86DB0 1155 1156#define mmTPC2_CFG_QM_TID_SIZE_DIM_4 0xE86DB4 1157 1158#define mmTPC2_CFG_QM_KERNEL_CONFIG 0xE86DB8 1159 1160#define mmTPC2_CFG_QM_KERNEL_ID 0xE86DBC 1161 1162#define mmTPC2_CFG_QM_SRF_0 0xE86DC0 1163 1164#define mmTPC2_CFG_QM_SRF_1 0xE86DC4 1165 1166#define mmTPC2_CFG_QM_SRF_2 0xE86DC8 1167 1168#define mmTPC2_CFG_QM_SRF_3 0xE86DCC 1169 1170#define mmTPC2_CFG_QM_SRF_4 0xE86DD0 1171 1172#define mmTPC2_CFG_QM_SRF_5 0xE86DD4 1173 1174#define mmTPC2_CFG_QM_SRF_6 0xE86DD8 1175 1176#define mmTPC2_CFG_QM_SRF_7 0xE86DDC 1177 1178#define mmTPC2_CFG_QM_SRF_8 0xE86DE0 1179 1180#define mmTPC2_CFG_QM_SRF_9 0xE86DE4 1181 1182#define mmTPC2_CFG_QM_SRF_10 0xE86DE8 1183 1184#define mmTPC2_CFG_QM_SRF_11 0xE86DEC 1185 1186#define mmTPC2_CFG_QM_SRF_12 0xE86DF0 1187 1188#define mmTPC2_CFG_QM_SRF_13 0xE86DF4 1189 1190#define mmTPC2_CFG_QM_SRF_14 0xE86DF8 1191 1192#define mmTPC2_CFG_QM_SRF_15 0xE86DFC 1193 1194#define mmTPC2_CFG_QM_SRF_16 0xE86E00 1195 1196#define mmTPC2_CFG_QM_SRF_17 0xE86E04 1197 1198#define mmTPC2_CFG_QM_SRF_18 0xE86E08 1199 1200#define mmTPC2_CFG_QM_SRF_19 0xE86E0C 1201 1202#define mmTPC2_CFG_QM_SRF_20 0xE86E10 1203 1204#define mmTPC2_CFG_QM_SRF_21 0xE86E14 1205 1206#define mmTPC2_CFG_QM_SRF_22 0xE86E18 1207 1208#define mmTPC2_CFG_QM_SRF_23 0xE86E1C 1209 1210#define mmTPC2_CFG_QM_SRF_24 0xE86E20 1211 1212#define mmTPC2_CFG_QM_SRF_25 0xE86E24 1213 1214#define mmTPC2_CFG_QM_SRF_26 0xE86E28 1215 1216#define mmTPC2_CFG_QM_SRF_27 0xE86E2C 1217 1218#define mmTPC2_CFG_QM_SRF_28 0xE86E30 1219 1220#define mmTPC2_CFG_QM_SRF_29 0xE86E34 1221 1222#define mmTPC2_CFG_QM_SRF_30 0xE86E38 1223 1224#define mmTPC2_CFG_QM_SRF_31 0xE86E3C 1225 1226#endif /* ASIC_REG_TPC2_CFG_REGS_H_ */
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