FILE
tpc1_cfg_regs.h
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linux-6.19.14/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_TPC1_CFG_REGS_H_ 14#define ASIC_REG_TPC1_CFG_REGS_H_ 15 16/* 17 ***************************************** 18 * TPC1_CFG (Prototype: TPC) 19 ***************************************** 20 */ 21 22#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE46400 23 24#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE46404 25 26#define mmTPC1_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE46408 27 28#define mmTPC1_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE4640C 29 30#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE46410 31 32#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE46414 33 34#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE46418 35 36#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE4641C 37 38#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE46420 39 40#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE46424 41 42#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE46428 43 44#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE4642C 45 46#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE46430 47 48#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE46434 49 50#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE46438 51 52#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE4643C 53 54#define mmTPC1_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE46440 55 56#define mmTPC1_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE46444 57 58#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE46448 59 60#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE4644C 61 62#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE46450 63 64#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE46454 65 66#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE46458 67 68#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE4645C 69 70#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE46460 71 72#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE46464 73 74#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE46468 75 76#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE4646C 77 78#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE46470 79 80#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE46474 81 82#define mmTPC1_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE46478 83 84#define mmTPC1_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE4647C 85 86#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE46480 87 88#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE46484 89 90#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE46488 91 92#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE4648C 93 94#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE46490 95 96#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE46494 97 98#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE46498 99 100#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE4649C 101 102#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE464A0 103 104#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE464A4 105 106#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE464A8 107 108#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE464AC 109 110#define mmTPC1_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE464B0 111 112#define mmTPC1_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE464B4 113 114#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE464B8 115 116#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE464BC 117 118#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE464C0 119 120#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE464C4 121 122#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE464C8 123 124#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE464CC 125 126#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE464D0 127 128#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE464D4 129 130#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE464D8 131 132#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE464DC 133 134#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE464E0 135 136#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE464E4 137 138#define mmTPC1_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE464E8 139 140#define mmTPC1_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE464EC 141 142#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE464F0 143 144#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE464F4 145 146#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE464F8 147 148#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE464FC 149 150#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE46500 151 152#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE46504 153 154#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE46508 155 156#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE4650C 157 158#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE46510 159 160#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE46514 161 162#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE46518 163 164#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE4651C 165 166#define mmTPC1_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE46520 167 168#define mmTPC1_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE46524 169 170#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE46528 171 172#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE4652C 173 174#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE46530 175 176#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE46534 177 178#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE46538 179 180#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE4653C 181 182#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE46540 183 184#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE46544 185 186#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE46548 187 188#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE4654C 189 190#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE46550 191 192#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE46554 193 194#define mmTPC1_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE46558 195 196#define mmTPC1_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE4655C 197 198#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE46560 199 200#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE46564 201 202#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE46568 203 204#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE4656C 205 206#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE46570 207 208#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE46574 209 210#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE46578 211 212#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE4657C 213 214#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE46580 215 216#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE46584 217 218#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE46588 219 220#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE4658C 221 222#define mmTPC1_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE46590 223 224#define mmTPC1_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE46594 225 226#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE46598 227 228#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE4659C 229 230#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE465A0 231 232#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE465A4 233 234#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE465A8 235 236#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE465AC 237 238#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE465B0 239 240#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE465B4 241 242#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE465B8 243 244#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE465BC 245 246#define mmTPC1_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE465C0 247 248#define mmTPC1_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE465C4 249 250#define mmTPC1_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE465C8 251 252#define mmTPC1_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE465CC 253 254#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE465D0 255 256#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE465D4 257 258#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE465D8 259 260#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE465DC 261 262#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE465E0 263 264#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE465E4 265 266#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE465E8 267 268#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE465EC 269 270#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE465F0 271 272#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE465F4 273 274#define mmTPC1_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE465F8 275 276#define mmTPC1_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE465FC 277 278#define mmTPC1_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE46600 279 280#define mmTPC1_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE46604 281 282#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE46608 283 284#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE4660C 285 286#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE46610 287 288#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE46614 289 290#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE46618 291 292#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE4661C 293 294#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE46620 295 296#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE46624 297 298#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE46628 299 300#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE4662C 301 302#define mmTPC1_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE46630 303 304#define mmTPC1_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE46634 305 306#define mmTPC1_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE46638 307 308#define mmTPC1_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE4663C 309 310#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE46640 311 312#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE46644 313 314#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE46648 315 316#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE4664C 317 318#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE46650 319 320#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE46654 321 322#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE46658 323 324#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE4665C 325 326#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE46660 327 328#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE46664 329 330#define mmTPC1_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE46668 331 332#define mmTPC1_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE4666C 333 334#define mmTPC1_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE46670 335 336#define mmTPC1_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE46674 337 338#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE46678 339 340#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE4667C 341 342#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE46680 343 344#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE46684 345 346#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE46688 347 348#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE4668C 349 350#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE46690 351 352#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE46694 353 354#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE46698 355 356#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE4669C 357 358#define mmTPC1_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE466A0 359 360#define mmTPC1_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE466A4 361 362#define mmTPC1_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE466A8 363 364#define mmTPC1_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE466AC 365 366#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE466B0 367 368#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE466B4 369 370#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE466B8 371 372#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE466BC 373 374#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE466C0 375 376#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE466C4 377 378#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE466C8 379 380#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE466CC 381 382#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE466D0 383 384#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE466D4 385 386#define mmTPC1_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE466D8 387 388#define mmTPC1_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE466DC 389 390#define mmTPC1_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE466E0 391 392#define mmTPC1_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE466E4 393 394#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE466E8 395 396#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE466EC 397 398#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE466F0 399 400#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE466F4 401 402#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE466F8 403 404#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE466FC 405 406#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE46700 407 408#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE46704 409 410#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE46708 411 412#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE4670C 413 414#define mmTPC1_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE46710 415 416#define mmTPC1_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE46714 417 418#define mmTPC1_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE46718 419 420#define mmTPC1_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE4671C 421 422#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE46720 423 424#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE46724 425 426#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE46728 427 428#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE4672C 429 430#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE46730 431 432#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE46734 433 434#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE46738 435 436#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE4673C 437 438#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE46740 439 440#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE46744 441 442#define mmTPC1_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE46748 443 444#define mmTPC1_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE4674C 445 446#define mmTPC1_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE46750 447 448#define mmTPC1_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE46754 449 450#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE46758 451 452#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE4675C 453 454#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE46760 455 456#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE46764 457 458#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE46768 459 460#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE4676C 461 462#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE46770 463 464#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE46774 465 466#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE46778 467 468#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE4677C 469 470#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE46780 471 472#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE46784 473 474#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE46788 475 476#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE4678C 477 478#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_0 0xE46790 479 480#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_0 0xE46794 481 482#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_1 0xE46798 483 484#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_1 0xE4679C 485 486#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_2 0xE467A0 487 488#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_2 0xE467A4 489 490#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_3 0xE467A8 491 492#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_3 0xE467AC 493 494#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_4 0xE467B0 495 496#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_4 0xE467B4 497 498#define mmTPC1_CFG_KERNEL_KERNEL_CONFIG 0xE467B8 499 500#define mmTPC1_CFG_KERNEL_KERNEL_ID 0xE467BC 501 502#define mmTPC1_CFG_KERNEL_SRF_0 0xE467C0 503 504#define mmTPC1_CFG_KERNEL_SRF_1 0xE467C4 505 506#define mmTPC1_CFG_KERNEL_SRF_2 0xE467C8 507 508#define mmTPC1_CFG_KERNEL_SRF_3 0xE467CC 509 510#define mmTPC1_CFG_KERNEL_SRF_4 0xE467D0 511 512#define mmTPC1_CFG_KERNEL_SRF_5 0xE467D4 513 514#define mmTPC1_CFG_KERNEL_SRF_6 0xE467D8 515 516#define mmTPC1_CFG_KERNEL_SRF_7 0xE467DC 517 518#define mmTPC1_CFG_KERNEL_SRF_8 0xE467E0 519 520#define mmTPC1_CFG_KERNEL_SRF_9 0xE467E4 521 522#define mmTPC1_CFG_KERNEL_SRF_10 0xE467E8 523 524#define mmTPC1_CFG_KERNEL_SRF_11 0xE467EC 525 526#define mmTPC1_CFG_KERNEL_SRF_12 0xE467F0 527 528#define mmTPC1_CFG_KERNEL_SRF_13 0xE467F4 529 530#define mmTPC1_CFG_KERNEL_SRF_14 0xE467F8 531 532#define mmTPC1_CFG_KERNEL_SRF_15 0xE467FC 533 534#define mmTPC1_CFG_KERNEL_SRF_16 0xE46800 535 536#define mmTPC1_CFG_KERNEL_SRF_17 0xE46804 537 538#define mmTPC1_CFG_KERNEL_SRF_18 0xE46808 539 540#define mmTPC1_CFG_KERNEL_SRF_19 0xE4680C 541 542#define mmTPC1_CFG_KERNEL_SRF_20 0xE46810 543 544#define mmTPC1_CFG_KERNEL_SRF_21 0xE46814 545 546#define mmTPC1_CFG_KERNEL_SRF_22 0xE46818 547 548#define mmTPC1_CFG_KERNEL_SRF_23 0xE4681C 549 550#define mmTPC1_CFG_KERNEL_SRF_24 0xE46820 551 552#define mmTPC1_CFG_KERNEL_SRF_25 0xE46824 553 554#define mmTPC1_CFG_KERNEL_SRF_26 0xE46828 555 556#define mmTPC1_CFG_KERNEL_SRF_27 0xE4682C 557 558#define mmTPC1_CFG_KERNEL_SRF_28 0xE46830 559 560#define mmTPC1_CFG_KERNEL_SRF_29 0xE46834 561 562#define mmTPC1_CFG_KERNEL_SRF_30 0xE46838 563 564#define mmTPC1_CFG_KERNEL_SRF_31 0xE4683C 565 566#define mmTPC1_CFG_ROUND_CSR 0xE468FC 567 568#define mmTPC1_CFG_PROT 0xE46900 569 570#define mmTPC1_CFG_SEMAPHORE 0xE46908 571 572#define mmTPC1_CFG_VFLAGS 0xE4690C 573 574#define mmTPC1_CFG_SFLAGS 0xE46910 575 576#define mmTPC1_CFG_LFSR_POLYNOM 0xE46918 577 578#define mmTPC1_CFG_STATUS 0xE4691C 579 580#define mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH 0xE46920 581 582#define mmTPC1_CFG_CFG_SUBTRACT_VALUE 0xE46924 583 584#define mmTPC1_CFG_SM_BASE_ADDRESS_HIGH 0xE4692C 585 586#define mmTPC1_CFG_TPC_CMD 0xE46930 587 588#define mmTPC1_CFG_TPC_EXECUTE 0xE46938 589 590#define mmTPC1_CFG_TPC_STALL 0xE4693C 591 592#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_LOW 0xE46940 593 594#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE46944 595 596#define mmTPC1_CFG_RD_RATE_LIMIT 0xE46948 597 598#define mmTPC1_CFG_WR_RATE_LIMIT 0xE46950 599 600#define mmTPC1_CFG_MSS_CONFIG 0xE46954 601 602#define mmTPC1_CFG_TPC_INTR_CAUSE 0xE46958 603 604#define mmTPC1_CFG_TPC_INTR_MASK 0xE4695C 605 606#define mmTPC1_CFG_WQ_CREDITS 0xE46960 607 608#define mmTPC1_CFG_ARUSER_LO 0xE46964 609 610#define mmTPC1_CFG_ARUSER_HI 0xE46968 611 612#define mmTPC1_CFG_AWUSER_LO 0xE4696C 613 614#define mmTPC1_CFG_AWUSER_HI 0xE46970 615 616#define mmTPC1_CFG_OPCODE_EXEC 0xE46974 617 618#define mmTPC1_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE46978 619 620#define mmTPC1_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE4697C 621 622#define mmTPC1_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE46980 623 624#define mmTPC1_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE46984 625 626#define mmTPC1_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE46988 627 628#define mmTPC1_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE4698C 629 630#define mmTPC1_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE46990 631 632#define mmTPC1_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE46994 633 634#define mmTPC1_CFG_TSB_CFG_MAX_SIZE 0xE46998 635 636#define mmTPC1_CFG_TSB_CFG 0xE4699C 637 638#define mmTPC1_CFG_DBGMEM_ADD 0xE469A0 639 640#define mmTPC1_CFG_DBGMEM_DATA_WR 0xE469A4 641 642#define mmTPC1_CFG_DBGMEM_DATA_RD 0xE469A8 643 644#define mmTPC1_CFG_DBGMEM_CTRL 0xE469AC 645 646#define mmTPC1_CFG_DBGMEM_RC 0xE469B0 647 648#define mmTPC1_CFG_TSB_INFLIGHT_CNTR 0xE469B4 649 650#define mmTPC1_CFG_WQ_INFLIGHT_CNTR 0xE469B8 651 652#define mmTPC1_CFG_WQ_LBW_TOTAL_CNTR 0xE469BC 653 654#define mmTPC1_CFG_WQ_HBW_TOTAL_CNTR 0xE469C0 655 656#define mmTPC1_CFG_IRQ_OCCOUPY_CNTR 0xE469C4 657 658#define mmTPC1_CFG_FUNC_MBIST_CNTRL 0xE469D0 659 660#define mmTPC1_CFG_FUNC_MBIST_PAT 0xE469D4 661 662#define mmTPC1_CFG_FUNC_MBIST_MEM_0 0xE469D8 663 664#define mmTPC1_CFG_FUNC_MBIST_MEM_1 0xE469DC 665 666#define mmTPC1_CFG_FUNC_MBIST_MEM_2 0xE469E0 667 668#define mmTPC1_CFG_FUNC_MBIST_MEM_3 0xE469E4 669 670#define mmTPC1_CFG_FUNC_MBIST_MEM_4 0xE469E8 671 672#define mmTPC1_CFG_FUNC_MBIST_MEM_5 0xE469EC 673 674#define mmTPC1_CFG_FUNC_MBIST_MEM_6 0xE469F0 675 676#define mmTPC1_CFG_FUNC_MBIST_MEM_7 0xE469F4 677 678#define mmTPC1_CFG_FUNC_MBIST_MEM_8 0xE469F8 679 680#define mmTPC1_CFG_FUNC_MBIST_MEM_9 0xE469FC 681 682#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE46A00 683 684#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE46A04 685 686#define mmTPC1_CFG_QM_TENSOR_0_PADDING_VALUE 0xE46A08 687 688#define mmTPC1_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE46A0C 689 690#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE46A10 691 692#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE46A14 693 694#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE46A18 695 696#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE46A1C 697 698#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE46A20 699 700#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE46A24 701 702#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE46A28 703 704#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE46A2C 705 706#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE46A30 707 708#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE46A34 709 710#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE46A38 711 712#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE46A3C 713 714#define mmTPC1_CFG_QM_TENSOR_1_PADDING_VALUE 0xE46A40 715 716#define mmTPC1_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE46A44 717 718#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE46A48 719 720#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE46A4C 721 722#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE46A50 723 724#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE46A54 725 726#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE46A58 727 728#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE46A5C 729 730#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE46A60 731 732#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE46A64 733 734#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE46A68 735 736#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE46A6C 737 738#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE46A70 739 740#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE46A74 741 742#define mmTPC1_CFG_QM_TENSOR_2_PADDING_VALUE 0xE46A78 743 744#define mmTPC1_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE46A7C 745 746#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE46A80 747 748#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE46A84 749 750#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE46A88 751 752#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE46A8C 753 754#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE46A90 755 756#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE46A94 757 758#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE46A98 759 760#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE46A9C 761 762#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE46AA0 763 764#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE46AA4 765 766#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE46AA8 767 768#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE46AAC 769 770#define mmTPC1_CFG_QM_TENSOR_3_PADDING_VALUE 0xE46AB0 771 772#define mmTPC1_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE46AB4 773 774#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE46AB8 775 776#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE46ABC 777 778#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE46AC0 779 780#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE46AC4 781 782#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE46AC8 783 784#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE46ACC 785 786#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE46AD0 787 788#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE46AD4 789 790#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE46AD8 791 792#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE46ADC 793 794#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE46AE0 795 796#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE46AE4 797 798#define mmTPC1_CFG_QM_TENSOR_4_PADDING_VALUE 0xE46AE8 799 800#define mmTPC1_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE46AEC 801 802#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE46AF0 803 804#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE46AF4 805 806#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE46AF8 807 808#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE46AFC 809 810#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE46B00 811 812#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE46B04 813 814#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE46B08 815 816#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE46B0C 817 818#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE46B10 819 820#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE46B14 821 822#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE46B18 823 824#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE46B1C 825 826#define mmTPC1_CFG_QM_TENSOR_5_PADDING_VALUE 0xE46B20 827 828#define mmTPC1_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE46B24 829 830#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE46B28 831 832#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE46B2C 833 834#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE46B30 835 836#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE46B34 837 838#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE46B38 839 840#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE46B3C 841 842#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE46B40 843 844#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE46B44 845 846#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE46B48 847 848#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE46B4C 849 850#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE46B50 851 852#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE46B54 853 854#define mmTPC1_CFG_QM_TENSOR_6_PADDING_VALUE 0xE46B58 855 856#define mmTPC1_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE46B5C 857 858#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE46B60 859 860#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE46B64 861 862#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE46B68 863 864#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE46B6C 865 866#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE46B70 867 868#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE46B74 869 870#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE46B78 871 872#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE46B7C 873 874#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE46B80 875 876#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE46B84 877 878#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE46B88 879 880#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE46B8C 881 882#define mmTPC1_CFG_QM_TENSOR_7_PADDING_VALUE 0xE46B90 883 884#define mmTPC1_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE46B94 885 886#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE46B98 887 888#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE46B9C 889 890#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE46BA0 891 892#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE46BA4 893 894#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE46BA8 895 896#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE46BAC 897 898#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE46BB0 899 900#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE46BB4 901 902#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE46BB8 903 904#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE46BBC 905 906#define mmTPC1_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE46BC0 907 908#define mmTPC1_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE46BC4 909 910#define mmTPC1_CFG_QM_TENSOR_8_PADDING_VALUE 0xE46BC8 911 912#define mmTPC1_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE46BCC 913 914#define mmTPC1_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE46BD0 915 916#define mmTPC1_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE46BD4 917 918#define mmTPC1_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE46BD8 919 920#define mmTPC1_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE46BDC 921 922#define mmTPC1_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE46BE0 923 924#define mmTPC1_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE46BE4 925 926#define mmTPC1_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE46BE8 927 928#define mmTPC1_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE46BEC 929 930#define mmTPC1_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE46BF0 931 932#define mmTPC1_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE46BF4 933 934#define mmTPC1_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE46BF8 935 936#define mmTPC1_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE46BFC 937 938#define mmTPC1_CFG_QM_TENSOR_9_PADDING_VALUE 0xE46C00 939 940#define mmTPC1_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE46C04 941 942#define mmTPC1_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE46C08 943 944#define mmTPC1_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE46C0C 945 946#define mmTPC1_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE46C10 947 948#define mmTPC1_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE46C14 949 950#define mmTPC1_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE46C18 951 952#define mmTPC1_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE46C1C 953 954#define mmTPC1_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE46C20 955 956#define mmTPC1_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE46C24 957 958#define mmTPC1_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE46C28 959 960#define mmTPC1_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE46C2C 961 962#define mmTPC1_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE46C30 963 964#define mmTPC1_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE46C34 965 966#define mmTPC1_CFG_QM_TENSOR_10_PADDING_VALUE 0xE46C38 967 968#define mmTPC1_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE46C3C 969 970#define mmTPC1_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE46C40 971 972#define mmTPC1_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE46C44 973 974#define mmTPC1_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE46C48 975 976#define mmTPC1_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE46C4C 977 978#define mmTPC1_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE46C50 979 980#define mmTPC1_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE46C54 981 982#define mmTPC1_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE46C58 983 984#define mmTPC1_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE46C5C 985 986#define mmTPC1_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE46C60 987 988#define mmTPC1_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE46C64 989 990#define mmTPC1_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE46C68 991 992#define mmTPC1_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE46C6C 993 994#define mmTPC1_CFG_QM_TENSOR_11_PADDING_VALUE 0xE46C70 995 996#define mmTPC1_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE46C74 997 998#define mmTPC1_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE46C78 999 1000#define mmTPC1_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE46C7C 1001 1002#define mmTPC1_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE46C80 1003 1004#define mmTPC1_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE46C84 1005 1006#define mmTPC1_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE46C88 1007 1008#define mmTPC1_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE46C8C 1009 1010#define mmTPC1_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE46C90 1011 1012#define mmTPC1_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE46C94 1013 1014#define mmTPC1_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE46C98 1015 1016#define mmTPC1_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE46C9C 1017 1018#define mmTPC1_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE46CA0 1019 1020#define mmTPC1_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE46CA4 1021 1022#define mmTPC1_CFG_QM_TENSOR_12_PADDING_VALUE 0xE46CA8 1023 1024#define mmTPC1_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE46CAC 1025 1026#define mmTPC1_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE46CB0 1027 1028#define mmTPC1_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE46CB4 1029 1030#define mmTPC1_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE46CB8 1031 1032#define mmTPC1_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE46CBC 1033 1034#define mmTPC1_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE46CC0 1035 1036#define mmTPC1_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE46CC4 1037 1038#define mmTPC1_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE46CC8 1039 1040#define mmTPC1_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE46CCC 1041 1042#define mmTPC1_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE46CD0 1043 1044#define mmTPC1_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE46CD4 1045 1046#define mmTPC1_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE46CD8 1047 1048#define mmTPC1_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE46CDC 1049 1050#define mmTPC1_CFG_QM_TENSOR_13_PADDING_VALUE 0xE46CE0 1051 1052#define mmTPC1_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE46CE4 1053 1054#define mmTPC1_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE46CE8 1055 1056#define mmTPC1_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE46CEC 1057 1058#define mmTPC1_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE46CF0 1059 1060#define mmTPC1_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE46CF4 1061 1062#define mmTPC1_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE46CF8 1063 1064#define mmTPC1_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE46CFC 1065 1066#define mmTPC1_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE46D00 1067 1068#define mmTPC1_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE46D04 1069 1070#define mmTPC1_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE46D08 1071 1072#define mmTPC1_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE46D0C 1073 1074#define mmTPC1_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE46D10 1075 1076#define mmTPC1_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE46D14 1077 1078#define mmTPC1_CFG_QM_TENSOR_14_PADDING_VALUE 0xE46D18 1079 1080#define mmTPC1_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE46D1C 1081 1082#define mmTPC1_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE46D20 1083 1084#define mmTPC1_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE46D24 1085 1086#define mmTPC1_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE46D28 1087 1088#define mmTPC1_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE46D2C 1089 1090#define mmTPC1_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE46D30 1091 1092#define mmTPC1_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE46D34 1093 1094#define mmTPC1_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE46D38 1095 1096#define mmTPC1_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE46D3C 1097 1098#define mmTPC1_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE46D40 1099 1100#define mmTPC1_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE46D44 1101 1102#define mmTPC1_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE46D48 1103 1104#define mmTPC1_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE46D4C 1105 1106#define mmTPC1_CFG_QM_TENSOR_15_PADDING_VALUE 0xE46D50 1107 1108#define mmTPC1_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE46D54 1109 1110#define mmTPC1_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE46D58 1111 1112#define mmTPC1_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE46D5C 1113 1114#define mmTPC1_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE46D60 1115 1116#define mmTPC1_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE46D64 1117 1118#define mmTPC1_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE46D68 1119 1120#define mmTPC1_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE46D6C 1121 1122#define mmTPC1_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE46D70 1123 1124#define mmTPC1_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE46D74 1125 1126#define mmTPC1_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE46D78 1127 1128#define mmTPC1_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE46D7C 1129 1130#define mmTPC1_CFG_QM_SYNC_OBJECT_MESSAGE 0xE46D80 1131 1132#define mmTPC1_CFG_QM_SYNC_OBJECT_ADDR 0xE46D84 1133 1134#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE46D88 1135 1136#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE46D8C 1137 1138#define mmTPC1_CFG_QM_TID_BASE_DIM_0 0xE46D90 1139 1140#define mmTPC1_CFG_QM_TID_SIZE_DIM_0 0xE46D94 1141 1142#define mmTPC1_CFG_QM_TID_BASE_DIM_1 0xE46D98 1143 1144#define mmTPC1_CFG_QM_TID_SIZE_DIM_1 0xE46D9C 1145 1146#define mmTPC1_CFG_QM_TID_BASE_DIM_2 0xE46DA0 1147 1148#define mmTPC1_CFG_QM_TID_SIZE_DIM_2 0xE46DA4 1149 1150#define mmTPC1_CFG_QM_TID_BASE_DIM_3 0xE46DA8 1151 1152#define mmTPC1_CFG_QM_TID_SIZE_DIM_3 0xE46DAC 1153 1154#define mmTPC1_CFG_QM_TID_BASE_DIM_4 0xE46DB0 1155 1156#define mmTPC1_CFG_QM_TID_SIZE_DIM_4 0xE46DB4 1157 1158#define mmTPC1_CFG_QM_KERNEL_CONFIG 0xE46DB8 1159 1160#define mmTPC1_CFG_QM_KERNEL_ID 0xE46DBC 1161 1162#define mmTPC1_CFG_QM_SRF_0 0xE46DC0 1163 1164#define mmTPC1_CFG_QM_SRF_1 0xE46DC4 1165 1166#define mmTPC1_CFG_QM_SRF_2 0xE46DC8 1167 1168#define mmTPC1_CFG_QM_SRF_3 0xE46DCC 1169 1170#define mmTPC1_CFG_QM_SRF_4 0xE46DD0 1171 1172#define mmTPC1_CFG_QM_SRF_5 0xE46DD4 1173 1174#define mmTPC1_CFG_QM_SRF_6 0xE46DD8 1175 1176#define mmTPC1_CFG_QM_SRF_7 0xE46DDC 1177 1178#define mmTPC1_CFG_QM_SRF_8 0xE46DE0 1179 1180#define mmTPC1_CFG_QM_SRF_9 0xE46DE4 1181 1182#define mmTPC1_CFG_QM_SRF_10 0xE46DE8 1183 1184#define mmTPC1_CFG_QM_SRF_11 0xE46DEC 1185 1186#define mmTPC1_CFG_QM_SRF_12 0xE46DF0 1187 1188#define mmTPC1_CFG_QM_SRF_13 0xE46DF4 1189 1190#define mmTPC1_CFG_QM_SRF_14 0xE46DF8 1191 1192#define mmTPC1_CFG_QM_SRF_15 0xE46DFC 1193 1194#define mmTPC1_CFG_QM_SRF_16 0xE46E00 1195 1196#define mmTPC1_CFG_QM_SRF_17 0xE46E04 1197 1198#define mmTPC1_CFG_QM_SRF_18 0xE46E08 1199 1200#define mmTPC1_CFG_QM_SRF_19 0xE46E0C 1201 1202#define mmTPC1_CFG_QM_SRF_20 0xE46E10 1203 1204#define mmTPC1_CFG_QM_SRF_21 0xE46E14 1205 1206#define mmTPC1_CFG_QM_SRF_22 0xE46E18 1207 1208#define mmTPC1_CFG_QM_SRF_23 0xE46E1C 1209 1210#define mmTPC1_CFG_QM_SRF_24 0xE46E20 1211 1212#define mmTPC1_CFG_QM_SRF_25 0xE46E24 1213 1214#define mmTPC1_CFG_QM_SRF_26 0xE46E28 1215 1216#define mmTPC1_CFG_QM_SRF_27 0xE46E2C 1217 1218#define mmTPC1_CFG_QM_SRF_28 0xE46E30 1219 1220#define mmTPC1_CFG_QM_SRF_29 0xE46E34 1221 1222#define mmTPC1_CFG_QM_SRF_30 0xE46E38 1223 1224#define mmTPC1_CFG_QM_SRF_31 0xE46E3C 1225 1226#endif /* ASIC_REG_TPC1_CFG_REGS_H_ */
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