FILE
nic0_qm0_regs.h
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linux-6.19.14/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_regs.h
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_NIC0_QM0_REGS_H_ 14#define ASIC_REG_NIC0_QM0_REGS_H_ 15 16/* 17 ***************************************** 18 * NIC0_QM0 (Prototype: QMAN) 19 ***************************************** 20 */ 21 22#define mmNIC0_QM0_GLBL_CFG0 0xCE0000 23 24#define mmNIC0_QM0_GLBL_CFG1 0xCE0004 25 26#define mmNIC0_QM0_GLBL_PROT 0xCE0008 27 28#define mmNIC0_QM0_GLBL_ERR_CFG 0xCE000C 29 30#define mmNIC0_QM0_GLBL_SECURE_PROPS_0 0xCE0010 31 32#define mmNIC0_QM0_GLBL_SECURE_PROPS_1 0xCE0014 33 34#define mmNIC0_QM0_GLBL_SECURE_PROPS_2 0xCE0018 35 36#define mmNIC0_QM0_GLBL_SECURE_PROPS_3 0xCE001C 37 38#define mmNIC0_QM0_GLBL_SECURE_PROPS_4 0xCE0020 39 40#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_0 0xCE0024 41 42#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_1 0xCE0028 43 44#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_2 0xCE002C 45 46#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_3 0xCE0030 47 48#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_4 0xCE0034 49 50#define mmNIC0_QM0_GLBL_STS0 0xCE0038 51 52#define mmNIC0_QM0_GLBL_STS1_0 0xCE0040 53 54#define mmNIC0_QM0_GLBL_STS1_1 0xCE0044 55 56#define mmNIC0_QM0_GLBL_STS1_2 0xCE0048 57 58#define mmNIC0_QM0_GLBL_STS1_3 0xCE004C 59 60#define mmNIC0_QM0_GLBL_STS1_4 0xCE0050 61 62#define mmNIC0_QM0_GLBL_MSG_EN_0 0xCE0054 63 64#define mmNIC0_QM0_GLBL_MSG_EN_1 0xCE0058 65 66#define mmNIC0_QM0_GLBL_MSG_EN_2 0xCE005C 67 68#define mmNIC0_QM0_GLBL_MSG_EN_3 0xCE0060 69 70#define mmNIC0_QM0_GLBL_MSG_EN_4 0xCE0068 71 72#define mmNIC0_QM0_PQ_BASE_LO_0 0xCE0070 73 74#define mmNIC0_QM0_PQ_BASE_LO_1 0xCE0074 75 76#define mmNIC0_QM0_PQ_BASE_LO_2 0xCE0078 77 78#define mmNIC0_QM0_PQ_BASE_LO_3 0xCE007C 79 80#define mmNIC0_QM0_PQ_BASE_HI_0 0xCE0080 81 82#define mmNIC0_QM0_PQ_BASE_HI_1 0xCE0084 83 84#define mmNIC0_QM0_PQ_BASE_HI_2 0xCE0088 85 86#define mmNIC0_QM0_PQ_BASE_HI_3 0xCE008C 87 88#define mmNIC0_QM0_PQ_SIZE_0 0xCE0090 89 90#define mmNIC0_QM0_PQ_SIZE_1 0xCE0094 91 92#define mmNIC0_QM0_PQ_SIZE_2 0xCE0098 93 94#define mmNIC0_QM0_PQ_SIZE_3 0xCE009C 95 96#define mmNIC0_QM0_PQ_PI_0 0xCE00A0 97 98#define mmNIC0_QM0_PQ_PI_1 0xCE00A4 99 100#define mmNIC0_QM0_PQ_PI_2 0xCE00A8 101 102#define mmNIC0_QM0_PQ_PI_3 0xCE00AC 103 104#define mmNIC0_QM0_PQ_CI_0 0xCE00B0 105 106#define mmNIC0_QM0_PQ_CI_1 0xCE00B4 107 108#define mmNIC0_QM0_PQ_CI_2 0xCE00B8 109 110#define mmNIC0_QM0_PQ_CI_3 0xCE00BC 111 112#define mmNIC0_QM0_PQ_CFG0_0 0xCE00C0 113 114#define mmNIC0_QM0_PQ_CFG0_1 0xCE00C4 115 116#define mmNIC0_QM0_PQ_CFG0_2 0xCE00C8 117 118#define mmNIC0_QM0_PQ_CFG0_3 0xCE00CC 119 120#define mmNIC0_QM0_PQ_CFG1_0 0xCE00D0 121 122#define mmNIC0_QM0_PQ_CFG1_1 0xCE00D4 123 124#define mmNIC0_QM0_PQ_CFG1_2 0xCE00D8 125 126#define mmNIC0_QM0_PQ_CFG1_3 0xCE00DC 127 128#define mmNIC0_QM0_PQ_ARUSER_31_11_0 0xCE00E0 129 130#define mmNIC0_QM0_PQ_ARUSER_31_11_1 0xCE00E4 131 132#define mmNIC0_QM0_PQ_ARUSER_31_11_2 0xCE00E8 133 134#define mmNIC0_QM0_PQ_ARUSER_31_11_3 0xCE00EC 135 136#define mmNIC0_QM0_PQ_STS0_0 0xCE00F0 137 138#define mmNIC0_QM0_PQ_STS0_1 0xCE00F4 139 140#define mmNIC0_QM0_PQ_STS0_2 0xCE00F8 141 142#define mmNIC0_QM0_PQ_STS0_3 0xCE00FC 143 144#define mmNIC0_QM0_PQ_STS1_0 0xCE0100 145 146#define mmNIC0_QM0_PQ_STS1_1 0xCE0104 147 148#define mmNIC0_QM0_PQ_STS1_2 0xCE0108 149 150#define mmNIC0_QM0_PQ_STS1_3 0xCE010C 151 152#define mmNIC0_QM0_CQ_CFG0_0 0xCE0110 153 154#define mmNIC0_QM0_CQ_CFG0_1 0xCE0114 155 156#define mmNIC0_QM0_CQ_CFG0_2 0xCE0118 157 158#define mmNIC0_QM0_CQ_CFG0_3 0xCE011C 159 160#define mmNIC0_QM0_CQ_CFG0_4 0xCE0120 161 162#define mmNIC0_QM0_CQ_CFG1_0 0xCE0124 163 164#define mmNIC0_QM0_CQ_CFG1_1 0xCE0128 165 166#define mmNIC0_QM0_CQ_CFG1_2 0xCE012C 167 168#define mmNIC0_QM0_CQ_CFG1_3 0xCE0130 169 170#define mmNIC0_QM0_CQ_CFG1_4 0xCE0134 171 172#define mmNIC0_QM0_CQ_ARUSER_31_11_0 0xCE0138 173 174#define mmNIC0_QM0_CQ_ARUSER_31_11_1 0xCE013C 175 176#define mmNIC0_QM0_CQ_ARUSER_31_11_2 0xCE0140 177 178#define mmNIC0_QM0_CQ_ARUSER_31_11_3 0xCE0144 179 180#define mmNIC0_QM0_CQ_ARUSER_31_11_4 0xCE0148 181 182#define mmNIC0_QM0_CQ_STS0_0 0xCE014C 183 184#define mmNIC0_QM0_CQ_STS0_1 0xCE0150 185 186#define mmNIC0_QM0_CQ_STS0_2 0xCE0154 187 188#define mmNIC0_QM0_CQ_STS0_3 0xCE0158 189 190#define mmNIC0_QM0_CQ_STS0_4 0xCE015C 191 192#define mmNIC0_QM0_CQ_STS1_0 0xCE0160 193 194#define mmNIC0_QM0_CQ_STS1_1 0xCE0164 195 196#define mmNIC0_QM0_CQ_STS1_2 0xCE0168 197 198#define mmNIC0_QM0_CQ_STS1_3 0xCE016C 199 200#define mmNIC0_QM0_CQ_STS1_4 0xCE0170 201 202#define mmNIC0_QM0_CQ_PTR_LO_0 0xCE0174 203 204#define mmNIC0_QM0_CQ_PTR_HI_0 0xCE0178 205 206#define mmNIC0_QM0_CQ_TSIZE_0 0xCE017C 207 208#define mmNIC0_QM0_CQ_CTL_0 0xCE0180 209 210#define mmNIC0_QM0_CQ_PTR_LO_1 0xCE0184 211 212#define mmNIC0_QM0_CQ_PTR_HI_1 0xCE0188 213 214#define mmNIC0_QM0_CQ_TSIZE_1 0xCE018C 215 216#define mmNIC0_QM0_CQ_CTL_1 0xCE0190 217 218#define mmNIC0_QM0_CQ_PTR_LO_2 0xCE0194 219 220#define mmNIC0_QM0_CQ_PTR_HI_2 0xCE0198 221 222#define mmNIC0_QM0_CQ_TSIZE_2 0xCE019C 223 224#define mmNIC0_QM0_CQ_CTL_2 0xCE01A0 225 226#define mmNIC0_QM0_CQ_PTR_LO_3 0xCE01A4 227 228#define mmNIC0_QM0_CQ_PTR_HI_3 0xCE01A8 229 230#define mmNIC0_QM0_CQ_TSIZE_3 0xCE01AC 231 232#define mmNIC0_QM0_CQ_CTL_3 0xCE01B0 233 234#define mmNIC0_QM0_CQ_PTR_LO_4 0xCE01B4 235 236#define mmNIC0_QM0_CQ_PTR_HI_4 0xCE01B8 237 238#define mmNIC0_QM0_CQ_TSIZE_4 0xCE01BC 239 240#define mmNIC0_QM0_CQ_CTL_4 0xCE01C0 241 242#define mmNIC0_QM0_CQ_PTR_LO_STS_0 0xCE01C4 243 244#define mmNIC0_QM0_CQ_PTR_LO_STS_1 0xCE01C8 245 246#define mmNIC0_QM0_CQ_PTR_LO_STS_2 0xCE01CC 247 248#define mmNIC0_QM0_CQ_PTR_LO_STS_3 0xCE01D0 249 250#define mmNIC0_QM0_CQ_PTR_LO_STS_4 0xCE01D4 251 252#define mmNIC0_QM0_CQ_PTR_HI_STS_0 0xCE01D8 253 254#define mmNIC0_QM0_CQ_PTR_HI_STS_1 0xCE01DC 255 256#define mmNIC0_QM0_CQ_PTR_HI_STS_2 0xCE01E0 257 258#define mmNIC0_QM0_CQ_PTR_HI_STS_3 0xCE01E4 259 260#define mmNIC0_QM0_CQ_PTR_HI_STS_4 0xCE01E8 261 262#define mmNIC0_QM0_CQ_TSIZE_STS_0 0xCE01EC 263 264#define mmNIC0_QM0_CQ_TSIZE_STS_1 0xCE01F0 265 266#define mmNIC0_QM0_CQ_TSIZE_STS_2 0xCE01F4 267 268#define mmNIC0_QM0_CQ_TSIZE_STS_3 0xCE01F8 269 270#define mmNIC0_QM0_CQ_TSIZE_STS_4 0xCE01FC 271 272#define mmNIC0_QM0_CQ_CTL_STS_0 0xCE0200 273 274#define mmNIC0_QM0_CQ_CTL_STS_1 0xCE0204 275 276#define mmNIC0_QM0_CQ_CTL_STS_2 0xCE0208 277 278#define mmNIC0_QM0_CQ_CTL_STS_3 0xCE020C 279 280#define mmNIC0_QM0_CQ_CTL_STS_4 0xCE0210 281 282#define mmNIC0_QM0_CQ_IFIFO_CNT_0 0xCE0214 283 284#define mmNIC0_QM0_CQ_IFIFO_CNT_1 0xCE0218 285 286#define mmNIC0_QM0_CQ_IFIFO_CNT_2 0xCE021C 287 288#define mmNIC0_QM0_CQ_IFIFO_CNT_3 0xCE0220 289 290#define mmNIC0_QM0_CQ_IFIFO_CNT_4 0xCE0224 291 292#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 0xCE0228 293 294#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1 0xCE022C 295 296#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2 0xCE0230 297 298#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3 0xCE0234 299 300#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4 0xCE0238 301 302#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 0xCE023C 303 304#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1 0xCE0240 305 306#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2 0xCE0244 307 308#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3 0xCE0248 309 310#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4 0xCE024C 311 312#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 0xCE0250 313 314#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1 0xCE0254 315 316#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2 0xCE0258 317 318#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3 0xCE025C 319 320#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4 0xCE0260 321 322#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 0xCE0264 323 324#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1 0xCE0268 325 326#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2 0xCE026C 327 328#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3 0xCE0270 329 330#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4 0xCE0274 331 332#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 0xCE0278 333 334#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1 0xCE027C 335 336#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2 0xCE0280 337 338#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3 0xCE0284 339 340#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4 0xCE0288 341 342#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 0xCE028C 343 344#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1 0xCE0290 345 346#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2 0xCE0294 347 348#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3 0xCE0298 349 350#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4 0xCE029C 351 352#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 0xCE02A0 353 354#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1 0xCE02A4 355 356#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2 0xCE02A8 357 358#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3 0xCE02AC 359 360#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4 0xCE02B0 361 362#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 0xCE02B4 363 364#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1 0xCE02B8 365 366#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2 0xCE02BC 367 368#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3 0xCE02C0 369 370#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4 0xCE02C4 371 372#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_0 0xCE02C8 373 374#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_1 0xCE02CC 375 376#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_2 0xCE02D0 377 378#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_3 0xCE02D4 379 380#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_4 0xCE02D8 381 382#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xCE02E0 383 384#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xCE02E4 385 386#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xCE02E8 387 388#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xCE02EC 389 390#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xCE02F0 391 392#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xCE02F4 393 394#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xCE02F8 395 396#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xCE02FC 397 398#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xCE0300 399 400#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xCE0304 401 402#define mmNIC0_QM0_CP_FENCE0_RDATA_0 0xCE0308 403 404#define mmNIC0_QM0_CP_FENCE0_RDATA_1 0xCE030C 405 406#define mmNIC0_QM0_CP_FENCE0_RDATA_2 0xCE0310 407 408#define mmNIC0_QM0_CP_FENCE0_RDATA_3 0xCE0314 409 410#define mmNIC0_QM0_CP_FENCE0_RDATA_4 0xCE0318 411 412#define mmNIC0_QM0_CP_FENCE1_RDATA_0 0xCE031C 413 414#define mmNIC0_QM0_CP_FENCE1_RDATA_1 0xCE0320 415 416#define mmNIC0_QM0_CP_FENCE1_RDATA_2 0xCE0324 417 418#define mmNIC0_QM0_CP_FENCE1_RDATA_3 0xCE0328 419 420#define mmNIC0_QM0_CP_FENCE1_RDATA_4 0xCE032C 421 422#define mmNIC0_QM0_CP_FENCE2_RDATA_0 0xCE0330 423 424#define mmNIC0_QM0_CP_FENCE2_RDATA_1 0xCE0334 425 426#define mmNIC0_QM0_CP_FENCE2_RDATA_2 0xCE0338 427 428#define mmNIC0_QM0_CP_FENCE2_RDATA_3 0xCE033C 429 430#define mmNIC0_QM0_CP_FENCE2_RDATA_4 0xCE0340 431 432#define mmNIC0_QM0_CP_FENCE3_RDATA_0 0xCE0344 433 434#define mmNIC0_QM0_CP_FENCE3_RDATA_1 0xCE0348 435 436#define mmNIC0_QM0_CP_FENCE3_RDATA_2 0xCE034C 437 438#define mmNIC0_QM0_CP_FENCE3_RDATA_3 0xCE0350 439 440#define mmNIC0_QM0_CP_FENCE3_RDATA_4 0xCE0354 441 442#define mmNIC0_QM0_CP_FENCE0_CNT_0 0xCE0358 443 444#define mmNIC0_QM0_CP_FENCE0_CNT_1 0xCE035C 445 446#define mmNIC0_QM0_CP_FENCE0_CNT_2 0xCE0360 447 448#define mmNIC0_QM0_CP_FENCE0_CNT_3 0xCE0364 449 450#define mmNIC0_QM0_CP_FENCE0_CNT_4 0xCE0368 451 452#define mmNIC0_QM0_CP_FENCE1_CNT_0 0xCE036C 453 454#define mmNIC0_QM0_CP_FENCE1_CNT_1 0xCE0370 455 456#define mmNIC0_QM0_CP_FENCE1_CNT_2 0xCE0374 457 458#define mmNIC0_QM0_CP_FENCE1_CNT_3 0xCE0378 459 460#define mmNIC0_QM0_CP_FENCE1_CNT_4 0xCE037C 461 462#define mmNIC0_QM0_CP_FENCE2_CNT_0 0xCE0380 463 464#define mmNIC0_QM0_CP_FENCE2_CNT_1 0xCE0384 465 466#define mmNIC0_QM0_CP_FENCE2_CNT_2 0xCE0388 467 468#define mmNIC0_QM0_CP_FENCE2_CNT_3 0xCE038C 469 470#define mmNIC0_QM0_CP_FENCE2_CNT_4 0xCE0390 471 472#define mmNIC0_QM0_CP_FENCE3_CNT_0 0xCE0394 473 474#define mmNIC0_QM0_CP_FENCE3_CNT_1 0xCE0398 475 476#define mmNIC0_QM0_CP_FENCE3_CNT_2 0xCE039C 477 478#define mmNIC0_QM0_CP_FENCE3_CNT_3 0xCE03A0 479 480#define mmNIC0_QM0_CP_FENCE3_CNT_4 0xCE03A4 481 482#define mmNIC0_QM0_CP_STS_0 0xCE03A8 483 484#define mmNIC0_QM0_CP_STS_1 0xCE03AC 485 486#define mmNIC0_QM0_CP_STS_2 0xCE03B0 487 488#define mmNIC0_QM0_CP_STS_3 0xCE03B4 489 490#define mmNIC0_QM0_CP_STS_4 0xCE03B8 491 492#define mmNIC0_QM0_CP_CURRENT_INST_LO_0 0xCE03BC 493 494#define mmNIC0_QM0_CP_CURRENT_INST_LO_1 0xCE03C0 495 496#define mmNIC0_QM0_CP_CURRENT_INST_LO_2 0xCE03C4 497 498#define mmNIC0_QM0_CP_CURRENT_INST_LO_3 0xCE03C8 499 500#define mmNIC0_QM0_CP_CURRENT_INST_LO_4 0xCE03CC 501 502#define mmNIC0_QM0_CP_CURRENT_INST_HI_0 0xCE03D0 503 504#define mmNIC0_QM0_CP_CURRENT_INST_HI_1 0xCE03D4 505 506#define mmNIC0_QM0_CP_CURRENT_INST_HI_2 0xCE03D8 507 508#define mmNIC0_QM0_CP_CURRENT_INST_HI_3 0xCE03DC 509 510#define mmNIC0_QM0_CP_CURRENT_INST_HI_4 0xCE03E0 511 512#define mmNIC0_QM0_CP_BARRIER_CFG_0 0xCE03F4 513 514#define mmNIC0_QM0_CP_BARRIER_CFG_1 0xCE03F8 515 516#define mmNIC0_QM0_CP_BARRIER_CFG_2 0xCE03FC 517 518#define mmNIC0_QM0_CP_BARRIER_CFG_3 0xCE0400 519 520#define mmNIC0_QM0_CP_BARRIER_CFG_4 0xCE0404 521 522#define mmNIC0_QM0_CP_DBG_0_0 0xCE0408 523 524#define mmNIC0_QM0_CP_DBG_0_1 0xCE040C 525 526#define mmNIC0_QM0_CP_DBG_0_2 0xCE0410 527 528#define mmNIC0_QM0_CP_DBG_0_3 0xCE0414 529 530#define mmNIC0_QM0_CP_DBG_0_4 0xCE0418 531 532#define mmNIC0_QM0_CP_ARUSER_31_11_0 0xCE041C 533 534#define mmNIC0_QM0_CP_ARUSER_31_11_1 0xCE0420 535 536#define mmNIC0_QM0_CP_ARUSER_31_11_2 0xCE0424 537 538#define mmNIC0_QM0_CP_ARUSER_31_11_3 0xCE0428 539 540#define mmNIC0_QM0_CP_ARUSER_31_11_4 0xCE042C 541 542#define mmNIC0_QM0_CP_AWUSER_31_11_0 0xCE0430 543 544#define mmNIC0_QM0_CP_AWUSER_31_11_1 0xCE0434 545 546#define mmNIC0_QM0_CP_AWUSER_31_11_2 0xCE0438 547 548#define mmNIC0_QM0_CP_AWUSER_31_11_3 0xCE043C 549 550#define mmNIC0_QM0_CP_AWUSER_31_11_4 0xCE0440 551 552#define mmNIC0_QM0_ARB_CFG_0 0xCE0A00 553 554#define mmNIC0_QM0_ARB_CHOISE_Q_PUSH 0xCE0A04 555 556#define mmNIC0_QM0_ARB_WRR_WEIGHT_0 0xCE0A08 557 558#define mmNIC0_QM0_ARB_WRR_WEIGHT_1 0xCE0A0C 559 560#define mmNIC0_QM0_ARB_WRR_WEIGHT_2 0xCE0A10 561 562#define mmNIC0_QM0_ARB_WRR_WEIGHT_3 0xCE0A14 563 564#define mmNIC0_QM0_ARB_CFG_1 0xCE0A18 565 566#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_0 0xCE0A20 567 568#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_1 0xCE0A24 569 570#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_2 0xCE0A28 571 572#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_3 0xCE0A2C 573 574#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_4 0xCE0A30 575 576#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_5 0xCE0A34 577 578#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_6 0xCE0A38 579 580#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_7 0xCE0A3C 581 582#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_8 0xCE0A40 583 584#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_9 0xCE0A44 585 586#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_10 0xCE0A48 587 588#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_11 0xCE0A4C 589 590#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_12 0xCE0A50 591 592#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_13 0xCE0A54 593 594#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_14 0xCE0A58 595 596#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_15 0xCE0A5C 597 598#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_16 0xCE0A60 599 600#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_17 0xCE0A64 601 602#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_18 0xCE0A68 603 604#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_19 0xCE0A6C 605 606#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_20 0xCE0A70 607 608#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_21 0xCE0A74 609 610#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_22 0xCE0A78 611 612#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_23 0xCE0A7C 613 614#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_24 0xCE0A80 615 616#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_25 0xCE0A84 617 618#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_26 0xCE0A88 619 620#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_27 0xCE0A8C 621 622#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_28 0xCE0A90 623 624#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_29 0xCE0A94 625 626#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_30 0xCE0A98 627 628#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_31 0xCE0A9C 629 630#define mmNIC0_QM0_ARB_MST_CRED_INC 0xCE0AA0 631 632#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xCE0AA4 633 634#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xCE0AA8 635 636#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xCE0AAC 637 638#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xCE0AB0 639 640#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xCE0AB4 641 642#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xCE0AB8 643 644#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xCE0ABC 645 646#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xCE0AC0 647 648#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xCE0AC4 649 650#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xCE0AC8 651 652#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xCE0ACC 653 654#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xCE0AD0 655 656#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xCE0AD4 657 658#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xCE0AD8 659 660#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xCE0ADC 661 662#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xCE0AE0 663 664#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xCE0AE4 665 666#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xCE0AE8 667 668#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xCE0AEC 669 670#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xCE0AF0 671 672#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xCE0AF4 673 674#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xCE0AF8 675 676#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xCE0AFC 677 678#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xCE0B00 679 680#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xCE0B04 681 682#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xCE0B08 683 684#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xCE0B0C 685 686#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xCE0B10 687 688#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xCE0B14 689 690#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xCE0B18 691 692#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xCE0B1C 693 694#define mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xCE0B20 695 696#define mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xCE0B28 697 698#define mmNIC0_QM0_ARB_MST_SLAVE_EN 0xCE0B2C 699 700#define mmNIC0_QM0_ARB_MST_QUIET_PER 0xCE0B34 701 702#define mmNIC0_QM0_ARB_SLV_CHOISE_WDT 0xCE0B38 703 704#define mmNIC0_QM0_ARB_SLV_ID 0xCE0B3C 705 706#define mmNIC0_QM0_ARB_MSG_MAX_INFLIGHT 0xCE0B44 707 708#define mmNIC0_QM0_ARB_MSG_AWUSER_31_11 0xCE0B48 709 710#define mmNIC0_QM0_ARB_MSG_AWUSER_SEC_PROP 0xCE0B4C 711 712#define mmNIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xCE0B50 713 714#define mmNIC0_QM0_ARB_BASE_LO 0xCE0B54 715 716#define mmNIC0_QM0_ARB_BASE_HI 0xCE0B58 717 718#define mmNIC0_QM0_ARB_STATE_STS 0xCE0B80 719 720#define mmNIC0_QM0_ARB_CHOISE_FULLNESS_STS 0xCE0B84 721 722#define mmNIC0_QM0_ARB_MSG_STS 0xCE0B88 723 724#define mmNIC0_QM0_ARB_SLV_CHOISE_Q_HEAD 0xCE0B8C 725 726#define mmNIC0_QM0_ARB_ERR_CAUSE 0xCE0B9C 727 728#define mmNIC0_QM0_ARB_ERR_MSG_EN 0xCE0BA0 729 730#define mmNIC0_QM0_ARB_ERR_STS_DRP 0xCE0BA8 731 732#define mmNIC0_QM0_ARB_MST_CRED_STS_0 0xCE0BB0 733 734#define mmNIC0_QM0_ARB_MST_CRED_STS_1 0xCE0BB4 735 736#define mmNIC0_QM0_ARB_MST_CRED_STS_2 0xCE0BB8 737 738#define mmNIC0_QM0_ARB_MST_CRED_STS_3 0xCE0BBC 739 740#define mmNIC0_QM0_ARB_MST_CRED_STS_4 0xCE0BC0 741 742#define mmNIC0_QM0_ARB_MST_CRED_STS_5 0xCE0BC4 743 744#define mmNIC0_QM0_ARB_MST_CRED_STS_6 0xCE0BC8 745 746#define mmNIC0_QM0_ARB_MST_CRED_STS_7 0xCE0BCC 747 748#define mmNIC0_QM0_ARB_MST_CRED_STS_8 0xCE0BD0 749 750#define mmNIC0_QM0_ARB_MST_CRED_STS_9 0xCE0BD4 751 752#define mmNIC0_QM0_ARB_MST_CRED_STS_10 0xCE0BD8 753 754#define mmNIC0_QM0_ARB_MST_CRED_STS_11 0xCE0BDC 755 756#define mmNIC0_QM0_ARB_MST_CRED_STS_12 0xCE0BE0 757 758#define mmNIC0_QM0_ARB_MST_CRED_STS_13 0xCE0BE4 759 760#define mmNIC0_QM0_ARB_MST_CRED_STS_14 0xCE0BE8 761 762#define mmNIC0_QM0_ARB_MST_CRED_STS_15 0xCE0BEC 763 764#define mmNIC0_QM0_ARB_MST_CRED_STS_16 0xCE0BF0 765 766#define mmNIC0_QM0_ARB_MST_CRED_STS_17 0xCE0BF4 767 768#define mmNIC0_QM0_ARB_MST_CRED_STS_18 0xCE0BF8 769 770#define mmNIC0_QM0_ARB_MST_CRED_STS_19 0xCE0BFC 771 772#define mmNIC0_QM0_ARB_MST_CRED_STS_20 0xCE0C00 773 774#define mmNIC0_QM0_ARB_MST_CRED_STS_21 0xCE0C04 775 776#define mmNIC0_QM0_ARB_MST_CRED_STS_22 0xCE0C08 777 778#define mmNIC0_QM0_ARB_MST_CRED_STS_23 0xCE0C0C 779 780#define mmNIC0_QM0_ARB_MST_CRED_STS_24 0xCE0C10 781 782#define mmNIC0_QM0_ARB_MST_CRED_STS_25 0xCE0C14 783 784#define mmNIC0_QM0_ARB_MST_CRED_STS_26 0xCE0C18 785 786#define mmNIC0_QM0_ARB_MST_CRED_STS_27 0xCE0C1C 787 788#define mmNIC0_QM0_ARB_MST_CRED_STS_28 0xCE0C20 789 790#define mmNIC0_QM0_ARB_MST_CRED_STS_29 0xCE0C24 791 792#define mmNIC0_QM0_ARB_MST_CRED_STS_30 0xCE0C28 793 794#define mmNIC0_QM0_ARB_MST_CRED_STS_31 0xCE0C2C 795 796#define mmNIC0_QM0_CGM_CFG 0xCE0C70 797 798#define mmNIC0_QM0_CGM_STS 0xCE0C74 799 800#define mmNIC0_QM0_CGM_CFG1 0xCE0C78 801 802#define mmNIC0_QM0_LOCAL_RANGE_BASE 0xCE0C80 803 804#define mmNIC0_QM0_LOCAL_RANGE_SIZE 0xCE0C84 805 806#define mmNIC0_QM0_CSMR_STRICT_PRIO_CFG 0xCE0C90 807 808#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_1 0xCE0C94 809 810#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_0 0xCE0C98 811 812#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_1 0xCE0C9C 813 814#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_0 0xCE0CA0 815 816#define mmNIC0_QM0_GLBL_AXCACHE 0xCE0CA4 817 818#define mmNIC0_QM0_IND_GW_APB_CFG 0xCE0CB0 819 820#define mmNIC0_QM0_IND_GW_APB_WDATA 0xCE0CB4 821 822#define mmNIC0_QM0_IND_GW_APB_RDATA 0xCE0CB8 823 824#define mmNIC0_QM0_IND_GW_APB_STATUS 0xCE0CBC 825 826#define mmNIC0_QM0_GLBL_ERR_ADDR_LO 0xCE0CD0 827 828#define mmNIC0_QM0_GLBL_ERR_ADDR_HI 0xCE0CD4 829 830#define mmNIC0_QM0_GLBL_ERR_WDATA 0xCE0CD8 831 832#define mmNIC0_QM0_GLBL_MEM_INIT_BUSY 0xCE0D00 833 834#endif /* ASIC_REG_NIC0_QM0_REGS_H_ */
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