nic0_qm0_masks.h

  1/* SPDX-License-Identifier: GPL-2.0
  2 *
  3 * Copyright 2016-2018 HabanaLabs, Ltd.
  4 * All Rights Reserved.
  5 *
  6 */
  7
  8/************************************
  9 ** This is an auto-generated file **
 10 **       DO NOT EDIT BELOW        **
 11 ************************************/
 12
 13#ifndef ASIC_REG_NIC0_QM0_MASKS_H_
 14#define ASIC_REG_NIC0_QM0_MASKS_H_
 15
 16/*
 17 *****************************************
 18 *   NIC0_QM0 (Prototype: QMAN)
 19 *****************************************
 20 */
 21
 22/* NIC0_QM0_GLBL_CFG0 */
 23#define NIC0_QM0_GLBL_CFG0_PQF_EN_SHIFT                              0
 24#define NIC0_QM0_GLBL_CFG0_PQF_EN_MASK                               0xF
 25#define NIC0_QM0_GLBL_CFG0_CQF_EN_SHIFT                              4
 26#define NIC0_QM0_GLBL_CFG0_CQF_EN_MASK                               0x1F0
 27#define NIC0_QM0_GLBL_CFG0_CP_EN_SHIFT                               9
 28#define NIC0_QM0_GLBL_CFG0_CP_EN_MASK                                0x3E00
 29
 30/* NIC0_QM0_GLBL_CFG1 */
 31#define NIC0_QM0_GLBL_CFG1_PQF_STOP_SHIFT                            0
 32#define NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK                             0xF
 33#define NIC0_QM0_GLBL_CFG1_CQF_STOP_SHIFT                            4
 34#define NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK                             0x1F0
 35#define NIC0_QM0_GLBL_CFG1_CP_STOP_SHIFT                             9
 36#define NIC0_QM0_GLBL_CFG1_CP_STOP_MASK                              0x3E00
 37#define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_SHIFT                           16
 38#define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_MASK                            0xF0000
 39#define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_SHIFT                           20
 40#define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_MASK                            0x1F00000
 41#define NIC0_QM0_GLBL_CFG1_CP_FLUSH_SHIFT                            25
 42#define NIC0_QM0_GLBL_CFG1_CP_FLUSH_MASK                             0x3E000000
 43
 44/* NIC0_QM0_GLBL_PROT */
 45#define NIC0_QM0_GLBL_PROT_PQF_SHIFT                                 0
 46#define NIC0_QM0_GLBL_PROT_PQF_MASK                                  0xF
 47#define NIC0_QM0_GLBL_PROT_CQF_SHIFT                                 4
 48#define NIC0_QM0_GLBL_PROT_CQF_MASK                                  0x1F0
 49#define NIC0_QM0_GLBL_PROT_CP_SHIFT                                  9
 50#define NIC0_QM0_GLBL_PROT_CP_MASK                                   0x3E00
 51#define NIC0_QM0_GLBL_PROT_ERR_SHIFT                                 14
 52#define NIC0_QM0_GLBL_PROT_ERR_MASK                                  0x4000
 53#define NIC0_QM0_GLBL_PROT_ARB_SHIFT                                 15
 54#define NIC0_QM0_GLBL_PROT_ARB_MASK                                  0x8000
 55
 56/* NIC0_QM0_GLBL_ERR_CFG */
 57#define NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT                   0
 58#define NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK                    0xF
 59#define NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT                   4
 60#define NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK                    0x1F0
 61#define NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT                    9
 62#define NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK                     0x3E00
 63#define NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT                  16
 64#define NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK                   0xF0000
 65#define NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT                  20
 66#define NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK                   0x1F00000
 67#define NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT                   25
 68#define NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK                    0x3E000000
 69#define NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT                  31
 70#define NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK                   0x80000000
 71
 72/* NIC0_QM0_GLBL_SECURE_PROPS */
 73#define NIC0_QM0_GLBL_SECURE_PROPS_0_ASID_SHIFT                      0
 74#define NIC0_QM0_GLBL_SECURE_PROPS_0_ASID_MASK                       0x3FF
 75#define NIC0_QM0_GLBL_SECURE_PROPS_1_ASID_SHIFT                      0
 76#define NIC0_QM0_GLBL_SECURE_PROPS_1_ASID_MASK                       0x3FF
 77#define NIC0_QM0_GLBL_SECURE_PROPS_2_ASID_SHIFT                      0
 78#define NIC0_QM0_GLBL_SECURE_PROPS_2_ASID_MASK                       0x3FF
 79#define NIC0_QM0_GLBL_SECURE_PROPS_3_ASID_SHIFT                      0
 80#define NIC0_QM0_GLBL_SECURE_PROPS_3_ASID_MASK                       0x3FF
 81#define NIC0_QM0_GLBL_SECURE_PROPS_4_ASID_SHIFT                      0
 82#define NIC0_QM0_GLBL_SECURE_PROPS_4_ASID_MASK                       0x3FF
 83#define NIC0_QM0_GLBL_SECURE_PROPS_0_MMBP_SHIFT                      10
 84#define NIC0_QM0_GLBL_SECURE_PROPS_0_MMBP_MASK                       0x400
 85#define NIC0_QM0_GLBL_SECURE_PROPS_1_MMBP_SHIFT                      10
 86#define NIC0_QM0_GLBL_SECURE_PROPS_1_MMBP_MASK                       0x400
 87#define NIC0_QM0_GLBL_SECURE_PROPS_2_MMBP_SHIFT                      10
 88#define NIC0_QM0_GLBL_SECURE_PROPS_2_MMBP_MASK                       0x400
 89#define NIC0_QM0_GLBL_SECURE_PROPS_3_MMBP_SHIFT                      10
 90#define NIC0_QM0_GLBL_SECURE_PROPS_3_MMBP_MASK                       0x400
 91#define NIC0_QM0_GLBL_SECURE_PROPS_4_MMBP_SHIFT                      10
 92#define NIC0_QM0_GLBL_SECURE_PROPS_4_MMBP_MASK                       0x400
 93
 94/* NIC0_QM0_GLBL_NON_SECURE_PROPS */
 95#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT                  0
 96#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_ASID_MASK                   0x3FF
 97#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT                  0
 98#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_ASID_MASK                   0x3FF
 99#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT                  0
100#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_ASID_MASK                   0x3FF
101#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT                  0
102#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_ASID_MASK                   0x3FF
103#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT                  0
104#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_ASID_MASK                   0x3FF
105#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT                  10
106#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_MMBP_MASK                   0x400
107#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT                  10
108#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_MMBP_MASK                   0x400
109#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT                  10
110#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_MMBP_MASK                   0x400
111#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT                  10
112#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_MMBP_MASK                   0x400
113#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT                  10
114#define NIC0_QM0_GLBL_NON_SECURE_PROPS_4_MMBP_MASK                   0x400
115
116/* NIC0_QM0_GLBL_STS0 */
117#define NIC0_QM0_GLBL_STS0_PQF_IDLE_SHIFT                            0
118#define NIC0_QM0_GLBL_STS0_PQF_IDLE_MASK                             0xF
119#define NIC0_QM0_GLBL_STS0_CQF_IDLE_SHIFT                            4
120#define NIC0_QM0_GLBL_STS0_CQF_IDLE_MASK                             0x1F0
121#define NIC0_QM0_GLBL_STS0_CP_IDLE_SHIFT                             9
122#define NIC0_QM0_GLBL_STS0_CP_IDLE_MASK                              0x3E00
123#define NIC0_QM0_GLBL_STS0_PQF_IS_STOP_SHIFT                         16
124#define NIC0_QM0_GLBL_STS0_PQF_IS_STOP_MASK                          0xF0000
125#define NIC0_QM0_GLBL_STS0_CQF_IS_STOP_SHIFT                         20
126#define NIC0_QM0_GLBL_STS0_CQF_IS_STOP_MASK                          0x1F00000
127#define NIC0_QM0_GLBL_STS0_CP_IS_STOP_SHIFT                          25
128#define NIC0_QM0_GLBL_STS0_CP_IS_STOP_MASK                           0x3E000000
129#define NIC0_QM0_GLBL_STS0_ARB_IS_STOP_SHIFT                         31
130#define NIC0_QM0_GLBL_STS0_ARB_IS_STOP_MASK                          0x80000000
131
132/* NIC0_QM0_GLBL_STS1 */
133#define NIC0_QM0_GLBL_STS1_PQF_RD_ERR_SHIFT                          0
134#define NIC0_QM0_GLBL_STS1_PQF_RD_ERR_MASK                           0x1
135#define NIC0_QM0_GLBL_STS1_CQF_RD_ERR_SHIFT                          1
136#define NIC0_QM0_GLBL_STS1_CQF_RD_ERR_MASK                           0x2
137#define NIC0_QM0_GLBL_STS1_CP_RD_ERR_SHIFT                           2
138#define NIC0_QM0_GLBL_STS1_CP_RD_ERR_MASK                            0x4
139#define NIC0_QM0_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT                    3
140#define NIC0_QM0_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK                     0x8
141#define NIC0_QM0_GLBL_STS1_CP_STOP_OP_SHIFT                          4
142#define NIC0_QM0_GLBL_STS1_CP_STOP_OP_MASK                           0x10
143#define NIC0_QM0_GLBL_STS1_CP_MSG_WR_ERR_SHIFT                       5
144#define NIC0_QM0_GLBL_STS1_CP_MSG_WR_ERR_MASK                        0x20
145#define NIC0_QM0_GLBL_STS1_CP_WREG_ERR_SHIFT                         6
146#define NIC0_QM0_GLBL_STS1_CP_WREG_ERR_MASK                          0x40
147#define NIC0_QM0_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT                   8
148#define NIC0_QM0_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK                    0x100
149#define NIC0_QM0_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT                   9
150#define NIC0_QM0_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK                    0x200
151#define NIC0_QM0_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT                   10
152#define NIC0_QM0_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK                    0x400
153#define NIC0_QM0_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT                   11
154#define NIC0_QM0_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK                    0x800
155#define NIC0_QM0_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT                   12
156#define NIC0_QM0_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK                    0x1000
157#define NIC0_QM0_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT                   13
158#define NIC0_QM0_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK                    0x2000
159#define NIC0_QM0_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT                   14
160#define NIC0_QM0_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK                    0x4000
161#define NIC0_QM0_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT                   15
162#define NIC0_QM0_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK                    0x8000
163
164/* NIC0_QM0_GLBL_STS1_4 */
165#define NIC0_QM0_GLBL_STS1_4_CQF_RD_ERR_SHIFT                        1
166#define NIC0_QM0_GLBL_STS1_4_CQF_RD_ERR_MASK                         0x2
167#define NIC0_QM0_GLBL_STS1_4_CP_RD_ERR_SHIFT                         2
168#define NIC0_QM0_GLBL_STS1_4_CP_RD_ERR_MASK                          0x4
169#define NIC0_QM0_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT                  3
170#define NIC0_QM0_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK                   0x8
171#define NIC0_QM0_GLBL_STS1_4_CP_STOP_OP_SHIFT                        4
172#define NIC0_QM0_GLBL_STS1_4_CP_STOP_OP_MASK                         0x10
173#define NIC0_QM0_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT                     5
174#define NIC0_QM0_GLBL_STS1_4_CP_MSG_WR_ERR_MASK                      0x20
175#define NIC0_QM0_GLBL_STS1_4_CP_WREG_ERR_SHIFT                       6
176#define NIC0_QM0_GLBL_STS1_4_CP_WREG_ERR_MASK                        0x40
177#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT                 8
178#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK                  0x100
179#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT                 9
180#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK                  0x200
181#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT                 10
182#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK                  0x400
183#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT                 11
184#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK                  0x800
185#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT                 12
186#define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK                  0x1000
187#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT                 13
188#define NIC0_QM0_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK                  0x2000
189#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT                 14
190#define NIC0_QM0_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK                  0x4000
191#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT                 15
192#define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK                  0x8000
193
194/* NIC0_QM0_GLBL_MSG_EN */
195#define NIC0_QM0_GLBL_MSG_EN_PQF_RD_ERR_SHIFT                        0
196#define NIC0_QM0_GLBL_MSG_EN_PQF_RD_ERR_MASK                         0x1
197#define NIC0_QM0_GLBL_MSG_EN_CQF_RD_ERR_SHIFT                        1
198#define NIC0_QM0_GLBL_MSG_EN_CQF_RD_ERR_MASK                         0x2
199#define NIC0_QM0_GLBL_MSG_EN_CP_RD_ERR_SHIFT                         2
200#define NIC0_QM0_GLBL_MSG_EN_CP_RD_ERR_MASK                          0x4
201#define NIC0_QM0_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT                  3
202#define NIC0_QM0_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK                   0x8
203#define NIC0_QM0_GLBL_MSG_EN_CP_STOP_OP_SHIFT                        4
204#define NIC0_QM0_GLBL_MSG_EN_CP_STOP_OP_MASK                         0x10
205#define NIC0_QM0_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT                     5
206#define NIC0_QM0_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK                      0x20
207#define NIC0_QM0_GLBL_MSG_EN_CP_WREG_ERR_SHIFT                       6
208#define NIC0_QM0_GLBL_MSG_EN_CP_WREG_ERR_MASK                        0x40
209#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT                 8
210#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK                  0x100
211#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT                 9
212#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK                  0x200
213#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT                 10
214#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK                  0x400
215#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT                 11
216#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK                  0x800
217#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT                 12
218#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK                  0x1000
219#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT                 13
220#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK                  0x2000
221#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT                 14
222#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK                  0x4000
223#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT                 15
224#define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK                  0x8000
225
226/* NIC0_QM0_GLBL_MSG_EN_4 */
227#define NIC0_QM0_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT                      1
228#define NIC0_QM0_GLBL_MSG_EN_4_CQF_RD_ERR_MASK                       0x2
229#define NIC0_QM0_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT                       2
230#define NIC0_QM0_GLBL_MSG_EN_4_CP_RD_ERR_MASK                        0x4
231#define NIC0_QM0_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT                3
232#define NIC0_QM0_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK                 0x8
233#define NIC0_QM0_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT                      4
234#define NIC0_QM0_GLBL_MSG_EN_4_CP_STOP_OP_MASK                       0x10
235#define NIC0_QM0_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT                   5
236#define NIC0_QM0_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK                    0x20
237#define NIC0_QM0_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT                     6
238#define NIC0_QM0_GLBL_MSG_EN_4_CP_WREG_ERR_MASK                      0x40
239#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT               8
240#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK                0x100
241#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT               9
242#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK                0x200
243#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT               10
244#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK                0x400
245#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT               11
246#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK                0x800
247#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT               12
248#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK                0x1000
249#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT               13
250#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK                0x2000
251#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT               14
252#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK                0x4000
253#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT               15
254#define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK                0x8000
255
256/* NIC0_QM0_PQ_BASE_LO */
257#define NIC0_QM0_PQ_BASE_LO_VAL_SHIFT                                0
258#define NIC0_QM0_PQ_BASE_LO_VAL_MASK                                 0xFFFFFFFF
259
260/* NIC0_QM0_PQ_BASE_HI */
261#define NIC0_QM0_PQ_BASE_HI_VAL_SHIFT                                0
262#define NIC0_QM0_PQ_BASE_HI_VAL_MASK                                 0xFFFFFFFF
263
264/* NIC0_QM0_PQ_SIZE */
265#define NIC0_QM0_PQ_SIZE_VAL_SHIFT                                   0
266#define NIC0_QM0_PQ_SIZE_VAL_MASK                                    0xFFFFFFFF
267
268/* NIC0_QM0_PQ_PI */
269#define NIC0_QM0_PQ_PI_VAL_SHIFT                                     0
270#define NIC0_QM0_PQ_PI_VAL_MASK                                      0xFFFFFFFF
271
272/* NIC0_QM0_PQ_CI */
273#define NIC0_QM0_PQ_CI_VAL_SHIFT                                     0
274#define NIC0_QM0_PQ_CI_VAL_MASK                                      0xFFFFFFFF
275
276/* NIC0_QM0_PQ_CFG0 */
277#define NIC0_QM0_PQ_CFG0_RESERVED_SHIFT                              0
278#define NIC0_QM0_PQ_CFG0_RESERVED_MASK                               0x1
279
280/* NIC0_QM0_PQ_CFG1 */
281#define NIC0_QM0_PQ_CFG1_CREDIT_LIM_SHIFT                            0
282#define NIC0_QM0_PQ_CFG1_CREDIT_LIM_MASK                             0xFFFF
283#define NIC0_QM0_PQ_CFG1_MAX_INFLIGHT_SHIFT                          16
284#define NIC0_QM0_PQ_CFG1_MAX_INFLIGHT_MASK                           0xFFFF0000
285
286/* NIC0_QM0_PQ_ARUSER_31_11 */
287#define NIC0_QM0_PQ_ARUSER_31_11_VAL_SHIFT                           0
288#define NIC0_QM0_PQ_ARUSER_31_11_VAL_MASK                            0x1FFFFF
289
290/* NIC0_QM0_PQ_STS0 */
291#define NIC0_QM0_PQ_STS0_PQ_CREDIT_CNT_SHIFT                         0
292#define NIC0_QM0_PQ_STS0_PQ_CREDIT_CNT_MASK                          0xFFFF
293#define NIC0_QM0_PQ_STS0_PQ_FREE_CNT_SHIFT                           16
294#define NIC0_QM0_PQ_STS0_PQ_FREE_CNT_MASK                            0xFFFF0000
295
296/* NIC0_QM0_PQ_STS1 */
297#define NIC0_QM0_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT                       0
298#define NIC0_QM0_PQ_STS1_PQ_INFLIGHT_CNT_MASK                        0xFFFF
299#define NIC0_QM0_PQ_STS1_PQ_BUF_EMPTY_SHIFT                          30
300#define NIC0_QM0_PQ_STS1_PQ_BUF_EMPTY_MASK                           0x40000000
301#define NIC0_QM0_PQ_STS1_PQ_BUSY_SHIFT                               31
302#define NIC0_QM0_PQ_STS1_PQ_BUSY_MASK                                0x80000000
303
304/* NIC0_QM0_CQ_CFG0 */
305#define NIC0_QM0_CQ_CFG0_RESERVED_SHIFT                              0
306#define NIC0_QM0_CQ_CFG0_RESERVED_MASK                               0x1
307
308/* NIC0_QM0_CQ_CFG1 */
309#define NIC0_QM0_CQ_CFG1_CREDIT_LIM_SHIFT                            0
310#define NIC0_QM0_CQ_CFG1_CREDIT_LIM_MASK                             0xFFFF
311#define NIC0_QM0_CQ_CFG1_MAX_INFLIGHT_SHIFT                          16
312#define NIC0_QM0_CQ_CFG1_MAX_INFLIGHT_MASK                           0xFFFF0000
313
314/* NIC0_QM0_CQ_ARUSER_31_11 */
315#define NIC0_QM0_CQ_ARUSER_31_11_VAL_SHIFT                           0
316#define NIC0_QM0_CQ_ARUSER_31_11_VAL_MASK                            0x1FFFFF
317
318/* NIC0_QM0_CQ_STS0 */
319#define NIC0_QM0_CQ_STS0_CQ_CREDIT_CNT_SHIFT                         0
320#define NIC0_QM0_CQ_STS0_CQ_CREDIT_CNT_MASK                          0xFFFF
321#define NIC0_QM0_CQ_STS0_CQ_FREE_CNT_SHIFT                           16
322#define NIC0_QM0_CQ_STS0_CQ_FREE_CNT_MASK                            0xFFFF0000
323
324/* NIC0_QM0_CQ_STS1 */
325#define NIC0_QM0_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT                       0
326#define NIC0_QM0_CQ_STS1_CQ_INFLIGHT_CNT_MASK                        0xFFFF
327#define NIC0_QM0_CQ_STS1_CQ_BUF_EMPTY_SHIFT                          30
328#define NIC0_QM0_CQ_STS1_CQ_BUF_EMPTY_MASK                           0x40000000
329#define NIC0_QM0_CQ_STS1_CQ_BUSY_SHIFT                               31
330#define NIC0_QM0_CQ_STS1_CQ_BUSY_MASK                                0x80000000
331
332/* NIC0_QM0_CQ_PTR_LO_0 */
333#define NIC0_QM0_CQ_PTR_LO_0_VAL_SHIFT                               0
334#define NIC0_QM0_CQ_PTR_LO_0_VAL_MASK                                0xFFFFFFFF
335
336/* NIC0_QM0_CQ_PTR_HI_0 */
337#define NIC0_QM0_CQ_PTR_HI_0_VAL_SHIFT                               0
338#define NIC0_QM0_CQ_PTR_HI_0_VAL_MASK                                0xFFFFFFFF
339
340/* NIC0_QM0_CQ_TSIZE_0 */
341#define NIC0_QM0_CQ_TSIZE_0_VAL_SHIFT                                0
342#define NIC0_QM0_CQ_TSIZE_0_VAL_MASK                                 0xFFFFFFFF
343
344/* NIC0_QM0_CQ_CTL_0 */
345#define NIC0_QM0_CQ_CTL_0_RPT_SHIFT                                  0
346#define NIC0_QM0_CQ_CTL_0_RPT_MASK                                   0xFFFF
347#define NIC0_QM0_CQ_CTL_0_CTL_SHIFT                                  16
348#define NIC0_QM0_CQ_CTL_0_CTL_MASK                                   0xFFFF0000
349
350/* NIC0_QM0_CQ_PTR_LO_1 */
351#define NIC0_QM0_CQ_PTR_LO_1_VAL_SHIFT                               0
352#define NIC0_QM0_CQ_PTR_LO_1_VAL_MASK                                0xFFFFFFFF
353
354/* NIC0_QM0_CQ_PTR_HI_1 */
355#define NIC0_QM0_CQ_PTR_HI_1_VAL_SHIFT                               0
356#define NIC0_QM0_CQ_PTR_HI_1_VAL_MASK                                0xFFFFFFFF
357
358/* NIC0_QM0_CQ_TSIZE_1 */
359#define NIC0_QM0_CQ_TSIZE_1_VAL_SHIFT                                0
360#define NIC0_QM0_CQ_TSIZE_1_VAL_MASK                                 0xFFFFFFFF
361
362/* NIC0_QM0_CQ_CTL_1 */
363#define NIC0_QM0_CQ_CTL_1_RPT_SHIFT                                  0
364#define NIC0_QM0_CQ_CTL_1_RPT_MASK                                   0xFFFF
365#define NIC0_QM0_CQ_CTL_1_CTL_SHIFT                                  16
366#define NIC0_QM0_CQ_CTL_1_CTL_MASK                                   0xFFFF0000
367
368/* NIC0_QM0_CQ_PTR_LO_2 */
369#define NIC0_QM0_CQ_PTR_LO_2_VAL_SHIFT                               0
370#define NIC0_QM0_CQ_PTR_LO_2_VAL_MASK                                0xFFFFFFFF
371
372/* NIC0_QM0_CQ_PTR_HI_2 */
373#define NIC0_QM0_CQ_PTR_HI_2_VAL_SHIFT                               0
374#define NIC0_QM0_CQ_PTR_HI_2_VAL_MASK                                0xFFFFFFFF
375
376/* NIC0_QM0_CQ_TSIZE_2 */
377#define NIC0_QM0_CQ_TSIZE_2_VAL_SHIFT                                0
378#define NIC0_QM0_CQ_TSIZE_2_VAL_MASK                                 0xFFFFFFFF
379
380/* NIC0_QM0_CQ_CTL_2 */
381#define NIC0_QM0_CQ_CTL_2_RPT_SHIFT                                  0
382#define NIC0_QM0_CQ_CTL_2_RPT_MASK                                   0xFFFF
383#define NIC0_QM0_CQ_CTL_2_CTL_SHIFT                                  16
384#define NIC0_QM0_CQ_CTL_2_CTL_MASK                                   0xFFFF0000
385
386/* NIC0_QM0_CQ_PTR_LO_3 */
387#define NIC0_QM0_CQ_PTR_LO_3_VAL_SHIFT                               0
388#define NIC0_QM0_CQ_PTR_LO_3_VAL_MASK                                0xFFFFFFFF
389
390/* NIC0_QM0_CQ_PTR_HI_3 */
391#define NIC0_QM0_CQ_PTR_HI_3_VAL_SHIFT                               0
392#define NIC0_QM0_CQ_PTR_HI_3_VAL_MASK                                0xFFFFFFFF
393
394/* NIC0_QM0_CQ_TSIZE_3 */
395#define NIC0_QM0_CQ_TSIZE_3_VAL_SHIFT                                0
396#define NIC0_QM0_CQ_TSIZE_3_VAL_MASK                                 0xFFFFFFFF
397
398/* NIC0_QM0_CQ_CTL_3 */
399#define NIC0_QM0_CQ_CTL_3_RPT_SHIFT                                  0
400#define NIC0_QM0_CQ_CTL_3_RPT_MASK                                   0xFFFF
401#define NIC0_QM0_CQ_CTL_3_CTL_SHIFT                                  16
402#define NIC0_QM0_CQ_CTL_3_CTL_MASK                                   0xFFFF0000
403
404/* NIC0_QM0_CQ_PTR_LO_4 */
405#define NIC0_QM0_CQ_PTR_LO_4_VAL_SHIFT                               0
406#define NIC0_QM0_CQ_PTR_LO_4_VAL_MASK                                0xFFFFFFFF
407
408/* NIC0_QM0_CQ_PTR_HI_4 */
409#define NIC0_QM0_CQ_PTR_HI_4_VAL_SHIFT                               0
410#define NIC0_QM0_CQ_PTR_HI_4_VAL_MASK                                0xFFFFFFFF
411
412/* NIC0_QM0_CQ_TSIZE_4 */
413#define NIC0_QM0_CQ_TSIZE_4_VAL_SHIFT                                0
414#define NIC0_QM0_CQ_TSIZE_4_VAL_MASK                                 0xFFFFFFFF
415
416/* NIC0_QM0_CQ_CTL_4 */
417#define NIC0_QM0_CQ_CTL_4_RPT_SHIFT                                  0
418#define NIC0_QM0_CQ_CTL_4_RPT_MASK                                   0xFFFF
419#define NIC0_QM0_CQ_CTL_4_CTL_SHIFT                                  16
420#define NIC0_QM0_CQ_CTL_4_CTL_MASK                                   0xFFFF0000
421
422/* NIC0_QM0_CQ_PTR_LO_STS */
423#define NIC0_QM0_CQ_PTR_LO_STS_VAL_SHIFT                             0
424#define NIC0_QM0_CQ_PTR_LO_STS_VAL_MASK                              0xFFFFFFFF
425
426/* NIC0_QM0_CQ_PTR_HI_STS */
427#define NIC0_QM0_CQ_PTR_HI_STS_VAL_SHIFT                             0
428#define NIC0_QM0_CQ_PTR_HI_STS_VAL_MASK                              0xFFFFFFFF
429
430/* NIC0_QM0_CQ_TSIZE_STS */
431#define NIC0_QM0_CQ_TSIZE_STS_VAL_SHIFT                              0
432#define NIC0_QM0_CQ_TSIZE_STS_VAL_MASK                               0xFFFFFFFF
433
434/* NIC0_QM0_CQ_CTL_STS */
435#define NIC0_QM0_CQ_CTL_STS_RPT_SHIFT                                0
436#define NIC0_QM0_CQ_CTL_STS_RPT_MASK                                 0xFFFF
437#define NIC0_QM0_CQ_CTL_STS_CTL_SHIFT                                16
438#define NIC0_QM0_CQ_CTL_STS_CTL_MASK                                 0xFFFF0000
439
440/* NIC0_QM0_CQ_IFIFO_CNT */
441#define NIC0_QM0_CQ_IFIFO_CNT_VAL_SHIFT                              0
442#define NIC0_QM0_CQ_IFIFO_CNT_VAL_MASK                               0x3
443
444/* NIC0_QM0_CP_MSG_BASE0_ADDR_LO */
445#define NIC0_QM0_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT                      0
446#define NIC0_QM0_CP_MSG_BASE0_ADDR_LO_VAL_MASK                       0xFFFFFFFF
447
448/* NIC0_QM0_CP_MSG_BASE0_ADDR_HI */
449#define NIC0_QM0_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT                      0
450#define NIC0_QM0_CP_MSG_BASE0_ADDR_HI_VAL_MASK                       0xFFFFFFFF
451
452/* NIC0_QM0_CP_MSG_BASE1_ADDR_LO */
453#define NIC0_QM0_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT                      0
454#define NIC0_QM0_CP_MSG_BASE1_ADDR_LO_VAL_MASK                       0xFFFFFFFF
455
456/* NIC0_QM0_CP_MSG_BASE1_ADDR_HI */
457#define NIC0_QM0_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT                      0
458#define NIC0_QM0_CP_MSG_BASE1_ADDR_HI_VAL_MASK                       0xFFFFFFFF
459
460/* NIC0_QM0_CP_MSG_BASE2_ADDR_LO */
461#define NIC0_QM0_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT                      0
462#define NIC0_QM0_CP_MSG_BASE2_ADDR_LO_VAL_MASK                       0xFFFFFFFF
463
464/* NIC0_QM0_CP_MSG_BASE2_ADDR_HI */
465#define NIC0_QM0_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT                      0
466#define NIC0_QM0_CP_MSG_BASE2_ADDR_HI_VAL_MASK                       0xFFFFFFFF
467
468/* NIC0_QM0_CP_MSG_BASE3_ADDR_LO */
469#define NIC0_QM0_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT                      0
470#define NIC0_QM0_CP_MSG_BASE3_ADDR_LO_VAL_MASK                       0xFFFFFFFF
471
472/* NIC0_QM0_CP_MSG_BASE3_ADDR_HI */
473#define NIC0_QM0_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT                      0
474#define NIC0_QM0_CP_MSG_BASE3_ADDR_HI_VAL_MASK                       0xFFFFFFFF
475
476/* NIC0_QM0_CP_LDMA_TSIZE_OFFSET */
477#define NIC0_QM0_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT                      0
478#define NIC0_QM0_CP_LDMA_TSIZE_OFFSET_VAL_MASK                       0xFFFFFFFF
479
480/* NIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET */
481#define NIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT                0
482#define NIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK                 0xFFFFFFFF
483
484/* NIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET */
485#define NIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT                0
486#define NIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK                 0xFFFFFFFF
487
488/* NIC0_QM0_CP_FENCE0_RDATA */
489#define NIC0_QM0_CP_FENCE0_RDATA_INC_VAL_SHIFT                       0
490#define NIC0_QM0_CP_FENCE0_RDATA_INC_VAL_MASK                        0xF
491
492/* NIC0_QM0_CP_FENCE1_RDATA */
493#define NIC0_QM0_CP_FENCE1_RDATA_INC_VAL_SHIFT                       0
494#define NIC0_QM0_CP_FENCE1_RDATA_INC_VAL_MASK                        0xF
495
496/* NIC0_QM0_CP_FENCE2_RDATA */
497#define NIC0_QM0_CP_FENCE2_RDATA_INC_VAL_SHIFT                       0
498#define NIC0_QM0_CP_FENCE2_RDATA_INC_VAL_MASK                        0xF
499
500/* NIC0_QM0_CP_FENCE3_RDATA */
501#define NIC0_QM0_CP_FENCE3_RDATA_INC_VAL_SHIFT                       0
502#define NIC0_QM0_CP_FENCE3_RDATA_INC_VAL_MASK                        0xF
503
504/* NIC0_QM0_CP_FENCE0_CNT */
505#define NIC0_QM0_CP_FENCE0_CNT_VAL_SHIFT                             0
506#define NIC0_QM0_CP_FENCE0_CNT_VAL_MASK                              0x3FFF
507
508/* NIC0_QM0_CP_FENCE1_CNT */
509#define NIC0_QM0_CP_FENCE1_CNT_VAL_SHIFT                             0
510#define NIC0_QM0_CP_FENCE1_CNT_VAL_MASK                              0x3FFF
511
512/* NIC0_QM0_CP_FENCE2_CNT */
513#define NIC0_QM0_CP_FENCE2_CNT_VAL_SHIFT                             0
514#define NIC0_QM0_CP_FENCE2_CNT_VAL_MASK                              0x3FFF
515
516/* NIC0_QM0_CP_FENCE3_CNT */
517#define NIC0_QM0_CP_FENCE3_CNT_VAL_SHIFT                             0
518#define NIC0_QM0_CP_FENCE3_CNT_VAL_MASK                              0x3FFF
519
520/* NIC0_QM0_CP_STS */
521#define NIC0_QM0_CP_STS_MSG_INFLIGHT_CNT_SHIFT                       0
522#define NIC0_QM0_CP_STS_MSG_INFLIGHT_CNT_MASK                        0xFFFF
523#define NIC0_QM0_CP_STS_ERDY_SHIFT                                   16
524#define NIC0_QM0_CP_STS_ERDY_MASK                                    0x10000
525#define NIC0_QM0_CP_STS_RRDY_SHIFT                                   17
526#define NIC0_QM0_CP_STS_RRDY_MASK                                    0x20000
527#define NIC0_QM0_CP_STS_MRDY_SHIFT                                   18
528#define NIC0_QM0_CP_STS_MRDY_MASK                                    0x40000
529#define NIC0_QM0_CP_STS_SW_STOP_SHIFT                                19
530#define NIC0_QM0_CP_STS_SW_STOP_MASK                                 0x80000
531#define NIC0_QM0_CP_STS_FENCE_ID_SHIFT                               20
532#define NIC0_QM0_CP_STS_FENCE_ID_MASK                                0x300000
533#define NIC0_QM0_CP_STS_FENCE_IN_PROGRESS_SHIFT                      22
534#define NIC0_QM0_CP_STS_FENCE_IN_PROGRESS_MASK                       0x400000
535
536/* NIC0_QM0_CP_CURRENT_INST_LO */
537#define NIC0_QM0_CP_CURRENT_INST_LO_VAL_SHIFT                        0
538#define NIC0_QM0_CP_CURRENT_INST_LO_VAL_MASK                         0xFFFFFFFF
539
540/* NIC0_QM0_CP_CURRENT_INST_HI */
541#define NIC0_QM0_CP_CURRENT_INST_HI_VAL_SHIFT                        0
542#define NIC0_QM0_CP_CURRENT_INST_HI_VAL_MASK                         0xFFFFFFFF
543
544/* NIC0_QM0_CP_BARRIER_CFG */
545#define NIC0_QM0_CP_BARRIER_CFG_EBGUARD_SHIFT                        0
546#define NIC0_QM0_CP_BARRIER_CFG_EBGUARD_MASK                         0xFFF
547#define NIC0_QM0_CP_BARRIER_CFG_RBGUARD_SHIFT                        16
548#define NIC0_QM0_CP_BARRIER_CFG_RBGUARD_MASK                         0xF0000
549
550/* NIC0_QM0_CP_DBG_0 */
551#define NIC0_QM0_CP_DBG_0_CS_SHIFT                                   0
552#define NIC0_QM0_CP_DBG_0_CS_MASK                                    0xF
553#define NIC0_QM0_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT                      4
554#define NIC0_QM0_CP_DBG_0_EB_CNT_NOT_ZERO_MASK                       0x10
555#define NIC0_QM0_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT                    5
556#define NIC0_QM0_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK                     0x20
557#define NIC0_QM0_CP_DBG_0_MREB_STALL_SHIFT                           6
558#define NIC0_QM0_CP_DBG_0_MREB_STALL_MASK                            0x40
559#define NIC0_QM0_CP_DBG_0_STALL_SHIFT                                7
560#define NIC0_QM0_CP_DBG_0_STALL_MASK                                 0x80
561
562/* NIC0_QM0_CP_ARUSER_31_11 */
563#define NIC0_QM0_CP_ARUSER_31_11_VAL_SHIFT                           0
564#define NIC0_QM0_CP_ARUSER_31_11_VAL_MASK                            0x1FFFFF
565
566/* NIC0_QM0_CP_AWUSER_31_11 */
567#define NIC0_QM0_CP_AWUSER_31_11_VAL_SHIFT                           0
568#define NIC0_QM0_CP_AWUSER_31_11_VAL_MASK                            0x1FFFFF
569
570/* NIC0_QM0_ARB_CFG_0 */
571#define NIC0_QM0_ARB_CFG_0_TYPE_SHIFT                                0
572#define NIC0_QM0_ARB_CFG_0_TYPE_MASK                                 0x1
573#define NIC0_QM0_ARB_CFG_0_IS_MASTER_SHIFT                           4
574#define NIC0_QM0_ARB_CFG_0_IS_MASTER_MASK                            0x10
575#define NIC0_QM0_ARB_CFG_0_EN_SHIFT                                  8
576#define NIC0_QM0_ARB_CFG_0_EN_MASK                                   0x100
577#define NIC0_QM0_ARB_CFG_0_MASK_SHIFT                                12
578#define NIC0_QM0_ARB_CFG_0_MASK_MASK                                 0xF000
579#define NIC0_QM0_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT                     16
580#define NIC0_QM0_ARB_CFG_0_MST_MSG_NOSTALL_MASK                      0x10000
581
582/* NIC0_QM0_ARB_CHOISE_Q_PUSH */
583#define NIC0_QM0_ARB_CHOISE_Q_PUSH_VAL_SHIFT                         0
584#define NIC0_QM0_ARB_CHOISE_Q_PUSH_VAL_MASK                          0x3
585
586/* NIC0_QM0_ARB_WRR_WEIGHT */
587#define NIC0_QM0_ARB_WRR_WEIGHT_VAL_SHIFT                            0
588#define NIC0_QM0_ARB_WRR_WEIGHT_VAL_MASK                             0xFFFFFFFF
589
590/* NIC0_QM0_ARB_CFG_1 */
591#define NIC0_QM0_ARB_CFG_1_CLR_SHIFT                                 0
592#define NIC0_QM0_ARB_CFG_1_CLR_MASK                                  0x1
593
594/* NIC0_QM0_ARB_MST_AVAIL_CRED */
595#define NIC0_QM0_ARB_MST_AVAIL_CRED_VAL_SHIFT                        0
596#define NIC0_QM0_ARB_MST_AVAIL_CRED_VAL_MASK                         0x7F
597
598/* NIC0_QM0_ARB_MST_CRED_INC */
599#define NIC0_QM0_ARB_MST_CRED_INC_VAL_SHIFT                          0
600#define NIC0_QM0_ARB_MST_CRED_INC_VAL_MASK                           0xFFFFFFFF
601
602/* NIC0_QM0_ARB_MST_CHOISE_PUSH_OFST */
603#define NIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT                  0
604#define NIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK                   0xFFFFFFFF
605
606/* NIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST */
607#define NIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT              0
608#define NIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK               0xFFFFFFFF
609
610/* NIC0_QM0_ARB_MST_SLAVE_EN */
611#define NIC0_QM0_ARB_MST_SLAVE_EN_VAL_SHIFT                          0
612#define NIC0_QM0_ARB_MST_SLAVE_EN_VAL_MASK                           0xFFFFFFFF
613
614/* NIC0_QM0_ARB_MST_QUIET_PER */
615#define NIC0_QM0_ARB_MST_QUIET_PER_VAL_SHIFT                         0
616#define NIC0_QM0_ARB_MST_QUIET_PER_VAL_MASK                          0xFFFFFFFF
617
618/* NIC0_QM0_ARB_SLV_CHOISE_WDT */
619#define NIC0_QM0_ARB_SLV_CHOISE_WDT_VAL_SHIFT                        0
620#define NIC0_QM0_ARB_SLV_CHOISE_WDT_VAL_MASK                         0xFFFFFFFF
621
622/* NIC0_QM0_ARB_SLV_ID */
623#define NIC0_QM0_ARB_SLV_ID_VAL_SHIFT                                0
624#define NIC0_QM0_ARB_SLV_ID_VAL_MASK                                 0x1F
625
626/* NIC0_QM0_ARB_MSG_MAX_INFLIGHT */
627#define NIC0_QM0_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT                      0
628#define NIC0_QM0_ARB_MSG_MAX_INFLIGHT_VAL_MASK                       0x3F
629
630/* NIC0_QM0_ARB_MSG_AWUSER_31_11 */
631#define NIC0_QM0_ARB_MSG_AWUSER_31_11_VAL_SHIFT                      0
632#define NIC0_QM0_ARB_MSG_AWUSER_31_11_VAL_MASK                       0x1FFFFF
633
634/* NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP */
635#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT                  0
636#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK                   0x3FF
637#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT                  10
638#define NIC0_QM0_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK                   0x400
639
640/* NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP */
641#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT              0
642#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK               0x3FF
643#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT              10
644#define NIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK               0x400
645
646/* NIC0_QM0_ARB_BASE_LO */
647#define NIC0_QM0_ARB_BASE_LO_VAL_SHIFT                               0
648#define NIC0_QM0_ARB_BASE_LO_VAL_MASK                                0xFFFFFFFF
649
650/* NIC0_QM0_ARB_BASE_HI */
651#define NIC0_QM0_ARB_BASE_HI_VAL_SHIFT                               0
652#define NIC0_QM0_ARB_BASE_HI_VAL_MASK                                0xFFFFFFFF
653
654/* NIC0_QM0_ARB_STATE_STS */
655#define NIC0_QM0_ARB_STATE_STS_VAL_SHIFT                             0
656#define NIC0_QM0_ARB_STATE_STS_VAL_MASK                              0xFFFFFFFF
657
658/* NIC0_QM0_ARB_CHOISE_FULLNESS_STS */
659#define NIC0_QM0_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT                   0
660#define NIC0_QM0_ARB_CHOISE_FULLNESS_STS_VAL_MASK                    0x7F
661
662/* NIC0_QM0_ARB_MSG_STS */
663#define NIC0_QM0_ARB_MSG_STS_FULL_SHIFT                              0
664#define NIC0_QM0_ARB_MSG_STS_FULL_MASK                               0x1
665#define NIC0_QM0_ARB_MSG_STS_NO_INFLIGHT_SHIFT                       1
666#define NIC0_QM0_ARB_MSG_STS_NO_INFLIGHT_MASK                        0x2
667
668/* NIC0_QM0_ARB_SLV_CHOISE_Q_HEAD */
669#define NIC0_QM0_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT                     0
670#define NIC0_QM0_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK                      0x3
671
672/* NIC0_QM0_ARB_ERR_CAUSE */
673#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT                      0
674#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_OVF_MASK                       0x1
675#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT                      1
676#define NIC0_QM0_ARB_ERR_CAUSE_CHOISE_WDT_MASK                       0x2
677#define NIC0_QM0_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT                     2
678#define NIC0_QM0_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK                      0x4
679
680/* NIC0_QM0_ARB_ERR_MSG_EN */
681#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT                     0
682#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_OVF_MASK                      0x1
683#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT                     1
684#define NIC0_QM0_ARB_ERR_MSG_EN_CHOISE_WDT_MASK                      0x2
685#define NIC0_QM0_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT                    2
686#define NIC0_QM0_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK                     0x4
687
688/* NIC0_QM0_ARB_ERR_STS_DRP */
689#define NIC0_QM0_ARB_ERR_STS_DRP_VAL_SHIFT                           0
690#define NIC0_QM0_ARB_ERR_STS_DRP_VAL_MASK                            0x3
691
692/* NIC0_QM0_ARB_MST_CRED_STS */
693#define NIC0_QM0_ARB_MST_CRED_STS_VAL_SHIFT                          0
694#define NIC0_QM0_ARB_MST_CRED_STS_VAL_MASK                           0x7F
695
696/* NIC0_QM0_CGM_CFG */
697#define NIC0_QM0_CGM_CFG_IDLE_TH_SHIFT                               0
698#define NIC0_QM0_CGM_CFG_IDLE_TH_MASK                                0xFFF
699#define NIC0_QM0_CGM_CFG_G2F_TH_SHIFT                                16
700#define NIC0_QM0_CGM_CFG_G2F_TH_MASK                                 0xFF0000
701#define NIC0_QM0_CGM_CFG_CP_IDLE_MASK_SHIFT                          24
702#define NIC0_QM0_CGM_CFG_CP_IDLE_MASK_MASK                           0x1F000000
703#define NIC0_QM0_CGM_CFG_EN_SHIFT                                    31
704#define NIC0_QM0_CGM_CFG_EN_MASK                                     0x80000000
705
706/* NIC0_QM0_CGM_STS */
707#define NIC0_QM0_CGM_STS_ST_SHIFT                                    0
708#define NIC0_QM0_CGM_STS_ST_MASK                                     0x3
709#define NIC0_QM0_CGM_STS_CG_SHIFT                                    4
710#define NIC0_QM0_CGM_STS_CG_MASK                                     0x10
711#define NIC0_QM0_CGM_STS_AGENT_IDLE_SHIFT                            8
712#define NIC0_QM0_CGM_STS_AGENT_IDLE_MASK                             0x100
713#define NIC0_QM0_CGM_STS_AXI_IDLE_SHIFT                              9
714#define NIC0_QM0_CGM_STS_AXI_IDLE_MASK                               0x200
715#define NIC0_QM0_CGM_STS_CP_IDLE_SHIFT                               10
716#define NIC0_QM0_CGM_STS_CP_IDLE_MASK                                0x400
717
718/* NIC0_QM0_CGM_CFG1 */
719#define NIC0_QM0_CGM_CFG1_MASK_TH_SHIFT                              0
720#define NIC0_QM0_CGM_CFG1_MASK_TH_MASK                               0xFF
721
722/* NIC0_QM0_LOCAL_RANGE_BASE */
723#define NIC0_QM0_LOCAL_RANGE_BASE_VAL_SHIFT                          0
724#define NIC0_QM0_LOCAL_RANGE_BASE_VAL_MASK                           0xFFFF
725
726/* NIC0_QM0_LOCAL_RANGE_SIZE */
727#define NIC0_QM0_LOCAL_RANGE_SIZE_VAL_SHIFT                          0
728#define NIC0_QM0_LOCAL_RANGE_SIZE_VAL_MASK                           0xFFFF
729
730/* NIC0_QM0_CSMR_STRICT_PRIO_CFG */
731#define NIC0_QM0_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT                     0
732#define NIC0_QM0_CSMR_STRICT_PRIO_CFG_TYPE_MASK                      0x1
733
734/* NIC0_QM0_HBW_RD_RATE_LIM_CFG_1 */
735#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT                    0
736#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK                     0xFF
737#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT                      31
738#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_1_EN_MASK                       0x80000000
739
740/* NIC0_QM0_LBW_WR_RATE_LIM_CFG_0 */
741#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT               0
742#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK                0xFF
743#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT                     16
744#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_0_SAT_MASK                      0xFF0000
745
746/* NIC0_QM0_LBW_WR_RATE_LIM_CFG_1 */
747#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT                    0
748#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK                     0xFF
749#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT                      31
750#define NIC0_QM0_LBW_WR_RATE_LIM_CFG_1_EN_MASK                       0x80000000
751
752/* NIC0_QM0_HBW_RD_RATE_LIM_CFG_0 */
753#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT               0
754#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK                0xFF
755#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT                     16
756#define NIC0_QM0_HBW_RD_RATE_LIM_CFG_0_SAT_MASK                      0xFF0000
757
758/* NIC0_QM0_GLBL_AXCACHE */
759#define NIC0_QM0_GLBL_AXCACHE_AR_SHIFT                               0
760#define NIC0_QM0_GLBL_AXCACHE_AR_MASK                                0xF
761#define NIC0_QM0_GLBL_AXCACHE_AW_SHIFT                               16
762#define NIC0_QM0_GLBL_AXCACHE_AW_MASK                                0xF0000
763
764/* NIC0_QM0_IND_GW_APB_CFG */
765#define NIC0_QM0_IND_GW_APB_CFG_ADDR_SHIFT                           0
766#define NIC0_QM0_IND_GW_APB_CFG_ADDR_MASK                            0x7FFFFFFF
767#define NIC0_QM0_IND_GW_APB_CFG_CMD_SHIFT                            31
768#define NIC0_QM0_IND_GW_APB_CFG_CMD_MASK                             0x80000000
769
770/* NIC0_QM0_IND_GW_APB_WDATA */
771#define NIC0_QM0_IND_GW_APB_WDATA_VAL_SHIFT                          0
772#define NIC0_QM0_IND_GW_APB_WDATA_VAL_MASK                           0xFFFFFFFF
773
774/* NIC0_QM0_IND_GW_APB_RDATA */
775#define NIC0_QM0_IND_GW_APB_RDATA_VAL_SHIFT                          0
776#define NIC0_QM0_IND_GW_APB_RDATA_VAL_MASK                           0xFFFFFFFF
777
778/* NIC0_QM0_IND_GW_APB_STATUS */
779#define NIC0_QM0_IND_GW_APB_STATUS_RDY_SHIFT                         0
780#define NIC0_QM0_IND_GW_APB_STATUS_RDY_MASK                          0x1
781#define NIC0_QM0_IND_GW_APB_STATUS_ERR_SHIFT                         1
782#define NIC0_QM0_IND_GW_APB_STATUS_ERR_MASK                          0x2
783
784/* NIC0_QM0_GLBL_ERR_ADDR_LO */
785#define NIC0_QM0_GLBL_ERR_ADDR_LO_VAL_SHIFT                          0
786#define NIC0_QM0_GLBL_ERR_ADDR_LO_VAL_MASK                           0xFFFFFFFF
787
788/* NIC0_QM0_GLBL_ERR_ADDR_HI */
789#define NIC0_QM0_GLBL_ERR_ADDR_HI_VAL_SHIFT                          0
790#define NIC0_QM0_GLBL_ERR_ADDR_HI_VAL_MASK                           0xFFFFFFFF
791
792/* NIC0_QM0_GLBL_ERR_WDATA */
793#define NIC0_QM0_GLBL_ERR_WDATA_VAL_SHIFT                            0
794#define NIC0_QM0_GLBL_ERR_WDATA_VAL_MASK                             0xFFFFFFFF
795
796/* NIC0_QM0_GLBL_MEM_INIT_BUSY */
797#define NIC0_QM0_GLBL_MEM_INIT_BUSY_RBUF_SHIFT                       0
798#define NIC0_QM0_GLBL_MEM_INIT_BUSY_RBUF_MASK                        0xF
799
800#endif /* ASIC_REG_NIC0_QM0_MASKS_H_ */