FILE
goya_security.c
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linux-6.19.14/drivers/accel/habanalabs/goya/goya_security.c
1// SPDX-License-Identifier: GPL-2.0 2 3/* 4 * Copyright 2016-2019 HabanaLabs, Ltd. 5 * All Rights Reserved. 6 */ 7 8#include "goyaP.h" 9#include "../include/goya/asic_reg/goya_regs.h" 10 11/* 12 * goya_set_block_as_protected - set the given block as protected 13 * 14 * @hdev: pointer to hl_device structure 15 * @block: block base address 16 * 17 */ 18static void goya_pb_set_block(struct hl_device *hdev, u64 base) 19{ 20 u32 pb_addr = base - CFG_BASE + PROT_BITS_OFFS; 21 22 while (pb_addr & 0xFFF) { 23 WREG32(pb_addr, 0); 24 pb_addr += 4; 25 } 26} 27 28static void goya_init_mme_protection_bits(struct hl_device *hdev) 29{ 30 u32 pb_addr, mask; 31 u8 word_offset; 32 33 /* TODO: change to real reg name when Soc Online is updated */ 34 u64 mmMME_SBB_POWER_ECO1 = 0xDFF60, 35 mmMME_SBB_POWER_ECO2 = 0xDFF64; 36 37 goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_0_BASE); 38 goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_1_BASE); 39 goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_2_BASE); 40 goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_3_BASE); 41 42 goya_pb_set_block(hdev, mmSBA_ECC_MEM_BASE); 43 goya_pb_set_block(hdev, mmSBB_ECC_MEM_BASE); 44 45 goya_pb_set_block(hdev, mmMME1_RTR_BASE); 46 goya_pb_set_block(hdev, mmMME1_RD_REGULATOR_BASE); 47 goya_pb_set_block(hdev, mmMME1_WR_REGULATOR_BASE); 48 goya_pb_set_block(hdev, mmMME2_RTR_BASE); 49 goya_pb_set_block(hdev, mmMME2_RD_REGULATOR_BASE); 50 goya_pb_set_block(hdev, mmMME2_WR_REGULATOR_BASE); 51 goya_pb_set_block(hdev, mmMME3_RTR_BASE); 52 goya_pb_set_block(hdev, mmMME3_RD_REGULATOR_BASE); 53 goya_pb_set_block(hdev, mmMME3_WR_REGULATOR_BASE); 54 55 goya_pb_set_block(hdev, mmMME4_RTR_BASE); 56 goya_pb_set_block(hdev, mmMME4_RD_REGULATOR_BASE); 57 goya_pb_set_block(hdev, mmMME4_WR_REGULATOR_BASE); 58 59 goya_pb_set_block(hdev, mmMME5_RTR_BASE); 60 goya_pb_set_block(hdev, mmMME5_RD_REGULATOR_BASE); 61 goya_pb_set_block(hdev, mmMME5_WR_REGULATOR_BASE); 62 63 goya_pb_set_block(hdev, mmMME6_RTR_BASE); 64 goya_pb_set_block(hdev, mmMME6_RD_REGULATOR_BASE); 65 goya_pb_set_block(hdev, mmMME6_WR_REGULATOR_BASE); 66 67 pb_addr = (mmMME_DUMMY & ~0xFFF) + PROT_BITS_OFFS; 68 word_offset = ((mmMME_DUMMY & PROT_BITS_OFFS) >> 7) << 2; 69 mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2); 70 mask |= 1 << ((mmMME_RESET & 0x7F) >> 2); 71 mask |= 1 << ((mmMME_STALL & 0x7F) >> 2); 72 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); 73 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); 74 mask |= 1 << ((mmMME_DBGMEM_ADD & 0x7F) >> 2); 75 mask |= 1 << ((mmMME_DBGMEM_DATA_WR & 0x7F) >> 2); 76 mask |= 1 << ((mmMME_DBGMEM_DATA_RD & 0x7F) >> 2); 77 mask |= 1 << ((mmMME_DBGMEM_CTRL & 0x7F) >> 2); 78 mask |= 1 << ((mmMME_DBGMEM_RC & 0x7F) >> 2); 79 mask |= 1 << ((mmMME_LOG_SHADOW & 0x7F) >> 2); 80 81 WREG32(pb_addr + word_offset, ~mask); 82 83 pb_addr = (mmMME_STORE_MAX_CREDIT & ~0xFFF) + PROT_BITS_OFFS; 84 word_offset = ((mmMME_STORE_MAX_CREDIT & PROT_BITS_OFFS) >> 7) << 2; 85 mask = 1 << ((mmMME_STORE_MAX_CREDIT & 0x7F) >> 2); 86 mask |= 1 << ((mmMME_AGU & 0x7F) >> 2); 87 mask |= 1 << ((mmMME_SBA & 0x7F) >> 2); 88 mask |= 1 << ((mmMME_SBB & 0x7F) >> 2); 89 mask |= 1 << ((mmMME_SBC & 0x7F) >> 2); 90 mask |= 1 << ((mmMME_WBC & 0x7F) >> 2); 91 mask |= 1 << ((mmMME_SBA_CONTROL_DATA & 0x7F) >> 2); 92 mask |= 1 << ((mmMME_SBB_CONTROL_DATA & 0x7F) >> 2); 93 mask |= 1 << ((mmMME_SBC_CONTROL_DATA & 0x7F) >> 2); 94 mask |= 1 << ((mmMME_WBC_CONTROL_DATA & 0x7F) >> 2); 95 mask |= 1 << ((mmMME_TE & 0x7F) >> 2); 96 mask |= 1 << ((mmMME_TE2DEC & 0x7F) >> 2); 97 mask |= 1 << ((mmMME_REI_STATUS & 0x7F) >> 2); 98 mask |= 1 << ((mmMME_REI_MASK & 0x7F) >> 2); 99 mask |= 1 << ((mmMME_SEI_STATUS & 0x7F) >> 2); 100 mask |= 1 << ((mmMME_SEI_MASK & 0x7F) >> 2); 101 mask |= 1 << ((mmMME_SPI_STATUS & 0x7F) >> 2); 102 mask |= 1 << ((mmMME_SPI_MASK & 0x7F) >> 2); 103 104 WREG32(pb_addr + word_offset, ~mask); 105 106 pb_addr = (mmMME_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 107 word_offset = ((mmMME_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 108 mask = 1 << ((mmMME_QM_GLBL_CFG0 & 0x7F) >> 2); 109 mask |= 1 << ((mmMME_QM_GLBL_CFG1 & 0x7F) >> 2); 110 mask |= 1 << ((mmMME_QM_GLBL_PROT & 0x7F) >> 2); 111 mask |= 1 << ((mmMME_QM_GLBL_ERR_CFG & 0x7F) >> 2); 112 mask |= 1 << ((mmMME_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 113 mask |= 1 << ((mmMME_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 114 mask |= 1 << ((mmMME_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 115 mask |= 1 << ((mmMME_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); 116 mask |= 1 << ((mmMME_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 117 mask |= 1 << ((mmMME_QM_GLBL_STS0 & 0x7F) >> 2); 118 mask |= 1 << ((mmMME_QM_GLBL_STS1 & 0x7F) >> 2); 119 mask |= 1 << ((mmMME_QM_PQ_BASE_LO & 0x7F) >> 2); 120 mask |= 1 << ((mmMME_QM_PQ_BASE_HI & 0x7F) >> 2); 121 mask |= 1 << ((mmMME_QM_PQ_SIZE & 0x7F) >> 2); 122 mask |= 1 << ((mmMME_QM_PQ_PI & 0x7F) >> 2); 123 mask |= 1 << ((mmMME_QM_PQ_CI & 0x7F) >> 2); 124 mask |= 1 << ((mmMME_QM_PQ_CFG0 & 0x7F) >> 2); 125 mask |= 1 << ((mmMME_QM_PQ_CFG1 & 0x7F) >> 2); 126 mask |= 1 << ((mmMME_QM_PQ_ARUSER & 0x7F) >> 2); 127 128 WREG32(pb_addr + word_offset, ~mask); 129 130 pb_addr = (mmMME_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; 131 word_offset = ((mmMME_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; 132 mask = 1 << ((mmMME_QM_PQ_PUSH0 & 0x7F) >> 2); 133 mask |= 1 << ((mmMME_QM_PQ_PUSH1 & 0x7F) >> 2); 134 mask |= 1 << ((mmMME_QM_PQ_PUSH2 & 0x7F) >> 2); 135 mask |= 1 << ((mmMME_QM_PQ_PUSH3 & 0x7F) >> 2); 136 mask |= 1 << ((mmMME_QM_PQ_STS0 & 0x7F) >> 2); 137 mask |= 1 << ((mmMME_QM_PQ_STS1 & 0x7F) >> 2); 138 mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); 139 mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 140 mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 141 mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 142 mask |= 1 << ((mmMME_QM_CQ_CFG0 & 0x7F) >> 2); 143 mask |= 1 << ((mmMME_QM_CQ_CFG1 & 0x7F) >> 2); 144 mask |= 1 << ((mmMME_QM_CQ_ARUSER & 0x7F) >> 2); 145 mask |= 1 << ((mmMME_QM_CQ_PTR_LO & 0x7F) >> 2); 146 mask |= 1 << ((mmMME_QM_CQ_PTR_HI & 0x7F) >> 2); 147 mask |= 1 << ((mmMME_QM_CQ_TSIZE & 0x7F) >> 2); 148 mask |= 1 << ((mmMME_QM_CQ_CTL & 0x7F) >> 2); 149 mask |= 1 << ((mmMME_QM_CQ_PTR_LO_STS & 0x7F) >> 2); 150 mask |= 1 << ((mmMME_QM_CQ_PTR_HI_STS & 0x7F) >> 2); 151 mask |= 1 << ((mmMME_QM_CQ_TSIZE_STS & 0x7F) >> 2); 152 mask |= 1 << ((mmMME_QM_CQ_CTL_STS & 0x7F) >> 2); 153 mask |= 1 << ((mmMME_QM_CQ_STS0 & 0x7F) >> 2); 154 mask |= 1 << ((mmMME_QM_CQ_STS1 & 0x7F) >> 2); 155 mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 156 mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 157 mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 158 mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 159 160 WREG32(pb_addr + word_offset, ~mask); 161 162 pb_addr = (mmMME_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 163 word_offset = ((mmMME_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 164 mask = 1 << ((mmMME_QM_CQ_IFIFO_CNT & 0x7F) >> 2); 165 mask |= 1 << ((mmMME_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 166 mask |= 1 << ((mmMME_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 167 mask |= 1 << ((mmMME_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 168 mask |= 1 << ((mmMME_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 169 mask |= 1 << ((mmMME_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 170 mask |= 1 << ((mmMME_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 171 mask |= 1 << ((mmMME_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 172 mask |= 1 << ((mmMME_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 173 mask |= 1 << ((mmMME_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 174 mask |= 1 << ((mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 175 mask |= 1 << ((mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 176 mask |= 1 << ((mmMME_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 177 mask |= 1 << ((mmMME_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 178 mask |= 1 << ((mmMME_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 179 180 WREG32(pb_addr + word_offset, ~mask); 181 182 pb_addr = (mmMME_QM_CP_STS & ~0xFFF) + PROT_BITS_OFFS; 183 word_offset = ((mmMME_QM_CP_STS & PROT_BITS_OFFS) >> 7) << 2; 184 mask = 1 << ((mmMME_QM_CP_STS & 0x7F) >> 2); 185 mask |= 1 << ((mmMME_QM_CP_CURRENT_INST_LO & 0x7F) >> 2); 186 mask |= 1 << ((mmMME_QM_CP_CURRENT_INST_HI & 0x7F) >> 2); 187 mask |= 1 << ((mmMME_QM_CP_BARRIER_CFG & 0x7F) >> 2); 188 mask |= 1 << ((mmMME_QM_CP_DBG_0 & 0x7F) >> 2); 189 mask |= 1 << ((mmMME_QM_PQ_BUF_ADDR & 0x7F) >> 2); 190 mask |= 1 << ((mmMME_QM_PQ_BUF_RDATA & 0x7F) >> 2); 191 mask |= 1 << ((mmMME_QM_CQ_BUF_ADDR & 0x7F) >> 2); 192 mask |= 1 << ((mmMME_QM_CQ_BUF_RDATA & 0x7F) >> 2); 193 194 WREG32(pb_addr + word_offset, ~mask); 195 196 pb_addr = (mmMME_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 197 word_offset = ((mmMME_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 198 mask = 1 << ((mmMME_CMDQ_GLBL_CFG0 & 0x7F) >> 2); 199 mask |= 1 << ((mmMME_CMDQ_GLBL_CFG1 & 0x7F) >> 2); 200 mask |= 1 << ((mmMME_CMDQ_GLBL_PROT & 0x7F) >> 2); 201 mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); 202 mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 203 mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 204 mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); 205 mask |= 1 << ((mmMME_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); 206 mask |= 1 << ((mmMME_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 207 mask |= 1 << ((mmMME_CMDQ_GLBL_STS0 & 0x7F) >> 2); 208 mask |= 1 << ((mmMME_CMDQ_GLBL_STS1 & 0x7F) >> 2); 209 210 WREG32(pb_addr + word_offset, ~mask); 211 212 pb_addr = (mmMME_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 213 word_offset = ((mmMME_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 214 mask = 1 << ((mmMME_CMDQ_CQ_CFG0 & 0x7F) >> 2); 215 mask |= 1 << ((mmMME_CMDQ_CQ_CFG1 & 0x7F) >> 2); 216 mask |= 1 << ((mmMME_CMDQ_CQ_ARUSER & 0x7F) >> 2); 217 mask |= 1 << ((mmMME_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); 218 mask |= 1 << ((mmMME_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); 219 mask |= 1 << ((mmMME_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); 220 mask |= 1 << ((mmMME_CMDQ_CQ_CTL_STS & 0x7F) >> 2); 221 mask |= 1 << ((mmMME_CMDQ_CQ_STS0 & 0x7F) >> 2); 222 mask |= 1 << ((mmMME_CMDQ_CQ_STS1 & 0x7F) >> 2); 223 mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 224 mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 225 mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 226 mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 227 228 WREG32(pb_addr + word_offset, ~mask); 229 230 pb_addr = (mmMME_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 231 word_offset = ((mmMME_CMDQ_CQ_IFIFO_CNT & 232 PROT_BITS_OFFS) >> 7) << 2; 233 mask = 1 << ((mmMME_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); 234 mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 235 mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 236 mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 237 mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 238 mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 239 mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 240 mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 241 mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 242 mask |= 1 << ((mmMME_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 243 mask |= 1 << ((mmMME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 244 mask |= 1 << ((mmMME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 245 mask |= 1 << ((mmMME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 246 mask |= 1 << ((mmMME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 247 mask |= 1 << ((mmMME_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 248 mask |= 1 << ((mmMME_CMDQ_CP_STS & 0x7F) >> 2); 249 mask |= 1 << ((mmMME_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); 250 251 WREG32(pb_addr + word_offset, ~mask); 252 253 pb_addr = (mmMME_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; 254 word_offset = ((mmMME_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) 255 << 2; 256 mask = 1 << ((mmMME_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); 257 mask |= 1 << ((mmMME_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); 258 mask |= 1 << ((mmMME_CMDQ_CP_DBG_0 & 0x7F) >> 2); 259 mask |= 1 << ((mmMME_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); 260 mask |= 1 << ((mmMME_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); 261 262 WREG32(pb_addr + word_offset, ~mask); 263 264 pb_addr = (mmMME_SBB_POWER_ECO1 & ~0xFFF) + PROT_BITS_OFFS; 265 word_offset = ((mmMME_SBB_POWER_ECO1 & PROT_BITS_OFFS) >> 7) << 2; 266 mask = 1 << ((mmMME_SBB_POWER_ECO1 & 0x7F) >> 2); 267 mask |= 1 << ((mmMME_SBB_POWER_ECO2 & 0x7F) >> 2); 268 269 WREG32(pb_addr + word_offset, ~mask); 270} 271 272static void goya_init_dma_protection_bits(struct hl_device *hdev) 273{ 274 u32 pb_addr, mask; 275 u8 word_offset; 276 277 goya_pb_set_block(hdev, mmDMA_NRTR_BASE); 278 goya_pb_set_block(hdev, mmDMA_RD_REGULATOR_BASE); 279 goya_pb_set_block(hdev, mmDMA_WR_REGULATOR_BASE); 280 281 pb_addr = (mmDMA_QM_0_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 282 word_offset = ((mmDMA_QM_0_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 283 mask = 1 << ((mmDMA_QM_0_GLBL_CFG0 & 0x7F) >> 2); 284 mask |= 1 << ((mmDMA_QM_0_GLBL_CFG1 & 0x7F) >> 2); 285 mask |= 1 << ((mmDMA_QM_0_GLBL_PROT & 0x7F) >> 2); 286 mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_CFG & 0x7F) >> 2); 287 mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 288 mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 289 mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_WDATA & 0x7F) >> 2); 290 mask |= 1 << ((mmDMA_QM_0_GLBL_SECURE_PROPS & 0x7F) >> 2); 291 mask |= 1 << ((mmDMA_QM_0_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 292 mask |= 1 << ((mmDMA_QM_0_GLBL_STS0 & 0x7F) >> 2); 293 mask |= 1 << ((mmDMA_QM_0_GLBL_STS1 & 0x7F) >> 2); 294 mask |= 1 << ((mmDMA_QM_0_PQ_BASE_LO & 0x7F) >> 2); 295 mask |= 1 << ((mmDMA_QM_0_PQ_BASE_HI & 0x7F) >> 2); 296 mask |= 1 << ((mmDMA_QM_0_PQ_SIZE & 0x7F) >> 2); 297 mask |= 1 << ((mmDMA_QM_0_PQ_PI & 0x7F) >> 2); 298 mask |= 1 << ((mmDMA_QM_0_PQ_CI & 0x7F) >> 2); 299 mask |= 1 << ((mmDMA_QM_0_PQ_CFG0 & 0x7F) >> 2); 300 mask |= 1 << ((mmDMA_QM_0_PQ_CFG1 & 0x7F) >> 2); 301 mask |= 1 << ((mmDMA_QM_0_PQ_ARUSER & 0x7F) >> 2); 302 303 WREG32(pb_addr + word_offset, ~mask); 304 305 pb_addr = (mmDMA_QM_0_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; 306 word_offset = ((mmDMA_QM_0_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; 307 mask = 1 << ((mmDMA_QM_0_PQ_PUSH0 & 0x7F) >> 2); 308 mask |= 1 << ((mmDMA_QM_0_PQ_PUSH1 & 0x7F) >> 2); 309 mask |= 1 << ((mmDMA_QM_0_PQ_PUSH2 & 0x7F) >> 2); 310 mask |= 1 << ((mmDMA_QM_0_PQ_PUSH3 & 0x7F) >> 2); 311 mask |= 1 << ((mmDMA_QM_0_PQ_STS0 & 0x7F) >> 2); 312 mask |= 1 << ((mmDMA_QM_0_PQ_STS1 & 0x7F) >> 2); 313 mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); 314 mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 315 mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 316 mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 317 mask |= 1 << ((mmDMA_QM_0_CQ_CFG0 & 0x7F) >> 2); 318 mask |= 1 << ((mmDMA_QM_0_CQ_CFG1 & 0x7F) >> 2); 319 mask |= 1 << ((mmDMA_QM_0_CQ_ARUSER & 0x7F) >> 2); 320 mask |= 1 << ((mmDMA_QM_0_CQ_PTR_LO & 0x7F) >> 2); 321 mask |= 1 << ((mmDMA_QM_0_CQ_PTR_HI & 0x7F) >> 2); 322 mask |= 1 << ((mmDMA_QM_0_CQ_TSIZE & 0x7F) >> 2); 323 mask |= 1 << ((mmDMA_QM_0_CQ_CTL & 0x7F) >> 2); 324 mask |= 1 << ((mmDMA_QM_0_CQ_PTR_LO_STS & 0x7F) >> 2); 325 mask |= 1 << ((mmDMA_QM_0_CQ_PTR_HI_STS & 0x7F) >> 2); 326 mask |= 1 << ((mmDMA_QM_0_CQ_TSIZE_STS & 0x7F) >> 2); 327 mask |= 1 << ((mmDMA_QM_0_CQ_CTL_STS & 0x7F) >> 2); 328 mask |= 1 << ((mmDMA_QM_0_CQ_STS0 & 0x7F) >> 2); 329 mask |= 1 << ((mmDMA_QM_0_CQ_STS1 & 0x7F) >> 2); 330 mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 331 mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 332 mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 333 mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 334 335 WREG32(pb_addr + word_offset, ~mask); 336 337 pb_addr = (mmDMA_QM_0_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 338 word_offset = ((mmDMA_QM_0_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 339 mask = 1 << ((mmDMA_QM_0_CQ_IFIFO_CNT & 0x7F) >> 2); 340 mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 341 mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 342 mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 343 mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 344 mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 345 mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 346 mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 347 mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 348 mask |= 1 << ((mmDMA_QM_0_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 349 mask |= 1 << ((mmDMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 350 mask |= 1 << ((mmDMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 351 mask |= 1 << ((mmDMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 352 mask |= 1 << ((mmDMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 353 mask |= 1 << ((mmDMA_QM_0_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 354 355 WREG32(pb_addr + word_offset, ~mask); 356 357 goya_pb_set_block(hdev, mmDMA_CH_0_BASE); 358 359 pb_addr = (mmDMA_QM_1_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 360 word_offset = ((mmDMA_QM_1_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 361 mask = 1 << ((mmDMA_QM_1_GLBL_CFG0 & 0x7F) >> 2); 362 mask |= 1 << ((mmDMA_QM_1_GLBL_CFG1 & 0x7F) >> 2); 363 mask |= 1 << ((mmDMA_QM_1_GLBL_PROT & 0x7F) >> 2); 364 mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_CFG & 0x7F) >> 2); 365 mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 366 mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 367 mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_WDATA & 0x7F) >> 2); 368 mask |= 1 << ((mmDMA_QM_1_GLBL_SECURE_PROPS & 0x7F) >> 2); 369 mask |= 1 << ((mmDMA_QM_1_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 370 mask |= 1 << ((mmDMA_QM_1_GLBL_STS0 & 0x7F) >> 2); 371 mask |= 1 << ((mmDMA_QM_1_GLBL_STS1 & 0x7F) >> 2); 372 mask |= 1 << ((mmDMA_QM_1_PQ_BASE_LO & 0x7F) >> 2); 373 mask |= 1 << ((mmDMA_QM_1_PQ_BASE_HI & 0x7F) >> 2); 374 mask |= 1 << ((mmDMA_QM_1_PQ_SIZE & 0x7F) >> 2); 375 mask |= 1 << ((mmDMA_QM_1_PQ_PI & 0x7F) >> 2); 376 mask |= 1 << ((mmDMA_QM_1_PQ_CI & 0x7F) >> 2); 377 mask |= 1 << ((mmDMA_QM_1_PQ_CFG0 & 0x7F) >> 2); 378 mask |= 1 << ((mmDMA_QM_1_PQ_CFG1 & 0x7F) >> 2); 379 mask |= 1 << ((mmDMA_QM_1_PQ_ARUSER & 0x7F) >> 2); 380 381 WREG32(pb_addr + word_offset, ~mask); 382 383 pb_addr = (mmDMA_QM_1_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; 384 word_offset = ((mmDMA_QM_1_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; 385 mask = 1 << ((mmDMA_QM_1_PQ_PUSH0 & 0x7F) >> 2); 386 mask |= 1 << ((mmDMA_QM_1_PQ_PUSH1 & 0x7F) >> 2); 387 mask |= 1 << ((mmDMA_QM_1_PQ_PUSH2 & 0x7F) >> 2); 388 mask |= 1 << ((mmDMA_QM_1_PQ_PUSH3 & 0x7F) >> 2); 389 mask |= 1 << ((mmDMA_QM_1_PQ_STS0 & 0x7F) >> 2); 390 mask |= 1 << ((mmDMA_QM_1_PQ_STS1 & 0x7F) >> 2); 391 mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); 392 mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 393 mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 394 mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 395 mask |= 1 << ((mmDMA_QM_1_CQ_CFG0 & 0x7F) >> 2); 396 mask |= 1 << ((mmDMA_QM_1_CQ_CFG1 & 0x7F) >> 2); 397 mask |= 1 << ((mmDMA_QM_1_CQ_ARUSER & 0x7F) >> 2); 398 mask |= 1 << ((mmDMA_QM_1_CQ_PTR_LO & 0x7F) >> 2); 399 mask |= 1 << ((mmDMA_QM_1_CQ_PTR_HI & 0x7F) >> 2); 400 mask |= 1 << ((mmDMA_QM_1_CQ_TSIZE & 0x7F) >> 2); 401 mask |= 1 << ((mmDMA_QM_1_CQ_CTL & 0x7F) >> 2); 402 mask |= 1 << ((mmDMA_QM_1_CQ_PTR_LO_STS & 0x7F) >> 2); 403 mask |= 1 << ((mmDMA_QM_1_CQ_PTR_HI_STS & 0x7F) >> 2); 404 mask |= 1 << ((mmDMA_QM_1_CQ_TSIZE_STS & 0x7F) >> 2); 405 mask |= 1 << ((mmDMA_QM_1_CQ_CTL_STS & 0x7F) >> 2); 406 mask |= 1 << ((mmDMA_QM_1_CQ_STS0 & 0x7F) >> 2); 407 mask |= 1 << ((mmDMA_QM_1_CQ_STS1 & 0x7F) >> 2); 408 mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 409 mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 410 mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 411 mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 412 413 WREG32(pb_addr + word_offset, ~mask); 414 415 pb_addr = (mmDMA_QM_1_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 416 word_offset = ((mmDMA_QM_1_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 417 mask = 1 << ((mmDMA_QM_1_CQ_IFIFO_CNT & 0x7F) >> 2); 418 mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 419 mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 420 mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 421 mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 422 mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 423 mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 424 mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 425 mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 426 mask |= 1 << ((mmDMA_QM_1_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 427 mask |= 1 << ((mmDMA_QM_1_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 428 mask |= 1 << ((mmDMA_QM_1_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 429 mask |= 1 << ((mmDMA_QM_1_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 430 mask |= 1 << ((mmDMA_QM_1_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 431 mask |= 1 << ((mmDMA_QM_1_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 432 433 WREG32(pb_addr + word_offset, ~mask); 434 435 goya_pb_set_block(hdev, mmDMA_CH_1_BASE); 436 437 pb_addr = (mmDMA_QM_2_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 438 word_offset = ((mmDMA_QM_2_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 439 mask = 1 << ((mmDMA_QM_2_GLBL_CFG0 & 0x7F) >> 2); 440 mask |= 1 << ((mmDMA_QM_2_GLBL_CFG1 & 0x7F) >> 2); 441 mask |= 1 << ((mmDMA_QM_2_GLBL_PROT & 0x7F) >> 2); 442 mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_CFG & 0x7F) >> 2); 443 mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 444 mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 445 mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_WDATA & 0x7F) >> 2); 446 mask |= 1 << ((mmDMA_QM_2_GLBL_SECURE_PROPS & 0x7F) >> 2); 447 mask |= 1 << ((mmDMA_QM_2_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 448 mask |= 1 << ((mmDMA_QM_2_GLBL_STS0 & 0x7F) >> 2); 449 mask |= 1 << ((mmDMA_QM_2_GLBL_STS1 & 0x7F) >> 2); 450 mask |= 1 << ((mmDMA_QM_2_PQ_BASE_LO & 0x7F) >> 2); 451 mask |= 1 << ((mmDMA_QM_2_PQ_BASE_HI & 0x7F) >> 2); 452 mask |= 1 << ((mmDMA_QM_2_PQ_SIZE & 0x7F) >> 2); 453 mask |= 1 << ((mmDMA_QM_2_PQ_PI & 0x7F) >> 2); 454 mask |= 1 << ((mmDMA_QM_2_PQ_CI & 0x7F) >> 2); 455 mask |= 1 << ((mmDMA_QM_2_PQ_CFG0 & 0x7F) >> 2); 456 mask |= 1 << ((mmDMA_QM_2_PQ_CFG1 & 0x7F) >> 2); 457 mask |= 1 << ((mmDMA_QM_2_PQ_ARUSER & 0x7F) >> 2); 458 459 WREG32(pb_addr + word_offset, ~mask); 460 461 pb_addr = (mmDMA_QM_2_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; 462 word_offset = ((mmDMA_QM_2_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; 463 mask = 1 << ((mmDMA_QM_2_PQ_PUSH0 & 0x7F) >> 2); 464 mask |= 1 << ((mmDMA_QM_2_PQ_PUSH1 & 0x7F) >> 2); 465 mask |= 1 << ((mmDMA_QM_2_PQ_PUSH2 & 0x7F) >> 2); 466 mask |= 1 << ((mmDMA_QM_2_PQ_PUSH3 & 0x7F) >> 2); 467 mask |= 1 << ((mmDMA_QM_2_PQ_STS0 & 0x7F) >> 2); 468 mask |= 1 << ((mmDMA_QM_2_PQ_STS1 & 0x7F) >> 2); 469 mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); 470 mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 471 mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 472 mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 473 mask |= 1 << ((mmDMA_QM_2_CQ_CFG0 & 0x7F) >> 2); 474 mask |= 1 << ((mmDMA_QM_2_CQ_CFG1 & 0x7F) >> 2); 475 mask |= 1 << ((mmDMA_QM_2_CQ_ARUSER & 0x7F) >> 2); 476 mask |= 1 << ((mmDMA_QM_2_CQ_PTR_LO & 0x7F) >> 2); 477 mask |= 1 << ((mmDMA_QM_2_CQ_PTR_HI & 0x7F) >> 2); 478 mask |= 1 << ((mmDMA_QM_2_CQ_TSIZE & 0x7F) >> 2); 479 mask |= 1 << ((mmDMA_QM_2_CQ_CTL & 0x7F) >> 2); 480 mask |= 1 << ((mmDMA_QM_2_CQ_PTR_LO_STS & 0x7F) >> 2); 481 mask |= 1 << ((mmDMA_QM_2_CQ_PTR_HI_STS & 0x7F) >> 2); 482 mask |= 1 << ((mmDMA_QM_2_CQ_TSIZE_STS & 0x7F) >> 2); 483 mask |= 1 << ((mmDMA_QM_2_CQ_CTL_STS & 0x7F) >> 2); 484 mask |= 1 << ((mmDMA_QM_2_CQ_STS0 & 0x7F) >> 2); 485 mask |= 1 << ((mmDMA_QM_2_CQ_STS1 & 0x7F) >> 2); 486 mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 487 mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 488 mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 489 mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 490 491 WREG32(pb_addr + word_offset, ~mask); 492 493 pb_addr = (mmDMA_QM_2_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 494 word_offset = ((mmDMA_QM_2_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 495 mask = 1 << ((mmDMA_QM_2_CQ_IFIFO_CNT & 0x7F) >> 2); 496 mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 497 mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 498 mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 499 mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 500 mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 501 mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 502 mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 503 mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 504 mask |= 1 << ((mmDMA_QM_2_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 505 mask |= 1 << ((mmDMA_QM_2_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 506 mask |= 1 << ((mmDMA_QM_2_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 507 mask |= 1 << ((mmDMA_QM_2_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 508 mask |= 1 << ((mmDMA_QM_2_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 509 mask |= 1 << ((mmDMA_QM_2_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 510 511 WREG32(pb_addr + word_offset, ~mask); 512 513 goya_pb_set_block(hdev, mmDMA_CH_2_BASE); 514 515 pb_addr = (mmDMA_QM_3_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 516 word_offset = ((mmDMA_QM_3_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 517 mask = 1 << ((mmDMA_QM_3_GLBL_CFG0 & 0x7F) >> 2); 518 mask |= 1 << ((mmDMA_QM_3_GLBL_CFG1 & 0x7F) >> 2); 519 mask |= 1 << ((mmDMA_QM_3_GLBL_PROT & 0x7F) >> 2); 520 mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_CFG & 0x7F) >> 2); 521 mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 522 mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 523 mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_WDATA & 0x7F) >> 2); 524 mask |= 1 << ((mmDMA_QM_3_GLBL_SECURE_PROPS & 0x7F) >> 2); 525 mask |= 1 << ((mmDMA_QM_3_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 526 mask |= 1 << ((mmDMA_QM_3_GLBL_STS0 & 0x7F) >> 2); 527 mask |= 1 << ((mmDMA_QM_3_GLBL_STS1 & 0x7F) >> 2); 528 mask |= 1 << ((mmDMA_QM_3_PQ_BASE_LO & 0x7F) >> 2); 529 mask |= 1 << ((mmDMA_QM_3_PQ_BASE_HI & 0x7F) >> 2); 530 mask |= 1 << ((mmDMA_QM_3_PQ_SIZE & 0x7F) >> 2); 531 mask |= 1 << ((mmDMA_QM_3_PQ_PI & 0x7F) >> 2); 532 mask |= 1 << ((mmDMA_QM_3_PQ_CI & 0x7F) >> 2); 533 mask |= 1 << ((mmDMA_QM_3_PQ_CFG0 & 0x7F) >> 2); 534 mask |= 1 << ((mmDMA_QM_3_PQ_CFG1 & 0x7F) >> 2); 535 mask |= 1 << ((mmDMA_QM_3_PQ_ARUSER & 0x7F) >> 2); 536 537 WREG32(pb_addr + word_offset, ~mask); 538 539 pb_addr = (mmDMA_QM_3_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; 540 word_offset = ((mmDMA_QM_3_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; 541 mask = 1 << ((mmDMA_QM_3_PQ_PUSH0 & 0x7F) >> 2); 542 mask |= 1 << ((mmDMA_QM_3_PQ_PUSH1 & 0x7F) >> 2); 543 mask |= 1 << ((mmDMA_QM_3_PQ_PUSH2 & 0x7F) >> 2); 544 mask |= 1 << ((mmDMA_QM_3_PQ_PUSH3 & 0x7F) >> 2); 545 mask |= 1 << ((mmDMA_QM_3_PQ_STS0 & 0x7F) >> 2); 546 mask |= 1 << ((mmDMA_QM_3_PQ_STS1 & 0x7F) >> 2); 547 mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); 548 mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 549 mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 550 mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 551 mask |= 1 << ((mmDMA_QM_3_CQ_CFG0 & 0x7F) >> 2); 552 mask |= 1 << ((mmDMA_QM_3_CQ_CFG1 & 0x7F) >> 2); 553 mask |= 1 << ((mmDMA_QM_3_CQ_ARUSER & 0x7F) >> 2); 554 mask |= 1 << ((mmDMA_QM_3_CQ_PTR_LO & 0x7F) >> 2); 555 mask |= 1 << ((mmDMA_QM_3_CQ_PTR_HI & 0x7F) >> 2); 556 mask |= 1 << ((mmDMA_QM_3_CQ_TSIZE & 0x7F) >> 2); 557 mask |= 1 << ((mmDMA_QM_3_CQ_CTL & 0x7F) >> 2); 558 mask |= 1 << ((mmDMA_QM_3_CQ_PTR_LO_STS & 0x7F) >> 2); 559 mask |= 1 << ((mmDMA_QM_3_CQ_PTR_HI_STS & 0x7F) >> 2); 560 mask |= 1 << ((mmDMA_QM_3_CQ_TSIZE_STS & 0x7F) >> 2); 561 mask |= 1 << ((mmDMA_QM_3_CQ_CTL_STS & 0x7F) >> 2); 562 mask |= 1 << ((mmDMA_QM_3_CQ_STS0 & 0x7F) >> 2); 563 mask |= 1 << ((mmDMA_QM_3_CQ_STS1 & 0x7F) >> 2); 564 mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 565 mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 566 mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 567 mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 568 569 WREG32(pb_addr + word_offset, ~mask); 570 571 pb_addr = (mmDMA_QM_3_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 572 word_offset = ((mmDMA_QM_3_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 573 mask = 1 << ((mmDMA_QM_3_CQ_IFIFO_CNT & 0x7F) >> 2); 574 mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 575 mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 576 mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 577 mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 578 mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 579 mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 580 mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 581 mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 582 mask |= 1 << ((mmDMA_QM_3_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 583 mask |= 1 << ((mmDMA_QM_3_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 584 mask |= 1 << ((mmDMA_QM_3_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 585 mask |= 1 << ((mmDMA_QM_3_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 586 mask |= 1 << ((mmDMA_QM_3_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 587 mask |= 1 << ((mmDMA_QM_3_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 588 589 WREG32(pb_addr + word_offset, ~mask); 590 591 goya_pb_set_block(hdev, mmDMA_CH_3_BASE); 592 593 pb_addr = (mmDMA_QM_4_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 594 word_offset = ((mmDMA_QM_4_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 595 mask = 1 << ((mmDMA_QM_4_GLBL_CFG0 & 0x7F) >> 2); 596 mask |= 1 << ((mmDMA_QM_4_GLBL_CFG1 & 0x7F) >> 2); 597 mask |= 1 << ((mmDMA_QM_4_GLBL_PROT & 0x7F) >> 2); 598 mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_CFG & 0x7F) >> 2); 599 mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 600 mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 601 mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_WDATA & 0x7F) >> 2); 602 mask |= 1 << ((mmDMA_QM_4_GLBL_SECURE_PROPS & 0x7F) >> 2); 603 mask |= 1 << ((mmDMA_QM_4_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 604 mask |= 1 << ((mmDMA_QM_4_GLBL_STS0 & 0x7F) >> 2); 605 mask |= 1 << ((mmDMA_QM_4_GLBL_STS1 & 0x7F) >> 2); 606 mask |= 1 << ((mmDMA_QM_4_PQ_BASE_LO & 0x7F) >> 2); 607 mask |= 1 << ((mmDMA_QM_4_PQ_BASE_HI & 0x7F) >> 2); 608 mask |= 1 << ((mmDMA_QM_4_PQ_SIZE & 0x7F) >> 2); 609 mask |= 1 << ((mmDMA_QM_4_PQ_PI & 0x7F) >> 2); 610 mask |= 1 << ((mmDMA_QM_4_PQ_CI & 0x7F) >> 2); 611 mask |= 1 << ((mmDMA_QM_4_PQ_CFG0 & 0x7F) >> 2); 612 mask |= 1 << ((mmDMA_QM_4_PQ_CFG1 & 0x7F) >> 2); 613 mask |= 1 << ((mmDMA_QM_4_PQ_ARUSER & 0x7F) >> 2); 614 615 WREG32(pb_addr + word_offset, ~mask); 616 617 pb_addr = (mmDMA_QM_4_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; 618 word_offset = ((mmDMA_QM_4_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; 619 mask = 1 << ((mmDMA_QM_4_PQ_PUSH0 & 0x7F) >> 2); 620 mask |= 1 << ((mmDMA_QM_4_PQ_PUSH1 & 0x7F) >> 2); 621 mask |= 1 << ((mmDMA_QM_4_PQ_PUSH2 & 0x7F) >> 2); 622 mask |= 1 << ((mmDMA_QM_4_PQ_PUSH3 & 0x7F) >> 2); 623 mask |= 1 << ((mmDMA_QM_4_PQ_STS0 & 0x7F) >> 2); 624 mask |= 1 << ((mmDMA_QM_4_PQ_STS1 & 0x7F) >> 2); 625 mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); 626 mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 627 mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 628 mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 629 mask |= 1 << ((mmDMA_QM_4_CQ_CFG0 & 0x7F) >> 2); 630 mask |= 1 << ((mmDMA_QM_4_CQ_CFG1 & 0x7F) >> 2); 631 mask |= 1 << ((mmDMA_QM_4_CQ_ARUSER & 0x7F) >> 2); 632 mask |= 1 << ((mmDMA_QM_4_CQ_PTR_LO & 0x7F) >> 2); 633 mask |= 1 << ((mmDMA_QM_4_CQ_PTR_HI & 0x7F) >> 2); 634 mask |= 1 << ((mmDMA_QM_4_CQ_TSIZE & 0x7F) >> 2); 635 mask |= 1 << ((mmDMA_QM_4_CQ_CTL & 0x7F) >> 2); 636 mask |= 1 << ((mmDMA_QM_4_CQ_PTR_LO_STS & 0x7F) >> 2); 637 mask |= 1 << ((mmDMA_QM_4_CQ_PTR_HI_STS & 0x7F) >> 2); 638 mask |= 1 << ((mmDMA_QM_4_CQ_TSIZE_STS & 0x7F) >> 2); 639 mask |= 1 << ((mmDMA_QM_4_CQ_CTL_STS & 0x7F) >> 2); 640 mask |= 1 << ((mmDMA_QM_4_CQ_STS0 & 0x7F) >> 2); 641 mask |= 1 << ((mmDMA_QM_4_CQ_STS1 & 0x7F) >> 2); 642 mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 643 mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 644 mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 645 mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 646 647 WREG32(pb_addr + word_offset, ~mask); 648 649 pb_addr = (mmDMA_QM_4_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 650 word_offset = ((mmDMA_QM_4_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 651 mask = 1 << ((mmDMA_QM_4_CQ_IFIFO_CNT & 0x7F) >> 2); 652 mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 653 mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 654 mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 655 mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 656 mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 657 mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 658 mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 659 mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 660 mask |= 1 << ((mmDMA_QM_4_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 661 mask |= 1 << ((mmDMA_QM_4_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 662 mask |= 1 << ((mmDMA_QM_4_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 663 mask |= 1 << ((mmDMA_QM_4_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 664 mask |= 1 << ((mmDMA_QM_4_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 665 mask |= 1 << ((mmDMA_QM_4_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 666 667 WREG32(pb_addr + word_offset, ~mask); 668 669 goya_pb_set_block(hdev, mmDMA_CH_4_BASE); 670} 671 672static void goya_init_tpc_protection_bits(struct hl_device *hdev) 673{ 674 u32 pb_addr, mask; 675 u8 word_offset; 676 677 goya_pb_set_block(hdev, mmTPC0_RD_REGULATOR_BASE); 678 goya_pb_set_block(hdev, mmTPC0_WR_REGULATOR_BASE); 679 680 pb_addr = (mmTPC0_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; 681 word_offset = ((mmTPC0_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; 682 683 mask = 1 << ((mmTPC0_CFG_SEMAPHORE & 0x7F) >> 2); 684 mask |= 1 << ((mmTPC0_CFG_VFLAGS & 0x7F) >> 2); 685 mask |= 1 << ((mmTPC0_CFG_SFLAGS & 0x7F) >> 2); 686 mask |= 1 << ((mmTPC0_CFG_STATUS & 0x7F) >> 2); 687 688 WREG32(pb_addr + word_offset, ~mask); 689 690 pb_addr = (mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; 691 word_offset = ((mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH & 692 PROT_BITS_OFFS) >> 7) << 2; 693 mask = 1 << ((mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); 694 mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); 695 mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); 696 mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); 697 mask |= 1 << ((mmTPC0_CFG_TPC_STALL & 0x7F) >> 2); 698 mask |= 1 << ((mmTPC0_CFG_MSS_CONFIG & 0x7F) >> 2); 699 mask |= 1 << ((mmTPC0_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); 700 mask |= 1 << ((mmTPC0_CFG_TPC_INTR_MASK & 0x7F) >> 2); 701 702 WREG32(pb_addr + word_offset, ~mask); 703 704 pb_addr = (mmTPC0_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS; 705 word_offset = ((mmTPC0_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2; 706 mask = 1 << ((mmTPC0_CFG_ARUSER & 0x7F) >> 2); 707 mask |= 1 << ((mmTPC0_CFG_AWUSER & 0x7F) >> 2); 708 709 WREG32(pb_addr + word_offset, ~mask); 710 711 pb_addr = (mmTPC0_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS; 712 word_offset = ((mmTPC0_CFG_FUNC_MBIST_CNTRL & 713 PROT_BITS_OFFS) >> 7) << 2; 714 mask = 1 << ((mmTPC0_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); 715 mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); 716 mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); 717 mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); 718 mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); 719 mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); 720 mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); 721 mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); 722 mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); 723 mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); 724 mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); 725 mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); 726 727 WREG32(pb_addr + word_offset, ~mask); 728 729 pb_addr = (mmTPC0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 730 word_offset = ((mmTPC0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 731 mask = 1 << ((mmTPC0_QM_GLBL_CFG0 & 0x7F) >> 2); 732 mask |= 1 << ((mmTPC0_QM_GLBL_CFG1 & 0x7F) >> 2); 733 mask |= 1 << ((mmTPC0_QM_GLBL_PROT & 0x7F) >> 2); 734 mask |= 1 << ((mmTPC0_QM_GLBL_ERR_CFG & 0x7F) >> 2); 735 mask |= 1 << ((mmTPC0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 736 mask |= 1 << ((mmTPC0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 737 mask |= 1 << ((mmTPC0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 738 mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); 739 mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 740 mask |= 1 << ((mmTPC0_QM_GLBL_STS0 & 0x7F) >> 2); 741 mask |= 1 << ((mmTPC0_QM_GLBL_STS1 & 0x7F) >> 2); 742 mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO & 0x7F) >> 2); 743 mask |= 1 << ((mmTPC0_QM_PQ_BASE_HI & 0x7F) >> 2); 744 mask |= 1 << ((mmTPC0_QM_PQ_SIZE & 0x7F) >> 2); 745 mask |= 1 << ((mmTPC0_QM_PQ_PI & 0x7F) >> 2); 746 mask |= 1 << ((mmTPC0_QM_PQ_CI & 0x7F) >> 2); 747 mask |= 1 << ((mmTPC0_QM_PQ_CFG0 & 0x7F) >> 2); 748 mask |= 1 << ((mmTPC0_QM_PQ_CFG1 & 0x7F) >> 2); 749 mask |= 1 << ((mmTPC0_QM_PQ_ARUSER & 0x7F) >> 2); 750 751 WREG32(pb_addr + word_offset, ~mask); 752 753 pb_addr = (mmTPC0_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; 754 word_offset = ((mmTPC0_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; 755 mask = 1 << ((mmTPC0_QM_PQ_PUSH0 & 0x7F) >> 2); 756 mask |= 1 << ((mmTPC0_QM_PQ_PUSH1 & 0x7F) >> 2); 757 mask |= 1 << ((mmTPC0_QM_PQ_PUSH2 & 0x7F) >> 2); 758 mask |= 1 << ((mmTPC0_QM_PQ_PUSH3 & 0x7F) >> 2); 759 mask |= 1 << ((mmTPC0_QM_PQ_STS0 & 0x7F) >> 2); 760 mask |= 1 << ((mmTPC0_QM_PQ_STS1 & 0x7F) >> 2); 761 mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); 762 mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 763 mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 764 mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 765 mask |= 1 << ((mmTPC0_QM_CQ_CFG0 & 0x7F) >> 2); 766 mask |= 1 << ((mmTPC0_QM_CQ_CFG1 & 0x7F) >> 2); 767 mask |= 1 << ((mmTPC0_QM_CQ_ARUSER & 0x7F) >> 2); 768 mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO & 0x7F) >> 2); 769 mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI & 0x7F) >> 2); 770 mask |= 1 << ((mmTPC0_QM_CQ_TSIZE & 0x7F) >> 2); 771 mask |= 1 << ((mmTPC0_QM_CQ_CTL & 0x7F) >> 2); 772 mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS & 0x7F) >> 2); 773 mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS & 0x7F) >> 2); 774 mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS & 0x7F) >> 2); 775 mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS & 0x7F) >> 2); 776 mask |= 1 << ((mmTPC0_QM_CQ_STS0 & 0x7F) >> 2); 777 mask |= 1 << ((mmTPC0_QM_CQ_STS1 & 0x7F) >> 2); 778 mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 779 mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 780 mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 781 mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 782 783 WREG32(pb_addr + word_offset, ~mask); 784 785 pb_addr = (mmTPC0_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 786 word_offset = ((mmTPC0_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 787 mask = 1 << ((mmTPC0_QM_CQ_IFIFO_CNT & 0x7F) >> 2); 788 mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 789 mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 790 mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 791 mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 792 mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 793 mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 794 mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 795 mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 796 mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 797 mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 798 mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 799 mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 800 mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 801 mask |= 1 << ((mmTPC0_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 802 803 WREG32(pb_addr + word_offset, ~mask); 804 805 pb_addr = (mmTPC0_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 806 word_offset = ((mmTPC0_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 807 mask = 1 << ((mmTPC0_CMDQ_GLBL_CFG0 & 0x7F) >> 2); 808 mask |= 1 << ((mmTPC0_CMDQ_GLBL_CFG1 & 0x7F) >> 2); 809 mask |= 1 << ((mmTPC0_CMDQ_GLBL_PROT & 0x7F) >> 2); 810 mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); 811 mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 812 mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 813 mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); 814 mask |= 1 << ((mmTPC0_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); 815 mask |= 1 << ((mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 816 mask |= 1 << ((mmTPC0_CMDQ_GLBL_STS0 & 0x7F) >> 2); 817 mask |= 1 << ((mmTPC0_CMDQ_GLBL_STS1 & 0x7F) >> 2); 818 819 WREG32(pb_addr + word_offset, ~mask); 820 821 pb_addr = (mmTPC0_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 822 word_offset = ((mmTPC0_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 823 mask = 1 << ((mmTPC0_CMDQ_CQ_CFG0 & 0x7F) >> 2); 824 mask |= 1 << ((mmTPC0_CMDQ_CQ_CFG1 & 0x7F) >> 2); 825 mask |= 1 << ((mmTPC0_CMDQ_CQ_ARUSER & 0x7F) >> 2); 826 mask |= 1 << ((mmTPC0_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); 827 mask |= 1 << ((mmTPC0_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); 828 mask |= 1 << ((mmTPC0_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); 829 mask |= 1 << ((mmTPC0_CMDQ_CQ_CTL_STS & 0x7F) >> 2); 830 mask |= 1 << ((mmTPC0_CMDQ_CQ_STS0 & 0x7F) >> 2); 831 mask |= 1 << ((mmTPC0_CMDQ_CQ_STS1 & 0x7F) >> 2); 832 mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 833 mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 834 mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 835 mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 836 837 WREG32(pb_addr + word_offset, ~mask); 838 839 pb_addr = (mmTPC0_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 840 word_offset = ((mmTPC0_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 841 mask = 1 << ((mmTPC0_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); 842 mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 843 mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 844 mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 845 mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 846 mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 847 mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 848 mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 849 mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 850 mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 851 mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 852 mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 853 mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 854 mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 855 mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 856 mask |= 1 << ((mmTPC0_CMDQ_CP_STS & 0x7F) >> 2); 857 mask |= 1 << ((mmTPC0_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); 858 859 WREG32(pb_addr + word_offset, ~mask); 860 861 pb_addr = (mmTPC0_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; 862 word_offset = ((mmTPC0_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) 863 << 2; 864 mask = 1 << ((mmTPC0_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); 865 mask |= 1 << ((mmTPC0_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); 866 mask |= 1 << ((mmTPC0_CMDQ_CP_DBG_0 & 0x7F) >> 2); 867 mask |= 1 << ((mmTPC0_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); 868 mask |= 1 << ((mmTPC0_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); 869 870 WREG32(pb_addr + word_offset, ~mask); 871 872 goya_pb_set_block(hdev, mmTPC1_RTR_BASE); 873 goya_pb_set_block(hdev, mmTPC1_RD_REGULATOR_BASE); 874 goya_pb_set_block(hdev, mmTPC1_WR_REGULATOR_BASE); 875 876 pb_addr = (mmTPC1_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; 877 word_offset = ((mmTPC1_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; 878 879 mask = 1 << ((mmTPC1_CFG_SEMAPHORE & 0x7F) >> 2); 880 mask |= 1 << ((mmTPC1_CFG_VFLAGS & 0x7F) >> 2); 881 mask |= 1 << ((mmTPC1_CFG_SFLAGS & 0x7F) >> 2); 882 mask |= 1 << ((mmTPC1_CFG_STATUS & 0x7F) >> 2); 883 884 WREG32(pb_addr + word_offset, ~mask); 885 886 pb_addr = (mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; 887 word_offset = ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & 888 PROT_BITS_OFFS) >> 7) << 2; 889 mask = 1 << ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); 890 mask |= 1 << ((mmTPC1_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); 891 mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); 892 mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); 893 mask |= 1 << ((mmTPC1_CFG_TPC_STALL & 0x7F) >> 2); 894 mask |= 1 << ((mmTPC1_CFG_MSS_CONFIG & 0x7F) >> 2); 895 mask |= 1 << ((mmTPC1_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); 896 mask |= 1 << ((mmTPC1_CFG_TPC_INTR_MASK & 0x7F) >> 2); 897 898 WREG32(pb_addr + word_offset, ~mask); 899 900 pb_addr = (mmTPC1_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS; 901 word_offset = ((mmTPC1_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2; 902 mask = 1 << ((mmTPC1_CFG_ARUSER & 0x7F) >> 2); 903 mask |= 1 << ((mmTPC1_CFG_AWUSER & 0x7F) >> 2); 904 905 WREG32(pb_addr + word_offset, ~mask); 906 907 pb_addr = (mmTPC1_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS; 908 word_offset = ((mmTPC1_CFG_FUNC_MBIST_CNTRL & PROT_BITS_OFFS) >> 7) 909 << 2; 910 mask = 1 << ((mmTPC1_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); 911 mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); 912 mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); 913 mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); 914 mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); 915 mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); 916 mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); 917 mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); 918 mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); 919 mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); 920 mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); 921 mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); 922 923 WREG32(pb_addr + word_offset, ~mask); 924 925 pb_addr = (mmTPC1_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 926 word_offset = ((mmTPC1_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 927 mask = 1 << ((mmTPC1_QM_GLBL_CFG0 & 0x7F) >> 2); 928 mask |= 1 << ((mmTPC1_QM_GLBL_CFG1 & 0x7F) >> 2); 929 mask |= 1 << ((mmTPC1_QM_GLBL_PROT & 0x7F) >> 2); 930 mask |= 1 << ((mmTPC1_QM_GLBL_ERR_CFG & 0x7F) >> 2); 931 mask |= 1 << ((mmTPC1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 932 mask |= 1 << ((mmTPC1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 933 mask |= 1 << ((mmTPC1_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 934 mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); 935 mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 936 mask |= 1 << ((mmTPC1_QM_GLBL_STS0 & 0x7F) >> 2); 937 mask |= 1 << ((mmTPC1_QM_GLBL_STS1 & 0x7F) >> 2); 938 mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO & 0x7F) >> 2); 939 mask |= 1 << ((mmTPC1_QM_PQ_BASE_HI & 0x7F) >> 2); 940 mask |= 1 << ((mmTPC1_QM_PQ_SIZE & 0x7F) >> 2); 941 mask |= 1 << ((mmTPC1_QM_PQ_PI & 0x7F) >> 2); 942 mask |= 1 << ((mmTPC1_QM_PQ_CI & 0x7F) >> 2); 943 mask |= 1 << ((mmTPC1_QM_PQ_CFG0 & 0x7F) >> 2); 944 mask |= 1 << ((mmTPC1_QM_PQ_CFG1 & 0x7F) >> 2); 945 mask |= 1 << ((mmTPC1_QM_PQ_ARUSER & 0x7F) >> 2); 946 947 WREG32(pb_addr + word_offset, ~mask); 948 949 pb_addr = (mmTPC1_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; 950 word_offset = ((mmTPC1_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; 951 mask = 1 << ((mmTPC1_QM_PQ_PUSH0 & 0x7F) >> 2); 952 mask |= 1 << ((mmTPC1_QM_PQ_PUSH1 & 0x7F) >> 2); 953 mask |= 1 << ((mmTPC1_QM_PQ_PUSH2 & 0x7F) >> 2); 954 mask |= 1 << ((mmTPC1_QM_PQ_PUSH3 & 0x7F) >> 2); 955 mask |= 1 << ((mmTPC1_QM_PQ_STS0 & 0x7F) >> 2); 956 mask |= 1 << ((mmTPC1_QM_PQ_STS1 & 0x7F) >> 2); 957 mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); 958 mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 959 mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 960 mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 961 mask |= 1 << ((mmTPC1_QM_CQ_CFG0 & 0x7F) >> 2); 962 mask |= 1 << ((mmTPC1_QM_CQ_CFG1 & 0x7F) >> 2); 963 mask |= 1 << ((mmTPC1_QM_CQ_ARUSER & 0x7F) >> 2); 964 mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO & 0x7F) >> 2); 965 mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI & 0x7F) >> 2); 966 mask |= 1 << ((mmTPC1_QM_CQ_TSIZE & 0x7F) >> 2); 967 mask |= 1 << ((mmTPC1_QM_CQ_CTL & 0x7F) >> 2); 968 mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS & 0x7F) >> 2); 969 mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS & 0x7F) >> 2); 970 mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS & 0x7F) >> 2); 971 mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS & 0x7F) >> 2); 972 mask |= 1 << ((mmTPC1_QM_CQ_STS0 & 0x7F) >> 2); 973 mask |= 1 << ((mmTPC1_QM_CQ_STS1 & 0x7F) >> 2); 974 mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 975 mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 976 mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 977 mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 978 979 WREG32(pb_addr + word_offset, ~mask); 980 981 pb_addr = (mmTPC1_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 982 word_offset = ((mmTPC1_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 983 mask = 1 << ((mmTPC1_QM_CQ_IFIFO_CNT & 0x7F) >> 2); 984 mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 985 mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 986 mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 987 mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 988 mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 989 mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 990 mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 991 mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 992 mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 993 mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 994 mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 995 mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 996 mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 997 mask |= 1 << ((mmTPC1_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 998 999 WREG32(pb_addr + word_offset, ~mask); 1000 1001 pb_addr = (mmTPC1_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1002 word_offset = ((mmTPC1_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1003 mask = 1 << ((mmTPC1_CMDQ_GLBL_CFG0 & 0x7F) >> 2); 1004 mask |= 1 << ((mmTPC1_CMDQ_GLBL_CFG1 & 0x7F) >> 2); 1005 mask |= 1 << ((mmTPC1_CMDQ_GLBL_PROT & 0x7F) >> 2); 1006 mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); 1007 mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 1008 mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 1009 mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); 1010 mask |= 1 << ((mmTPC1_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); 1011 mask |= 1 << ((mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 1012 mask |= 1 << ((mmTPC1_CMDQ_GLBL_STS0 & 0x7F) >> 2); 1013 mask |= 1 << ((mmTPC1_CMDQ_GLBL_STS1 & 0x7F) >> 2); 1014 1015 WREG32(pb_addr + word_offset, ~mask); 1016 1017 pb_addr = (mmTPC1_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1018 word_offset = ((mmTPC1_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1019 mask = 1 << ((mmTPC1_CMDQ_CQ_CFG0 & 0x7F) >> 2); 1020 mask |= 1 << ((mmTPC1_CMDQ_CQ_CFG1 & 0x7F) >> 2); 1021 mask |= 1 << ((mmTPC1_CMDQ_CQ_ARUSER & 0x7F) >> 2); 1022 mask |= 1 << ((mmTPC1_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); 1023 mask |= 1 << ((mmTPC1_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); 1024 mask |= 1 << ((mmTPC1_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); 1025 mask |= 1 << ((mmTPC1_CMDQ_CQ_CTL_STS & 0x7F) >> 2); 1026 mask |= 1 << ((mmTPC1_CMDQ_CQ_STS0 & 0x7F) >> 2); 1027 mask |= 1 << ((mmTPC1_CMDQ_CQ_STS1 & 0x7F) >> 2); 1028 mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 1029 mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 1030 mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 1031 mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 1032 1033 WREG32(pb_addr + word_offset, ~mask); 1034 1035 pb_addr = (mmTPC1_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 1036 word_offset = ((mmTPC1_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 1037 mask = 1 << ((mmTPC1_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); 1038 mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 1039 mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 1040 mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 1041 mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 1042 mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 1043 mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 1044 mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 1045 mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 1046 mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 1047 mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 1048 mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 1049 mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 1050 mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 1051 mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 1052 mask |= 1 << ((mmTPC1_CMDQ_CP_STS & 0x7F) >> 2); 1053 mask |= 1 << ((mmTPC1_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); 1054 1055 WREG32(pb_addr + word_offset, ~mask); 1056 1057 pb_addr = (mmTPC1_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; 1058 word_offset = ((mmTPC1_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) 1059 << 2; 1060 mask = 1 << ((mmTPC1_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); 1061 mask |= 1 << ((mmTPC1_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); 1062 mask |= 1 << ((mmTPC1_CMDQ_CP_DBG_0 & 0x7F) >> 2); 1063 mask |= 1 << ((mmTPC1_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); 1064 mask |= 1 << ((mmTPC1_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); 1065 1066 WREG32(pb_addr + word_offset, ~mask); 1067 1068 goya_pb_set_block(hdev, mmTPC2_RTR_BASE); 1069 goya_pb_set_block(hdev, mmTPC2_RD_REGULATOR_BASE); 1070 goya_pb_set_block(hdev, mmTPC2_WR_REGULATOR_BASE); 1071 1072 pb_addr = (mmTPC2_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; 1073 word_offset = ((mmTPC2_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; 1074 1075 mask = 1 << ((mmTPC2_CFG_SEMAPHORE & 0x7F) >> 2); 1076 mask |= 1 << ((mmTPC2_CFG_VFLAGS & 0x7F) >> 2); 1077 mask |= 1 << ((mmTPC2_CFG_SFLAGS & 0x7F) >> 2); 1078 mask |= 1 << ((mmTPC2_CFG_STATUS & 0x7F) >> 2); 1079 1080 WREG32(pb_addr + word_offset, ~mask); 1081 1082 pb_addr = (mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; 1083 word_offset = ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & 1084 PROT_BITS_OFFS) >> 7) << 2; 1085 mask = 1 << ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); 1086 mask |= 1 << ((mmTPC2_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); 1087 mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); 1088 mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); 1089 mask |= 1 << ((mmTPC2_CFG_TPC_STALL & 0x7F) >> 2); 1090 mask |= 1 << ((mmTPC2_CFG_MSS_CONFIG & 0x7F) >> 2); 1091 mask |= 1 << ((mmTPC2_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); 1092 mask |= 1 << ((mmTPC2_CFG_TPC_INTR_MASK & 0x7F) >> 2); 1093 1094 WREG32(pb_addr + word_offset, ~mask); 1095 1096 pb_addr = (mmTPC2_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS; 1097 word_offset = ((mmTPC2_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2; 1098 mask = 1 << ((mmTPC2_CFG_ARUSER & 0x7F) >> 2); 1099 mask |= 1 << ((mmTPC2_CFG_AWUSER & 0x7F) >> 2); 1100 1101 WREG32(pb_addr + word_offset, ~mask); 1102 1103 pb_addr = (mmTPC2_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS; 1104 word_offset = ((mmTPC2_CFG_FUNC_MBIST_CNTRL & PROT_BITS_OFFS) >> 7) 1105 << 2; 1106 mask = 1 << ((mmTPC2_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); 1107 mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); 1108 mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); 1109 mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); 1110 mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); 1111 mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); 1112 mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); 1113 mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); 1114 mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); 1115 mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); 1116 mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); 1117 mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); 1118 1119 WREG32(pb_addr + word_offset, ~mask); 1120 1121 pb_addr = (mmTPC2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1122 word_offset = ((mmTPC2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1123 mask = 1 << ((mmTPC2_QM_GLBL_CFG0 & 0x7F) >> 2); 1124 mask |= 1 << ((mmTPC2_QM_GLBL_CFG1 & 0x7F) >> 2); 1125 mask |= 1 << ((mmTPC2_QM_GLBL_PROT & 0x7F) >> 2); 1126 mask |= 1 << ((mmTPC2_QM_GLBL_ERR_CFG & 0x7F) >> 2); 1127 mask |= 1 << ((mmTPC2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 1128 mask |= 1 << ((mmTPC2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 1129 mask |= 1 << ((mmTPC2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 1130 mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); 1131 mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 1132 mask |= 1 << ((mmTPC2_QM_GLBL_STS0 & 0x7F) >> 2); 1133 mask |= 1 << ((mmTPC2_QM_GLBL_STS1 & 0x7F) >> 2); 1134 mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO & 0x7F) >> 2); 1135 mask |= 1 << ((mmTPC2_QM_PQ_BASE_HI & 0x7F) >> 2); 1136 mask |= 1 << ((mmTPC2_QM_PQ_SIZE & 0x7F) >> 2); 1137 mask |= 1 << ((mmTPC2_QM_PQ_PI & 0x7F) >> 2); 1138 mask |= 1 << ((mmTPC2_QM_PQ_CI & 0x7F) >> 2); 1139 mask |= 1 << ((mmTPC2_QM_PQ_CFG0 & 0x7F) >> 2); 1140 mask |= 1 << ((mmTPC2_QM_PQ_CFG1 & 0x7F) >> 2); 1141 mask |= 1 << ((mmTPC2_QM_PQ_ARUSER & 0x7F) >> 2); 1142 1143 WREG32(pb_addr + word_offset, ~mask); 1144 1145 pb_addr = (mmTPC2_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; 1146 word_offset = ((mmTPC2_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; 1147 mask = 1 << ((mmTPC2_QM_PQ_PUSH0 & 0x7F) >> 2); 1148 mask |= 1 << ((mmTPC2_QM_PQ_PUSH1 & 0x7F) >> 2); 1149 mask |= 1 << ((mmTPC2_QM_PQ_PUSH2 & 0x7F) >> 2); 1150 mask |= 1 << ((mmTPC2_QM_PQ_PUSH3 & 0x7F) >> 2); 1151 mask |= 1 << ((mmTPC2_QM_PQ_STS0 & 0x7F) >> 2); 1152 mask |= 1 << ((mmTPC2_QM_PQ_STS1 & 0x7F) >> 2); 1153 mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); 1154 mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 1155 mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 1156 mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 1157 mask |= 1 << ((mmTPC2_QM_CQ_CFG0 & 0x7F) >> 2); 1158 mask |= 1 << ((mmTPC2_QM_CQ_CFG1 & 0x7F) >> 2); 1159 mask |= 1 << ((mmTPC2_QM_CQ_ARUSER & 0x7F) >> 2); 1160 mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO & 0x7F) >> 2); 1161 mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI & 0x7F) >> 2); 1162 mask |= 1 << ((mmTPC2_QM_CQ_TSIZE & 0x7F) >> 2); 1163 mask |= 1 << ((mmTPC2_QM_CQ_CTL & 0x7F) >> 2); 1164 mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS & 0x7F) >> 2); 1165 mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS & 0x7F) >> 2); 1166 mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS & 0x7F) >> 2); 1167 mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS & 0x7F) >> 2); 1168 mask |= 1 << ((mmTPC2_QM_CQ_STS0 & 0x7F) >> 2); 1169 mask |= 1 << ((mmTPC2_QM_CQ_STS1 & 0x7F) >> 2); 1170 mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 1171 mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 1172 mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 1173 mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 1174 1175 WREG32(pb_addr + word_offset, ~mask); 1176 1177 pb_addr = (mmTPC2_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 1178 word_offset = ((mmTPC2_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 1179 mask = 1 << ((mmTPC2_QM_CQ_IFIFO_CNT & 0x7F) >> 2); 1180 mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 1181 mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 1182 mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 1183 mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 1184 mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 1185 mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 1186 mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 1187 mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 1188 mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 1189 mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 1190 mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 1191 mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 1192 mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 1193 mask |= 1 << ((mmTPC2_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 1194 1195 WREG32(pb_addr + word_offset, ~mask); 1196 1197 pb_addr = (mmTPC2_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1198 word_offset = ((mmTPC2_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1199 mask = 1 << ((mmTPC2_CMDQ_GLBL_CFG0 & 0x7F) >> 2); 1200 mask |= 1 << ((mmTPC2_CMDQ_GLBL_CFG1 & 0x7F) >> 2); 1201 mask |= 1 << ((mmTPC2_CMDQ_GLBL_PROT & 0x7F) >> 2); 1202 mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); 1203 mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 1204 mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 1205 mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); 1206 mask |= 1 << ((mmTPC2_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); 1207 mask |= 1 << ((mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 1208 mask |= 1 << ((mmTPC2_CMDQ_GLBL_STS0 & 0x7F) >> 2); 1209 mask |= 1 << ((mmTPC2_CMDQ_GLBL_STS1 & 0x7F) >> 2); 1210 1211 WREG32(pb_addr + word_offset, ~mask); 1212 1213 pb_addr = (mmTPC2_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1214 word_offset = ((mmTPC2_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1215 mask = 1 << ((mmTPC2_CMDQ_CQ_CFG0 & 0x7F) >> 2); 1216 mask |= 1 << ((mmTPC2_CMDQ_CQ_CFG1 & 0x7F) >> 2); 1217 mask |= 1 << ((mmTPC2_CMDQ_CQ_ARUSER & 0x7F) >> 2); 1218 mask |= 1 << ((mmTPC2_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); 1219 mask |= 1 << ((mmTPC2_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); 1220 mask |= 1 << ((mmTPC2_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); 1221 mask |= 1 << ((mmTPC2_CMDQ_CQ_CTL_STS & 0x7F) >> 2); 1222 mask |= 1 << ((mmTPC2_CMDQ_CQ_STS0 & 0x7F) >> 2); 1223 mask |= 1 << ((mmTPC2_CMDQ_CQ_STS1 & 0x7F) >> 2); 1224 mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 1225 mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 1226 mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 1227 mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 1228 1229 WREG32(pb_addr + word_offset, ~mask); 1230 1231 pb_addr = (mmTPC2_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 1232 word_offset = ((mmTPC2_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 1233 mask = 1 << ((mmTPC2_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); 1234 mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 1235 mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 1236 mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 1237 mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 1238 mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 1239 mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 1240 mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 1241 mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 1242 mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 1243 mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 1244 mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 1245 mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 1246 mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 1247 mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 1248 mask |= 1 << ((mmTPC2_CMDQ_CP_STS & 0x7F) >> 2); 1249 mask |= 1 << ((mmTPC2_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); 1250 1251 WREG32(pb_addr + word_offset, ~mask); 1252 1253 pb_addr = (mmTPC2_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; 1254 word_offset = ((mmTPC2_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) 1255 << 2; 1256 mask = 1 << ((mmTPC2_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); 1257 mask |= 1 << ((mmTPC2_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); 1258 mask |= 1 << ((mmTPC2_CMDQ_CP_DBG_0 & 0x7F) >> 2); 1259 mask |= 1 << ((mmTPC2_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); 1260 mask |= 1 << ((mmTPC2_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); 1261 1262 WREG32(pb_addr + word_offset, ~mask); 1263 1264 goya_pb_set_block(hdev, mmTPC3_RTR_BASE); 1265 goya_pb_set_block(hdev, mmTPC3_RD_REGULATOR_BASE); 1266 goya_pb_set_block(hdev, mmTPC3_WR_REGULATOR_BASE); 1267 1268 pb_addr = (mmTPC3_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; 1269 word_offset = ((mmTPC3_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; 1270 1271 mask = 1 << ((mmTPC3_CFG_SEMAPHORE & 0x7F) >> 2); 1272 mask |= 1 << ((mmTPC3_CFG_VFLAGS & 0x7F) >> 2); 1273 mask |= 1 << ((mmTPC3_CFG_SFLAGS & 0x7F) >> 2); 1274 mask |= 1 << ((mmTPC3_CFG_STATUS & 0x7F) >> 2); 1275 1276 WREG32(pb_addr + word_offset, ~mask); 1277 1278 pb_addr = (mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; 1279 word_offset = ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH 1280 & PROT_BITS_OFFS) >> 7) << 2; 1281 mask = 1 << ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); 1282 mask |= 1 << ((mmTPC3_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); 1283 mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); 1284 mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); 1285 mask |= 1 << ((mmTPC3_CFG_TPC_STALL & 0x7F) >> 2); 1286 mask |= 1 << ((mmTPC3_CFG_MSS_CONFIG & 0x7F) >> 2); 1287 mask |= 1 << ((mmTPC3_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); 1288 mask |= 1 << ((mmTPC3_CFG_TPC_INTR_MASK & 0x7F) >> 2); 1289 1290 WREG32(pb_addr + word_offset, ~mask); 1291 1292 pb_addr = (mmTPC3_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS; 1293 word_offset = ((mmTPC3_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2; 1294 mask = 1 << ((mmTPC3_CFG_ARUSER & 0x7F) >> 2); 1295 mask |= 1 << ((mmTPC3_CFG_AWUSER & 0x7F) >> 2); 1296 1297 WREG32(pb_addr + word_offset, ~mask); 1298 1299 pb_addr = (mmTPC3_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS; 1300 word_offset = ((mmTPC3_CFG_FUNC_MBIST_CNTRL 1301 & PROT_BITS_OFFS) >> 7) << 2; 1302 mask = 1 << ((mmTPC3_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); 1303 mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); 1304 mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); 1305 mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); 1306 mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); 1307 mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); 1308 mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); 1309 mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); 1310 mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); 1311 mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); 1312 mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); 1313 mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); 1314 1315 WREG32(pb_addr + word_offset, ~mask); 1316 1317 pb_addr = (mmTPC3_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1318 word_offset = ((mmTPC3_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1319 mask = 1 << ((mmTPC3_QM_GLBL_CFG0 & 0x7F) >> 2); 1320 mask |= 1 << ((mmTPC3_QM_GLBL_CFG1 & 0x7F) >> 2); 1321 mask |= 1 << ((mmTPC3_QM_GLBL_PROT & 0x7F) >> 2); 1322 mask |= 1 << ((mmTPC3_QM_GLBL_ERR_CFG & 0x7F) >> 2); 1323 mask |= 1 << ((mmTPC3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 1324 mask |= 1 << ((mmTPC3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 1325 mask |= 1 << ((mmTPC3_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 1326 mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); 1327 mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 1328 mask |= 1 << ((mmTPC3_QM_GLBL_STS0 & 0x7F) >> 2); 1329 mask |= 1 << ((mmTPC3_QM_GLBL_STS1 & 0x7F) >> 2); 1330 mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO & 0x7F) >> 2); 1331 mask |= 1 << ((mmTPC3_QM_PQ_BASE_HI & 0x7F) >> 2); 1332 mask |= 1 << ((mmTPC3_QM_PQ_SIZE & 0x7F) >> 2); 1333 mask |= 1 << ((mmTPC3_QM_PQ_PI & 0x7F) >> 2); 1334 mask |= 1 << ((mmTPC3_QM_PQ_CI & 0x7F) >> 2); 1335 mask |= 1 << ((mmTPC3_QM_PQ_CFG0 & 0x7F) >> 2); 1336 mask |= 1 << ((mmTPC3_QM_PQ_CFG1 & 0x7F) >> 2); 1337 mask |= 1 << ((mmTPC3_QM_PQ_ARUSER & 0x7F) >> 2); 1338 1339 WREG32(pb_addr + word_offset, ~mask); 1340 1341 pb_addr = (mmTPC3_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; 1342 word_offset = ((mmTPC3_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; 1343 mask = 1 << ((mmTPC3_QM_PQ_PUSH0 & 0x7F) >> 2); 1344 mask |= 1 << ((mmTPC3_QM_PQ_PUSH1 & 0x7F) >> 2); 1345 mask |= 1 << ((mmTPC3_QM_PQ_PUSH2 & 0x7F) >> 2); 1346 mask |= 1 << ((mmTPC3_QM_PQ_PUSH3 & 0x7F) >> 2); 1347 mask |= 1 << ((mmTPC3_QM_PQ_STS0 & 0x7F) >> 2); 1348 mask |= 1 << ((mmTPC3_QM_PQ_STS1 & 0x7F) >> 2); 1349 mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); 1350 mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 1351 mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 1352 mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 1353 mask |= 1 << ((mmTPC3_QM_CQ_CFG0 & 0x7F) >> 2); 1354 mask |= 1 << ((mmTPC3_QM_CQ_CFG1 & 0x7F) >> 2); 1355 mask |= 1 << ((mmTPC3_QM_CQ_ARUSER & 0x7F) >> 2); 1356 mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO & 0x7F) >> 2); 1357 mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI & 0x7F) >> 2); 1358 mask |= 1 << ((mmTPC3_QM_CQ_TSIZE & 0x7F) >> 2); 1359 mask |= 1 << ((mmTPC3_QM_CQ_CTL & 0x7F) >> 2); 1360 mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS & 0x7F) >> 2); 1361 mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS & 0x7F) >> 2); 1362 mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS & 0x7F) >> 2); 1363 mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS & 0x7F) >> 2); 1364 mask |= 1 << ((mmTPC3_QM_CQ_STS0 & 0x7F) >> 2); 1365 mask |= 1 << ((mmTPC3_QM_CQ_STS1 & 0x7F) >> 2); 1366 mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 1367 mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 1368 mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 1369 mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 1370 1371 WREG32(pb_addr + word_offset, ~mask); 1372 1373 pb_addr = (mmTPC3_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 1374 word_offset = ((mmTPC3_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 1375 mask = 1 << ((mmTPC3_QM_CQ_IFIFO_CNT & 0x7F) >> 2); 1376 mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 1377 mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 1378 mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 1379 mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 1380 mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 1381 mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 1382 mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 1383 mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 1384 mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 1385 mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 1386 mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 1387 mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 1388 mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 1389 mask |= 1 << ((mmTPC3_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 1390 1391 WREG32(pb_addr + word_offset, ~mask); 1392 1393 pb_addr = (mmTPC3_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1394 word_offset = ((mmTPC3_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1395 mask = 1 << ((mmTPC3_CMDQ_GLBL_CFG0 & 0x7F) >> 2); 1396 mask |= 1 << ((mmTPC3_CMDQ_GLBL_CFG1 & 0x7F) >> 2); 1397 mask |= 1 << ((mmTPC3_CMDQ_GLBL_PROT & 0x7F) >> 2); 1398 mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); 1399 mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 1400 mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 1401 mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); 1402 mask |= 1 << ((mmTPC3_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); 1403 mask |= 1 << ((mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 1404 mask |= 1 << ((mmTPC3_CMDQ_GLBL_STS0 & 0x7F) >> 2); 1405 mask |= 1 << ((mmTPC3_CMDQ_GLBL_STS1 & 0x7F) >> 2); 1406 1407 WREG32(pb_addr + word_offset, ~mask); 1408 1409 pb_addr = (mmTPC3_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1410 word_offset = ((mmTPC3_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1411 mask = 1 << ((mmTPC3_CMDQ_CQ_CFG0 & 0x7F) >> 2); 1412 mask |= 1 << ((mmTPC3_CMDQ_CQ_CFG1 & 0x7F) >> 2); 1413 mask |= 1 << ((mmTPC3_CMDQ_CQ_ARUSER & 0x7F) >> 2); 1414 mask |= 1 << ((mmTPC3_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); 1415 mask |= 1 << ((mmTPC3_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); 1416 mask |= 1 << ((mmTPC3_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); 1417 mask |= 1 << ((mmTPC3_CMDQ_CQ_CTL_STS & 0x7F) >> 2); 1418 mask |= 1 << ((mmTPC3_CMDQ_CQ_STS0 & 0x7F) >> 2); 1419 mask |= 1 << ((mmTPC3_CMDQ_CQ_STS1 & 0x7F) >> 2); 1420 mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 1421 mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 1422 mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 1423 mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 1424 1425 WREG32(pb_addr + word_offset, ~mask); 1426 1427 pb_addr = (mmTPC3_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 1428 word_offset = ((mmTPC3_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 1429 mask = 1 << ((mmTPC3_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); 1430 mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 1431 mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 1432 mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 1433 mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 1434 mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 1435 mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 1436 mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 1437 mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 1438 mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 1439 mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 1440 mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 1441 mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 1442 mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 1443 mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 1444 mask |= 1 << ((mmTPC3_CMDQ_CP_STS & 0x7F) >> 2); 1445 mask |= 1 << ((mmTPC3_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); 1446 1447 WREG32(pb_addr + word_offset, ~mask); 1448 1449 pb_addr = (mmTPC3_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; 1450 word_offset = ((mmTPC3_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) 1451 << 2; 1452 mask = 1 << ((mmTPC3_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); 1453 mask |= 1 << ((mmTPC3_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); 1454 mask |= 1 << ((mmTPC3_CMDQ_CP_DBG_0 & 0x7F) >> 2); 1455 mask |= 1 << ((mmTPC3_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); 1456 mask |= 1 << ((mmTPC3_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); 1457 1458 WREG32(pb_addr + word_offset, ~mask); 1459 1460 goya_pb_set_block(hdev, mmTPC4_RTR_BASE); 1461 goya_pb_set_block(hdev, mmTPC4_RD_REGULATOR_BASE); 1462 goya_pb_set_block(hdev, mmTPC4_WR_REGULATOR_BASE); 1463 1464 pb_addr = (mmTPC4_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; 1465 word_offset = ((mmTPC4_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; 1466 1467 mask = 1 << ((mmTPC4_CFG_SEMAPHORE & 0x7F) >> 2); 1468 mask |= 1 << ((mmTPC4_CFG_VFLAGS & 0x7F) >> 2); 1469 mask |= 1 << ((mmTPC4_CFG_SFLAGS & 0x7F) >> 2); 1470 mask |= 1 << ((mmTPC4_CFG_STATUS & 0x7F) >> 2); 1471 1472 WREG32(pb_addr + word_offset, ~mask); 1473 1474 pb_addr = (mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; 1475 word_offset = ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & 1476 PROT_BITS_OFFS) >> 7) << 2; 1477 mask = 1 << ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); 1478 mask |= 1 << ((mmTPC4_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); 1479 mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); 1480 mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); 1481 mask |= 1 << ((mmTPC4_CFG_TPC_STALL & 0x7F) >> 2); 1482 mask |= 1 << ((mmTPC4_CFG_MSS_CONFIG & 0x7F) >> 2); 1483 mask |= 1 << ((mmTPC4_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); 1484 mask |= 1 << ((mmTPC4_CFG_TPC_INTR_MASK & 0x7F) >> 2); 1485 1486 WREG32(pb_addr + word_offset, ~mask); 1487 1488 pb_addr = (mmTPC4_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS; 1489 word_offset = ((mmTPC4_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2; 1490 mask = 1 << ((mmTPC4_CFG_ARUSER & 0x7F) >> 2); 1491 mask |= 1 << ((mmTPC4_CFG_AWUSER & 0x7F) >> 2); 1492 1493 WREG32(pb_addr + word_offset, ~mask); 1494 1495 pb_addr = (mmTPC4_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS; 1496 word_offset = ((mmTPC4_CFG_FUNC_MBIST_CNTRL & 1497 PROT_BITS_OFFS) >> 7) << 2; 1498 mask = 1 << ((mmTPC4_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); 1499 mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); 1500 mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); 1501 mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); 1502 mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); 1503 mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); 1504 mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); 1505 mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); 1506 mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); 1507 mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); 1508 mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); 1509 mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); 1510 1511 WREG32(pb_addr + word_offset, ~mask); 1512 1513 pb_addr = (mmTPC4_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1514 word_offset = ((mmTPC4_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1515 mask = 1 << ((mmTPC4_QM_GLBL_CFG0 & 0x7F) >> 2); 1516 mask |= 1 << ((mmTPC4_QM_GLBL_CFG1 & 0x7F) >> 2); 1517 mask |= 1 << ((mmTPC4_QM_GLBL_PROT & 0x7F) >> 2); 1518 mask |= 1 << ((mmTPC4_QM_GLBL_ERR_CFG & 0x7F) >> 2); 1519 mask |= 1 << ((mmTPC4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 1520 mask |= 1 << ((mmTPC4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 1521 mask |= 1 << ((mmTPC4_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 1522 mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); 1523 mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 1524 mask |= 1 << ((mmTPC4_QM_GLBL_STS0 & 0x7F) >> 2); 1525 mask |= 1 << ((mmTPC4_QM_GLBL_STS1 & 0x7F) >> 2); 1526 mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO & 0x7F) >> 2); 1527 mask |= 1 << ((mmTPC4_QM_PQ_BASE_HI & 0x7F) >> 2); 1528 mask |= 1 << ((mmTPC4_QM_PQ_SIZE & 0x7F) >> 2); 1529 mask |= 1 << ((mmTPC4_QM_PQ_PI & 0x7F) >> 2); 1530 mask |= 1 << ((mmTPC4_QM_PQ_CI & 0x7F) >> 2); 1531 mask |= 1 << ((mmTPC4_QM_PQ_CFG0 & 0x7F) >> 2); 1532 mask |= 1 << ((mmTPC4_QM_PQ_CFG1 & 0x7F) >> 2); 1533 mask |= 1 << ((mmTPC4_QM_PQ_ARUSER & 0x7F) >> 2); 1534 1535 WREG32(pb_addr + word_offset, ~mask); 1536 1537 pb_addr = (mmTPC4_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; 1538 word_offset = ((mmTPC4_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; 1539 mask = 1 << ((mmTPC4_QM_PQ_PUSH0 & 0x7F) >> 2); 1540 mask |= 1 << ((mmTPC4_QM_PQ_PUSH1 & 0x7F) >> 2); 1541 mask |= 1 << ((mmTPC4_QM_PQ_PUSH2 & 0x7F) >> 2); 1542 mask |= 1 << ((mmTPC4_QM_PQ_PUSH3 & 0x7F) >> 2); 1543 mask |= 1 << ((mmTPC4_QM_PQ_STS0 & 0x7F) >> 2); 1544 mask |= 1 << ((mmTPC4_QM_PQ_STS1 & 0x7F) >> 2); 1545 mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); 1546 mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 1547 mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 1548 mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 1549 mask |= 1 << ((mmTPC4_QM_CQ_CFG0 & 0x7F) >> 2); 1550 mask |= 1 << ((mmTPC4_QM_CQ_CFG1 & 0x7F) >> 2); 1551 mask |= 1 << ((mmTPC4_QM_CQ_ARUSER & 0x7F) >> 2); 1552 mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO & 0x7F) >> 2); 1553 mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI & 0x7F) >> 2); 1554 mask |= 1 << ((mmTPC4_QM_CQ_TSIZE & 0x7F) >> 2); 1555 mask |= 1 << ((mmTPC4_QM_CQ_CTL & 0x7F) >> 2); 1556 mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS & 0x7F) >> 2); 1557 mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS & 0x7F) >> 2); 1558 mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS & 0x7F) >> 2); 1559 mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS & 0x7F) >> 2); 1560 mask |= 1 << ((mmTPC4_QM_CQ_STS0 & 0x7F) >> 2); 1561 mask |= 1 << ((mmTPC4_QM_CQ_STS1 & 0x7F) >> 2); 1562 mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 1563 mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 1564 mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 1565 mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 1566 1567 WREG32(pb_addr + word_offset, ~mask); 1568 1569 pb_addr = (mmTPC4_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 1570 word_offset = ((mmTPC4_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 1571 mask = 1 << ((mmTPC4_QM_CQ_IFIFO_CNT & 0x7F) >> 2); 1572 mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 1573 mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 1574 mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 1575 mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 1576 mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 1577 mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 1578 mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 1579 mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 1580 mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 1581 mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 1582 mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 1583 mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 1584 mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 1585 mask |= 1 << ((mmTPC4_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 1586 1587 WREG32(pb_addr + word_offset, ~mask); 1588 1589 pb_addr = (mmTPC4_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1590 word_offset = ((mmTPC4_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1591 mask = 1 << ((mmTPC4_CMDQ_GLBL_CFG0 & 0x7F) >> 2); 1592 mask |= 1 << ((mmTPC4_CMDQ_GLBL_CFG1 & 0x7F) >> 2); 1593 mask |= 1 << ((mmTPC4_CMDQ_GLBL_PROT & 0x7F) >> 2); 1594 mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); 1595 mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 1596 mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 1597 mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); 1598 mask |= 1 << ((mmTPC4_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); 1599 mask |= 1 << ((mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 1600 mask |= 1 << ((mmTPC4_CMDQ_GLBL_STS0 & 0x7F) >> 2); 1601 mask |= 1 << ((mmTPC4_CMDQ_GLBL_STS1 & 0x7F) >> 2); 1602 1603 WREG32(pb_addr + word_offset, ~mask); 1604 1605 pb_addr = (mmTPC4_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1606 word_offset = ((mmTPC4_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1607 mask = 1 << ((mmTPC4_CMDQ_CQ_CFG0 & 0x7F) >> 2); 1608 mask |= 1 << ((mmTPC4_CMDQ_CQ_CFG1 & 0x7F) >> 2); 1609 mask |= 1 << ((mmTPC4_CMDQ_CQ_ARUSER & 0x7F) >> 2); 1610 mask |= 1 << ((mmTPC4_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); 1611 mask |= 1 << ((mmTPC4_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); 1612 mask |= 1 << ((mmTPC4_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); 1613 mask |= 1 << ((mmTPC4_CMDQ_CQ_CTL_STS & 0x7F) >> 2); 1614 mask |= 1 << ((mmTPC4_CMDQ_CQ_STS0 & 0x7F) >> 2); 1615 mask |= 1 << ((mmTPC4_CMDQ_CQ_STS1 & 0x7F) >> 2); 1616 mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 1617 mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 1618 mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 1619 mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 1620 1621 WREG32(pb_addr + word_offset, ~mask); 1622 1623 pb_addr = (mmTPC4_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 1624 word_offset = ((mmTPC4_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 1625 mask = 1 << ((mmTPC4_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); 1626 mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 1627 mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 1628 mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 1629 mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 1630 mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 1631 mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 1632 mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 1633 mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 1634 mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 1635 mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 1636 mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 1637 mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 1638 mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 1639 mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 1640 mask |= 1 << ((mmTPC4_CMDQ_CP_STS & 0x7F) >> 2); 1641 mask |= 1 << ((mmTPC4_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); 1642 1643 WREG32(pb_addr + word_offset, ~mask); 1644 1645 pb_addr = (mmTPC4_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; 1646 word_offset = ((mmTPC4_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) 1647 << 2; 1648 mask = 1 << ((mmTPC4_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); 1649 mask |= 1 << ((mmTPC4_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); 1650 mask |= 1 << ((mmTPC4_CMDQ_CP_DBG_0 & 0x7F) >> 2); 1651 mask |= 1 << ((mmTPC4_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); 1652 mask |= 1 << ((mmTPC4_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); 1653 1654 WREG32(pb_addr + word_offset, ~mask); 1655 1656 goya_pb_set_block(hdev, mmTPC5_RTR_BASE); 1657 goya_pb_set_block(hdev, mmTPC5_RD_REGULATOR_BASE); 1658 goya_pb_set_block(hdev, mmTPC5_WR_REGULATOR_BASE); 1659 1660 pb_addr = (mmTPC5_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; 1661 word_offset = ((mmTPC5_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; 1662 1663 mask = 1 << ((mmTPC5_CFG_SEMAPHORE & 0x7F) >> 2); 1664 mask |= 1 << ((mmTPC5_CFG_VFLAGS & 0x7F) >> 2); 1665 mask |= 1 << ((mmTPC5_CFG_SFLAGS & 0x7F) >> 2); 1666 mask |= 1 << ((mmTPC5_CFG_STATUS & 0x7F) >> 2); 1667 1668 WREG32(pb_addr + word_offset, ~mask); 1669 1670 pb_addr = (mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; 1671 word_offset = ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & 1672 PROT_BITS_OFFS) >> 7) << 2; 1673 mask = 1 << ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); 1674 mask |= 1 << ((mmTPC5_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); 1675 mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); 1676 mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); 1677 mask |= 1 << ((mmTPC5_CFG_TPC_STALL & 0x7F) >> 2); 1678 mask |= 1 << ((mmTPC5_CFG_MSS_CONFIG & 0x7F) >> 2); 1679 mask |= 1 << ((mmTPC5_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); 1680 mask |= 1 << ((mmTPC5_CFG_TPC_INTR_MASK & 0x7F) >> 2); 1681 1682 WREG32(pb_addr + word_offset, ~mask); 1683 1684 pb_addr = (mmTPC5_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS; 1685 word_offset = ((mmTPC5_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2; 1686 mask = 1 << ((mmTPC5_CFG_ARUSER & 0x7F) >> 2); 1687 mask |= 1 << ((mmTPC5_CFG_AWUSER & 0x7F) >> 2); 1688 1689 WREG32(pb_addr + word_offset, ~mask); 1690 1691 pb_addr = (mmTPC5_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS; 1692 word_offset = ((mmTPC5_CFG_FUNC_MBIST_CNTRL & 1693 PROT_BITS_OFFS) >> 7) << 2; 1694 mask = 1 << ((mmTPC5_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); 1695 mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); 1696 mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); 1697 mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); 1698 mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); 1699 mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); 1700 mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); 1701 mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); 1702 mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); 1703 mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); 1704 mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); 1705 mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); 1706 1707 WREG32(pb_addr + word_offset, ~mask); 1708 1709 pb_addr = (mmTPC5_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1710 word_offset = ((mmTPC5_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1711 mask = 1 << ((mmTPC5_QM_GLBL_CFG0 & 0x7F) >> 2); 1712 mask |= 1 << ((mmTPC5_QM_GLBL_CFG1 & 0x7F) >> 2); 1713 mask |= 1 << ((mmTPC5_QM_GLBL_PROT & 0x7F) >> 2); 1714 mask |= 1 << ((mmTPC5_QM_GLBL_ERR_CFG & 0x7F) >> 2); 1715 mask |= 1 << ((mmTPC5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 1716 mask |= 1 << ((mmTPC5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 1717 mask |= 1 << ((mmTPC5_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 1718 mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); 1719 mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 1720 mask |= 1 << ((mmTPC5_QM_GLBL_STS0 & 0x7F) >> 2); 1721 mask |= 1 << ((mmTPC5_QM_GLBL_STS1 & 0x7F) >> 2); 1722 mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO & 0x7F) >> 2); 1723 mask |= 1 << ((mmTPC5_QM_PQ_BASE_HI & 0x7F) >> 2); 1724 mask |= 1 << ((mmTPC5_QM_PQ_SIZE & 0x7F) >> 2); 1725 mask |= 1 << ((mmTPC5_QM_PQ_PI & 0x7F) >> 2); 1726 mask |= 1 << ((mmTPC5_QM_PQ_CI & 0x7F) >> 2); 1727 mask |= 1 << ((mmTPC5_QM_PQ_CFG0 & 0x7F) >> 2); 1728 mask |= 1 << ((mmTPC5_QM_PQ_CFG1 & 0x7F) >> 2); 1729 mask |= 1 << ((mmTPC5_QM_PQ_ARUSER & 0x7F) >> 2); 1730 1731 WREG32(pb_addr + word_offset, ~mask); 1732 1733 pb_addr = (mmTPC5_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; 1734 word_offset = ((mmTPC5_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; 1735 mask = 1 << ((mmTPC5_QM_PQ_PUSH0 & 0x7F) >> 2); 1736 mask |= 1 << ((mmTPC5_QM_PQ_PUSH1 & 0x7F) >> 2); 1737 mask |= 1 << ((mmTPC5_QM_PQ_PUSH2 & 0x7F) >> 2); 1738 mask |= 1 << ((mmTPC5_QM_PQ_PUSH3 & 0x7F) >> 2); 1739 mask |= 1 << ((mmTPC5_QM_PQ_STS0 & 0x7F) >> 2); 1740 mask |= 1 << ((mmTPC5_QM_PQ_STS1 & 0x7F) >> 2); 1741 mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); 1742 mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 1743 mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 1744 mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 1745 mask |= 1 << ((mmTPC5_QM_CQ_CFG0 & 0x7F) >> 2); 1746 mask |= 1 << ((mmTPC5_QM_CQ_CFG1 & 0x7F) >> 2); 1747 mask |= 1 << ((mmTPC5_QM_CQ_ARUSER & 0x7F) >> 2); 1748 mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO & 0x7F) >> 2); 1749 mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI & 0x7F) >> 2); 1750 mask |= 1 << ((mmTPC5_QM_CQ_TSIZE & 0x7F) >> 2); 1751 mask |= 1 << ((mmTPC5_QM_CQ_CTL & 0x7F) >> 2); 1752 mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS & 0x7F) >> 2); 1753 mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS & 0x7F) >> 2); 1754 mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS & 0x7F) >> 2); 1755 mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS & 0x7F) >> 2); 1756 mask |= 1 << ((mmTPC5_QM_CQ_STS0 & 0x7F) >> 2); 1757 mask |= 1 << ((mmTPC5_QM_CQ_STS1 & 0x7F) >> 2); 1758 mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 1759 mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 1760 mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 1761 mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 1762 1763 WREG32(pb_addr + word_offset, ~mask); 1764 1765 pb_addr = (mmTPC5_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 1766 word_offset = ((mmTPC5_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 1767 mask = 1 << ((mmTPC5_QM_CQ_IFIFO_CNT & 0x7F) >> 2); 1768 mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 1769 mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 1770 mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 1771 mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 1772 mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 1773 mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 1774 mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 1775 mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 1776 mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 1777 mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 1778 mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 1779 mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 1780 mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 1781 mask |= 1 << ((mmTPC5_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 1782 1783 WREG32(pb_addr + word_offset, ~mask); 1784 1785 pb_addr = (mmTPC5_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1786 word_offset = ((mmTPC5_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1787 mask = 1 << ((mmTPC5_CMDQ_GLBL_CFG0 & 0x7F) >> 2); 1788 mask |= 1 << ((mmTPC5_CMDQ_GLBL_CFG1 & 0x7F) >> 2); 1789 mask |= 1 << ((mmTPC5_CMDQ_GLBL_PROT & 0x7F) >> 2); 1790 mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); 1791 mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 1792 mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 1793 mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); 1794 mask |= 1 << ((mmTPC5_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); 1795 mask |= 1 << ((mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 1796 mask |= 1 << ((mmTPC5_CMDQ_GLBL_STS0 & 0x7F) >> 2); 1797 mask |= 1 << ((mmTPC5_CMDQ_GLBL_STS1 & 0x7F) >> 2); 1798 1799 WREG32(pb_addr + word_offset, ~mask); 1800 1801 pb_addr = (mmTPC5_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1802 word_offset = ((mmTPC5_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1803 mask = 1 << ((mmTPC5_CMDQ_CQ_CFG0 & 0x7F) >> 2); 1804 mask |= 1 << ((mmTPC5_CMDQ_CQ_CFG1 & 0x7F) >> 2); 1805 mask |= 1 << ((mmTPC5_CMDQ_CQ_ARUSER & 0x7F) >> 2); 1806 mask |= 1 << ((mmTPC5_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); 1807 mask |= 1 << ((mmTPC5_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); 1808 mask |= 1 << ((mmTPC5_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); 1809 mask |= 1 << ((mmTPC5_CMDQ_CQ_CTL_STS & 0x7F) >> 2); 1810 mask |= 1 << ((mmTPC5_CMDQ_CQ_STS0 & 0x7F) >> 2); 1811 mask |= 1 << ((mmTPC5_CMDQ_CQ_STS1 & 0x7F) >> 2); 1812 mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 1813 mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 1814 mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 1815 mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 1816 1817 WREG32(pb_addr + word_offset, ~mask); 1818 1819 pb_addr = (mmTPC5_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 1820 word_offset = ((mmTPC5_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 1821 mask = 1 << ((mmTPC5_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); 1822 mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 1823 mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 1824 mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 1825 mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 1826 mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 1827 mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 1828 mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 1829 mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 1830 mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 1831 mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 1832 mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 1833 mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 1834 mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 1835 mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 1836 mask |= 1 << ((mmTPC5_CMDQ_CP_STS & 0x7F) >> 2); 1837 mask |= 1 << ((mmTPC5_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); 1838 1839 WREG32(pb_addr + word_offset, ~mask); 1840 1841 pb_addr = (mmTPC5_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; 1842 word_offset = ((mmTPC5_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) 1843 << 2; 1844 mask = 1 << ((mmTPC5_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); 1845 mask |= 1 << ((mmTPC5_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); 1846 mask |= 1 << ((mmTPC5_CMDQ_CP_DBG_0 & 0x7F) >> 2); 1847 mask |= 1 << ((mmTPC5_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); 1848 mask |= 1 << ((mmTPC5_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); 1849 1850 WREG32(pb_addr + word_offset, ~mask); 1851 1852 goya_pb_set_block(hdev, mmTPC6_RTR_BASE); 1853 goya_pb_set_block(hdev, mmTPC6_RD_REGULATOR_BASE); 1854 goya_pb_set_block(hdev, mmTPC6_WR_REGULATOR_BASE); 1855 1856 pb_addr = (mmTPC6_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; 1857 word_offset = ((mmTPC6_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; 1858 1859 mask = 1 << ((mmTPC6_CFG_SEMAPHORE & 0x7F) >> 2); 1860 mask |= 1 << ((mmTPC6_CFG_VFLAGS & 0x7F) >> 2); 1861 mask |= 1 << ((mmTPC6_CFG_SFLAGS & 0x7F) >> 2); 1862 mask |= 1 << ((mmTPC6_CFG_STATUS & 0x7F) >> 2); 1863 1864 WREG32(pb_addr + word_offset, ~mask); 1865 1866 pb_addr = (mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; 1867 word_offset = ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & 1868 PROT_BITS_OFFS) >> 7) << 2; 1869 mask = 1 << ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); 1870 mask |= 1 << ((mmTPC6_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); 1871 mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); 1872 mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); 1873 mask |= 1 << ((mmTPC6_CFG_TPC_STALL & 0x7F) >> 2); 1874 mask |= 1 << ((mmTPC6_CFG_MSS_CONFIG & 0x7F) >> 2); 1875 mask |= 1 << ((mmTPC6_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); 1876 mask |= 1 << ((mmTPC6_CFG_TPC_INTR_MASK & 0x7F) >> 2); 1877 1878 WREG32(pb_addr + word_offset, ~mask); 1879 1880 pb_addr = (mmTPC6_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS; 1881 word_offset = ((mmTPC6_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2; 1882 mask = 1 << ((mmTPC6_CFG_ARUSER & 0x7F) >> 2); 1883 mask |= 1 << ((mmTPC6_CFG_AWUSER & 0x7F) >> 2); 1884 1885 WREG32(pb_addr + word_offset, ~mask); 1886 1887 pb_addr = (mmTPC6_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS; 1888 word_offset = ((mmTPC6_CFG_FUNC_MBIST_CNTRL & 1889 PROT_BITS_OFFS) >> 7) << 2; 1890 mask = 1 << ((mmTPC6_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); 1891 mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); 1892 mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); 1893 mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); 1894 mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); 1895 mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); 1896 mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); 1897 mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); 1898 mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); 1899 mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); 1900 mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); 1901 mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); 1902 1903 WREG32(pb_addr + word_offset, ~mask); 1904 1905 pb_addr = (mmTPC6_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1906 word_offset = ((mmTPC6_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1907 mask = 1 << ((mmTPC6_QM_GLBL_CFG0 & 0x7F) >> 2); 1908 mask |= 1 << ((mmTPC6_QM_GLBL_CFG1 & 0x7F) >> 2); 1909 mask |= 1 << ((mmTPC6_QM_GLBL_PROT & 0x7F) >> 2); 1910 mask |= 1 << ((mmTPC6_QM_GLBL_ERR_CFG & 0x7F) >> 2); 1911 mask |= 1 << ((mmTPC6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 1912 mask |= 1 << ((mmTPC6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 1913 mask |= 1 << ((mmTPC6_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 1914 mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); 1915 mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 1916 mask |= 1 << ((mmTPC6_QM_GLBL_STS0 & 0x7F) >> 2); 1917 mask |= 1 << ((mmTPC6_QM_GLBL_STS1 & 0x7F) >> 2); 1918 mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO & 0x7F) >> 2); 1919 mask |= 1 << ((mmTPC6_QM_PQ_BASE_HI & 0x7F) >> 2); 1920 mask |= 1 << ((mmTPC6_QM_PQ_SIZE & 0x7F) >> 2); 1921 mask |= 1 << ((mmTPC6_QM_PQ_PI & 0x7F) >> 2); 1922 mask |= 1 << ((mmTPC6_QM_PQ_CI & 0x7F) >> 2); 1923 mask |= 1 << ((mmTPC6_QM_PQ_CFG0 & 0x7F) >> 2); 1924 mask |= 1 << ((mmTPC6_QM_PQ_CFG1 & 0x7F) >> 2); 1925 mask |= 1 << ((mmTPC6_QM_PQ_ARUSER & 0x7F) >> 2); 1926 1927 WREG32(pb_addr + word_offset, ~mask); 1928 1929 pb_addr = (mmTPC6_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; 1930 word_offset = ((mmTPC6_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; 1931 mask = 1 << ((mmTPC6_QM_PQ_PUSH0 & 0x7F) >> 2); 1932 mask |= 1 << ((mmTPC6_QM_PQ_PUSH1 & 0x7F) >> 2); 1933 mask |= 1 << ((mmTPC6_QM_PQ_PUSH2 & 0x7F) >> 2); 1934 mask |= 1 << ((mmTPC6_QM_PQ_PUSH3 & 0x7F) >> 2); 1935 mask |= 1 << ((mmTPC6_QM_PQ_STS0 & 0x7F) >> 2); 1936 mask |= 1 << ((mmTPC6_QM_PQ_STS1 & 0x7F) >> 2); 1937 mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); 1938 mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 1939 mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 1940 mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 1941 mask |= 1 << ((mmTPC6_QM_CQ_CFG0 & 0x7F) >> 2); 1942 mask |= 1 << ((mmTPC6_QM_CQ_CFG1 & 0x7F) >> 2); 1943 mask |= 1 << ((mmTPC6_QM_CQ_ARUSER & 0x7F) >> 2); 1944 mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO & 0x7F) >> 2); 1945 mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI & 0x7F) >> 2); 1946 mask |= 1 << ((mmTPC6_QM_CQ_TSIZE & 0x7F) >> 2); 1947 mask |= 1 << ((mmTPC6_QM_CQ_CTL & 0x7F) >> 2); 1948 mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS & 0x7F) >> 2); 1949 mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS & 0x7F) >> 2); 1950 mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS & 0x7F) >> 2); 1951 mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS & 0x7F) >> 2); 1952 mask |= 1 << ((mmTPC6_QM_CQ_STS0 & 0x7F) >> 2); 1953 mask |= 1 << ((mmTPC6_QM_CQ_STS1 & 0x7F) >> 2); 1954 mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 1955 mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 1956 mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 1957 mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 1958 1959 WREG32(pb_addr + word_offset, ~mask); 1960 1961 pb_addr = (mmTPC6_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 1962 word_offset = ((mmTPC6_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 1963 mask = 1 << ((mmTPC6_QM_CQ_IFIFO_CNT & 0x7F) >> 2); 1964 mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 1965 mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 1966 mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 1967 mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 1968 mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 1969 mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 1970 mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 1971 mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 1972 mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 1973 mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 1974 mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 1975 mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 1976 mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 1977 mask |= 1 << ((mmTPC6_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 1978 1979 WREG32(pb_addr + word_offset, ~mask); 1980 1981 pb_addr = (mmTPC6_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1982 word_offset = ((mmTPC6_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1983 mask = 1 << ((mmTPC6_CMDQ_GLBL_CFG0 & 0x7F) >> 2); 1984 mask |= 1 << ((mmTPC6_CMDQ_GLBL_CFG1 & 0x7F) >> 2); 1985 mask |= 1 << ((mmTPC6_CMDQ_GLBL_PROT & 0x7F) >> 2); 1986 mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); 1987 mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 1988 mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 1989 mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); 1990 mask |= 1 << ((mmTPC6_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); 1991 mask |= 1 << ((mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 1992 mask |= 1 << ((mmTPC6_CMDQ_GLBL_STS0 & 0x7F) >> 2); 1993 mask |= 1 << ((mmTPC6_CMDQ_GLBL_STS1 & 0x7F) >> 2); 1994 1995 WREG32(pb_addr + word_offset, ~mask); 1996 1997 pb_addr = (mmTPC6_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1998 word_offset = ((mmTPC6_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1999 mask = 1 << ((mmTPC6_CMDQ_CQ_CFG0 & 0x7F) >> 2); 2000 mask |= 1 << ((mmTPC6_CMDQ_CQ_CFG1 & 0x7F) >> 2); 2001 mask |= 1 << ((mmTPC6_CMDQ_CQ_ARUSER & 0x7F) >> 2); 2002 mask |= 1 << ((mmTPC6_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); 2003 mask |= 1 << ((mmTPC6_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); 2004 mask |= 1 << ((mmTPC6_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); 2005 mask |= 1 << ((mmTPC6_CMDQ_CQ_CTL_STS & 0x7F) >> 2); 2006 mask |= 1 << ((mmTPC6_CMDQ_CQ_STS0 & 0x7F) >> 2); 2007 mask |= 1 << ((mmTPC6_CMDQ_CQ_STS1 & 0x7F) >> 2); 2008 mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 2009 mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 2010 mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 2011 mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 2012 2013 WREG32(pb_addr + word_offset, ~mask); 2014 2015 pb_addr = (mmTPC6_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 2016 word_offset = ((mmTPC6_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 2017 mask = 1 << ((mmTPC6_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); 2018 mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 2019 mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 2020 mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 2021 mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 2022 mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 2023 mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 2024 mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 2025 mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 2026 mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 2027 mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 2028 mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 2029 mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 2030 mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 2031 mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 2032 mask |= 1 << ((mmTPC6_CMDQ_CP_STS & 0x7F) >> 2); 2033 mask |= 1 << ((mmTPC6_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); 2034 2035 WREG32(pb_addr + word_offset, ~mask); 2036 2037 pb_addr = (mmTPC6_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; 2038 word_offset = ((mmTPC6_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) 2039 << 2; 2040 mask = 1 << ((mmTPC6_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); 2041 mask |= 1 << ((mmTPC6_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); 2042 mask |= 1 << ((mmTPC6_CMDQ_CP_DBG_0 & 0x7F) >> 2); 2043 mask |= 1 << ((mmTPC6_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); 2044 mask |= 1 << ((mmTPC6_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); 2045 2046 WREG32(pb_addr + word_offset, ~mask); 2047 2048 goya_pb_set_block(hdev, mmTPC7_NRTR_BASE); 2049 goya_pb_set_block(hdev, mmTPC7_RD_REGULATOR_BASE); 2050 goya_pb_set_block(hdev, mmTPC7_WR_REGULATOR_BASE); 2051 2052 pb_addr = (mmTPC7_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; 2053 word_offset = ((mmTPC7_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; 2054 2055 mask = 1 << ((mmTPC7_CFG_SEMAPHORE & 0x7F) >> 2); 2056 mask |= 1 << ((mmTPC7_CFG_VFLAGS & 0x7F) >> 2); 2057 mask |= 1 << ((mmTPC7_CFG_SFLAGS & 0x7F) >> 2); 2058 mask |= 1 << ((mmTPC7_CFG_STATUS & 0x7F) >> 2); 2059 2060 WREG32(pb_addr + word_offset, ~mask); 2061 2062 pb_addr = (mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; 2063 word_offset = ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & 2064 PROT_BITS_OFFS) >> 7) << 2; 2065 mask = 1 << ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); 2066 mask |= 1 << ((mmTPC7_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); 2067 mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); 2068 mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); 2069 mask |= 1 << ((mmTPC7_CFG_TPC_STALL & 0x7F) >> 2); 2070 mask |= 1 << ((mmTPC7_CFG_MSS_CONFIG & 0x7F) >> 2); 2071 mask |= 1 << ((mmTPC7_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); 2072 mask |= 1 << ((mmTPC7_CFG_TPC_INTR_MASK & 0x7F) >> 2); 2073 2074 WREG32(pb_addr + word_offset, ~mask); 2075 2076 pb_addr = (mmTPC7_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS; 2077 word_offset = ((mmTPC7_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2; 2078 mask = 1 << ((mmTPC7_CFG_ARUSER & 0x7F) >> 2); 2079 mask |= 1 << ((mmTPC7_CFG_AWUSER & 0x7F) >> 2); 2080 2081 WREG32(pb_addr + word_offset, ~mask); 2082 2083 pb_addr = (mmTPC7_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS; 2084 word_offset = ((mmTPC7_CFG_FUNC_MBIST_CNTRL & 2085 PROT_BITS_OFFS) >> 7) << 2; 2086 mask = 1 << ((mmTPC7_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); 2087 mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); 2088 mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); 2089 mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); 2090 mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); 2091 mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); 2092 mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); 2093 mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); 2094 mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); 2095 mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); 2096 mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); 2097 mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); 2098 2099 WREG32(pb_addr + word_offset, ~mask); 2100 2101 pb_addr = (mmTPC7_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 2102 word_offset = ((mmTPC7_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 2103 mask = 1 << ((mmTPC7_QM_GLBL_CFG0 & 0x7F) >> 2); 2104 mask |= 1 << ((mmTPC7_QM_GLBL_CFG1 & 0x7F) >> 2); 2105 mask |= 1 << ((mmTPC7_QM_GLBL_PROT & 0x7F) >> 2); 2106 mask |= 1 << ((mmTPC7_QM_GLBL_ERR_CFG & 0x7F) >> 2); 2107 mask |= 1 << ((mmTPC7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 2108 mask |= 1 << ((mmTPC7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 2109 mask |= 1 << ((mmTPC7_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 2110 mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); 2111 mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 2112 mask |= 1 << ((mmTPC7_QM_GLBL_STS0 & 0x7F) >> 2); 2113 mask |= 1 << ((mmTPC7_QM_GLBL_STS1 & 0x7F) >> 2); 2114 mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO & 0x7F) >> 2); 2115 mask |= 1 << ((mmTPC7_QM_PQ_BASE_HI & 0x7F) >> 2); 2116 mask |= 1 << ((mmTPC7_QM_PQ_SIZE & 0x7F) >> 2); 2117 mask |= 1 << ((mmTPC7_QM_PQ_PI & 0x7F) >> 2); 2118 mask |= 1 << ((mmTPC7_QM_PQ_CI & 0x7F) >> 2); 2119 mask |= 1 << ((mmTPC7_QM_PQ_CFG0 & 0x7F) >> 2); 2120 mask |= 1 << ((mmTPC7_QM_PQ_CFG1 & 0x7F) >> 2); 2121 mask |= 1 << ((mmTPC7_QM_PQ_ARUSER & 0x7F) >> 2); 2122 2123 WREG32(pb_addr + word_offset, ~mask); 2124 2125 pb_addr = (mmTPC7_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS; 2126 word_offset = ((mmTPC7_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2; 2127 mask = 1 << ((mmTPC7_QM_PQ_PUSH0 & 0x7F) >> 2); 2128 mask |= 1 << ((mmTPC7_QM_PQ_PUSH1 & 0x7F) >> 2); 2129 mask |= 1 << ((mmTPC7_QM_PQ_PUSH2 & 0x7F) >> 2); 2130 mask |= 1 << ((mmTPC7_QM_PQ_PUSH3 & 0x7F) >> 2); 2131 mask |= 1 << ((mmTPC7_QM_PQ_STS0 & 0x7F) >> 2); 2132 mask |= 1 << ((mmTPC7_QM_PQ_STS1 & 0x7F) >> 2); 2133 mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); 2134 mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 2135 mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 2136 mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 2137 mask |= 1 << ((mmTPC7_QM_CQ_CFG0 & 0x7F) >> 2); 2138 mask |= 1 << ((mmTPC7_QM_CQ_CFG1 & 0x7F) >> 2); 2139 mask |= 1 << ((mmTPC7_QM_CQ_ARUSER & 0x7F) >> 2); 2140 mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO & 0x7F) >> 2); 2141 mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI & 0x7F) >> 2); 2142 mask |= 1 << ((mmTPC7_QM_CQ_TSIZE & 0x7F) >> 2); 2143 mask |= 1 << ((mmTPC7_QM_CQ_CTL & 0x7F) >> 2); 2144 mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS & 0x7F) >> 2); 2145 mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS & 0x7F) >> 2); 2146 mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS & 0x7F) >> 2); 2147 mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS & 0x7F) >> 2); 2148 mask |= 1 << ((mmTPC7_QM_CQ_STS0 & 0x7F) >> 2); 2149 mask |= 1 << ((mmTPC7_QM_CQ_STS1 & 0x7F) >> 2); 2150 mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 2151 mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 2152 mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 2153 mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 2154 2155 WREG32(pb_addr + word_offset, ~mask); 2156 2157 pb_addr = (mmTPC7_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 2158 word_offset = ((mmTPC7_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 2159 mask = 1 << ((mmTPC7_QM_CQ_IFIFO_CNT & 0x7F) >> 2); 2160 mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 2161 mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 2162 mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 2163 mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 2164 mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 2165 mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 2166 mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 2167 mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 2168 mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 2169 mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 2170 mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 2171 mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 2172 mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 2173 mask |= 1 << ((mmTPC7_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 2174 2175 WREG32(pb_addr + word_offset, ~mask); 2176 2177 pb_addr = (mmTPC7_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 2178 word_offset = ((mmTPC7_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 2179 mask = 1 << ((mmTPC7_CMDQ_GLBL_CFG0 & 0x7F) >> 2); 2180 mask |= 1 << ((mmTPC7_CMDQ_GLBL_CFG1 & 0x7F) >> 2); 2181 mask |= 1 << ((mmTPC7_CMDQ_GLBL_PROT & 0x7F) >> 2); 2182 mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); 2183 mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 2184 mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 2185 mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); 2186 mask |= 1 << ((mmTPC7_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); 2187 mask |= 1 << ((mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); 2188 mask |= 1 << ((mmTPC7_CMDQ_GLBL_STS0 & 0x7F) >> 2); 2189 mask |= 1 << ((mmTPC7_CMDQ_GLBL_STS1 & 0x7F) >> 2); 2190 2191 WREG32(pb_addr + word_offset, ~mask); 2192 2193 pb_addr = (mmTPC7_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 2194 word_offset = ((mmTPC7_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 2195 mask = 1 << ((mmTPC7_CMDQ_CQ_CFG0 & 0x7F) >> 2); 2196 mask |= 1 << ((mmTPC7_CMDQ_CQ_CFG1 & 0x7F) >> 2); 2197 mask |= 1 << ((mmTPC7_CMDQ_CQ_ARUSER & 0x7F) >> 2); 2198 mask |= 1 << ((mmTPC7_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); 2199 mask |= 1 << ((mmTPC7_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); 2200 mask |= 1 << ((mmTPC7_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); 2201 mask |= 1 << ((mmTPC7_CMDQ_CQ_CTL_STS & 0x7F) >> 2); 2202 mask |= 1 << ((mmTPC7_CMDQ_CQ_STS0 & 0x7F) >> 2); 2203 mask |= 1 << ((mmTPC7_CMDQ_CQ_STS1 & 0x7F) >> 2); 2204 mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); 2205 mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); 2206 mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); 2207 mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); 2208 2209 WREG32(pb_addr + word_offset, ~mask); 2210 2211 pb_addr = (mmTPC7_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS; 2212 word_offset = ((mmTPC7_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2; 2213 mask = 1 << ((mmTPC7_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); 2214 mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); 2215 mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); 2216 mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); 2217 mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); 2218 mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); 2219 mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); 2220 mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); 2221 mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); 2222 mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); 2223 mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); 2224 mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); 2225 mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); 2226 mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); 2227 mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); 2228 mask |= 1 << ((mmTPC7_CMDQ_CP_STS & 0x7F) >> 2); 2229 mask |= 1 << ((mmTPC7_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); 2230 2231 WREG32(pb_addr + word_offset, ~mask); 2232 2233 pb_addr = (mmTPC7_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS; 2234 word_offset = ((mmTPC7_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7) 2235 << 2; 2236 mask = 1 << ((mmTPC7_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); 2237 mask |= 1 << ((mmTPC7_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); 2238 mask |= 1 << ((mmTPC7_CMDQ_CP_DBG_0 & 0x7F) >> 2); 2239 mask |= 1 << ((mmTPC7_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); 2240 mask |= 1 << ((mmTPC7_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); 2241 2242 WREG32(pb_addr + word_offset, ~mask); 2243} 2244 2245/* 2246 * goya_init_protection_bits - Initialize protection bits for specific registers 2247 * 2248 * @hdev: pointer to hl_device structure 2249 * 2250 * All protection bits are 1 by default, means not protected. Need to set to 0 2251 * each bit that belongs to a protected register. 2252 * 2253 */ 2254static void goya_init_protection_bits(struct hl_device *hdev) 2255{ 2256 /* 2257 * In each 4K block of registers, the last 128 bytes are protection 2258 * bits - total of 1024 bits, one for each register. Each bit is related 2259 * to a specific register, by the order of the registers. 2260 * So in order to calculate the bit that is related to a given register, 2261 * we need to calculate its word offset and then the exact bit inside 2262 * the word (which is 4 bytes). 2263 * 2264 * Register address: 2265 * 2266 * 31 12 11 7 6 2 1 0 2267 * ----------------------------------------------------------------- 2268 * | Don't | word | bit location | 0 | 2269 * | care | offset | inside word | | 2270 * ----------------------------------------------------------------- 2271 * 2272 * Bits 7-11 represents the word offset inside the 128 bytes. 2273 * Bits 2-6 represents the bit location inside the word. 2274 */ 2275 u32 pb_addr, mask; 2276 u8 word_offset; 2277 2278 goya_pb_set_block(hdev, mmPCI_NRTR_BASE); 2279 goya_pb_set_block(hdev, mmPCI_RD_REGULATOR_BASE); 2280 goya_pb_set_block(hdev, mmPCI_WR_REGULATOR_BASE); 2281 2282 goya_pb_set_block(hdev, mmSRAM_Y0_X0_BANK_BASE); 2283 goya_pb_set_block(hdev, mmSRAM_Y0_X0_RTR_BASE); 2284 goya_pb_set_block(hdev, mmSRAM_Y0_X1_BANK_BASE); 2285 goya_pb_set_block(hdev, mmSRAM_Y0_X1_RTR_BASE); 2286 goya_pb_set_block(hdev, mmSRAM_Y0_X2_BANK_BASE); 2287 goya_pb_set_block(hdev, mmSRAM_Y0_X2_RTR_BASE); 2288 goya_pb_set_block(hdev, mmSRAM_Y0_X3_BANK_BASE); 2289 goya_pb_set_block(hdev, mmSRAM_Y0_X3_RTR_BASE); 2290 goya_pb_set_block(hdev, mmSRAM_Y0_X4_BANK_BASE); 2291 goya_pb_set_block(hdev, mmSRAM_Y0_X4_RTR_BASE); 2292 2293 goya_pb_set_block(hdev, mmSRAM_Y1_X0_BANK_BASE); 2294 goya_pb_set_block(hdev, mmSRAM_Y1_X0_RTR_BASE); 2295 goya_pb_set_block(hdev, mmSRAM_Y1_X1_BANK_BASE); 2296 goya_pb_set_block(hdev, mmSRAM_Y1_X1_RTR_BASE); 2297 goya_pb_set_block(hdev, mmSRAM_Y1_X2_BANK_BASE); 2298 goya_pb_set_block(hdev, mmSRAM_Y1_X2_RTR_BASE); 2299 goya_pb_set_block(hdev, mmSRAM_Y1_X3_BANK_BASE); 2300 goya_pb_set_block(hdev, mmSRAM_Y1_X3_RTR_BASE); 2301 goya_pb_set_block(hdev, mmSRAM_Y1_X4_BANK_BASE); 2302 goya_pb_set_block(hdev, mmSRAM_Y1_X4_RTR_BASE); 2303 2304 goya_pb_set_block(hdev, mmSRAM_Y2_X0_BANK_BASE); 2305 goya_pb_set_block(hdev, mmSRAM_Y2_X0_RTR_BASE); 2306 goya_pb_set_block(hdev, mmSRAM_Y2_X1_BANK_BASE); 2307 goya_pb_set_block(hdev, mmSRAM_Y2_X1_RTR_BASE); 2308 goya_pb_set_block(hdev, mmSRAM_Y2_X2_BANK_BASE); 2309 goya_pb_set_block(hdev, mmSRAM_Y2_X2_RTR_BASE); 2310 goya_pb_set_block(hdev, mmSRAM_Y2_X3_BANK_BASE); 2311 goya_pb_set_block(hdev, mmSRAM_Y2_X3_RTR_BASE); 2312 goya_pb_set_block(hdev, mmSRAM_Y2_X4_BANK_BASE); 2313 goya_pb_set_block(hdev, mmSRAM_Y2_X4_RTR_BASE); 2314 2315 goya_pb_set_block(hdev, mmSRAM_Y3_X0_BANK_BASE); 2316 goya_pb_set_block(hdev, mmSRAM_Y3_X0_RTR_BASE); 2317 goya_pb_set_block(hdev, mmSRAM_Y3_X1_BANK_BASE); 2318 goya_pb_set_block(hdev, mmSRAM_Y3_X1_RTR_BASE); 2319 goya_pb_set_block(hdev, mmSRAM_Y3_X2_BANK_BASE); 2320 goya_pb_set_block(hdev, mmSRAM_Y3_X2_RTR_BASE); 2321 goya_pb_set_block(hdev, mmSRAM_Y3_X3_BANK_BASE); 2322 goya_pb_set_block(hdev, mmSRAM_Y3_X3_RTR_BASE); 2323 goya_pb_set_block(hdev, mmSRAM_Y3_X4_BANK_BASE); 2324 goya_pb_set_block(hdev, mmSRAM_Y3_X4_RTR_BASE); 2325 2326 goya_pb_set_block(hdev, mmSRAM_Y4_X0_BANK_BASE); 2327 goya_pb_set_block(hdev, mmSRAM_Y4_X0_RTR_BASE); 2328 goya_pb_set_block(hdev, mmSRAM_Y4_X1_BANK_BASE); 2329 goya_pb_set_block(hdev, mmSRAM_Y4_X1_RTR_BASE); 2330 goya_pb_set_block(hdev, mmSRAM_Y4_X2_BANK_BASE); 2331 goya_pb_set_block(hdev, mmSRAM_Y4_X2_RTR_BASE); 2332 goya_pb_set_block(hdev, mmSRAM_Y4_X3_BANK_BASE); 2333 goya_pb_set_block(hdev, mmSRAM_Y4_X3_RTR_BASE); 2334 goya_pb_set_block(hdev, mmSRAM_Y4_X4_BANK_BASE); 2335 goya_pb_set_block(hdev, mmSRAM_Y4_X4_RTR_BASE); 2336 2337 goya_pb_set_block(hdev, mmSRAM_Y5_X0_BANK_BASE); 2338 goya_pb_set_block(hdev, mmSRAM_Y5_X0_RTR_BASE); 2339 goya_pb_set_block(hdev, mmSRAM_Y5_X1_BANK_BASE); 2340 goya_pb_set_block(hdev, mmSRAM_Y5_X1_RTR_BASE); 2341 goya_pb_set_block(hdev, mmSRAM_Y5_X2_BANK_BASE); 2342 goya_pb_set_block(hdev, mmSRAM_Y5_X2_RTR_BASE); 2343 goya_pb_set_block(hdev, mmSRAM_Y5_X3_BANK_BASE); 2344 goya_pb_set_block(hdev, mmSRAM_Y5_X3_RTR_BASE); 2345 goya_pb_set_block(hdev, mmSRAM_Y5_X4_BANK_BASE); 2346 goya_pb_set_block(hdev, mmSRAM_Y5_X4_RTR_BASE); 2347 2348 goya_pb_set_block(hdev, mmPCIE_WRAP_BASE); 2349 goya_pb_set_block(hdev, mmPCIE_CORE_BASE); 2350 goya_pb_set_block(hdev, mmPCIE_DB_CFG_BASE); 2351 goya_pb_set_block(hdev, mmPCIE_DB_CMD_BASE); 2352 goya_pb_set_block(hdev, mmPCIE_AUX_BASE); 2353 goya_pb_set_block(hdev, mmPCIE_DB_RSV_BASE); 2354 goya_pb_set_block(hdev, mmPCIE_PHY_BASE); 2355 goya_pb_set_block(hdev, mmTPC0_NRTR_BASE); 2356 goya_pb_set_block(hdev, mmTPC_PLL_BASE); 2357 2358 pb_addr = (mmTPC_PLL_CLK_RLX_0 & ~0xFFF) + PROT_BITS_OFFS; 2359 word_offset = ((mmTPC_PLL_CLK_RLX_0 & PROT_BITS_OFFS) >> 7) << 2; 2360 mask = 1 << ((mmTPC_PLL_CLK_RLX_0 & 0x7C) >> 2); 2361 2362 WREG32(pb_addr + word_offset, mask); 2363 2364 goya_init_mme_protection_bits(hdev); 2365 2366 goya_init_dma_protection_bits(hdev); 2367 2368 goya_init_tpc_protection_bits(hdev); 2369} 2370 2371/* 2372 * goya_init_security - Initialize security model 2373 * 2374 * @hdev: pointer to hl_device structure 2375 * 2376 * Initialize the security model of the device 2377 * That includes range registers and protection bit per register 2378 * 2379 */ 2380void goya_init_security(struct hl_device *hdev) 2381{ 2382 struct goya_device *goya = hdev->asic_specific; 2383 2384 u32 dram_addr_lo = lower_32_bits(DRAM_PHYS_BASE); 2385 u32 dram_addr_hi = upper_32_bits(DRAM_PHYS_BASE); 2386 2387 u32 lbw_rng0_base = 0xFC440000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2388 u32 lbw_rng0_mask = 0xFFFF0000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2389 2390 u32 lbw_rng1_base = 0xFC480000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2391 u32 lbw_rng1_mask = 0xFFF80000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2392 2393 u32 lbw_rng2_base = 0xFC600000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2394 u32 lbw_rng2_mask = 0xFFE00000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2395 2396 u32 lbw_rng3_base = 0xFC800000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2397 u32 lbw_rng3_mask = 0xFFF00000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2398 2399 u32 lbw_rng4_base = 0xFCC02000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2400 u32 lbw_rng4_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2401 2402 u32 lbw_rng5_base = 0xFCC40000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2403 u32 lbw_rng5_mask = 0xFFFF8000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2404 2405 u32 lbw_rng6_base = 0xFCC48000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2406 u32 lbw_rng6_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2407 2408 u32 lbw_rng7_base = 0xFCC4A000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2409 u32 lbw_rng7_mask = 0xFFFFE000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2410 2411 u32 lbw_rng8_base = 0xFCC4C000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2412 u32 lbw_rng8_mask = 0xFFFFC000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2413 2414 u32 lbw_rng9_base = 0xFCC50000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2415 u32 lbw_rng9_mask = 0xFFFF0000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2416 2417 u32 lbw_rng10_base = 0xFCC60000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2418 u32 lbw_rng10_mask = 0xFFFE0000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2419 2420 u32 lbw_rng11_base = 0xFCE02000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2421 u32 lbw_rng11_mask = 0xFFFFE000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2422 2423 u32 lbw_rng12_base = 0xFE484000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2424 u32 lbw_rng12_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2425 2426 u32 lbw_rng13_base = 0xFEC43000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2427 u32 lbw_rng13_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK; 2428 2429 WREG32(mmDMA_MACRO_LBW_RANGE_HIT_BLOCK, 0xFFFF); 2430 WREG32(mmDMA_MACRO_HBW_RANGE_HIT_BLOCK, 0xFF); 2431 2432 if (!(goya->hw_cap_initialized & HW_CAP_MMU)) { 2433 WREG32(mmDMA_MACRO_HBW_RANGE_HIT_BLOCK, 0xFE); 2434 2435 /* Protect HOST */ 2436 WREG32(mmDMA_MACRO_HBW_RANGE_BASE_31_0_0, 0); 2437 WREG32(mmDMA_MACRO_HBW_RANGE_BASE_49_32_0, 0); 2438 WREG32(mmDMA_MACRO_HBW_RANGE_MASK_31_0_0, 0); 2439 WREG32(mmDMA_MACRO_HBW_RANGE_MASK_49_32_0, 0xFFF80); 2440 } 2441 2442 /* 2443 * Protect DDR @ 2444 * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END 2445 * The mask protects the first 512MB 2446 */ 2447 WREG32(mmDMA_MACRO_HBW_RANGE_BASE_31_0_1, dram_addr_lo); 2448 WREG32(mmDMA_MACRO_HBW_RANGE_BASE_49_32_1, dram_addr_hi); 2449 WREG32(mmDMA_MACRO_HBW_RANGE_MASK_31_0_1, 0xE0000000); 2450 WREG32(mmDMA_MACRO_HBW_RANGE_MASK_49_32_1, 0x3FFFF); 2451 2452 /* Protect registers */ 2453 2454 WREG32(mmDMA_MACRO_LBW_RANGE_BASE_0, lbw_rng0_base); 2455 WREG32(mmDMA_MACRO_LBW_RANGE_MASK_0, lbw_rng0_mask); 2456 WREG32(mmDMA_MACRO_LBW_RANGE_BASE_1, lbw_rng1_base); 2457 WREG32(mmDMA_MACRO_LBW_RANGE_MASK_1, lbw_rng1_mask); 2458 WREG32(mmDMA_MACRO_LBW_RANGE_BASE_2, lbw_rng2_base); 2459 WREG32(mmDMA_MACRO_LBW_RANGE_MASK_2, lbw_rng2_mask); 2460 WREG32(mmDMA_MACRO_LBW_RANGE_BASE_3, lbw_rng3_base); 2461 WREG32(mmDMA_MACRO_LBW_RANGE_MASK_3, lbw_rng3_mask); 2462 WREG32(mmDMA_MACRO_LBW_RANGE_BASE_4, lbw_rng4_base); 2463 WREG32(mmDMA_MACRO_LBW_RANGE_MASK_4, lbw_rng4_mask); 2464 WREG32(mmDMA_MACRO_LBW_RANGE_BASE_5, lbw_rng5_base); 2465 WREG32(mmDMA_MACRO_LBW_RANGE_MASK_5, lbw_rng5_mask); 2466 WREG32(mmDMA_MACRO_LBW_RANGE_BASE_6, lbw_rng6_base); 2467 WREG32(mmDMA_MACRO_LBW_RANGE_MASK_6, lbw_rng6_mask); 2468 WREG32(mmDMA_MACRO_LBW_RANGE_BASE_7, lbw_rng7_base); 2469 WREG32(mmDMA_MACRO_LBW_RANGE_MASK_7, lbw_rng7_mask); 2470 WREG32(mmDMA_MACRO_LBW_RANGE_BASE_8, lbw_rng8_base); 2471 WREG32(mmDMA_MACRO_LBW_RANGE_MASK_8, lbw_rng8_mask); 2472 WREG32(mmDMA_MACRO_LBW_RANGE_BASE_9, lbw_rng9_base); 2473 WREG32(mmDMA_MACRO_LBW_RANGE_MASK_9, lbw_rng9_mask); 2474 WREG32(mmDMA_MACRO_LBW_RANGE_BASE_10, lbw_rng10_base); 2475 WREG32(mmDMA_MACRO_LBW_RANGE_MASK_10, lbw_rng10_mask); 2476 WREG32(mmDMA_MACRO_LBW_RANGE_BASE_11, lbw_rng11_base); 2477 WREG32(mmDMA_MACRO_LBW_RANGE_MASK_11, lbw_rng11_mask); 2478 WREG32(mmDMA_MACRO_LBW_RANGE_BASE_12, lbw_rng12_base); 2479 WREG32(mmDMA_MACRO_LBW_RANGE_MASK_12, lbw_rng12_mask); 2480 WREG32(mmDMA_MACRO_LBW_RANGE_BASE_13, lbw_rng13_base); 2481 WREG32(mmDMA_MACRO_LBW_RANGE_MASK_13, lbw_rng13_mask); 2482 2483 WREG32(mmMME1_RTR_LBW_RANGE_HIT, 0xFFFF); 2484 WREG32(mmMME2_RTR_LBW_RANGE_HIT, 0xFFFF); 2485 WREG32(mmMME3_RTR_LBW_RANGE_HIT, 0xFFFF); 2486 WREG32(mmMME4_RTR_LBW_RANGE_HIT, 0xFFFF); 2487 WREG32(mmMME5_RTR_LBW_RANGE_HIT, 0xFFFF); 2488 WREG32(mmMME6_RTR_LBW_RANGE_HIT, 0xFFFF); 2489 2490 WREG32(mmMME1_RTR_HBW_RANGE_HIT, 0xFE); 2491 WREG32(mmMME2_RTR_HBW_RANGE_HIT, 0xFE); 2492 WREG32(mmMME3_RTR_HBW_RANGE_HIT, 0xFE); 2493 WREG32(mmMME4_RTR_HBW_RANGE_HIT, 0xFE); 2494 WREG32(mmMME5_RTR_HBW_RANGE_HIT, 0xFE); 2495 WREG32(mmMME6_RTR_HBW_RANGE_HIT, 0xFE); 2496 2497 /* Protect HOST */ 2498 WREG32(mmMME1_RTR_HBW_RANGE_BASE_L_0, 0); 2499 WREG32(mmMME1_RTR_HBW_RANGE_BASE_H_0, 0); 2500 WREG32(mmMME1_RTR_HBW_RANGE_MASK_L_0, 0); 2501 WREG32(mmMME1_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); 2502 2503 WREG32(mmMME2_RTR_HBW_RANGE_BASE_L_0, 0); 2504 WREG32(mmMME2_RTR_HBW_RANGE_BASE_H_0, 0); 2505 WREG32(mmMME2_RTR_HBW_RANGE_MASK_L_0, 0); 2506 WREG32(mmMME2_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); 2507 2508 WREG32(mmMME3_RTR_HBW_RANGE_BASE_L_0, 0); 2509 WREG32(mmMME3_RTR_HBW_RANGE_BASE_H_0, 0); 2510 WREG32(mmMME3_RTR_HBW_RANGE_MASK_L_0, 0); 2511 WREG32(mmMME3_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); 2512 2513 WREG32(mmMME4_RTR_HBW_RANGE_BASE_L_0, 0); 2514 WREG32(mmMME4_RTR_HBW_RANGE_BASE_H_0, 0); 2515 WREG32(mmMME4_RTR_HBW_RANGE_MASK_L_0, 0); 2516 WREG32(mmMME4_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); 2517 2518 WREG32(mmMME5_RTR_HBW_RANGE_BASE_L_0, 0); 2519 WREG32(mmMME5_RTR_HBW_RANGE_BASE_H_0, 0); 2520 WREG32(mmMME5_RTR_HBW_RANGE_MASK_L_0, 0); 2521 WREG32(mmMME5_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); 2522 2523 WREG32(mmMME6_RTR_HBW_RANGE_BASE_L_0, 0); 2524 WREG32(mmMME6_RTR_HBW_RANGE_BASE_H_0, 0); 2525 WREG32(mmMME6_RTR_HBW_RANGE_MASK_L_0, 0); 2526 WREG32(mmMME6_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); 2527 2528 /* 2529 * Protect DDR @ 2530 * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END 2531 * The mask protects the first 512MB 2532 */ 2533 WREG32(mmMME1_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); 2534 WREG32(mmMME1_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); 2535 WREG32(mmMME1_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); 2536 WREG32(mmMME1_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); 2537 2538 WREG32(mmMME2_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); 2539 WREG32(mmMME2_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); 2540 WREG32(mmMME2_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); 2541 WREG32(mmMME2_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); 2542 2543 WREG32(mmMME3_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); 2544 WREG32(mmMME3_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); 2545 WREG32(mmMME3_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); 2546 WREG32(mmMME3_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); 2547 2548 WREG32(mmMME4_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); 2549 WREG32(mmMME4_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); 2550 WREG32(mmMME4_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); 2551 WREG32(mmMME4_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); 2552 2553 WREG32(mmMME5_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); 2554 WREG32(mmMME5_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); 2555 WREG32(mmMME5_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); 2556 WREG32(mmMME5_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); 2557 2558 WREG32(mmMME6_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); 2559 WREG32(mmMME6_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); 2560 WREG32(mmMME6_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); 2561 WREG32(mmMME6_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); 2562 2563 WREG32(mmMME1_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); 2564 WREG32(mmMME1_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); 2565 WREG32(mmMME1_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); 2566 WREG32(mmMME1_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); 2567 WREG32(mmMME1_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); 2568 WREG32(mmMME1_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); 2569 WREG32(mmMME1_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); 2570 WREG32(mmMME1_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); 2571 WREG32(mmMME1_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); 2572 WREG32(mmMME1_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); 2573 WREG32(mmMME1_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); 2574 WREG32(mmMME1_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); 2575 WREG32(mmMME1_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); 2576 WREG32(mmMME1_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); 2577 WREG32(mmMME1_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); 2578 WREG32(mmMME1_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); 2579 WREG32(mmMME1_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); 2580 WREG32(mmMME1_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); 2581 WREG32(mmMME1_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); 2582 WREG32(mmMME1_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); 2583 WREG32(mmMME1_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); 2584 WREG32(mmMME1_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); 2585 WREG32(mmMME1_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); 2586 WREG32(mmMME1_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); 2587 WREG32(mmMME1_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); 2588 WREG32(mmMME1_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); 2589 WREG32(mmMME1_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); 2590 WREG32(mmMME1_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); 2591 2592 WREG32(mmMME2_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); 2593 WREG32(mmMME2_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); 2594 WREG32(mmMME2_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); 2595 WREG32(mmMME2_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); 2596 WREG32(mmMME2_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); 2597 WREG32(mmMME2_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); 2598 WREG32(mmMME2_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); 2599 WREG32(mmMME2_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); 2600 WREG32(mmMME2_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); 2601 WREG32(mmMME2_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); 2602 WREG32(mmMME2_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); 2603 WREG32(mmMME2_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); 2604 WREG32(mmMME2_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); 2605 WREG32(mmMME2_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); 2606 WREG32(mmMME2_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); 2607 WREG32(mmMME2_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); 2608 WREG32(mmMME2_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); 2609 WREG32(mmMME2_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); 2610 WREG32(mmMME2_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); 2611 WREG32(mmMME2_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); 2612 WREG32(mmMME2_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); 2613 WREG32(mmMME2_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); 2614 WREG32(mmMME2_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); 2615 WREG32(mmMME2_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); 2616 WREG32(mmMME2_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); 2617 WREG32(mmMME2_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); 2618 WREG32(mmMME2_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); 2619 WREG32(mmMME2_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); 2620 2621 WREG32(mmMME3_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); 2622 WREG32(mmMME3_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); 2623 WREG32(mmMME3_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); 2624 WREG32(mmMME3_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); 2625 WREG32(mmMME3_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); 2626 WREG32(mmMME3_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); 2627 WREG32(mmMME3_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); 2628 WREG32(mmMME3_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); 2629 WREG32(mmMME3_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); 2630 WREG32(mmMME3_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); 2631 WREG32(mmMME3_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); 2632 WREG32(mmMME3_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); 2633 WREG32(mmMME3_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); 2634 WREG32(mmMME3_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); 2635 WREG32(mmMME3_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); 2636 WREG32(mmMME3_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); 2637 WREG32(mmMME3_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); 2638 WREG32(mmMME3_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); 2639 WREG32(mmMME3_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); 2640 WREG32(mmMME3_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); 2641 WREG32(mmMME3_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); 2642 WREG32(mmMME3_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); 2643 WREG32(mmMME3_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); 2644 WREG32(mmMME3_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); 2645 WREG32(mmMME3_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); 2646 WREG32(mmMME3_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); 2647 WREG32(mmMME3_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); 2648 WREG32(mmMME3_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); 2649 2650 WREG32(mmMME4_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); 2651 WREG32(mmMME4_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); 2652 WREG32(mmMME4_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); 2653 WREG32(mmMME4_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); 2654 WREG32(mmMME4_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); 2655 WREG32(mmMME4_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); 2656 WREG32(mmMME4_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); 2657 WREG32(mmMME4_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); 2658 WREG32(mmMME4_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); 2659 WREG32(mmMME4_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); 2660 WREG32(mmMME4_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); 2661 WREG32(mmMME4_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); 2662 WREG32(mmMME4_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); 2663 WREG32(mmMME4_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); 2664 WREG32(mmMME4_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); 2665 WREG32(mmMME4_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); 2666 WREG32(mmMME4_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); 2667 WREG32(mmMME4_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); 2668 WREG32(mmMME4_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); 2669 WREG32(mmMME4_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); 2670 WREG32(mmMME4_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); 2671 WREG32(mmMME4_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); 2672 WREG32(mmMME4_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); 2673 WREG32(mmMME4_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); 2674 WREG32(mmMME4_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); 2675 WREG32(mmMME4_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); 2676 WREG32(mmMME4_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); 2677 WREG32(mmMME4_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); 2678 2679 WREG32(mmMME5_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); 2680 WREG32(mmMME5_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); 2681 WREG32(mmMME5_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); 2682 WREG32(mmMME5_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); 2683 WREG32(mmMME5_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); 2684 WREG32(mmMME5_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); 2685 WREG32(mmMME5_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); 2686 WREG32(mmMME5_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); 2687 WREG32(mmMME5_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); 2688 WREG32(mmMME5_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); 2689 WREG32(mmMME5_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); 2690 WREG32(mmMME5_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); 2691 WREG32(mmMME5_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); 2692 WREG32(mmMME5_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); 2693 WREG32(mmMME5_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); 2694 WREG32(mmMME5_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); 2695 WREG32(mmMME5_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); 2696 WREG32(mmMME5_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); 2697 WREG32(mmMME5_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); 2698 WREG32(mmMME5_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); 2699 WREG32(mmMME5_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); 2700 WREG32(mmMME5_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); 2701 WREG32(mmMME5_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); 2702 WREG32(mmMME5_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); 2703 WREG32(mmMME5_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); 2704 WREG32(mmMME5_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); 2705 WREG32(mmMME5_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); 2706 WREG32(mmMME5_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); 2707 2708 WREG32(mmMME6_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); 2709 WREG32(mmMME6_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); 2710 WREG32(mmMME6_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); 2711 WREG32(mmMME6_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); 2712 WREG32(mmMME6_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); 2713 WREG32(mmMME6_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); 2714 WREG32(mmMME6_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); 2715 WREG32(mmMME6_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); 2716 WREG32(mmMME6_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); 2717 WREG32(mmMME6_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); 2718 WREG32(mmMME6_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); 2719 WREG32(mmMME6_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); 2720 WREG32(mmMME6_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); 2721 WREG32(mmMME6_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); 2722 WREG32(mmMME6_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); 2723 WREG32(mmMME6_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); 2724 WREG32(mmMME6_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); 2725 WREG32(mmMME6_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); 2726 WREG32(mmMME6_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); 2727 WREG32(mmMME6_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); 2728 WREG32(mmMME6_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); 2729 WREG32(mmMME6_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); 2730 WREG32(mmMME6_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); 2731 WREG32(mmMME6_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); 2732 WREG32(mmMME6_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); 2733 WREG32(mmMME6_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); 2734 WREG32(mmMME6_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); 2735 WREG32(mmMME6_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); 2736 2737 WREG32(mmTPC0_NRTR_LBW_RANGE_HIT, 0xFFFF); 2738 WREG32(mmTPC0_NRTR_HBW_RANGE_HIT, 0xFE); 2739 2740 /* Protect HOST */ 2741 WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_L_0, 0); 2742 WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_H_0, 0); 2743 WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_L_0, 0); 2744 WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_H_0, 0xFFF80); 2745 2746 /* 2747 * Protect DDR @ 2748 * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END 2749 * The mask protects the first 512MB 2750 */ 2751 WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_L_1, dram_addr_lo); 2752 WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_H_1, dram_addr_hi); 2753 WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_L_1, 0xE0000000); 2754 WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_H_1, 0x3FFFF); 2755 2756 WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_0, lbw_rng0_base); 2757 WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_0, lbw_rng0_mask); 2758 WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_1, lbw_rng1_base); 2759 WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_1, lbw_rng1_mask); 2760 WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_2, lbw_rng2_base); 2761 WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_2, lbw_rng2_mask); 2762 WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_3, lbw_rng3_base); 2763 WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_3, lbw_rng3_mask); 2764 WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_4, lbw_rng4_base); 2765 WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_4, lbw_rng4_mask); 2766 WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_5, lbw_rng5_base); 2767 WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_5, lbw_rng5_mask); 2768 WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_6, lbw_rng6_base); 2769 WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_6, lbw_rng6_mask); 2770 WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_7, lbw_rng7_base); 2771 WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_7, lbw_rng7_mask); 2772 WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_8, lbw_rng8_base); 2773 WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_8, lbw_rng8_mask); 2774 WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_9, lbw_rng9_base); 2775 WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_9, lbw_rng9_mask); 2776 WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_10, lbw_rng10_base); 2777 WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_10, lbw_rng10_mask); 2778 WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_11, lbw_rng11_base); 2779 WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_11, lbw_rng11_mask); 2780 WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_12, lbw_rng12_base); 2781 WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_12, lbw_rng12_mask); 2782 WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_13, lbw_rng13_base); 2783 WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_13, lbw_rng13_mask); 2784 2785 WREG32(mmTPC1_RTR_LBW_RANGE_HIT, 0xFFFF); 2786 WREG32(mmTPC1_RTR_HBW_RANGE_HIT, 0xFE); 2787 2788 /* Protect HOST */ 2789 WREG32(mmTPC1_RTR_HBW_RANGE_BASE_L_0, 0); 2790 WREG32(mmTPC1_RTR_HBW_RANGE_BASE_H_0, 0); 2791 WREG32(mmTPC1_RTR_HBW_RANGE_MASK_L_0, 0); 2792 WREG32(mmTPC1_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); 2793 2794 /* 2795 * Protect DDR @ 2796 * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END 2797 * The mask protects the first 512MB 2798 */ 2799 WREG32(mmTPC1_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); 2800 WREG32(mmTPC1_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); 2801 WREG32(mmTPC1_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); 2802 WREG32(mmTPC1_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); 2803 2804 WREG32(mmTPC1_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); 2805 WREG32(mmTPC1_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); 2806 WREG32(mmTPC1_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); 2807 WREG32(mmTPC1_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); 2808 WREG32(mmTPC1_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); 2809 WREG32(mmTPC1_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); 2810 WREG32(mmTPC1_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); 2811 WREG32(mmTPC1_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); 2812 WREG32(mmTPC1_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); 2813 WREG32(mmTPC1_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); 2814 WREG32(mmTPC1_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); 2815 WREG32(mmTPC1_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); 2816 WREG32(mmTPC1_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); 2817 WREG32(mmTPC1_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); 2818 WREG32(mmTPC1_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); 2819 WREG32(mmTPC1_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); 2820 WREG32(mmTPC1_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); 2821 WREG32(mmTPC1_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); 2822 WREG32(mmTPC1_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); 2823 WREG32(mmTPC1_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); 2824 WREG32(mmTPC1_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); 2825 WREG32(mmTPC1_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); 2826 WREG32(mmTPC1_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); 2827 WREG32(mmTPC1_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); 2828 WREG32(mmTPC1_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); 2829 WREG32(mmTPC1_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); 2830 WREG32(mmTPC1_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); 2831 WREG32(mmTPC1_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); 2832 2833 WREG32(mmTPC2_RTR_LBW_RANGE_HIT, 0xFFFF); 2834 WREG32(mmTPC2_RTR_HBW_RANGE_HIT, 0xFE); 2835 2836 /* Protect HOST */ 2837 WREG32(mmTPC2_RTR_HBW_RANGE_BASE_L_0, 0); 2838 WREG32(mmTPC2_RTR_HBW_RANGE_BASE_H_0, 0); 2839 WREG32(mmTPC2_RTR_HBW_RANGE_MASK_L_0, 0); 2840 WREG32(mmTPC2_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); 2841 2842 /* 2843 * Protect DDR @ 2844 * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END 2845 * The mask protects the first 512MB 2846 */ 2847 WREG32(mmTPC2_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); 2848 WREG32(mmTPC2_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); 2849 WREG32(mmTPC2_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); 2850 WREG32(mmTPC2_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); 2851 2852 WREG32(mmTPC2_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); 2853 WREG32(mmTPC2_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); 2854 WREG32(mmTPC2_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); 2855 WREG32(mmTPC2_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); 2856 WREG32(mmTPC2_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); 2857 WREG32(mmTPC2_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); 2858 WREG32(mmTPC2_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); 2859 WREG32(mmTPC2_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); 2860 WREG32(mmTPC2_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); 2861 WREG32(mmTPC2_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); 2862 WREG32(mmTPC2_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); 2863 WREG32(mmTPC2_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); 2864 WREG32(mmTPC2_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); 2865 WREG32(mmTPC2_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); 2866 WREG32(mmTPC2_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); 2867 WREG32(mmTPC2_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); 2868 WREG32(mmTPC2_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); 2869 WREG32(mmTPC2_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); 2870 WREG32(mmTPC2_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); 2871 WREG32(mmTPC2_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); 2872 WREG32(mmTPC2_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); 2873 WREG32(mmTPC2_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); 2874 WREG32(mmTPC2_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); 2875 WREG32(mmTPC2_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); 2876 WREG32(mmTPC2_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); 2877 WREG32(mmTPC2_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); 2878 WREG32(mmTPC2_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); 2879 WREG32(mmTPC2_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); 2880 2881 WREG32(mmTPC3_RTR_LBW_RANGE_HIT, 0xFFFF); 2882 WREG32(mmTPC3_RTR_HBW_RANGE_HIT, 0xFE); 2883 2884 /* Protect HOST */ 2885 WREG32(mmTPC3_RTR_HBW_RANGE_BASE_L_0, 0); 2886 WREG32(mmTPC3_RTR_HBW_RANGE_BASE_H_0, 0); 2887 WREG32(mmTPC3_RTR_HBW_RANGE_MASK_L_0, 0); 2888 WREG32(mmTPC3_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); 2889 2890 /* 2891 * Protect DDR @ 2892 * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END 2893 * The mask protects the first 512MB 2894 */ 2895 WREG32(mmTPC3_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); 2896 WREG32(mmTPC3_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); 2897 WREG32(mmTPC3_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); 2898 WREG32(mmTPC3_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); 2899 2900 WREG32(mmTPC3_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); 2901 WREG32(mmTPC3_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); 2902 WREG32(mmTPC3_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); 2903 WREG32(mmTPC3_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); 2904 WREG32(mmTPC3_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); 2905 WREG32(mmTPC3_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); 2906 WREG32(mmTPC3_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); 2907 WREG32(mmTPC3_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); 2908 WREG32(mmTPC3_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); 2909 WREG32(mmTPC3_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); 2910 WREG32(mmTPC3_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); 2911 WREG32(mmTPC3_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); 2912 WREG32(mmTPC3_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); 2913 WREG32(mmTPC3_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); 2914 WREG32(mmTPC3_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); 2915 WREG32(mmTPC3_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); 2916 WREG32(mmTPC3_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); 2917 WREG32(mmTPC3_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); 2918 WREG32(mmTPC3_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); 2919 WREG32(mmTPC3_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); 2920 WREG32(mmTPC3_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); 2921 WREG32(mmTPC3_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); 2922 WREG32(mmTPC3_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); 2923 WREG32(mmTPC3_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); 2924 WREG32(mmTPC3_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); 2925 WREG32(mmTPC3_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); 2926 WREG32(mmTPC3_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); 2927 WREG32(mmTPC3_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); 2928 2929 WREG32(mmTPC4_RTR_LBW_RANGE_HIT, 0xFFFF); 2930 WREG32(mmTPC4_RTR_HBW_RANGE_HIT, 0xFE); 2931 2932 /* Protect HOST */ 2933 WREG32(mmTPC4_RTR_HBW_RANGE_BASE_L_0, 0); 2934 WREG32(mmTPC4_RTR_HBW_RANGE_BASE_H_0, 0); 2935 WREG32(mmTPC4_RTR_HBW_RANGE_MASK_L_0, 0); 2936 WREG32(mmTPC4_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); 2937 2938 /* 2939 * Protect DDR @ 2940 * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END 2941 * The mask protects the first 512MB 2942 */ 2943 WREG32(mmTPC4_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); 2944 WREG32(mmTPC4_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); 2945 WREG32(mmTPC4_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); 2946 WREG32(mmTPC4_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); 2947 2948 WREG32(mmTPC4_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); 2949 WREG32(mmTPC4_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); 2950 WREG32(mmTPC4_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); 2951 WREG32(mmTPC4_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); 2952 WREG32(mmTPC4_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); 2953 WREG32(mmTPC4_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); 2954 WREG32(mmTPC4_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); 2955 WREG32(mmTPC4_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); 2956 WREG32(mmTPC4_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); 2957 WREG32(mmTPC4_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); 2958 WREG32(mmTPC4_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); 2959 WREG32(mmTPC4_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); 2960 WREG32(mmTPC4_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); 2961 WREG32(mmTPC4_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); 2962 WREG32(mmTPC4_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); 2963 WREG32(mmTPC4_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); 2964 WREG32(mmTPC4_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); 2965 WREG32(mmTPC4_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); 2966 WREG32(mmTPC4_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); 2967 WREG32(mmTPC4_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); 2968 WREG32(mmTPC4_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); 2969 WREG32(mmTPC4_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); 2970 WREG32(mmTPC4_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); 2971 WREG32(mmTPC4_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); 2972 WREG32(mmTPC4_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); 2973 WREG32(mmTPC4_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); 2974 WREG32(mmTPC4_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); 2975 WREG32(mmTPC4_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); 2976 2977 WREG32(mmTPC5_RTR_LBW_RANGE_HIT, 0xFFFF); 2978 WREG32(mmTPC5_RTR_HBW_RANGE_HIT, 0xFE); 2979 2980 /* Protect HOST */ 2981 WREG32(mmTPC5_RTR_HBW_RANGE_BASE_L_0, 0); 2982 WREG32(mmTPC5_RTR_HBW_RANGE_BASE_H_0, 0); 2983 WREG32(mmTPC5_RTR_HBW_RANGE_MASK_L_0, 0); 2984 WREG32(mmTPC5_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); 2985 2986 /* 2987 * Protect DDR @ 2988 * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END 2989 * The mask protects the first 512MB 2990 */ 2991 WREG32(mmTPC5_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); 2992 WREG32(mmTPC5_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); 2993 WREG32(mmTPC5_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); 2994 WREG32(mmTPC5_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); 2995 2996 WREG32(mmTPC5_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); 2997 WREG32(mmTPC5_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); 2998 WREG32(mmTPC5_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); 2999 WREG32(mmTPC5_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); 3000 WREG32(mmTPC5_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); 3001 WREG32(mmTPC5_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); 3002 WREG32(mmTPC5_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); 3003 WREG32(mmTPC5_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); 3004 WREG32(mmTPC5_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); 3005 WREG32(mmTPC5_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); 3006 WREG32(mmTPC5_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); 3007 WREG32(mmTPC5_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); 3008 WREG32(mmTPC5_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); 3009 WREG32(mmTPC5_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); 3010 WREG32(mmTPC5_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); 3011 WREG32(mmTPC5_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); 3012 WREG32(mmTPC5_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); 3013 WREG32(mmTPC5_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); 3014 WREG32(mmTPC5_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); 3015 WREG32(mmTPC5_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); 3016 WREG32(mmTPC5_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); 3017 WREG32(mmTPC5_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); 3018 WREG32(mmTPC5_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); 3019 WREG32(mmTPC5_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); 3020 WREG32(mmTPC5_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); 3021 WREG32(mmTPC5_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); 3022 WREG32(mmTPC5_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); 3023 WREG32(mmTPC5_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); 3024 3025 WREG32(mmTPC6_RTR_LBW_RANGE_HIT, 0xFFFF); 3026 WREG32(mmTPC6_RTR_HBW_RANGE_HIT, 0xFE); 3027 3028 /* Protect HOST */ 3029 WREG32(mmTPC6_RTR_HBW_RANGE_BASE_L_0, 0); 3030 WREG32(mmTPC6_RTR_HBW_RANGE_BASE_H_0, 0); 3031 WREG32(mmTPC6_RTR_HBW_RANGE_MASK_L_0, 0); 3032 WREG32(mmTPC6_RTR_HBW_RANGE_MASK_H_0, 0xFFF80); 3033 3034 /* 3035 * Protect DDR @ 3036 * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END 3037 * The mask protects the first 512MB 3038 */ 3039 WREG32(mmTPC6_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo); 3040 WREG32(mmTPC6_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi); 3041 WREG32(mmTPC6_RTR_HBW_RANGE_MASK_L_1, 0xE0000000); 3042 WREG32(mmTPC6_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF); 3043 3044 WREG32(mmTPC6_RTR_LBW_RANGE_BASE_0, lbw_rng0_base); 3045 WREG32(mmTPC6_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask); 3046 WREG32(mmTPC6_RTR_LBW_RANGE_BASE_1, lbw_rng1_base); 3047 WREG32(mmTPC6_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask); 3048 WREG32(mmTPC6_RTR_LBW_RANGE_BASE_2, lbw_rng2_base); 3049 WREG32(mmTPC6_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask); 3050 WREG32(mmTPC6_RTR_LBW_RANGE_BASE_3, lbw_rng3_base); 3051 WREG32(mmTPC6_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask); 3052 WREG32(mmTPC6_RTR_LBW_RANGE_BASE_4, lbw_rng4_base); 3053 WREG32(mmTPC6_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask); 3054 WREG32(mmTPC6_RTR_LBW_RANGE_BASE_5, lbw_rng5_base); 3055 WREG32(mmTPC6_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask); 3056 WREG32(mmTPC6_RTR_LBW_RANGE_BASE_6, lbw_rng6_base); 3057 WREG32(mmTPC6_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask); 3058 WREG32(mmTPC6_RTR_LBW_RANGE_BASE_7, lbw_rng7_base); 3059 WREG32(mmTPC6_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask); 3060 WREG32(mmTPC6_RTR_LBW_RANGE_BASE_8, lbw_rng8_base); 3061 WREG32(mmTPC6_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask); 3062 WREG32(mmTPC6_RTR_LBW_RANGE_BASE_9, lbw_rng9_base); 3063 WREG32(mmTPC6_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask); 3064 WREG32(mmTPC6_RTR_LBW_RANGE_BASE_10, lbw_rng10_base); 3065 WREG32(mmTPC6_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask); 3066 WREG32(mmTPC6_RTR_LBW_RANGE_BASE_11, lbw_rng11_base); 3067 WREG32(mmTPC6_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask); 3068 WREG32(mmTPC6_RTR_LBW_RANGE_BASE_12, lbw_rng12_base); 3069 WREG32(mmTPC6_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask); 3070 WREG32(mmTPC6_RTR_LBW_RANGE_BASE_13, lbw_rng13_base); 3071 WREG32(mmTPC6_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask); 3072 3073 WREG32(mmTPC7_NRTR_LBW_RANGE_HIT, 0xFFFF); 3074 WREG32(mmTPC7_NRTR_HBW_RANGE_HIT, 0xFE); 3075 3076 /* Protect HOST */ 3077 WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_L_0, 0); 3078 WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_H_0, 0); 3079 WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_L_0, 0); 3080 WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_H_0, 0xFFF80); 3081 3082 /* 3083 * Protect DDR @ 3084 * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END 3085 * The mask protects the first 512MB 3086 */ 3087 WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_L_1, dram_addr_lo); 3088 WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_H_1, dram_addr_hi); 3089 WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_L_1, 0xE0000000); 3090 WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_H_1, 0x3FFFF); 3091 3092 WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_0, lbw_rng0_base); 3093 WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_0, lbw_rng0_mask); 3094 WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_1, lbw_rng1_base); 3095 WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_1, lbw_rng1_mask); 3096 WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_2, lbw_rng2_base); 3097 WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_2, lbw_rng2_mask); 3098 WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_3, lbw_rng3_base); 3099 WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_3, lbw_rng3_mask); 3100 WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_4, lbw_rng4_base); 3101 WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_4, lbw_rng4_mask); 3102 WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_5, lbw_rng5_base); 3103 WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_5, lbw_rng5_mask); 3104 WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_6, lbw_rng6_base); 3105 WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_6, lbw_rng6_mask); 3106 WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_7, lbw_rng7_base); 3107 WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_7, lbw_rng7_mask); 3108 WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_8, lbw_rng8_base); 3109 WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_8, lbw_rng8_mask); 3110 WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_9, lbw_rng9_base); 3111 WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_9, lbw_rng9_mask); 3112 WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_10, lbw_rng10_base); 3113 WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_10, lbw_rng10_mask); 3114 WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_11, lbw_rng11_base); 3115 WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_11, lbw_rng11_mask); 3116 WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_12, lbw_rng12_base); 3117 WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_12, lbw_rng12_mask); 3118 WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_13, lbw_rng13_base); 3119 WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_13, lbw_rng13_mask); 3120 3121 goya_init_protection_bits(hdev); 3122} 3123 3124void goya_ack_protection_bits_errors(struct hl_device *hdev) 3125{ 3126 3127}
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