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gaudi_security.c
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linux-6.19.14/drivers/accel/habanalabs/gaudi/gaudi_security.c
1// SPDX-License-Identifier: GPL-2.0 2 3/* 4 * Copyright 2016-2018 HabanaLabs, Ltd. 5 * All Rights Reserved. 6 */ 7 8#include "gaudiP.h" 9#include "../include/gaudi/asic_reg/gaudi_regs.h" 10 11#define GAUDI_NUMBER_OF_LBW_RR_REGS 28 12#define GAUDI_NUMBER_OF_HBW_RR_REGS 24 13#define GAUDI_NUMBER_OF_LBW_RANGES 10 14 15static u64 gaudi_rr_lbw_hit_aw_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = { 16 mmDMA_IF_W_S_SOB_HIT_WPROT, 17 mmDMA_IF_W_S_DMA0_HIT_WPROT, 18 mmDMA_IF_W_S_DMA1_HIT_WPROT, 19 mmDMA_IF_E_S_SOB_HIT_WPROT, 20 mmDMA_IF_E_S_DMA0_HIT_WPROT, 21 mmDMA_IF_E_S_DMA1_HIT_WPROT, 22 mmDMA_IF_W_N_SOB_HIT_WPROT, 23 mmDMA_IF_W_N_DMA0_HIT_WPROT, 24 mmDMA_IF_W_N_DMA1_HIT_WPROT, 25 mmDMA_IF_E_N_SOB_HIT_WPROT, 26 mmDMA_IF_E_N_DMA0_HIT_WPROT, 27 mmDMA_IF_E_N_DMA1_HIT_WPROT, 28 mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AW, 29 mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AW, 30 mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AW, 31 mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AW, 32 mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AW, 33 mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AW, 34 mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AW, 35 mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AW, 36 mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AW, 37 mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AW, 38 mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AW, 39 mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AW, 40 mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AW, 41 mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AW, 42 mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AW, 43 mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AW, 44}; 45 46static u64 gaudi_rr_lbw_hit_ar_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = { 47 mmDMA_IF_W_S_SOB_HIT_RPROT, 48 mmDMA_IF_W_S_DMA0_HIT_RPROT, 49 mmDMA_IF_W_S_DMA1_HIT_RPROT, 50 mmDMA_IF_E_S_SOB_HIT_RPROT, 51 mmDMA_IF_E_S_DMA0_HIT_RPROT, 52 mmDMA_IF_E_S_DMA1_HIT_RPROT, 53 mmDMA_IF_W_N_SOB_HIT_RPROT, 54 mmDMA_IF_W_N_DMA0_HIT_RPROT, 55 mmDMA_IF_W_N_DMA1_HIT_RPROT, 56 mmDMA_IF_E_N_SOB_HIT_RPROT, 57 mmDMA_IF_E_N_DMA0_HIT_RPROT, 58 mmDMA_IF_E_N_DMA1_HIT_RPROT, 59 mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AR, 60 mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AR, 61 mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AR, 62 mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AR, 63 mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AR, 64 mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AR, 65 mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AR, 66 mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AR, 67 mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AR, 68 mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AR, 69 mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AR, 70 mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AR, 71 mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AR, 72 mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AR, 73 mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AR, 74 mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AR, 75}; 76 77static u64 gaudi_rr_lbw_min_aw_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = { 78 mmDMA_IF_W_S_SOB_MIN_WPROT_0, 79 mmDMA_IF_W_S_DMA0_MIN_WPROT_0, 80 mmDMA_IF_W_S_DMA1_MIN_WPROT_0, 81 mmDMA_IF_E_S_SOB_MIN_WPROT_0, 82 mmDMA_IF_E_S_DMA0_MIN_WPROT_0, 83 mmDMA_IF_E_S_DMA1_MIN_WPROT_0, 84 mmDMA_IF_W_N_SOB_MIN_WPROT_0, 85 mmDMA_IF_W_N_DMA0_MIN_WPROT_0, 86 mmDMA_IF_W_N_DMA1_MIN_WPROT_0, 87 mmDMA_IF_E_N_SOB_MIN_WPROT_0, 88 mmDMA_IF_E_N_DMA0_MIN_WPROT_0, 89 mmDMA_IF_E_N_DMA1_MIN_WPROT_0, 90 mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0, 91 mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0, 92 mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0, 93 mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0, 94 mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0, 95 mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0, 96 mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0, 97 mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0, 98 mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0, 99 mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0, 100 mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0, 101 mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0, 102 mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0, 103 mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0, 104 mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0, 105 mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0, 106}; 107 108static u64 gaudi_rr_lbw_max_aw_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = { 109 mmDMA_IF_W_S_SOB_MAX_WPROT_0, 110 mmDMA_IF_W_S_DMA0_MAX_WPROT_0, 111 mmDMA_IF_W_S_DMA1_MAX_WPROT_0, 112 mmDMA_IF_E_S_SOB_MAX_WPROT_0, 113 mmDMA_IF_E_S_DMA0_MAX_WPROT_0, 114 mmDMA_IF_E_S_DMA1_MAX_WPROT_0, 115 mmDMA_IF_W_N_SOB_MAX_WPROT_0, 116 mmDMA_IF_W_N_DMA0_MAX_WPROT_0, 117 mmDMA_IF_W_N_DMA1_MAX_WPROT_0, 118 mmDMA_IF_E_N_SOB_MAX_WPROT_0, 119 mmDMA_IF_E_N_DMA0_MAX_WPROT_0, 120 mmDMA_IF_E_N_DMA1_MAX_WPROT_0, 121 mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0, 122 mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0, 123 mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0, 124 mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0, 125 mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0, 126 mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0, 127 mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0, 128 mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0, 129 mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0, 130 mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0, 131 mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0, 132 mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0, 133 mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0, 134 mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0, 135 mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0, 136 mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0, 137}; 138 139static u64 gaudi_rr_lbw_min_ar_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = { 140 mmDMA_IF_W_S_SOB_MIN_RPROT_0, 141 mmDMA_IF_W_S_DMA0_MIN_RPROT_0, 142 mmDMA_IF_W_S_DMA1_MIN_RPROT_0, 143 mmDMA_IF_E_S_SOB_MIN_RPROT_0, 144 mmDMA_IF_E_S_DMA0_MIN_RPROT_0, 145 mmDMA_IF_E_S_DMA1_MIN_RPROT_0, 146 mmDMA_IF_W_N_SOB_MIN_RPROT_0, 147 mmDMA_IF_W_N_DMA0_MIN_RPROT_0, 148 mmDMA_IF_W_N_DMA1_MIN_RPROT_0, 149 mmDMA_IF_E_N_SOB_MIN_RPROT_0, 150 mmDMA_IF_E_N_DMA0_MIN_RPROT_0, 151 mmDMA_IF_E_N_DMA1_MIN_RPROT_0, 152 mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0, 153 mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0, 154 mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0, 155 mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0, 156 mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0, 157 mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0, 158 mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0, 159 mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0, 160 mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0, 161 mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0, 162 mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0, 163 mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0, 164 mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0, 165 mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0, 166 mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0, 167 mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0, 168}; 169 170static u64 gaudi_rr_lbw_max_ar_regs[GAUDI_NUMBER_OF_LBW_RR_REGS] = { 171 mmDMA_IF_W_S_SOB_MAX_RPROT_0, 172 mmDMA_IF_W_S_DMA0_MAX_RPROT_0, 173 mmDMA_IF_W_S_DMA1_MAX_RPROT_0, 174 mmDMA_IF_E_S_SOB_MAX_RPROT_0, 175 mmDMA_IF_E_S_DMA0_MAX_RPROT_0, 176 mmDMA_IF_E_S_DMA1_MAX_RPROT_0, 177 mmDMA_IF_W_N_SOB_MAX_RPROT_0, 178 mmDMA_IF_W_N_DMA0_MAX_RPROT_0, 179 mmDMA_IF_W_N_DMA1_MAX_RPROT_0, 180 mmDMA_IF_E_N_SOB_MAX_RPROT_0, 181 mmDMA_IF_E_N_DMA0_MAX_RPROT_0, 182 mmDMA_IF_E_N_DMA1_MAX_RPROT_0, 183 mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0, 184 mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0, 185 mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0, 186 mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0, 187 mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0, 188 mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0, 189 mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0, 190 mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0, 191 mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0, 192 mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0, 193 mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0, 194 mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0, 195 mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0, 196 mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0, 197 mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0, 198 mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0, 199}; 200 201static u64 gaudi_rr_hbw_hit_aw_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = { 202 mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AW, 203 mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AW, 204 mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AW, 205 mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AW, 206 mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AW, 207 mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AW, 208 mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AW, 209 mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AW, 210 mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AW, 211 mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AW, 212 mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AW, 213 mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AW, 214 mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AW, 215 mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AW, 216 mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AW, 217 mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AW, 218 mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AW, 219 mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AW, 220 mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AW, 221 mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AW, 222 mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AW, 223 mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AW, 224 mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AW, 225 mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AW 226}; 227 228static u64 gaudi_rr_hbw_hit_ar_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = { 229 mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AR, 230 mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AR, 231 mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AR, 232 mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AR, 233 mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AR, 234 mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AR, 235 mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AR, 236 mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AR, 237 mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AR, 238 mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AR, 239 mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AR, 240 mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AR, 241 mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AR, 242 mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AR, 243 mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AR, 244 mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AR, 245 mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AR, 246 mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AR, 247 mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AR, 248 mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AR, 249 mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AR, 250 mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AR, 251 mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AR, 252 mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AR 253}; 254 255static u64 gaudi_rr_hbw_base_low_aw_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = { 256 mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0, 257 mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0, 258 mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0, 259 mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0, 260 mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0, 261 mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0, 262 mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0, 263 mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0, 264 mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0, 265 mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0, 266 mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0, 267 mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0, 268 mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0, 269 mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0, 270 mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0, 271 mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0, 272 mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0, 273 mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0, 274 mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0, 275 mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0, 276 mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0, 277 mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0, 278 mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0, 279 mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0 280}; 281 282static u64 gaudi_rr_hbw_base_high_aw_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = { 283 mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0, 284 mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0, 285 mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0, 286 mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0, 287 mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0, 288 mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0, 289 mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0, 290 mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0, 291 mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0, 292 mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0, 293 mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0, 294 mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0, 295 mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0, 296 mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0, 297 mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0, 298 mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0, 299 mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0, 300 mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0, 301 mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0, 302 mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0, 303 mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0, 304 mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0, 305 mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0, 306 mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0 307}; 308 309static u64 gaudi_rr_hbw_mask_low_aw_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = { 310 mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0, 311 mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0, 312 mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0, 313 mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0, 314 mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0, 315 mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0, 316 mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0, 317 mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0, 318 mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0, 319 mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0, 320 mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0, 321 mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0, 322 mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0, 323 mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0, 324 mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0, 325 mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0, 326 mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0, 327 mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0, 328 mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0, 329 mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0, 330 mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0, 331 mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0, 332 mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0, 333 mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0 334}; 335 336static u64 gaudi_rr_hbw_mask_high_aw_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = { 337 mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0, 338 mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0, 339 mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0, 340 mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0, 341 mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0, 342 mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0, 343 mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0, 344 mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0, 345 mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0, 346 mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0, 347 mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0, 348 mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0, 349 mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0, 350 mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0, 351 mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0, 352 mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0, 353 mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0, 354 mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0, 355 mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0, 356 mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0, 357 mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0, 358 mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0, 359 mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0, 360 mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0 361}; 362 363static u64 gaudi_rr_hbw_base_low_ar_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = { 364 mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0, 365 mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0, 366 mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0, 367 mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0, 368 mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0, 369 mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0, 370 mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0, 371 mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0, 372 mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0, 373 mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0, 374 mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0, 375 mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0, 376 mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0, 377 mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0, 378 mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0, 379 mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0, 380 mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0, 381 mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0, 382 mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0, 383 mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0, 384 mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0, 385 mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0, 386 mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0, 387 mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0 388}; 389 390static u64 gaudi_rr_hbw_base_high_ar_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = { 391 mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0, 392 mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0, 393 mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0, 394 mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0, 395 mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0, 396 mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0, 397 mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0, 398 mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0, 399 mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0, 400 mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0, 401 mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0, 402 mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0, 403 mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0, 404 mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0, 405 mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0, 406 mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0, 407 mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0, 408 mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0, 409 mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0, 410 mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0, 411 mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0, 412 mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0, 413 mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0, 414 mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0 415}; 416 417static u64 gaudi_rr_hbw_mask_low_ar_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = { 418 mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0, 419 mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0, 420 mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0, 421 mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0, 422 mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0, 423 mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0, 424 mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0, 425 mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0, 426 mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0, 427 mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0, 428 mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0, 429 mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0, 430 mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0, 431 mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0, 432 mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0, 433 mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0, 434 mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0, 435 mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0, 436 mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0, 437 mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0, 438 mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0, 439 mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0, 440 mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0, 441 mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0 442}; 443 444static u64 gaudi_rr_hbw_mask_high_ar_regs[GAUDI_NUMBER_OF_HBW_RR_REGS] = { 445 mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0, 446 mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0, 447 mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0, 448 mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0, 449 mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0, 450 mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0, 451 mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0, 452 mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0, 453 mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0, 454 mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0, 455 mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0, 456 mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0, 457 mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0, 458 mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0, 459 mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0, 460 mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0, 461 mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0, 462 mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0, 463 mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0, 464 mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0, 465 mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0, 466 mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0, 467 mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0, 468 mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0 469}; 470 471/** 472 * gaudi_pb_set_block - set the given block as protected 473 * 474 * @hdev: pointer to hl_device structure 475 * @base: block base address 476 */ 477static void gaudi_pb_set_block(struct hl_device *hdev, u64 base) 478{ 479 u32 pb_addr = base - CFG_BASE + PROT_BITS_OFFS; 480 481 while (pb_addr & 0xFFF) { 482 WREG32(pb_addr, 0); 483 pb_addr += 4; 484 } 485} 486 487static void gaudi_init_mme_protection_bits(struct hl_device *hdev) 488{ 489 u32 pb_addr, mask; 490 u8 word_offset; 491 492 gaudi_pb_set_block(hdev, mmMME0_ACC_BASE); 493 gaudi_pb_set_block(hdev, mmMME0_SBAB_BASE); 494 gaudi_pb_set_block(hdev, mmMME0_PRTN_BASE); 495 gaudi_pb_set_block(hdev, mmMME1_ACC_BASE); 496 gaudi_pb_set_block(hdev, mmMME1_SBAB_BASE); 497 gaudi_pb_set_block(hdev, mmMME1_PRTN_BASE); 498 gaudi_pb_set_block(hdev, mmMME2_ACC_BASE); 499 gaudi_pb_set_block(hdev, mmMME2_SBAB_BASE); 500 gaudi_pb_set_block(hdev, mmMME2_PRTN_BASE); 501 gaudi_pb_set_block(hdev, mmMME3_ACC_BASE); 502 gaudi_pb_set_block(hdev, mmMME3_SBAB_BASE); 503 gaudi_pb_set_block(hdev, mmMME3_PRTN_BASE); 504 505 WREG32(mmMME0_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 506 WREG32(mmMME1_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 507 WREG32(mmMME2_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 508 WREG32(mmMME3_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 509 510 WREG32(mmMME0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 511 WREG32(mmMME2_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 512 513 pb_addr = (mmMME0_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; 514 word_offset = ((mmMME0_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; 515 mask = 1U << ((mmMME0_CTRL_RESET & 0x7F) >> 2); 516 mask |= 1U << ((mmMME0_CTRL_QM_STALL & 0x7F) >> 2); 517 mask |= 1U << ((mmMME0_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); 518 mask |= 1U << ((mmMME0_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); 519 mask |= 1U << ((mmMME0_CTRL_INTR_CAUSE & 0x7F) >> 2); 520 mask |= 1U << ((mmMME0_CTRL_INTR_MASK & 0x7F) >> 2); 521 mask |= 1U << ((mmMME0_CTRL_LOG_SHADOW & 0x7F) >> 2); 522 mask |= 1U << ((mmMME0_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); 523 mask |= 1U << ((mmMME0_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); 524 mask |= 1U << ((mmMME0_CTRL_PCU_RL_TH & 0x7F) >> 2); 525 mask |= 1U << ((mmMME0_CTRL_PCU_RL_MIN & 0x7F) >> 2); 526 mask |= 1U << ((mmMME0_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); 527 mask |= 1U << ((mmMME0_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); 528 mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); 529 mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); 530 mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); 531 mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); 532 mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); 533 mask |= 1U << ((mmMME0_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); 534 mask |= 1U << ((mmMME0_CTRL_PROT & 0x7F) >> 2); 535 mask |= 1U << ((mmMME0_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); 536 mask |= 1U << ((mmMME0_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); 537 mask |= 1U << ((mmMME0_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); 538 mask |= 1U << ((mmMME0_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); 539 mask |= 1U << ((mmMME0_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); 540 mask |= 1U << ((mmMME0_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); 541 mask |= 1U << ((mmMME0_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); 542 mask |= 1U << ((mmMME0_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); 543 mask |= 1U << ((mmMME0_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); 544 mask |= 1U << ((mmMME0_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); 545 546 WREG32(pb_addr + word_offset, ~mask); 547 548 pb_addr = (mmMME0_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS; 549 word_offset = ((mmMME0_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7) 550 << 2; 551 mask = 1U << ((mmMME0_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); 552 553 WREG32(pb_addr + word_offset, ~mask); 554 555 pb_addr = (mmMME0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 556 word_offset = ((mmMME0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 557 mask = 1U << ((mmMME0_QM_GLBL_CFG0 & 0x7F) >> 2); 558 mask |= 1U << ((mmMME0_QM_GLBL_CFG1 & 0x7F) >> 2); 559 mask |= 1U << ((mmMME0_QM_GLBL_PROT & 0x7F) >> 2); 560 mask |= 1U << ((mmMME0_QM_GLBL_ERR_CFG & 0x7F) >> 2); 561 mask |= 1U << ((mmMME0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 562 mask |= 1U << ((mmMME0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 563 mask |= 1U << ((mmMME0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 564 mask |= 1U << ((mmMME0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 565 mask |= 1U << ((mmMME0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 566 mask |= 1U << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 567 mask |= 1U << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 568 mask |= 1U << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 569 mask |= 1U << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 570 mask |= 1U << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 571 mask |= 1U << ((mmMME0_QM_GLBL_STS0 & 0x7F) >> 2); 572 mask |= 1U << ((mmMME0_QM_GLBL_STS1_0 & 0x7F) >> 2); 573 mask |= 1U << ((mmMME0_QM_GLBL_STS1_1 & 0x7F) >> 2); 574 mask |= 1U << ((mmMME0_QM_GLBL_STS1_2 & 0x7F) >> 2); 575 mask |= 1U << ((mmMME0_QM_GLBL_STS1_3 & 0x7F) >> 2); 576 mask |= 1U << ((mmMME0_QM_GLBL_STS1_4 & 0x7F) >> 2); 577 mask |= 1U << ((mmMME0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 578 mask |= 1U << ((mmMME0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 579 mask |= 1U << ((mmMME0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 580 mask |= 1U << ((mmMME0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 581 mask |= 1U << ((mmMME0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 582 mask |= 1U << ((mmMME0_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 583 mask |= 1U << ((mmMME0_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 584 mask |= 1U << ((mmMME0_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 585 mask |= 1U << ((mmMME0_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 586 587 WREG32(pb_addr + word_offset, ~mask); 588 589 pb_addr = (mmMME0_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 590 word_offset = ((mmMME0_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 591 mask = 1U << ((mmMME0_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 592 mask |= 1U << ((mmMME0_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 593 mask |= 1U << ((mmMME0_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 594 mask |= 1U << ((mmMME0_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 595 mask |= 1U << ((mmMME0_QM_PQ_SIZE_0 & 0x7F) >> 2); 596 mask |= 1U << ((mmMME0_QM_PQ_SIZE_1 & 0x7F) >> 2); 597 mask |= 1U << ((mmMME0_QM_PQ_SIZE_2 & 0x7F) >> 2); 598 mask |= 1U << ((mmMME0_QM_PQ_SIZE_3 & 0x7F) >> 2); 599 mask |= 1U << ((mmMME0_QM_PQ_PI_0 & 0x7F) >> 2); 600 mask |= 1U << ((mmMME0_QM_PQ_PI_1 & 0x7F) >> 2); 601 mask |= 1U << ((mmMME0_QM_PQ_PI_2 & 0x7F) >> 2); 602 mask |= 1U << ((mmMME0_QM_PQ_PI_3 & 0x7F) >> 2); 603 mask |= 1U << ((mmMME0_QM_PQ_CI_0 & 0x7F) >> 2); 604 mask |= 1U << ((mmMME0_QM_PQ_CI_1 & 0x7F) >> 2); 605 mask |= 1U << ((mmMME0_QM_PQ_CI_2 & 0x7F) >> 2); 606 mask |= 1U << ((mmMME0_QM_PQ_CI_3 & 0x7F) >> 2); 607 mask |= 1U << ((mmMME0_QM_PQ_CFG0_0 & 0x7F) >> 2); 608 mask |= 1U << ((mmMME0_QM_PQ_CFG0_1 & 0x7F) >> 2); 609 mask |= 1U << ((mmMME0_QM_PQ_CFG0_2 & 0x7F) >> 2); 610 mask |= 1U << ((mmMME0_QM_PQ_CFG0_3 & 0x7F) >> 2); 611 mask |= 1U << ((mmMME0_QM_PQ_CFG1_0 & 0x7F) >> 2); 612 mask |= 1U << ((mmMME0_QM_PQ_CFG1_1 & 0x7F) >> 2); 613 mask |= 1U << ((mmMME0_QM_PQ_CFG1_2 & 0x7F) >> 2); 614 mask |= 1U << ((mmMME0_QM_PQ_CFG1_3 & 0x7F) >> 2); 615 mask |= 1U << ((mmMME0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 616 mask |= 1U << ((mmMME0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 617 mask |= 1U << ((mmMME0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 618 mask |= 1U << ((mmMME0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 619 mask |= 1U << ((mmMME0_QM_PQ_STS0_0 & 0x7F) >> 2); 620 mask |= 1U << ((mmMME0_QM_PQ_STS0_1 & 0x7F) >> 2); 621 mask |= 1U << ((mmMME0_QM_PQ_STS0_2 & 0x7F) >> 2); 622 mask |= 1U << ((mmMME0_QM_PQ_STS0_3 & 0x7F) >> 2); 623 624 WREG32(pb_addr + word_offset, ~mask); 625 626 pb_addr = (mmMME0_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 627 word_offset = ((mmMME0_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 628 mask = 1U << ((mmMME0_QM_PQ_STS1_0 & 0x7F) >> 2); 629 mask |= 1U << ((mmMME0_QM_PQ_STS1_1 & 0x7F) >> 2); 630 mask |= 1U << ((mmMME0_QM_PQ_STS1_2 & 0x7F) >> 2); 631 mask |= 1U << ((mmMME0_QM_PQ_STS1_3 & 0x7F) >> 2); 632 mask |= 1U << ((mmMME0_QM_CQ_STS0_0 & 0x7F) >> 2); 633 mask |= 1U << ((mmMME0_QM_CQ_STS0_1 & 0x7F) >> 2); 634 mask |= 1U << ((mmMME0_QM_CQ_STS0_2 & 0x7F) >> 2); 635 mask |= 1U << ((mmMME0_QM_CQ_STS0_3 & 0x7F) >> 2); 636 mask |= 1U << ((mmMME0_QM_CQ_STS1_0 & 0x7F) >> 2); 637 mask |= 1U << ((mmMME0_QM_CQ_STS1_1 & 0x7F) >> 2); 638 mask |= 1U << ((mmMME0_QM_CQ_STS1_2 & 0x7F) >> 2); 639 mask |= 1U << ((mmMME0_QM_CQ_STS1_3 & 0x7F) >> 2); 640 mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 641 mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 642 mask |= 1U << ((mmMME0_QM_CQ_TSIZE_0 & 0x7F) >> 2); 643 644 WREG32(pb_addr + word_offset, ~mask); 645 646 pb_addr = (mmMME0_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 647 word_offset = ((mmMME0_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 648 mask = 1U << ((mmMME0_QM_CQ_CTL_0 & 0x7F) >> 2); 649 mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 650 mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 651 mask |= 1U << ((mmMME0_QM_CQ_TSIZE_1 & 0x7F) >> 2); 652 mask |= 1U << ((mmMME0_QM_CQ_CTL_1 & 0x7F) >> 2); 653 mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 654 mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 655 mask |= 1U << ((mmMME0_QM_CQ_TSIZE_2 & 0x7F) >> 2); 656 mask |= 1U << ((mmMME0_QM_CQ_CTL_2 & 0x7F) >> 2); 657 mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 658 mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 659 mask |= 1U << ((mmMME0_QM_CQ_TSIZE_3 & 0x7F) >> 2); 660 mask |= 1U << ((mmMME0_QM_CQ_CTL_3 & 0x7F) >> 2); 661 mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 662 mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 663 mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 664 mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 665 mask |= 1U << ((mmMME0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 666 mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 667 mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 668 mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 669 mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 670 mask |= 1U << ((mmMME0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 671 mask |= 1U << ((mmMME0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 672 mask |= 1U << ((mmMME0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 673 mask |= 1U << ((mmMME0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 674 mask |= 1U << ((mmMME0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 675 mask |= 1U << ((mmMME0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 676 677 WREG32(pb_addr + word_offset, ~mask); 678 679 pb_addr = (mmMME0_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 680 word_offset = ((mmMME0_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 681 mask = 1U << ((mmMME0_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 682 mask |= 1U << ((mmMME0_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 683 mask |= 1U << ((mmMME0_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 684 mask |= 1U << ((mmMME0_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 685 mask |= 1U << ((mmMME0_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 686 mask |= 1U << ((mmMME0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 687 mask |= 1U << ((mmMME0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 688 mask |= 1U << ((mmMME0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 689 mask |= 1U << ((mmMME0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 690 mask |= 1U << ((mmMME0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 691 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 692 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 693 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 694 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 695 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 696 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 697 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 698 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 699 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 700 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 701 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 702 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 703 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 704 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 705 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 706 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 707 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 708 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 709 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 710 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 711 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 712 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 713 714 WREG32(pb_addr + word_offset, ~mask); 715 716 pb_addr = (mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 717 word_offset = ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 718 << 2; 719 mask = 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 720 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 721 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 722 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 723 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 724 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 725 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 726 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 727 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 728 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 729 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 730 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 731 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 732 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 733 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 734 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 735 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 736 mask |= 1U << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 737 mask |= 1U << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 738 mask |= 1U << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 739 mask |= 1U << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 740 mask |= 1U << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 741 mask |= 1U << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 742 mask |= 1U << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 743 mask |= 1U << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 744 mask |= 1U << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 745 mask |= 1U << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 746 mask |= 1U << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 747 mask |= 1U << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 748 mask |= 1U << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 749 mask |= 1U << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 750 751 WREG32(pb_addr + word_offset, ~mask); 752 753 pb_addr = (mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 754 PROT_BITS_OFFS; 755 word_offset = ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 756 PROT_BITS_OFFS) >> 7) << 2; 757 mask = 1U << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 758 mask |= 1U << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 759 760 WREG32(pb_addr + word_offset, ~mask); 761 762 pb_addr = (mmMME0_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 763 word_offset = ((mmMME0_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 764 mask = 1U << ((mmMME0_QM_CP_STS_0 & 0x7F) >> 2); 765 mask |= 1U << ((mmMME0_QM_CP_STS_1 & 0x7F) >> 2); 766 mask |= 1U << ((mmMME0_QM_CP_STS_2 & 0x7F) >> 2); 767 mask |= 1U << ((mmMME0_QM_CP_STS_3 & 0x7F) >> 2); 768 mask |= 1U << ((mmMME0_QM_CP_STS_4 & 0x7F) >> 2); 769 mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 770 mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 771 mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 772 mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 773 mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 774 mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 775 mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 776 mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 777 mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 778 mask |= 1U << ((mmMME0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 779 mask |= 1U << ((mmMME0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 780 mask |= 1U << ((mmMME0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 781 mask |= 1U << ((mmMME0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 782 783 WREG32(pb_addr + word_offset, ~mask); 784 785 pb_addr = (mmMME0_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 786 word_offset = ((mmMME0_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 787 mask = 1U << ((mmMME0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 788 mask |= 1U << ((mmMME0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 789 mask |= 1U << ((mmMME0_QM_CP_DBG_0_0 & 0x7F) >> 2); 790 mask |= 1U << ((mmMME0_QM_CP_DBG_0_1 & 0x7F) >> 2); 791 792 WREG32(pb_addr + word_offset, ~mask); 793 794 pb_addr = (mmMME0_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 795 word_offset = ((mmMME0_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 796 mask = 1U << ((mmMME0_QM_CP_DBG_0_2 & 0x7F) >> 2); 797 mask |= 1U << ((mmMME0_QM_CP_DBG_0_3 & 0x7F) >> 2); 798 mask |= 1U << ((mmMME0_QM_CP_DBG_0_4 & 0x7F) >> 2); 799 mask |= 1U << ((mmMME0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 800 mask |= 1U << ((mmMME0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 801 mask |= 1U << ((mmMME0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 802 mask |= 1U << ((mmMME0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 803 mask |= 1U << ((mmMME0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 804 mask |= 1U << ((mmMME0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 805 mask |= 1U << ((mmMME0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 806 mask |= 1U << ((mmMME0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 807 mask |= 1U << ((mmMME0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 808 mask |= 1U << ((mmMME0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 809 810 WREG32(pb_addr + word_offset, ~mask); 811 812 pb_addr = (mmMME0_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 813 word_offset = ((mmMME0_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 814 mask = 1U << ((mmMME0_QM_ARB_CFG_1 & 0x7F) >> 2); 815 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 816 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 817 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 818 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 819 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 820 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 821 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 822 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 823 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 824 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 825 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 826 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 827 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 828 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 829 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 830 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 831 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 832 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 833 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 834 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 835 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 836 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 837 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 838 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 839 840 WREG32(pb_addr + word_offset, ~mask); 841 842 pb_addr = (mmMME0_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 843 word_offset = ((mmMME0_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 844 << 2; 845 mask = 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 846 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 847 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 848 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 849 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 850 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 851 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 852 mask |= 1U << ((mmMME0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 853 WREG32(pb_addr + word_offset, ~mask); 854 855 pb_addr = (mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 856 PROT_BITS_OFFS; 857 word_offset = ((mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & 858 PROT_BITS_OFFS) >> 7) << 2; 859 mask = 1U << ((mmMME0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 860 mask |= 1U << ((mmMME0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 861 mask |= 1U << ((mmMME0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 862 mask |= 1U << ((mmMME0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 863 mask |= 1U << ((mmMME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 864 865 WREG32(pb_addr + word_offset, ~mask); 866 867 pb_addr = (mmMME0_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 868 word_offset = ((mmMME0_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 869 mask = 1U << ((mmMME0_QM_ARB_STATE_STS & 0x7F) >> 2); 870 mask |= 1U << ((mmMME0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 871 mask |= 1U << ((mmMME0_QM_ARB_MSG_STS & 0x7F) >> 2); 872 mask |= 1U << ((mmMME0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 873 mask |= 1U << ((mmMME0_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 874 mask |= 1U << ((mmMME0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 875 mask |= 1U << ((mmMME0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 876 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 877 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 878 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 879 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 880 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 881 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 882 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 883 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 884 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 885 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 886 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 887 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 888 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 889 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 890 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 891 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 892 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 893 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 894 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 895 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 896 897 WREG32(pb_addr + word_offset, ~mask); 898 899 pb_addr = (mmMME0_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 900 word_offset = ((mmMME0_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 901 << 2; 902 mask = 1U << ((mmMME0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 903 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 904 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 905 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 906 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 907 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 908 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 909 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 910 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 911 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 912 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 913 mask |= 1U << ((mmMME0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 914 mask |= 1U << ((mmMME0_QM_CGM_CFG & 0x7F) >> 2); 915 mask |= 1U << ((mmMME0_QM_CGM_STS & 0x7F) >> 2); 916 mask |= 1U << ((mmMME0_QM_CGM_CFG1 & 0x7F) >> 2); 917 918 WREG32(pb_addr + word_offset, ~mask); 919 920 pb_addr = (mmMME0_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 921 word_offset = ((mmMME0_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 922 mask = 1U << ((mmMME0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 923 mask |= 1U << ((mmMME0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 924 mask |= 1U << ((mmMME0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 925 mask |= 1U << ((mmMME0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 926 mask |= 1U << ((mmMME0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 927 mask |= 1U << ((mmMME0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 928 mask |= 1U << ((mmMME0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 929 mask |= 1U << ((mmMME0_QM_GLBL_AXCACHE & 0x7F) >> 2); 930 mask |= 1U << ((mmMME0_QM_IND_GW_APB_CFG & 0x7F) >> 2); 931 mask |= 1U << ((mmMME0_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 932 mask |= 1U << ((mmMME0_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 933 mask |= 1U << ((mmMME0_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 934 mask |= 1U << ((mmMME0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 935 mask |= 1U << ((mmMME0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 936 mask |= 1U << ((mmMME0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 937 938 WREG32(pb_addr + word_offset, ~mask); 939 940 pb_addr = (mmMME0_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 941 word_offset = ((mmMME0_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 942 << 2; 943 mask = 1U << ((mmMME0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 944 945 WREG32(pb_addr + word_offset, ~mask); 946 947 pb_addr = (mmMME1_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; 948 word_offset = ((mmMME1_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; 949 mask = 1U << ((mmMME1_CTRL_RESET & 0x7F) >> 2); 950 mask |= 1U << ((mmMME1_CTRL_QM_STALL & 0x7F) >> 2); 951 mask |= 1U << ((mmMME1_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); 952 mask |= 1U << ((mmMME1_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); 953 mask |= 1U << ((mmMME1_CTRL_INTR_CAUSE & 0x7F) >> 2); 954 mask |= 1U << ((mmMME1_CTRL_INTR_MASK & 0x7F) >> 2); 955 mask |= 1U << ((mmMME1_CTRL_LOG_SHADOW & 0x7F) >> 2); 956 mask |= 1U << ((mmMME1_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); 957 mask |= 1U << ((mmMME1_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); 958 mask |= 1U << ((mmMME1_CTRL_PCU_RL_TH & 0x7F) >> 2); 959 mask |= 1U << ((mmMME1_CTRL_PCU_RL_MIN & 0x7F) >> 2); 960 mask |= 1U << ((mmMME1_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); 961 mask |= 1U << ((mmMME1_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); 962 mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); 963 mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); 964 mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); 965 mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); 966 mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); 967 mask |= 1U << ((mmMME1_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); 968 mask |= 1U << ((mmMME1_CTRL_PROT & 0x7F) >> 2); 969 mask |= 1U << ((mmMME1_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); 970 mask |= 1U << ((mmMME1_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); 971 mask |= 1U << ((mmMME1_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); 972 mask |= 1U << ((mmMME1_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); 973 mask |= 1U << ((mmMME1_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); 974 mask |= 1U << ((mmMME1_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); 975 mask |= 1U << ((mmMME1_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); 976 mask |= 1U << ((mmMME1_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); 977 mask |= 1U << ((mmMME1_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); 978 mask |= 1U << ((mmMME1_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); 979 980 WREG32(pb_addr + word_offset, ~mask); 981 982 pb_addr = (mmMME1_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS; 983 word_offset = ((mmMME1_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7) 984 << 2; 985 mask = 1U << ((mmMME1_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); 986 987 WREG32(pb_addr + word_offset, ~mask); 988 989 /* MME 1 is slave, hence its whole QM block is protected (with RR) */ 990 991 pb_addr = (mmMME2_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; 992 word_offset = ((mmMME2_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; 993 mask = 1U << ((mmMME2_CTRL_RESET & 0x7F) >> 2); 994 mask |= 1U << ((mmMME2_CTRL_QM_STALL & 0x7F) >> 2); 995 mask |= 1U << ((mmMME2_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); 996 mask |= 1U << ((mmMME2_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); 997 mask |= 1U << ((mmMME2_CTRL_INTR_CAUSE & 0x7F) >> 2); 998 mask |= 1U << ((mmMME2_CTRL_INTR_MASK & 0x7F) >> 2); 999 mask |= 1U << ((mmMME2_CTRL_LOG_SHADOW & 0x7F) >> 2); 1000 mask |= 1U << ((mmMME2_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); 1001 mask |= 1U << ((mmMME2_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); 1002 mask |= 1U << ((mmMME2_CTRL_PCU_RL_TH & 0x7F) >> 2); 1003 mask |= 1U << ((mmMME2_CTRL_PCU_RL_MIN & 0x7F) >> 2); 1004 mask |= 1U << ((mmMME2_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); 1005 mask |= 1U << ((mmMME2_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); 1006 mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); 1007 mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); 1008 mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); 1009 mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); 1010 mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); 1011 mask |= 1U << ((mmMME2_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); 1012 mask |= 1U << ((mmMME2_CTRL_PROT & 0x7F) >> 2); 1013 mask |= 1U << ((mmMME2_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); 1014 mask |= 1U << ((mmMME2_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); 1015 mask |= 1U << ((mmMME2_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); 1016 mask |= 1U << ((mmMME2_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); 1017 mask |= 1U << ((mmMME2_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); 1018 mask |= 1U << ((mmMME2_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); 1019 mask |= 1U << ((mmMME2_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); 1020 mask |= 1U << ((mmMME2_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); 1021 mask |= 1U << ((mmMME2_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); 1022 mask |= 1U << ((mmMME2_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); 1023 1024 WREG32(pb_addr + word_offset, ~mask); 1025 1026 pb_addr = (mmMME2_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS; 1027 word_offset = ((mmMME2_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7) 1028 << 2; 1029 mask = 1U << ((mmMME2_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); 1030 1031 WREG32(pb_addr + word_offset, ~mask); 1032 1033 pb_addr = (mmMME2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1034 word_offset = ((mmMME2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1035 mask = 1U << ((mmMME2_QM_GLBL_CFG0 & 0x7F) >> 2); 1036 mask |= 1U << ((mmMME2_QM_GLBL_CFG1 & 0x7F) >> 2); 1037 mask |= 1U << ((mmMME2_QM_GLBL_PROT & 0x7F) >> 2); 1038 mask |= 1U << ((mmMME2_QM_GLBL_ERR_CFG & 0x7F) >> 2); 1039 mask |= 1U << ((mmMME2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 1040 mask |= 1U << ((mmMME2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 1041 mask |= 1U << ((mmMME2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 1042 mask |= 1U << ((mmMME2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 1043 mask |= 1U << ((mmMME2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 1044 mask |= 1U << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 1045 mask |= 1U << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 1046 mask |= 1U << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 1047 mask |= 1U << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 1048 mask |= 1U << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 1049 mask |= 1U << ((mmMME2_QM_GLBL_STS0 & 0x7F) >> 2); 1050 mask |= 1U << ((mmMME2_QM_GLBL_STS1_0 & 0x7F) >> 2); 1051 mask |= 1U << ((mmMME2_QM_GLBL_STS1_1 & 0x7F) >> 2); 1052 mask |= 1U << ((mmMME2_QM_GLBL_STS1_2 & 0x7F) >> 2); 1053 mask |= 1U << ((mmMME2_QM_GLBL_STS1_3 & 0x7F) >> 2); 1054 mask |= 1U << ((mmMME2_QM_GLBL_STS1_4 & 0x7F) >> 2); 1055 mask |= 1U << ((mmMME2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 1056 mask |= 1U << ((mmMME2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 1057 mask |= 1U << ((mmMME2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 1058 mask |= 1U << ((mmMME2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 1059 mask |= 1U << ((mmMME2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 1060 mask |= 1U << ((mmMME2_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 1061 mask |= 1U << ((mmMME2_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 1062 mask |= 1U << ((mmMME2_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 1063 mask |= 1U << ((mmMME2_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 1064 1065 WREG32(pb_addr + word_offset, ~mask); 1066 1067 pb_addr = (mmMME2_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 1068 word_offset = ((mmMME2_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 1069 mask = 1U << ((mmMME2_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 1070 mask |= 1U << ((mmMME2_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 1071 mask |= 1U << ((mmMME2_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 1072 mask |= 1U << ((mmMME2_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 1073 mask |= 1U << ((mmMME2_QM_PQ_SIZE_0 & 0x7F) >> 2); 1074 mask |= 1U << ((mmMME2_QM_PQ_SIZE_1 & 0x7F) >> 2); 1075 mask |= 1U << ((mmMME2_QM_PQ_SIZE_2 & 0x7F) >> 2); 1076 mask |= 1U << ((mmMME2_QM_PQ_SIZE_3 & 0x7F) >> 2); 1077 mask |= 1U << ((mmMME2_QM_PQ_PI_0 & 0x7F) >> 2); 1078 mask |= 1U << ((mmMME2_QM_PQ_PI_1 & 0x7F) >> 2); 1079 mask |= 1U << ((mmMME2_QM_PQ_PI_2 & 0x7F) >> 2); 1080 mask |= 1U << ((mmMME2_QM_PQ_PI_3 & 0x7F) >> 2); 1081 mask |= 1U << ((mmMME2_QM_PQ_CI_0 & 0x7F) >> 2); 1082 mask |= 1U << ((mmMME2_QM_PQ_CI_1 & 0x7F) >> 2); 1083 mask |= 1U << ((mmMME2_QM_PQ_CI_2 & 0x7F) >> 2); 1084 mask |= 1U << ((mmMME2_QM_PQ_CI_3 & 0x7F) >> 2); 1085 mask |= 1U << ((mmMME2_QM_PQ_CFG0_0 & 0x7F) >> 2); 1086 mask |= 1U << ((mmMME2_QM_PQ_CFG0_1 & 0x7F) >> 2); 1087 mask |= 1U << ((mmMME2_QM_PQ_CFG0_2 & 0x7F) >> 2); 1088 mask |= 1U << ((mmMME2_QM_PQ_CFG0_3 & 0x7F) >> 2); 1089 mask |= 1U << ((mmMME2_QM_PQ_CFG1_0 & 0x7F) >> 2); 1090 mask |= 1U << ((mmMME2_QM_PQ_CFG1_1 & 0x7F) >> 2); 1091 mask |= 1U << ((mmMME2_QM_PQ_CFG1_2 & 0x7F) >> 2); 1092 mask |= 1U << ((mmMME2_QM_PQ_CFG1_3 & 0x7F) >> 2); 1093 mask |= 1U << ((mmMME2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 1094 mask |= 1U << ((mmMME2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 1095 mask |= 1U << ((mmMME2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 1096 mask |= 1U << ((mmMME2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 1097 mask |= 1U << ((mmMME2_QM_PQ_STS0_0 & 0x7F) >> 2); 1098 mask |= 1U << ((mmMME2_QM_PQ_STS0_1 & 0x7F) >> 2); 1099 mask |= 1U << ((mmMME2_QM_PQ_STS0_2 & 0x7F) >> 2); 1100 mask |= 1U << ((mmMME2_QM_PQ_STS0_3 & 0x7F) >> 2); 1101 1102 WREG32(pb_addr + word_offset, ~mask); 1103 1104 pb_addr = (mmMME2_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 1105 word_offset = ((mmMME2_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 1106 mask = 1U << ((mmMME2_QM_PQ_STS1_0 & 0x7F) >> 2); 1107 mask |= 1U << ((mmMME2_QM_PQ_STS1_1 & 0x7F) >> 2); 1108 mask |= 1U << ((mmMME2_QM_PQ_STS1_2 & 0x7F) >> 2); 1109 mask |= 1U << ((mmMME2_QM_PQ_STS1_3 & 0x7F) >> 2); 1110 mask |= 1U << ((mmMME2_QM_CQ_STS0_0 & 0x7F) >> 2); 1111 mask |= 1U << ((mmMME2_QM_CQ_STS0_1 & 0x7F) >> 2); 1112 mask |= 1U << ((mmMME2_QM_CQ_STS0_2 & 0x7F) >> 2); 1113 mask |= 1U << ((mmMME2_QM_CQ_STS0_3 & 0x7F) >> 2); 1114 mask |= 1U << ((mmMME2_QM_CQ_STS1_0 & 0x7F) >> 2); 1115 mask |= 1U << ((mmMME2_QM_CQ_STS1_1 & 0x7F) >> 2); 1116 mask |= 1U << ((mmMME2_QM_CQ_STS1_2 & 0x7F) >> 2); 1117 mask |= 1U << ((mmMME2_QM_CQ_STS1_3 & 0x7F) >> 2); 1118 mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 1119 mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 1120 mask |= 1U << ((mmMME2_QM_CQ_TSIZE_0 & 0x7F) >> 2); 1121 1122 WREG32(pb_addr + word_offset, ~mask); 1123 1124 pb_addr = (mmMME2_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 1125 word_offset = ((mmMME2_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 1126 mask = 1U << ((mmMME2_QM_CQ_CTL_0 & 0x7F) >> 2); 1127 mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 1128 mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 1129 mask |= 1U << ((mmMME2_QM_CQ_TSIZE_1 & 0x7F) >> 2); 1130 mask |= 1U << ((mmMME2_QM_CQ_CTL_1 & 0x7F) >> 2); 1131 mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 1132 mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 1133 mask |= 1U << ((mmMME2_QM_CQ_TSIZE_2 & 0x7F) >> 2); 1134 mask |= 1U << ((mmMME2_QM_CQ_CTL_2 & 0x7F) >> 2); 1135 mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 1136 mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 1137 mask |= 1U << ((mmMME2_QM_CQ_TSIZE_3 & 0x7F) >> 2); 1138 mask |= 1U << ((mmMME2_QM_CQ_CTL_3 & 0x7F) >> 2); 1139 mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 1140 mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 1141 mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 1142 mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 1143 mask |= 1U << ((mmMME2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 1144 mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 1145 mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 1146 mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 1147 mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 1148 mask |= 1U << ((mmMME2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 1149 mask |= 1U << ((mmMME2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 1150 mask |= 1U << ((mmMME2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 1151 mask |= 1U << ((mmMME2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 1152 mask |= 1U << ((mmMME2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 1153 mask |= 1U << ((mmMME2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 1154 1155 WREG32(pb_addr + word_offset, ~mask); 1156 1157 pb_addr = (mmMME2_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 1158 word_offset = ((mmMME2_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 1159 mask = 1U << ((mmMME2_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 1160 mask |= 1U << ((mmMME2_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 1161 mask |= 1U << ((mmMME2_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 1162 mask |= 1U << ((mmMME2_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 1163 mask |= 1U << ((mmMME2_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 1164 mask |= 1U << ((mmMME2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 1165 mask |= 1U << ((mmMME2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 1166 mask |= 1U << ((mmMME2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 1167 mask |= 1U << ((mmMME2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 1168 mask |= 1U << ((mmMME2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 1169 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 1170 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 1171 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 1172 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 1173 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 1174 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 1175 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 1176 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 1177 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 1178 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 1179 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 1180 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 1181 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 1182 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 1183 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 1184 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 1185 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 1186 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 1187 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 1188 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 1189 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 1190 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 1191 1192 WREG32(pb_addr + word_offset, ~mask); 1193 1194 pb_addr = (mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 1195 word_offset = ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 1196 << 2; 1197 mask = 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 1198 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 1199 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 1200 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 1201 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 1202 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 1203 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 1204 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 1205 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 1206 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 1207 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 1208 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 1209 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 1210 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 1211 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 1212 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 1213 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 1214 mask |= 1U << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 1215 mask |= 1U << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 1216 mask |= 1U << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 1217 mask |= 1U << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 1218 mask |= 1U << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 1219 mask |= 1U << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 1220 mask |= 1U << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 1221 mask |= 1U << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 1222 mask |= 1U << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 1223 mask |= 1U << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 1224 mask |= 1U << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 1225 mask |= 1U << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 1226 mask |= 1U << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 1227 mask |= 1U << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 1228 1229 WREG32(pb_addr + word_offset, ~mask); 1230 1231 pb_addr = (mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 1232 PROT_BITS_OFFS; 1233 word_offset = ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) 1234 >> 7) << 2; 1235 mask = 1U << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 1236 mask |= 1U << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 1237 1238 WREG32(pb_addr + word_offset, ~mask); 1239 1240 pb_addr = (mmMME2_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 1241 word_offset = ((mmMME2_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 1242 mask = 1U << ((mmMME2_QM_CP_STS_0 & 0x7F) >> 2); 1243 mask |= 1U << ((mmMME2_QM_CP_STS_1 & 0x7F) >> 2); 1244 mask |= 1U << ((mmMME2_QM_CP_STS_2 & 0x7F) >> 2); 1245 mask |= 1U << ((mmMME2_QM_CP_STS_3 & 0x7F) >> 2); 1246 mask |= 1U << ((mmMME2_QM_CP_STS_4 & 0x7F) >> 2); 1247 mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 1248 mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 1249 mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 1250 mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 1251 mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 1252 mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 1253 mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 1254 mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 1255 mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 1256 mask |= 1U << ((mmMME2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 1257 mask |= 1U << ((mmMME2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 1258 mask |= 1U << ((mmMME2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 1259 mask |= 1U << ((mmMME2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 1260 1261 WREG32(pb_addr + word_offset, ~mask); 1262 1263 pb_addr = (mmMME2_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 1264 word_offset = ((mmMME2_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 1265 mask = 1U << ((mmMME2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 1266 mask |= 1U << ((mmMME2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 1267 mask |= 1U << ((mmMME2_QM_CP_DBG_0_0 & 0x7F) >> 2); 1268 mask |= 1U << ((mmMME2_QM_CP_DBG_0_1 & 0x7F) >> 2); 1269 1270 WREG32(pb_addr + word_offset, ~mask); 1271 1272 pb_addr = (mmMME2_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 1273 word_offset = ((mmMME2_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 1274 mask = 1U << ((mmMME2_QM_CP_DBG_0_2 & 0x7F) >> 2); 1275 mask |= 1U << ((mmMME2_QM_CP_DBG_0_3 & 0x7F) >> 2); 1276 mask |= 1U << ((mmMME2_QM_CP_DBG_0_4 & 0x7F) >> 2); 1277 mask |= 1U << ((mmMME2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 1278 mask |= 1U << ((mmMME2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 1279 mask |= 1U << ((mmMME2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 1280 mask |= 1U << ((mmMME2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 1281 mask |= 1U << ((mmMME2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 1282 mask |= 1U << ((mmMME2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 1283 mask |= 1U << ((mmMME2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 1284 mask |= 1U << ((mmMME2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 1285 mask |= 1U << ((mmMME2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 1286 mask |= 1U << ((mmMME2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 1287 1288 WREG32(pb_addr + word_offset, ~mask); 1289 1290 pb_addr = (mmMME2_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 1291 word_offset = ((mmMME2_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 1292 mask = 1U << ((mmMME2_QM_ARB_CFG_1 & 0x7F) >> 2); 1293 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 1294 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 1295 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 1296 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 1297 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 1298 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 1299 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 1300 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 1301 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 1302 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 1303 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 1304 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 1305 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 1306 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 1307 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 1308 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 1309 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 1310 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 1311 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 1312 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 1313 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 1314 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 1315 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 1316 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 1317 1318 WREG32(pb_addr + word_offset, ~mask); 1319 1320 pb_addr = (mmMME2_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 1321 word_offset = ((mmMME2_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 1322 << 2; 1323 mask = 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 1324 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 1325 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 1326 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 1327 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 1328 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 1329 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 1330 mask |= 1U << ((mmMME2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 1331 1332 WREG32(pb_addr + word_offset, ~mask); 1333 1334 pb_addr = (mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 1335 PROT_BITS_OFFS; 1336 word_offset = ((mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & 1337 PROT_BITS_OFFS) >> 7) << 2; 1338 mask = 1U << ((mmMME2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 1339 mask |= 1U << ((mmMME2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 1340 mask |= 1U << ((mmMME2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 1341 mask |= 1U << ((mmMME2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 1342 mask |= 1U << ((mmMME2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 1343 1344 WREG32(pb_addr + word_offset, ~mask); 1345 1346 pb_addr = (mmMME2_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 1347 word_offset = ((mmMME2_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 1348 mask = 1U << ((mmMME2_QM_ARB_STATE_STS & 0x7F) >> 2); 1349 mask |= 1U << ((mmMME2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 1350 mask |= 1U << ((mmMME2_QM_ARB_MSG_STS & 0x7F) >> 2); 1351 mask |= 1U << ((mmMME2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 1352 mask |= 1U << ((mmMME2_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 1353 mask |= 1U << ((mmMME2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 1354 mask |= 1U << ((mmMME2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 1355 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 1356 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 1357 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 1358 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 1359 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 1360 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 1361 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 1362 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 1363 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 1364 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 1365 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 1366 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 1367 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 1368 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 1369 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 1370 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 1371 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 1372 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 1373 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 1374 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 1375 1376 WREG32(pb_addr + word_offset, ~mask); 1377 1378 pb_addr = (mmMME2_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 1379 word_offset = ((mmMME2_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 1380 << 2; 1381 mask = 1U << ((mmMME2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 1382 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 1383 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 1384 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 1385 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 1386 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 1387 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 1388 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 1389 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 1390 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 1391 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 1392 mask |= 1U << ((mmMME2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 1393 mask |= 1U << ((mmMME2_QM_CGM_CFG & 0x7F) >> 2); 1394 mask |= 1U << ((mmMME2_QM_CGM_STS & 0x7F) >> 2); 1395 mask |= 1U << ((mmMME2_QM_CGM_CFG1 & 0x7F) >> 2); 1396 1397 WREG32(pb_addr + word_offset, ~mask); 1398 1399 pb_addr = (mmMME2_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 1400 word_offset = ((mmMME2_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 1401 mask = 1U << ((mmMME2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 1402 mask |= 1U << ((mmMME2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 1403 mask |= 1U << ((mmMME2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 1404 mask |= 1U << ((mmMME2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 1405 mask |= 1U << ((mmMME2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 1406 mask |= 1U << ((mmMME2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 1407 mask |= 1U << ((mmMME2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 1408 mask |= 1U << ((mmMME2_QM_GLBL_AXCACHE & 0x7F) >> 2); 1409 mask |= 1U << ((mmMME2_QM_IND_GW_APB_CFG & 0x7F) >> 2); 1410 mask |= 1U << ((mmMME2_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 1411 mask |= 1U << ((mmMME2_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 1412 mask |= 1U << ((mmMME2_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 1413 mask |= 1U << ((mmMME2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 1414 mask |= 1U << ((mmMME2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 1415 mask |= 1U << ((mmMME2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 1416 1417 WREG32(pb_addr + word_offset, ~mask); 1418 1419 pb_addr = (mmMME2_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 1420 word_offset = ((mmMME2_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 1421 << 2; 1422 mask = 1U << ((mmMME2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 1423 1424 WREG32(pb_addr + word_offset, ~mask); 1425 1426 pb_addr = (mmMME3_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; 1427 word_offset = ((mmMME3_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; 1428 mask = 1U << ((mmMME3_CTRL_RESET & 0x7F) >> 2); 1429 mask |= 1U << ((mmMME3_CTRL_QM_STALL & 0x7F) >> 2); 1430 mask |= 1U << ((mmMME3_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); 1431 mask |= 1U << ((mmMME3_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); 1432 mask |= 1U << ((mmMME3_CTRL_INTR_CAUSE & 0x7F) >> 2); 1433 mask |= 1U << ((mmMME3_CTRL_INTR_MASK & 0x7F) >> 2); 1434 mask |= 1U << ((mmMME3_CTRL_LOG_SHADOW & 0x7F) >> 2); 1435 mask |= 1U << ((mmMME3_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); 1436 mask |= 1U << ((mmMME3_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); 1437 mask |= 1U << ((mmMME3_CTRL_PCU_RL_TH & 0x7F) >> 2); 1438 mask |= 1U << ((mmMME3_CTRL_PCU_RL_MIN & 0x7F) >> 2); 1439 mask |= 1U << ((mmMME3_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); 1440 mask |= 1U << ((mmMME3_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); 1441 mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); 1442 mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); 1443 mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); 1444 mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); 1445 mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); 1446 mask |= 1U << ((mmMME3_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); 1447 mask |= 1U << ((mmMME3_CTRL_PROT & 0x7F) >> 2); 1448 mask |= 1U << ((mmMME3_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); 1449 mask |= 1U << ((mmMME3_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); 1450 mask |= 1U << ((mmMME3_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); 1451 mask |= 1U << ((mmMME3_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); 1452 mask |= 1U << ((mmMME3_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); 1453 mask |= 1U << ((mmMME3_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); 1454 mask |= 1U << ((mmMME3_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); 1455 mask |= 1U << ((mmMME3_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); 1456 mask |= 1U << ((mmMME3_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); 1457 mask |= 1U << ((mmMME3_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); 1458 1459 WREG32(pb_addr + word_offset, ~mask); 1460 1461 pb_addr = (mmMME3_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS; 1462 word_offset = ((mmMME3_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7) 1463 << 2; 1464 mask = 1U << ((mmMME3_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); 1465 1466 WREG32(pb_addr + word_offset, ~mask); 1467 1468 /* MME 3 is slave, hence its whole QM block is protected (with RR) */ 1469} 1470 1471static void gaudi_init_dma_protection_bits(struct hl_device *hdev) 1472{ 1473 u32 pb_addr, mask; 1474 u8 word_offset; 1475 1476 if (!hdev->asic_prop.fw_security_enabled) { 1477 gaudi_pb_set_block(hdev, mmDMA_IF_E_S_BASE); 1478 gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_CH0_BASE); 1479 gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_CH1_BASE); 1480 gaudi_pb_set_block(hdev, mmDMA_E_PLL_BASE); 1481 gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_BASE); 1482 1483 gaudi_pb_set_block(hdev, mmDMA_IF_W_N_BASE); 1484 gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_CH0_BASE); 1485 gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_CH1_BASE); 1486 gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_BASE); 1487 1488 gaudi_pb_set_block(hdev, mmDMA_IF_E_N_BASE); 1489 gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_CH0_BASE); 1490 gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_CH1_BASE); 1491 gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_BASE); 1492 } 1493 1494 WREG32(mmDMA0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 1495 WREG32(mmDMA1_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 1496 WREG32(mmDMA2_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 1497 WREG32(mmDMA3_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 1498 WREG32(mmDMA4_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 1499 WREG32(mmDMA5_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 1500 WREG32(mmDMA6_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 1501 WREG32(mmDMA7_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 1502 1503 WREG32(mmDMA0_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 1504 WREG32(mmDMA1_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 1505 WREG32(mmDMA2_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 1506 WREG32(mmDMA3_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 1507 WREG32(mmDMA4_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 1508 WREG32(mmDMA5_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 1509 WREG32(mmDMA6_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 1510 WREG32(mmDMA7_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 1511 1512 pb_addr = (mmDMA0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1513 word_offset = ((mmDMA0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1514 mask = 1U << ((mmDMA0_QM_GLBL_CFG0 & 0x7F) >> 2); 1515 mask |= 1U << ((mmDMA0_QM_GLBL_CFG1 & 0x7F) >> 2); 1516 mask |= 1U << ((mmDMA0_QM_GLBL_PROT & 0x7F) >> 2); 1517 mask |= 1U << ((mmDMA0_QM_GLBL_ERR_CFG & 0x7F) >> 2); 1518 mask |= 1U << ((mmDMA0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 1519 mask |= 1U << ((mmDMA0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 1520 mask |= 1U << ((mmDMA0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 1521 mask |= 1U << ((mmDMA0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 1522 mask |= 1U << ((mmDMA0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 1523 mask |= 1U << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 1524 mask |= 1U << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 1525 mask |= 1U << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 1526 mask |= 1U << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 1527 mask |= 1U << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 1528 mask |= 1U << ((mmDMA0_QM_GLBL_STS0 & 0x7F) >> 2); 1529 mask |= 1U << ((mmDMA0_QM_GLBL_STS1_0 & 0x7F) >> 2); 1530 mask |= 1U << ((mmDMA0_QM_GLBL_STS1_1 & 0x7F) >> 2); 1531 mask |= 1U << ((mmDMA0_QM_GLBL_STS1_2 & 0x7F) >> 2); 1532 mask |= 1U << ((mmDMA0_QM_GLBL_STS1_3 & 0x7F) >> 2); 1533 mask |= 1U << ((mmDMA0_QM_GLBL_STS1_4 & 0x7F) >> 2); 1534 mask |= 1U << ((mmDMA0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 1535 mask |= 1U << ((mmDMA0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 1536 mask |= 1U << ((mmDMA0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 1537 mask |= 1U << ((mmDMA0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 1538 mask |= 1U << ((mmDMA0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 1539 mask |= 1U << ((mmDMA0_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 1540 mask |= 1U << ((mmDMA0_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 1541 mask |= 1U << ((mmDMA0_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 1542 mask |= 1U << ((mmDMA0_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 1543 1544 WREG32(pb_addr + word_offset, ~mask); 1545 1546 pb_addr = (mmDMA0_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 1547 word_offset = ((mmDMA0_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 1548 mask = 1U << ((mmDMA0_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 1549 mask |= 1U << ((mmDMA0_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 1550 mask |= 1U << ((mmDMA0_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 1551 mask |= 1U << ((mmDMA0_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 1552 mask |= 1U << ((mmDMA0_QM_PQ_SIZE_0 & 0x7F) >> 2); 1553 mask |= 1U << ((mmDMA0_QM_PQ_SIZE_1 & 0x7F) >> 2); 1554 mask |= 1U << ((mmDMA0_QM_PQ_SIZE_2 & 0x7F) >> 2); 1555 mask |= 1U << ((mmDMA0_QM_PQ_SIZE_3 & 0x7F) >> 2); 1556 mask |= 1U << ((mmDMA0_QM_PQ_PI_0 & 0x7F) >> 2); 1557 mask |= 1U << ((mmDMA0_QM_PQ_PI_1 & 0x7F) >> 2); 1558 mask |= 1U << ((mmDMA0_QM_PQ_PI_2 & 0x7F) >> 2); 1559 mask |= 1U << ((mmDMA0_QM_PQ_PI_3 & 0x7F) >> 2); 1560 mask |= 1U << ((mmDMA0_QM_PQ_CI_0 & 0x7F) >> 2); 1561 mask |= 1U << ((mmDMA0_QM_PQ_CI_1 & 0x7F) >> 2); 1562 mask |= 1U << ((mmDMA0_QM_PQ_CI_2 & 0x7F) >> 2); 1563 mask |= 1U << ((mmDMA0_QM_PQ_CI_3 & 0x7F) >> 2); 1564 mask |= 1U << ((mmDMA0_QM_PQ_CFG0_0 & 0x7F) >> 2); 1565 mask |= 1U << ((mmDMA0_QM_PQ_CFG0_1 & 0x7F) >> 2); 1566 mask |= 1U << ((mmDMA0_QM_PQ_CFG0_2 & 0x7F) >> 2); 1567 mask |= 1U << ((mmDMA0_QM_PQ_CFG0_3 & 0x7F) >> 2); 1568 mask |= 1U << ((mmDMA0_QM_PQ_CFG1_0 & 0x7F) >> 2); 1569 mask |= 1U << ((mmDMA0_QM_PQ_CFG1_1 & 0x7F) >> 2); 1570 mask |= 1U << ((mmDMA0_QM_PQ_CFG1_2 & 0x7F) >> 2); 1571 mask |= 1U << ((mmDMA0_QM_PQ_CFG1_3 & 0x7F) >> 2); 1572 mask |= 1U << ((mmDMA0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 1573 mask |= 1U << ((mmDMA0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 1574 mask |= 1U << ((mmDMA0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 1575 mask |= 1U << ((mmDMA0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 1576 mask |= 1U << ((mmDMA0_QM_PQ_STS0_0 & 0x7F) >> 2); 1577 mask |= 1U << ((mmDMA0_QM_PQ_STS0_1 & 0x7F) >> 2); 1578 mask |= 1U << ((mmDMA0_QM_PQ_STS0_2 & 0x7F) >> 2); 1579 mask |= 1U << ((mmDMA0_QM_PQ_STS0_3 & 0x7F) >> 2); 1580 1581 WREG32(pb_addr + word_offset, ~mask); 1582 1583 pb_addr = (mmDMA0_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 1584 word_offset = ((mmDMA0_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 1585 mask = 1U << ((mmDMA0_QM_PQ_STS1_0 & 0x7F) >> 2); 1586 mask |= 1U << ((mmDMA0_QM_PQ_STS1_1 & 0x7F) >> 2); 1587 mask |= 1U << ((mmDMA0_QM_PQ_STS1_2 & 0x7F) >> 2); 1588 mask |= 1U << ((mmDMA0_QM_PQ_STS1_3 & 0x7F) >> 2); 1589 mask |= 1U << ((mmDMA0_QM_CQ_STS0_0 & 0x7F) >> 2); 1590 mask |= 1U << ((mmDMA0_QM_CQ_STS0_1 & 0x7F) >> 2); 1591 mask |= 1U << ((mmDMA0_QM_CQ_STS0_2 & 0x7F) >> 2); 1592 mask |= 1U << ((mmDMA0_QM_CQ_STS0_3 & 0x7F) >> 2); 1593 mask |= 1U << ((mmDMA0_QM_CQ_STS1_0 & 0x7F) >> 2); 1594 mask |= 1U << ((mmDMA0_QM_CQ_STS1_1 & 0x7F) >> 2); 1595 mask |= 1U << ((mmDMA0_QM_CQ_STS1_2 & 0x7F) >> 2); 1596 mask |= 1U << ((mmDMA0_QM_CQ_STS1_3 & 0x7F) >> 2); 1597 mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 1598 mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 1599 mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_0 & 0x7F) >> 2); 1600 1601 WREG32(pb_addr + word_offset, ~mask); 1602 1603 pb_addr = (mmDMA0_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 1604 word_offset = ((mmDMA0_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 1605 mask = 1U << ((mmDMA0_QM_CQ_CTL_0 & 0x7F) >> 2); 1606 mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 1607 mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 1608 mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_1 & 0x7F) >> 2); 1609 mask |= 1U << ((mmDMA0_QM_CQ_CTL_1 & 0x7F) >> 2); 1610 mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 1611 mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 1612 mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_2 & 0x7F) >> 2); 1613 mask |= 1U << ((mmDMA0_QM_CQ_CTL_2 & 0x7F) >> 2); 1614 mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 1615 mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 1616 mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_3 & 0x7F) >> 2); 1617 mask |= 1U << ((mmDMA0_QM_CQ_CTL_3 & 0x7F) >> 2); 1618 mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 1619 mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 1620 mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 1621 mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 1622 mask |= 1U << ((mmDMA0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 1623 mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 1624 mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 1625 mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 1626 mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 1627 mask |= 1U << ((mmDMA0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 1628 mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 1629 mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 1630 mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 1631 mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 1632 mask |= 1U << ((mmDMA0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 1633 1634 WREG32(pb_addr + word_offset, ~mask); 1635 1636 pb_addr = (mmDMA0_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 1637 word_offset = ((mmDMA0_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 1638 mask = 1U << ((mmDMA0_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 1639 mask |= 1U << ((mmDMA0_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 1640 mask |= 1U << ((mmDMA0_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 1641 mask |= 1U << ((mmDMA0_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 1642 mask |= 1U << ((mmDMA0_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 1643 mask |= 1U << ((mmDMA0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 1644 mask |= 1U << ((mmDMA0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 1645 mask |= 1U << ((mmDMA0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 1646 mask |= 1U << ((mmDMA0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 1647 mask |= 1U << ((mmDMA0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 1648 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 1649 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 1650 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 1651 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 1652 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 1653 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 1654 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 1655 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 1656 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 1657 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 1658 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 1659 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 1660 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 1661 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 1662 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 1663 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 1664 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 1665 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 1666 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 1667 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 1668 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 1669 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 1670 1671 WREG32(pb_addr + word_offset, ~mask); 1672 1673 pb_addr = (mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 1674 word_offset = ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 1675 << 2; 1676 mask = 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 1677 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 1678 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 1679 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 1680 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 1681 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 1682 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 1683 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 1684 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 1685 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 1686 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 1687 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 1688 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 1689 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 1690 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 1691 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 1692 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 1693 mask |= 1U << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 1694 mask |= 1U << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 1695 mask |= 1U << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 1696 mask |= 1U << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 1697 mask |= 1U << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 1698 mask |= 1U << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 1699 mask |= 1U << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 1700 mask |= 1U << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 1701 mask |= 1U << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 1702 mask |= 1U << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 1703 mask |= 1U << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 1704 mask |= 1U << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 1705 mask |= 1U << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 1706 mask |= 1U << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 1707 1708 WREG32(pb_addr + word_offset, ~mask); 1709 1710 pb_addr = (mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 1711 PROT_BITS_OFFS; 1712 word_offset = 1713 ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) 1714 << 2; 1715 mask = 1U << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 1716 mask |= 1U << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 1717 1718 WREG32(pb_addr + word_offset, ~mask); 1719 1720 pb_addr = (mmDMA0_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 1721 word_offset = ((mmDMA0_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 1722 mask = 1U << ((mmDMA0_QM_CP_STS_0 & 0x7F) >> 2); 1723 mask |= 1U << ((mmDMA0_QM_CP_STS_1 & 0x7F) >> 2); 1724 mask |= 1U << ((mmDMA0_QM_CP_STS_2 & 0x7F) >> 2); 1725 mask |= 1U << ((mmDMA0_QM_CP_STS_3 & 0x7F) >> 2); 1726 mask |= 1U << ((mmDMA0_QM_CP_STS_4 & 0x7F) >> 2); 1727 mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 1728 mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 1729 mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 1730 mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 1731 mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 1732 mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 1733 mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 1734 mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 1735 mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 1736 mask |= 1U << ((mmDMA0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 1737 mask |= 1U << ((mmDMA0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 1738 mask |= 1U << ((mmDMA0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 1739 mask |= 1U << ((mmDMA0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 1740 1741 WREG32(pb_addr + word_offset, ~mask); 1742 1743 pb_addr = (mmDMA0_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 1744 word_offset = ((mmDMA0_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 1745 mask = 1U << ((mmDMA0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 1746 mask |= 1U << ((mmDMA0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 1747 mask |= 1U << ((mmDMA0_QM_CP_DBG_0_0 & 0x7F) >> 2); 1748 mask |= 1U << ((mmDMA0_QM_CP_DBG_0_1 & 0x7F) >> 2); 1749 1750 WREG32(pb_addr + word_offset, ~mask); 1751 1752 pb_addr = (mmDMA0_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 1753 word_offset = ((mmDMA0_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 1754 mask = 1U << ((mmDMA0_QM_CP_DBG_0_2 & 0x7F) >> 2); 1755 mask |= 1U << ((mmDMA0_QM_CP_DBG_0_3 & 0x7F) >> 2); 1756 mask |= 1U << ((mmDMA0_QM_CP_DBG_0_4 & 0x7F) >> 2); 1757 mask |= 1U << ((mmDMA0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 1758 mask |= 1U << ((mmDMA0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 1759 mask |= 1U << ((mmDMA0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 1760 mask |= 1U << ((mmDMA0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 1761 mask |= 1U << ((mmDMA0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 1762 mask |= 1U << ((mmDMA0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 1763 mask |= 1U << ((mmDMA0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 1764 mask |= 1U << ((mmDMA0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 1765 mask |= 1U << ((mmDMA0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 1766 mask |= 1U << ((mmDMA0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 1767 1768 WREG32(pb_addr + word_offset, ~mask); 1769 1770 pb_addr = (mmDMA0_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 1771 word_offset = ((mmDMA0_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 1772 mask = 1U << ((mmDMA0_QM_ARB_CFG_1 & 0x7F) >> 2); 1773 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 1774 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 1775 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 1776 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 1777 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 1778 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 1779 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 1780 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 1781 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 1782 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 1783 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 1784 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 1785 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 1786 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 1787 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 1788 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 1789 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 1790 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 1791 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 1792 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 1793 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 1794 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 1795 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 1796 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 1797 1798 WREG32(pb_addr + word_offset, ~mask); 1799 1800 pb_addr = (mmDMA0_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 1801 word_offset = ((mmDMA0_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 1802 << 2; 1803 mask = 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 1804 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 1805 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 1806 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 1807 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 1808 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 1809 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 1810 mask |= 1U << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 1811 WREG32(pb_addr + word_offset, ~mask); 1812 1813 pb_addr = (mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 1814 PROT_BITS_OFFS; 1815 word_offset = 1816 ((mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) 1817 << 2; 1818 mask = 1U << ((mmDMA0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 1819 mask |= 1U << ((mmDMA0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 1820 mask |= 1U << ((mmDMA0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 1821 mask |= 1U << ((mmDMA0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 1822 mask |= 1U << ((mmDMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 1823 1824 WREG32(pb_addr + word_offset, ~mask); 1825 1826 pb_addr = (mmDMA0_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 1827 word_offset = ((mmDMA0_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 1828 mask = 1U << ((mmDMA0_QM_ARB_STATE_STS & 0x7F) >> 2); 1829 mask |= 1U << ((mmDMA0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 1830 mask |= 1U << ((mmDMA0_QM_ARB_MSG_STS & 0x7F) >> 2); 1831 mask |= 1U << ((mmDMA0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 1832 mask |= 1U << ((mmDMA0_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 1833 mask |= 1U << ((mmDMA0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 1834 mask |= 1U << ((mmDMA0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 1835 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 1836 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 1837 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 1838 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 1839 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 1840 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 1841 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 1842 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 1843 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 1844 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 1845 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 1846 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 1847 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 1848 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 1849 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 1850 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 1851 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 1852 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 1853 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 1854 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 1855 1856 WREG32(pb_addr + word_offset, ~mask); 1857 1858 pb_addr = (mmDMA0_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 1859 word_offset = ((mmDMA0_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 1860 << 2; 1861 mask = 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 1862 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 1863 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 1864 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 1865 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 1866 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 1867 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 1868 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 1869 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 1870 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 1871 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 1872 mask |= 1U << ((mmDMA0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 1873 mask |= 1U << ((mmDMA0_QM_CGM_CFG & 0x7F) >> 2); 1874 mask |= 1U << ((mmDMA0_QM_CGM_STS & 0x7F) >> 2); 1875 mask |= 1U << ((mmDMA0_QM_CGM_CFG1 & 0x7F) >> 2); 1876 1877 WREG32(pb_addr + word_offset, ~mask); 1878 1879 pb_addr = (mmDMA0_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 1880 word_offset = ((mmDMA0_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 1881 mask = 1U << ((mmDMA0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 1882 mask |= 1U << ((mmDMA0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 1883 mask |= 1U << ((mmDMA0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 1884 mask |= 1U << ((mmDMA0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 1885 mask |= 1U << ((mmDMA0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 1886 mask |= 1U << ((mmDMA0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 1887 mask |= 1U << ((mmDMA0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 1888 mask |= 1U << ((mmDMA0_QM_GLBL_AXCACHE & 0x7F) >> 2); 1889 mask |= 1U << ((mmDMA0_QM_IND_GW_APB_CFG & 0x7F) >> 2); 1890 mask |= 1U << ((mmDMA0_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 1891 mask |= 1U << ((mmDMA0_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 1892 mask |= 1U << ((mmDMA0_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 1893 mask |= 1U << ((mmDMA0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 1894 mask |= 1U << ((mmDMA0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 1895 mask |= 1U << ((mmDMA0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 1896 1897 WREG32(pb_addr + word_offset, ~mask); 1898 1899 pb_addr = (mmDMA0_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 1900 word_offset = ((mmDMA0_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 1901 << 2; 1902 mask = 1U << ((mmDMA0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 1903 1904 WREG32(pb_addr + word_offset, ~mask); 1905 1906 pb_addr = (mmDMA1_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 1907 word_offset = ((mmDMA1_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 1908 mask = 1U << ((mmDMA1_QM_GLBL_CFG0 & 0x7F) >> 2); 1909 mask |= 1U << ((mmDMA1_QM_GLBL_CFG1 & 0x7F) >> 2); 1910 mask |= 1U << ((mmDMA1_QM_GLBL_PROT & 0x7F) >> 2); 1911 mask |= 1U << ((mmDMA1_QM_GLBL_ERR_CFG & 0x7F) >> 2); 1912 mask |= 1U << ((mmDMA1_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 1913 mask |= 1U << ((mmDMA1_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 1914 mask |= 1U << ((mmDMA1_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 1915 mask |= 1U << ((mmDMA1_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 1916 mask |= 1U << ((mmDMA1_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 1917 mask |= 1U << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 1918 mask |= 1U << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 1919 mask |= 1U << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 1920 mask |= 1U << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 1921 mask |= 1U << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 1922 mask |= 1U << ((mmDMA1_QM_GLBL_STS0 & 0x7F) >> 2); 1923 mask |= 1U << ((mmDMA1_QM_GLBL_STS1_0 & 0x7F) >> 2); 1924 mask |= 1U << ((mmDMA1_QM_GLBL_STS1_1 & 0x7F) >> 2); 1925 mask |= 1U << ((mmDMA1_QM_GLBL_STS1_2 & 0x7F) >> 2); 1926 mask |= 1U << ((mmDMA1_QM_GLBL_STS1_3 & 0x7F) >> 2); 1927 mask |= 1U << ((mmDMA1_QM_GLBL_STS1_4 & 0x7F) >> 2); 1928 mask |= 1U << ((mmDMA1_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 1929 mask |= 1U << ((mmDMA1_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 1930 mask |= 1U << ((mmDMA1_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 1931 mask |= 1U << ((mmDMA1_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 1932 mask |= 1U << ((mmDMA1_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 1933 mask |= 1U << ((mmDMA1_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 1934 mask |= 1U << ((mmDMA1_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 1935 mask |= 1U << ((mmDMA1_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 1936 mask |= 1U << ((mmDMA1_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 1937 1938 WREG32(pb_addr + word_offset, ~mask); 1939 1940 pb_addr = (mmDMA1_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 1941 word_offset = ((mmDMA1_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 1942 mask = 1U << ((mmDMA1_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 1943 mask |= 1U << ((mmDMA1_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 1944 mask |= 1U << ((mmDMA1_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 1945 mask |= 1U << ((mmDMA1_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 1946 mask |= 1U << ((mmDMA1_QM_PQ_SIZE_0 & 0x7F) >> 2); 1947 mask |= 1U << ((mmDMA1_QM_PQ_SIZE_1 & 0x7F) >> 2); 1948 mask |= 1U << ((mmDMA1_QM_PQ_SIZE_2 & 0x7F) >> 2); 1949 mask |= 1U << ((mmDMA1_QM_PQ_SIZE_3 & 0x7F) >> 2); 1950 mask |= 1U << ((mmDMA1_QM_PQ_PI_0 & 0x7F) >> 2); 1951 mask |= 1U << ((mmDMA1_QM_PQ_PI_1 & 0x7F) >> 2); 1952 mask |= 1U << ((mmDMA1_QM_PQ_PI_2 & 0x7F) >> 2); 1953 mask |= 1U << ((mmDMA1_QM_PQ_PI_3 & 0x7F) >> 2); 1954 mask |= 1U << ((mmDMA1_QM_PQ_CI_0 & 0x7F) >> 2); 1955 mask |= 1U << ((mmDMA1_QM_PQ_CI_1 & 0x7F) >> 2); 1956 mask |= 1U << ((mmDMA1_QM_PQ_CI_2 & 0x7F) >> 2); 1957 mask |= 1U << ((mmDMA1_QM_PQ_CI_3 & 0x7F) >> 2); 1958 mask |= 1U << ((mmDMA1_QM_PQ_CFG0_0 & 0x7F) >> 2); 1959 mask |= 1U << ((mmDMA1_QM_PQ_CFG0_1 & 0x7F) >> 2); 1960 mask |= 1U << ((mmDMA1_QM_PQ_CFG0_2 & 0x7F) >> 2); 1961 mask |= 1U << ((mmDMA1_QM_PQ_CFG0_3 & 0x7F) >> 2); 1962 mask |= 1U << ((mmDMA1_QM_PQ_CFG1_0 & 0x7F) >> 2); 1963 mask |= 1U << ((mmDMA1_QM_PQ_CFG1_1 & 0x7F) >> 2); 1964 mask |= 1U << ((mmDMA1_QM_PQ_CFG1_2 & 0x7F) >> 2); 1965 mask |= 1U << ((mmDMA1_QM_PQ_CFG1_3 & 0x7F) >> 2); 1966 mask |= 1U << ((mmDMA1_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 1967 mask |= 1U << ((mmDMA1_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 1968 mask |= 1U << ((mmDMA1_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 1969 mask |= 1U << ((mmDMA1_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 1970 mask |= 1U << ((mmDMA1_QM_PQ_STS0_0 & 0x7F) >> 2); 1971 mask |= 1U << ((mmDMA1_QM_PQ_STS0_1 & 0x7F) >> 2); 1972 mask |= 1U << ((mmDMA1_QM_PQ_STS0_2 & 0x7F) >> 2); 1973 mask |= 1U << ((mmDMA1_QM_PQ_STS0_3 & 0x7F) >> 2); 1974 1975 WREG32(pb_addr + word_offset, ~mask); 1976 1977 pb_addr = (mmDMA1_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 1978 word_offset = ((mmDMA1_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 1979 mask = 1U << ((mmDMA1_QM_PQ_STS1_0 & 0x7F) >> 2); 1980 mask |= 1U << ((mmDMA1_QM_PQ_STS1_1 & 0x7F) >> 2); 1981 mask |= 1U << ((mmDMA1_QM_PQ_STS1_2 & 0x7F) >> 2); 1982 mask |= 1U << ((mmDMA1_QM_PQ_STS1_3 & 0x7F) >> 2); 1983 mask |= 1U << ((mmDMA1_QM_CQ_STS0_0 & 0x7F) >> 2); 1984 mask |= 1U << ((mmDMA1_QM_CQ_STS0_1 & 0x7F) >> 2); 1985 mask |= 1U << ((mmDMA1_QM_CQ_STS0_2 & 0x7F) >> 2); 1986 mask |= 1U << ((mmDMA1_QM_CQ_STS0_3 & 0x7F) >> 2); 1987 mask |= 1U << ((mmDMA1_QM_CQ_STS1_0 & 0x7F) >> 2); 1988 mask |= 1U << ((mmDMA1_QM_CQ_STS1_1 & 0x7F) >> 2); 1989 mask |= 1U << ((mmDMA1_QM_CQ_STS1_2 & 0x7F) >> 2); 1990 mask |= 1U << ((mmDMA1_QM_CQ_STS1_3 & 0x7F) >> 2); 1991 mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 1992 mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 1993 mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_0 & 0x7F) >> 2); 1994 1995 WREG32(pb_addr + word_offset, ~mask); 1996 1997 pb_addr = (mmDMA1_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 1998 word_offset = ((mmDMA1_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 1999 mask = 1U << ((mmDMA1_QM_CQ_CTL_0 & 0x7F) >> 2); 2000 mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 2001 mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 2002 mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_1 & 0x7F) >> 2); 2003 mask |= 1U << ((mmDMA1_QM_CQ_CTL_1 & 0x7F) >> 2); 2004 mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 2005 mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 2006 mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_2 & 0x7F) >> 2); 2007 mask |= 1U << ((mmDMA1_QM_CQ_CTL_2 & 0x7F) >> 2); 2008 mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 2009 mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 2010 mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_3 & 0x7F) >> 2); 2011 mask |= 1U << ((mmDMA1_QM_CQ_CTL_3 & 0x7F) >> 2); 2012 mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 2013 mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 2014 mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 2015 mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 2016 mask |= 1U << ((mmDMA1_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 2017 mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 2018 mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 2019 mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 2020 mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 2021 mask |= 1U << ((mmDMA1_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 2022 mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 2023 mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 2024 mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 2025 mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 2026 mask |= 1U << ((mmDMA1_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 2027 2028 WREG32(pb_addr + word_offset, ~mask); 2029 2030 pb_addr = (mmDMA1_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 2031 word_offset = ((mmDMA1_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 2032 mask = 1U << ((mmDMA1_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 2033 mask |= 1U << ((mmDMA1_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 2034 mask |= 1U << ((mmDMA1_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 2035 mask |= 1U << ((mmDMA1_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 2036 mask |= 1U << ((mmDMA1_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 2037 mask |= 1U << ((mmDMA1_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 2038 mask |= 1U << ((mmDMA1_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 2039 mask |= 1U << ((mmDMA1_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 2040 mask |= 1U << ((mmDMA1_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 2041 mask |= 1U << ((mmDMA1_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 2042 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 2043 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 2044 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 2045 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 2046 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 2047 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 2048 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 2049 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 2050 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 2051 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 2052 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 2053 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 2054 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 2055 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 2056 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 2057 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 2058 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 2059 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 2060 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 2061 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 2062 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 2063 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 2064 2065 WREG32(pb_addr + word_offset, ~mask); 2066 2067 pb_addr = (mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 2068 word_offset = ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 2069 << 2; 2070 mask = 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 2071 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 2072 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 2073 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 2074 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 2075 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 2076 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 2077 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 2078 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 2079 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 2080 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 2081 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 2082 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 2083 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 2084 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 2085 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 2086 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 2087 mask |= 1U << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 2088 mask |= 1U << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 2089 mask |= 1U << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 2090 mask |= 1U << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 2091 mask |= 1U << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 2092 mask |= 1U << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 2093 mask |= 1U << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 2094 mask |= 1U << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 2095 mask |= 1U << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 2096 mask |= 1U << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 2097 mask |= 1U << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 2098 mask |= 1U << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 2099 mask |= 1U << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 2100 mask |= 1U << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 2101 2102 WREG32(pb_addr + word_offset, ~mask); 2103 2104 pb_addr = (mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 2105 PROT_BITS_OFFS; 2106 word_offset = 2107 ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) 2108 << 2; 2109 mask = 1U << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 2110 mask |= 1U << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 2111 2112 WREG32(pb_addr + word_offset, ~mask); 2113 2114 pb_addr = (mmDMA1_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 2115 word_offset = ((mmDMA1_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 2116 mask = 1U << ((mmDMA1_QM_CP_STS_0 & 0x7F) >> 2); 2117 mask |= 1U << ((mmDMA1_QM_CP_STS_1 & 0x7F) >> 2); 2118 mask |= 1U << ((mmDMA1_QM_CP_STS_2 & 0x7F) >> 2); 2119 mask |= 1U << ((mmDMA1_QM_CP_STS_3 & 0x7F) >> 2); 2120 mask |= 1U << ((mmDMA1_QM_CP_STS_4 & 0x7F) >> 2); 2121 mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 2122 mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 2123 mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 2124 mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 2125 mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 2126 mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 2127 mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 2128 mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 2129 mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 2130 mask |= 1U << ((mmDMA1_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 2131 mask |= 1U << ((mmDMA1_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 2132 mask |= 1U << ((mmDMA1_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 2133 mask |= 1U << ((mmDMA1_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 2134 2135 WREG32(pb_addr + word_offset, ~mask); 2136 2137 pb_addr = (mmDMA1_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 2138 word_offset = ((mmDMA1_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 2139 mask = 1U << ((mmDMA1_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 2140 mask |= 1U << ((mmDMA1_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 2141 mask |= 1U << ((mmDMA1_QM_CP_DBG_0_0 & 0x7F) >> 2); 2142 mask |= 1U << ((mmDMA1_QM_CP_DBG_0_1 & 0x7F) >> 2); 2143 2144 WREG32(pb_addr + word_offset, ~mask); 2145 2146 pb_addr = (mmDMA1_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 2147 word_offset = ((mmDMA1_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 2148 mask = 1U << ((mmDMA1_QM_CP_DBG_0_2 & 0x7F) >> 2); 2149 mask |= 1U << ((mmDMA1_QM_CP_DBG_0_3 & 0x7F) >> 2); 2150 mask |= 1U << ((mmDMA1_QM_CP_DBG_0_4 & 0x7F) >> 2); 2151 mask |= 1U << ((mmDMA1_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 2152 mask |= 1U << ((mmDMA1_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 2153 mask |= 1U << ((mmDMA1_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 2154 mask |= 1U << ((mmDMA1_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 2155 mask |= 1U << ((mmDMA1_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 2156 mask |= 1U << ((mmDMA1_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 2157 mask |= 1U << ((mmDMA1_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 2158 mask |= 1U << ((mmDMA1_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 2159 mask |= 1U << ((mmDMA1_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 2160 mask |= 1U << ((mmDMA1_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 2161 2162 WREG32(pb_addr + word_offset, ~mask); 2163 2164 pb_addr = (mmDMA1_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 2165 word_offset = ((mmDMA1_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 2166 mask = 1U << ((mmDMA1_QM_ARB_CFG_1 & 0x7F) >> 2); 2167 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 2168 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 2169 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 2170 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 2171 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 2172 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 2173 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 2174 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 2175 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 2176 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 2177 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 2178 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 2179 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 2180 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 2181 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 2182 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 2183 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 2184 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 2185 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 2186 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 2187 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 2188 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 2189 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 2190 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 2191 2192 WREG32(pb_addr + word_offset, ~mask); 2193 2194 pb_addr = (mmDMA1_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 2195 word_offset = ((mmDMA1_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 2196 << 2; 2197 mask = 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 2198 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 2199 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 2200 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 2201 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 2202 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 2203 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 2204 mask |= 1U << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 2205 2206 WREG32(pb_addr + word_offset, ~mask); 2207 2208 pb_addr = (mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 2209 PROT_BITS_OFFS; 2210 word_offset = 2211 ((mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) 2212 << 2; 2213 mask = 1U << ((mmDMA1_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 2214 mask |= 1U << ((mmDMA1_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 2215 mask |= 1U << ((mmDMA1_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 2216 mask |= 1U << ((mmDMA1_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 2217 mask |= 1U << ((mmDMA1_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 2218 2219 WREG32(pb_addr + word_offset, ~mask); 2220 2221 pb_addr = (mmDMA1_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 2222 word_offset = ((mmDMA1_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 2223 mask = 1U << ((mmDMA1_QM_ARB_STATE_STS & 0x7F) >> 2); 2224 mask |= 1U << ((mmDMA1_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 2225 mask |= 1U << ((mmDMA1_QM_ARB_MSG_STS & 0x7F) >> 2); 2226 mask |= 1U << ((mmDMA1_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 2227 mask |= 1U << ((mmDMA1_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 2228 mask |= 1U << ((mmDMA1_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 2229 mask |= 1U << ((mmDMA1_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 2230 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 2231 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 2232 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 2233 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 2234 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 2235 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 2236 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 2237 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 2238 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 2239 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 2240 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 2241 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 2242 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 2243 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 2244 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 2245 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 2246 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 2247 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 2248 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 2249 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 2250 2251 WREG32(pb_addr + word_offset, ~mask); 2252 2253 pb_addr = (mmDMA1_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 2254 word_offset = ((mmDMA1_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 2255 << 2; 2256 mask = 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 2257 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 2258 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 2259 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 2260 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 2261 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 2262 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 2263 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 2264 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 2265 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 2266 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 2267 mask |= 1U << ((mmDMA1_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 2268 mask |= 1U << ((mmDMA1_QM_CGM_CFG & 0x7F) >> 2); 2269 mask |= 1U << ((mmDMA1_QM_CGM_STS & 0x7F) >> 2); 2270 mask |= 1U << ((mmDMA1_QM_CGM_CFG1 & 0x7F) >> 2); 2271 2272 WREG32(pb_addr + word_offset, ~mask); 2273 2274 pb_addr = (mmDMA1_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 2275 word_offset = ((mmDMA1_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 2276 mask = 1U << ((mmDMA1_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 2277 mask |= 1U << ((mmDMA1_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 2278 mask |= 1U << ((mmDMA1_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 2279 mask |= 1U << ((mmDMA1_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 2280 mask |= 1U << ((mmDMA1_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 2281 mask |= 1U << ((mmDMA1_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 2282 mask |= 1U << ((mmDMA1_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 2283 mask |= 1U << ((mmDMA1_QM_GLBL_AXCACHE & 0x7F) >> 2); 2284 mask |= 1U << ((mmDMA1_QM_IND_GW_APB_CFG & 0x7F) >> 2); 2285 mask |= 1U << ((mmDMA1_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 2286 mask |= 1U << ((mmDMA1_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 2287 mask |= 1U << ((mmDMA1_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 2288 mask |= 1U << ((mmDMA1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 2289 mask |= 1U << ((mmDMA1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 2290 mask |= 1U << ((mmDMA1_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 2291 2292 WREG32(pb_addr + word_offset, ~mask); 2293 2294 pb_addr = (mmDMA1_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 2295 word_offset = ((mmDMA1_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 2296 << 2; 2297 mask = 1U << ((mmDMA1_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 2298 2299 WREG32(pb_addr + word_offset, ~mask); 2300 2301 pb_addr = (mmDMA2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 2302 word_offset = ((mmDMA2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 2303 mask = 1U << ((mmDMA2_QM_GLBL_CFG0 & 0x7F) >> 2); 2304 mask |= 1U << ((mmDMA2_QM_GLBL_CFG1 & 0x7F) >> 2); 2305 mask |= 1U << ((mmDMA2_QM_GLBL_PROT & 0x7F) >> 2); 2306 mask |= 1U << ((mmDMA2_QM_GLBL_ERR_CFG & 0x7F) >> 2); 2307 mask |= 1U << ((mmDMA2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 2308 mask |= 1U << ((mmDMA2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 2309 mask |= 1U << ((mmDMA2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 2310 mask |= 1U << ((mmDMA2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 2311 mask |= 1U << ((mmDMA2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 2312 mask |= 1U << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 2313 mask |= 1U << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 2314 mask |= 1U << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 2315 mask |= 1U << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 2316 mask |= 1U << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 2317 mask |= 1U << ((mmDMA2_QM_GLBL_STS0 & 0x7F) >> 2); 2318 mask |= 1U << ((mmDMA2_QM_GLBL_STS1_0 & 0x7F) >> 2); 2319 mask |= 1U << ((mmDMA2_QM_GLBL_STS1_1 & 0x7F) >> 2); 2320 mask |= 1U << ((mmDMA2_QM_GLBL_STS1_2 & 0x7F) >> 2); 2321 mask |= 1U << ((mmDMA2_QM_GLBL_STS1_3 & 0x7F) >> 2); 2322 mask |= 1U << ((mmDMA2_QM_GLBL_STS1_4 & 0x7F) >> 2); 2323 mask |= 1U << ((mmDMA2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 2324 mask |= 1U << ((mmDMA2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 2325 mask |= 1U << ((mmDMA2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 2326 mask |= 1U << ((mmDMA2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 2327 mask |= 1U << ((mmDMA2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 2328 mask |= 1U << ((mmDMA2_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 2329 mask |= 1U << ((mmDMA2_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 2330 mask |= 1U << ((mmDMA2_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 2331 mask |= 1U << ((mmDMA2_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 2332 2333 WREG32(pb_addr + word_offset, ~mask); 2334 2335 pb_addr = (mmDMA2_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 2336 word_offset = ((mmDMA2_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 2337 mask = 1U << ((mmDMA2_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 2338 mask |= 1U << ((mmDMA2_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 2339 mask |= 1U << ((mmDMA2_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 2340 mask |= 1U << ((mmDMA2_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 2341 mask |= 1U << ((mmDMA2_QM_PQ_SIZE_0 & 0x7F) >> 2); 2342 mask |= 1U << ((mmDMA2_QM_PQ_SIZE_1 & 0x7F) >> 2); 2343 mask |= 1U << ((mmDMA2_QM_PQ_SIZE_2 & 0x7F) >> 2); 2344 mask |= 1U << ((mmDMA2_QM_PQ_SIZE_3 & 0x7F) >> 2); 2345 mask |= 1U << ((mmDMA2_QM_PQ_PI_0 & 0x7F) >> 2); 2346 mask |= 1U << ((mmDMA2_QM_PQ_PI_1 & 0x7F) >> 2); 2347 mask |= 1U << ((mmDMA2_QM_PQ_PI_2 & 0x7F) >> 2); 2348 mask |= 1U << ((mmDMA2_QM_PQ_PI_3 & 0x7F) >> 2); 2349 mask |= 1U << ((mmDMA2_QM_PQ_CI_0 & 0x7F) >> 2); 2350 mask |= 1U << ((mmDMA2_QM_PQ_CI_1 & 0x7F) >> 2); 2351 mask |= 1U << ((mmDMA2_QM_PQ_CI_2 & 0x7F) >> 2); 2352 mask |= 1U << ((mmDMA2_QM_PQ_CI_3 & 0x7F) >> 2); 2353 mask |= 1U << ((mmDMA2_QM_PQ_CFG0_0 & 0x7F) >> 2); 2354 mask |= 1U << ((mmDMA2_QM_PQ_CFG0_1 & 0x7F) >> 2); 2355 mask |= 1U << ((mmDMA2_QM_PQ_CFG0_2 & 0x7F) >> 2); 2356 mask |= 1U << ((mmDMA2_QM_PQ_CFG0_3 & 0x7F) >> 2); 2357 mask |= 1U << ((mmDMA2_QM_PQ_CFG1_0 & 0x7F) >> 2); 2358 mask |= 1U << ((mmDMA2_QM_PQ_CFG1_1 & 0x7F) >> 2); 2359 mask |= 1U << ((mmDMA2_QM_PQ_CFG1_2 & 0x7F) >> 2); 2360 mask |= 1U << ((mmDMA2_QM_PQ_CFG1_3 & 0x7F) >> 2); 2361 mask |= 1U << ((mmDMA2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 2362 mask |= 1U << ((mmDMA2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 2363 mask |= 1U << ((mmDMA2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 2364 mask |= 1U << ((mmDMA2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 2365 mask |= 1U << ((mmDMA2_QM_PQ_STS0_0 & 0x7F) >> 2); 2366 mask |= 1U << ((mmDMA2_QM_PQ_STS0_1 & 0x7F) >> 2); 2367 mask |= 1U << ((mmDMA2_QM_PQ_STS0_2 & 0x7F) >> 2); 2368 mask |= 1U << ((mmDMA2_QM_PQ_STS0_3 & 0x7F) >> 2); 2369 2370 WREG32(pb_addr + word_offset, ~mask); 2371 2372 pb_addr = (mmDMA2_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 2373 word_offset = ((mmDMA2_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 2374 mask = 1U << ((mmDMA2_QM_PQ_STS1_0 & 0x7F) >> 2); 2375 mask |= 1U << ((mmDMA2_QM_PQ_STS1_1 & 0x7F) >> 2); 2376 mask |= 1U << ((mmDMA2_QM_PQ_STS1_2 & 0x7F) >> 2); 2377 mask |= 1U << ((mmDMA2_QM_PQ_STS1_3 & 0x7F) >> 2); 2378 mask |= 1U << ((mmDMA2_QM_CQ_STS0_0 & 0x7F) >> 2); 2379 mask |= 1U << ((mmDMA2_QM_CQ_STS0_1 & 0x7F) >> 2); 2380 mask |= 1U << ((mmDMA2_QM_CQ_STS0_2 & 0x7F) >> 2); 2381 mask |= 1U << ((mmDMA2_QM_CQ_STS0_3 & 0x7F) >> 2); 2382 mask |= 1U << ((mmDMA2_QM_CQ_STS1_0 & 0x7F) >> 2); 2383 mask |= 1U << ((mmDMA2_QM_CQ_STS1_1 & 0x7F) >> 2); 2384 mask |= 1U << ((mmDMA2_QM_CQ_STS1_2 & 0x7F) >> 2); 2385 mask |= 1U << ((mmDMA2_QM_CQ_STS1_3 & 0x7F) >> 2); 2386 mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 2387 mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 2388 mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_0 & 0x7F) >> 2); 2389 2390 WREG32(pb_addr + word_offset, ~mask); 2391 2392 pb_addr = (mmDMA2_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 2393 word_offset = ((mmDMA2_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 2394 mask = 1U << ((mmDMA2_QM_CQ_CTL_0 & 0x7F) >> 2); 2395 mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 2396 mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 2397 mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_1 & 0x7F) >> 2); 2398 mask |= 1U << ((mmDMA2_QM_CQ_CTL_1 & 0x7F) >> 2); 2399 mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 2400 mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 2401 mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_2 & 0x7F) >> 2); 2402 mask |= 1U << ((mmDMA2_QM_CQ_CTL_2 & 0x7F) >> 2); 2403 mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 2404 mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 2405 mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_3 & 0x7F) >> 2); 2406 mask |= 1U << ((mmDMA2_QM_CQ_CTL_3 & 0x7F) >> 2); 2407 mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 2408 mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 2409 mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 2410 mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 2411 mask |= 1U << ((mmDMA2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 2412 mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 2413 mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 2414 mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 2415 mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 2416 mask |= 1U << ((mmDMA2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 2417 mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 2418 mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 2419 mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 2420 mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 2421 mask |= 1U << ((mmDMA2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 2422 2423 WREG32(pb_addr + word_offset, ~mask); 2424 2425 pb_addr = (mmDMA2_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 2426 word_offset = ((mmDMA2_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 2427 mask = 1U << ((mmDMA2_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 2428 mask |= 1U << ((mmDMA2_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 2429 mask |= 1U << ((mmDMA2_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 2430 mask |= 1U << ((mmDMA2_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 2431 mask |= 1U << ((mmDMA2_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 2432 mask |= 1U << ((mmDMA2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 2433 mask |= 1U << ((mmDMA2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 2434 mask |= 1U << ((mmDMA2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 2435 mask |= 1U << ((mmDMA2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 2436 mask |= 1U << ((mmDMA2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 2437 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 2438 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 2439 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 2440 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 2441 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 2442 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 2443 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 2444 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 2445 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 2446 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 2447 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 2448 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 2449 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 2450 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 2451 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 2452 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 2453 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 2454 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 2455 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 2456 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 2457 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 2458 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 2459 2460 WREG32(pb_addr + word_offset, ~mask); 2461 2462 pb_addr = (mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 2463 word_offset = ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 2464 << 2; 2465 mask = 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 2466 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 2467 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 2468 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 2469 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 2470 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 2471 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 2472 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 2473 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 2474 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 2475 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 2476 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 2477 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 2478 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 2479 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 2480 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 2481 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 2482 mask |= 1U << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 2483 mask |= 1U << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 2484 mask |= 1U << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 2485 mask |= 1U << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 2486 mask |= 1U << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 2487 mask |= 1U << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 2488 mask |= 1U << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 2489 mask |= 1U << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 2490 mask |= 1U << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 2491 mask |= 1U << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 2492 mask |= 1U << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 2493 mask |= 1U << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 2494 mask |= 1U << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 2495 mask |= 1U << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 2496 2497 WREG32(pb_addr + word_offset, ~mask); 2498 2499 pb_addr = (mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 2500 PROT_BITS_OFFS; 2501 word_offset = 2502 ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) 2503 << 2; 2504 mask = 1U << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 2505 mask |= 1U << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 2506 2507 WREG32(pb_addr + word_offset, ~mask); 2508 2509 pb_addr = (mmDMA2_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 2510 word_offset = ((mmDMA2_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 2511 mask = 1U << ((mmDMA2_QM_CP_STS_0 & 0x7F) >> 2); 2512 mask |= 1U << ((mmDMA2_QM_CP_STS_1 & 0x7F) >> 2); 2513 mask |= 1U << ((mmDMA2_QM_CP_STS_2 & 0x7F) >> 2); 2514 mask |= 1U << ((mmDMA2_QM_CP_STS_3 & 0x7F) >> 2); 2515 mask |= 1U << ((mmDMA2_QM_CP_STS_4 & 0x7F) >> 2); 2516 mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 2517 mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 2518 mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 2519 mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 2520 mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 2521 mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 2522 mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 2523 mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 2524 mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 2525 mask |= 1U << ((mmDMA2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 2526 mask |= 1U << ((mmDMA2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 2527 mask |= 1U << ((mmDMA2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 2528 mask |= 1U << ((mmDMA2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 2529 2530 WREG32(pb_addr + word_offset, ~mask); 2531 2532 pb_addr = (mmDMA2_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 2533 word_offset = ((mmDMA2_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 2534 mask = 1U << ((mmDMA2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 2535 mask |= 1U << ((mmDMA2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 2536 mask |= 1U << ((mmDMA2_QM_CP_DBG_0_0 & 0x7F) >> 2); 2537 mask |= 1U << ((mmDMA2_QM_CP_DBG_0_1 & 0x7F) >> 2); 2538 2539 WREG32(pb_addr + word_offset, ~mask); 2540 2541 pb_addr = (mmDMA2_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 2542 word_offset = ((mmDMA2_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 2543 mask = 1U << ((mmDMA2_QM_CP_DBG_0_2 & 0x7F) >> 2); 2544 mask |= 1U << ((mmDMA2_QM_CP_DBG_0_3 & 0x7F) >> 2); 2545 mask |= 1U << ((mmDMA2_QM_CP_DBG_0_4 & 0x7F) >> 2); 2546 mask |= 1U << ((mmDMA2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 2547 mask |= 1U << ((mmDMA2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 2548 mask |= 1U << ((mmDMA2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 2549 mask |= 1U << ((mmDMA2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 2550 mask |= 1U << ((mmDMA2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 2551 mask |= 1U << ((mmDMA2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 2552 mask |= 1U << ((mmDMA2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 2553 mask |= 1U << ((mmDMA2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 2554 mask |= 1U << ((mmDMA2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 2555 mask |= 1U << ((mmDMA2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 2556 2557 WREG32(pb_addr + word_offset, ~mask); 2558 2559 pb_addr = (mmDMA2_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 2560 word_offset = ((mmDMA2_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 2561 mask = 1U << ((mmDMA2_QM_ARB_CFG_1 & 0x7F) >> 2); 2562 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 2563 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 2564 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 2565 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 2566 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 2567 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 2568 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 2569 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 2570 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 2571 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 2572 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 2573 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 2574 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 2575 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 2576 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 2577 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 2578 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 2579 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 2580 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 2581 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 2582 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 2583 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 2584 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 2585 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 2586 2587 WREG32(pb_addr + word_offset, ~mask); 2588 2589 pb_addr = (mmDMA2_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 2590 word_offset = ((mmDMA2_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 2591 << 2; 2592 mask = 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 2593 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 2594 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 2595 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 2596 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 2597 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 2598 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 2599 mask |= 1U << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 2600 2601 WREG32(pb_addr + word_offset, ~mask); 2602 2603 pb_addr = (mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 2604 PROT_BITS_OFFS; 2605 word_offset = 2606 ((mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) 2607 << 2; 2608 mask = 1U << ((mmDMA2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 2609 mask |= 1U << ((mmDMA2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 2610 mask |= 1U << ((mmDMA2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 2611 mask |= 1U << ((mmDMA2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 2612 mask |= 1U << ((mmDMA2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 2613 2614 WREG32(pb_addr + word_offset, ~mask); 2615 2616 pb_addr = (mmDMA2_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 2617 word_offset = ((mmDMA2_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 2618 mask = 1U << ((mmDMA2_QM_ARB_STATE_STS & 0x7F) >> 2); 2619 mask |= 1U << ((mmDMA2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 2620 mask |= 1U << ((mmDMA2_QM_ARB_MSG_STS & 0x7F) >> 2); 2621 mask |= 1U << ((mmDMA2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 2622 mask |= 1U << ((mmDMA2_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 2623 mask |= 1U << ((mmDMA2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 2624 mask |= 1U << ((mmDMA2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 2625 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 2626 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 2627 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 2628 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 2629 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 2630 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 2631 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 2632 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 2633 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 2634 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 2635 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 2636 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 2637 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 2638 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 2639 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 2640 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 2641 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 2642 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 2643 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 2644 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 2645 2646 WREG32(pb_addr + word_offset, ~mask); 2647 2648 pb_addr = (mmDMA2_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 2649 word_offset = ((mmDMA2_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 2650 << 2; 2651 mask = 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 2652 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 2653 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 2654 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 2655 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 2656 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 2657 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 2658 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 2659 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 2660 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 2661 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 2662 mask |= 1U << ((mmDMA2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 2663 mask |= 1U << ((mmDMA2_QM_CGM_CFG & 0x7F) >> 2); 2664 mask |= 1U << ((mmDMA2_QM_CGM_STS & 0x7F) >> 2); 2665 mask |= 1U << ((mmDMA2_QM_CGM_CFG1 & 0x7F) >> 2); 2666 2667 WREG32(pb_addr + word_offset, ~mask); 2668 2669 pb_addr = (mmDMA2_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 2670 word_offset = ((mmDMA2_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 2671 mask = 1U << ((mmDMA2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 2672 mask |= 1U << ((mmDMA2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 2673 mask |= 1U << ((mmDMA2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 2674 mask |= 1U << ((mmDMA2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 2675 mask |= 1U << ((mmDMA2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 2676 mask |= 1U << ((mmDMA2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 2677 mask |= 1U << ((mmDMA2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 2678 mask |= 1U << ((mmDMA2_QM_GLBL_AXCACHE & 0x7F) >> 2); 2679 mask |= 1U << ((mmDMA2_QM_IND_GW_APB_CFG & 0x7F) >> 2); 2680 mask |= 1U << ((mmDMA2_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 2681 mask |= 1U << ((mmDMA2_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 2682 mask |= 1U << ((mmDMA2_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 2683 mask |= 1U << ((mmDMA2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 2684 mask |= 1U << ((mmDMA2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 2685 mask |= 1U << ((mmDMA2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 2686 2687 WREG32(pb_addr + word_offset, ~mask); 2688 2689 pb_addr = (mmDMA2_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 2690 word_offset = ((mmDMA2_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 2691 << 2; 2692 mask = 1U << ((mmDMA2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 2693 2694 WREG32(pb_addr + word_offset, ~mask); 2695 2696 pb_addr = (mmDMA3_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 2697 word_offset = ((mmDMA3_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 2698 mask = 1U << ((mmDMA3_QM_GLBL_CFG0 & 0x7F) >> 2); 2699 mask |= 1U << ((mmDMA3_QM_GLBL_CFG1 & 0x7F) >> 2); 2700 mask |= 1U << ((mmDMA3_QM_GLBL_PROT & 0x7F) >> 2); 2701 mask |= 1U << ((mmDMA3_QM_GLBL_ERR_CFG & 0x7F) >> 2); 2702 mask |= 1U << ((mmDMA3_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 2703 mask |= 1U << ((mmDMA3_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 2704 mask |= 1U << ((mmDMA3_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 2705 mask |= 1U << ((mmDMA3_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 2706 mask |= 1U << ((mmDMA3_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 2707 mask |= 1U << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 2708 mask |= 1U << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 2709 mask |= 1U << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 2710 mask |= 1U << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 2711 mask |= 1U << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 2712 mask |= 1U << ((mmDMA3_QM_GLBL_STS0 & 0x7F) >> 2); 2713 mask |= 1U << ((mmDMA3_QM_GLBL_STS1_0 & 0x7F) >> 2); 2714 mask |= 1U << ((mmDMA3_QM_GLBL_STS1_1 & 0x7F) >> 2); 2715 mask |= 1U << ((mmDMA3_QM_GLBL_STS1_2 & 0x7F) >> 2); 2716 mask |= 1U << ((mmDMA3_QM_GLBL_STS1_3 & 0x7F) >> 2); 2717 mask |= 1U << ((mmDMA3_QM_GLBL_STS1_4 & 0x7F) >> 2); 2718 mask |= 1U << ((mmDMA3_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 2719 mask |= 1U << ((mmDMA3_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 2720 mask |= 1U << ((mmDMA3_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 2721 mask |= 1U << ((mmDMA3_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 2722 mask |= 1U << ((mmDMA3_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 2723 mask |= 1U << ((mmDMA3_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 2724 mask |= 1U << ((mmDMA3_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 2725 mask |= 1U << ((mmDMA3_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 2726 mask |= 1U << ((mmDMA3_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 2727 2728 WREG32(pb_addr + word_offset, ~mask); 2729 2730 pb_addr = (mmDMA3_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 2731 word_offset = ((mmDMA3_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 2732 mask = 1U << ((mmDMA3_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 2733 mask |= 1U << ((mmDMA3_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 2734 mask |= 1U << ((mmDMA3_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 2735 mask |= 1U << ((mmDMA3_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 2736 mask |= 1U << ((mmDMA3_QM_PQ_SIZE_0 & 0x7F) >> 2); 2737 mask |= 1U << ((mmDMA3_QM_PQ_SIZE_1 & 0x7F) >> 2); 2738 mask |= 1U << ((mmDMA3_QM_PQ_SIZE_2 & 0x7F) >> 2); 2739 mask |= 1U << ((mmDMA3_QM_PQ_SIZE_3 & 0x7F) >> 2); 2740 mask |= 1U << ((mmDMA3_QM_PQ_PI_0 & 0x7F) >> 2); 2741 mask |= 1U << ((mmDMA3_QM_PQ_PI_1 & 0x7F) >> 2); 2742 mask |= 1U << ((mmDMA3_QM_PQ_PI_2 & 0x7F) >> 2); 2743 mask |= 1U << ((mmDMA3_QM_PQ_PI_3 & 0x7F) >> 2); 2744 mask |= 1U << ((mmDMA3_QM_PQ_CI_0 & 0x7F) >> 2); 2745 mask |= 1U << ((mmDMA3_QM_PQ_CI_1 & 0x7F) >> 2); 2746 mask |= 1U << ((mmDMA3_QM_PQ_CI_2 & 0x7F) >> 2); 2747 mask |= 1U << ((mmDMA3_QM_PQ_CI_3 & 0x7F) >> 2); 2748 mask |= 1U << ((mmDMA3_QM_PQ_CFG0_0 & 0x7F) >> 2); 2749 mask |= 1U << ((mmDMA3_QM_PQ_CFG0_1 & 0x7F) >> 2); 2750 mask |= 1U << ((mmDMA3_QM_PQ_CFG0_2 & 0x7F) >> 2); 2751 mask |= 1U << ((mmDMA3_QM_PQ_CFG0_3 & 0x7F) >> 2); 2752 mask |= 1U << ((mmDMA3_QM_PQ_CFG1_0 & 0x7F) >> 2); 2753 mask |= 1U << ((mmDMA3_QM_PQ_CFG1_1 & 0x7F) >> 2); 2754 mask |= 1U << ((mmDMA3_QM_PQ_CFG1_2 & 0x7F) >> 2); 2755 mask |= 1U << ((mmDMA3_QM_PQ_CFG1_3 & 0x7F) >> 2); 2756 mask |= 1U << ((mmDMA3_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 2757 mask |= 1U << ((mmDMA3_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 2758 mask |= 1U << ((mmDMA3_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 2759 mask |= 1U << ((mmDMA3_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 2760 mask |= 1U << ((mmDMA3_QM_PQ_STS0_0 & 0x7F) >> 2); 2761 mask |= 1U << ((mmDMA3_QM_PQ_STS0_1 & 0x7F) >> 2); 2762 mask |= 1U << ((mmDMA3_QM_PQ_STS0_2 & 0x7F) >> 2); 2763 mask |= 1U << ((mmDMA3_QM_PQ_STS0_3 & 0x7F) >> 2); 2764 2765 WREG32(pb_addr + word_offset, ~mask); 2766 2767 pb_addr = (mmDMA3_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 2768 word_offset = ((mmDMA3_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 2769 mask = 1U << ((mmDMA3_QM_PQ_STS1_0 & 0x7F) >> 2); 2770 mask |= 1U << ((mmDMA3_QM_PQ_STS1_1 & 0x7F) >> 2); 2771 mask |= 1U << ((mmDMA3_QM_PQ_STS1_2 & 0x7F) >> 2); 2772 mask |= 1U << ((mmDMA3_QM_PQ_STS1_3 & 0x7F) >> 2); 2773 mask |= 1U << ((mmDMA3_QM_CQ_STS0_0 & 0x7F) >> 2); 2774 mask |= 1U << ((mmDMA3_QM_CQ_STS0_1 & 0x7F) >> 2); 2775 mask |= 1U << ((mmDMA3_QM_CQ_STS0_2 & 0x7F) >> 2); 2776 mask |= 1U << ((mmDMA3_QM_CQ_STS0_3 & 0x7F) >> 2); 2777 mask |= 1U << ((mmDMA3_QM_CQ_STS1_0 & 0x7F) >> 2); 2778 mask |= 1U << ((mmDMA3_QM_CQ_STS1_1 & 0x7F) >> 2); 2779 mask |= 1U << ((mmDMA3_QM_CQ_STS1_2 & 0x7F) >> 2); 2780 mask |= 1U << ((mmDMA3_QM_CQ_STS1_3 & 0x7F) >> 2); 2781 mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 2782 mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 2783 mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_0 & 0x7F) >> 2); 2784 2785 WREG32(pb_addr + word_offset, ~mask); 2786 2787 pb_addr = (mmDMA3_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 2788 word_offset = ((mmDMA3_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 2789 mask = 1U << ((mmDMA3_QM_CQ_CTL_0 & 0x7F) >> 2); 2790 mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 2791 mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 2792 mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_1 & 0x7F) >> 2); 2793 mask |= 1U << ((mmDMA3_QM_CQ_CTL_1 & 0x7F) >> 2); 2794 mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 2795 mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 2796 mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_2 & 0x7F) >> 2); 2797 mask |= 1U << ((mmDMA3_QM_CQ_CTL_2 & 0x7F) >> 2); 2798 mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 2799 mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 2800 mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_3 & 0x7F) >> 2); 2801 mask |= 1U << ((mmDMA3_QM_CQ_CTL_3 & 0x7F) >> 2); 2802 mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 2803 mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 2804 mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 2805 mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 2806 mask |= 1U << ((mmDMA3_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 2807 mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 2808 mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 2809 mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 2810 mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 2811 mask |= 1U << ((mmDMA3_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 2812 mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 2813 mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 2814 mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 2815 mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 2816 mask |= 1U << ((mmDMA3_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 2817 2818 WREG32(pb_addr + word_offset, ~mask); 2819 2820 pb_addr = (mmDMA3_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 2821 word_offset = ((mmDMA3_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 2822 mask = 1U << ((mmDMA3_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 2823 mask |= 1U << ((mmDMA3_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 2824 mask |= 1U << ((mmDMA3_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 2825 mask |= 1U << ((mmDMA3_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 2826 mask |= 1U << ((mmDMA3_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 2827 mask |= 1U << ((mmDMA3_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 2828 mask |= 1U << ((mmDMA3_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 2829 mask |= 1U << ((mmDMA3_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 2830 mask |= 1U << ((mmDMA3_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 2831 mask |= 1U << ((mmDMA3_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 2832 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 2833 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 2834 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 2835 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 2836 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 2837 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 2838 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 2839 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 2840 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 2841 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 2842 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 2843 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 2844 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 2845 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 2846 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 2847 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 2848 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 2849 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 2850 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 2851 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 2852 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 2853 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 2854 2855 WREG32(pb_addr + word_offset, ~mask); 2856 2857 pb_addr = (mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 2858 word_offset = ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 2859 << 2; 2860 mask = 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 2861 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 2862 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 2863 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 2864 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 2865 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 2866 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 2867 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 2868 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 2869 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 2870 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 2871 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 2872 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 2873 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 2874 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 2875 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 2876 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 2877 mask |= 1U << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 2878 mask |= 1U << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 2879 mask |= 1U << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 2880 mask |= 1U << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 2881 mask |= 1U << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 2882 mask |= 1U << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 2883 mask |= 1U << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 2884 mask |= 1U << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 2885 mask |= 1U << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 2886 mask |= 1U << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 2887 mask |= 1U << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 2888 mask |= 1U << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 2889 mask |= 1U << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 2890 mask |= 1U << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 2891 2892 WREG32(pb_addr + word_offset, ~mask); 2893 2894 pb_addr = (mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 2895 PROT_BITS_OFFS; 2896 word_offset = 2897 ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) 2898 << 2; 2899 mask = 1U << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 2900 mask |= 1U << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 2901 2902 WREG32(pb_addr + word_offset, ~mask); 2903 2904 pb_addr = (mmDMA3_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 2905 word_offset = ((mmDMA3_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 2906 mask = 1U << ((mmDMA3_QM_CP_STS_0 & 0x7F) >> 2); 2907 mask |= 1U << ((mmDMA3_QM_CP_STS_1 & 0x7F) >> 2); 2908 mask |= 1U << ((mmDMA3_QM_CP_STS_2 & 0x7F) >> 2); 2909 mask |= 1U << ((mmDMA3_QM_CP_STS_3 & 0x7F) >> 2); 2910 mask |= 1U << ((mmDMA3_QM_CP_STS_4 & 0x7F) >> 2); 2911 mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 2912 mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 2913 mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 2914 mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 2915 mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 2916 mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 2917 mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 2918 mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 2919 mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 2920 mask |= 1U << ((mmDMA3_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 2921 mask |= 1U << ((mmDMA3_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 2922 mask |= 1U << ((mmDMA3_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 2923 mask |= 1U << ((mmDMA3_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 2924 2925 WREG32(pb_addr + word_offset, ~mask); 2926 2927 pb_addr = (mmDMA3_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 2928 word_offset = ((mmDMA3_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 2929 mask = 1U << ((mmDMA3_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 2930 mask |= 1U << ((mmDMA3_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 2931 mask |= 1U << ((mmDMA3_QM_CP_DBG_0_0 & 0x7F) >> 2); 2932 mask |= 1U << ((mmDMA3_QM_CP_DBG_0_1 & 0x7F) >> 2); 2933 2934 WREG32(pb_addr + word_offset, ~mask); 2935 2936 pb_addr = (mmDMA3_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 2937 word_offset = ((mmDMA3_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 2938 mask = 1U << ((mmDMA3_QM_CP_DBG_0_2 & 0x7F) >> 2); 2939 mask |= 1U << ((mmDMA3_QM_CP_DBG_0_3 & 0x7F) >> 2); 2940 mask |= 1U << ((mmDMA3_QM_CP_DBG_0_4 & 0x7F) >> 2); 2941 mask |= 1U << ((mmDMA3_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 2942 mask |= 1U << ((mmDMA3_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 2943 mask |= 1U << ((mmDMA3_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 2944 mask |= 1U << ((mmDMA3_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 2945 mask |= 1U << ((mmDMA3_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 2946 mask |= 1U << ((mmDMA3_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 2947 mask |= 1U << ((mmDMA3_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 2948 mask |= 1U << ((mmDMA3_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 2949 mask |= 1U << ((mmDMA3_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 2950 mask |= 1U << ((mmDMA3_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 2951 2952 WREG32(pb_addr + word_offset, ~mask); 2953 2954 pb_addr = (mmDMA3_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 2955 word_offset = ((mmDMA3_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 2956 mask = 1U << ((mmDMA3_QM_ARB_CFG_1 & 0x7F) >> 2); 2957 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 2958 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 2959 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 2960 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 2961 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 2962 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 2963 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 2964 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 2965 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 2966 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 2967 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 2968 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 2969 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 2970 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 2971 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 2972 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 2973 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 2974 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 2975 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 2976 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 2977 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 2978 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 2979 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 2980 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 2981 2982 WREG32(pb_addr + word_offset, ~mask); 2983 2984 pb_addr = (mmDMA3_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 2985 word_offset = ((mmDMA3_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 2986 << 2; 2987 mask = 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 2988 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 2989 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 2990 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 2991 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 2992 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 2993 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 2994 mask |= 1U << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 2995 2996 WREG32(pb_addr + word_offset, ~mask); 2997 2998 pb_addr = (mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 2999 PROT_BITS_OFFS; 3000 word_offset = 3001 ((mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) 3002 << 2; 3003 mask = 1U << ((mmDMA3_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 3004 mask |= 1U << ((mmDMA3_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 3005 mask |= 1U << ((mmDMA3_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 3006 mask |= 1U << ((mmDMA3_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 3007 mask |= 1U << ((mmDMA3_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 3008 3009 WREG32(pb_addr + word_offset, ~mask); 3010 3011 pb_addr = (mmDMA3_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 3012 word_offset = ((mmDMA3_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 3013 mask = 1U << ((mmDMA3_QM_ARB_STATE_STS & 0x7F) >> 2); 3014 mask |= 1U << ((mmDMA3_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 3015 mask |= 1U << ((mmDMA3_QM_ARB_MSG_STS & 0x7F) >> 2); 3016 mask |= 1U << ((mmDMA3_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 3017 mask |= 1U << ((mmDMA3_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 3018 mask |= 1U << ((mmDMA3_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 3019 mask |= 1U << ((mmDMA3_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 3020 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 3021 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 3022 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 3023 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 3024 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 3025 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 3026 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 3027 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 3028 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 3029 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 3030 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 3031 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 3032 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 3033 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 3034 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 3035 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 3036 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 3037 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 3038 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 3039 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 3040 3041 WREG32(pb_addr + word_offset, ~mask); 3042 3043 pb_addr = (mmDMA3_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 3044 word_offset = ((mmDMA3_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 3045 << 2; 3046 mask = 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 3047 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 3048 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 3049 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 3050 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 3051 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 3052 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 3053 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 3054 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 3055 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 3056 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 3057 mask |= 1U << ((mmDMA3_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 3058 mask |= 1U << ((mmDMA3_QM_CGM_CFG & 0x7F) >> 2); 3059 mask |= 1U << ((mmDMA3_QM_CGM_STS & 0x7F) >> 2); 3060 mask |= 1U << ((mmDMA3_QM_CGM_CFG1 & 0x7F) >> 2); 3061 3062 WREG32(pb_addr + word_offset, ~mask); 3063 3064 pb_addr = (mmDMA3_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 3065 word_offset = ((mmDMA3_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 3066 mask = 1U << ((mmDMA3_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 3067 mask |= 1U << ((mmDMA3_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 3068 mask |= 1U << ((mmDMA3_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 3069 mask |= 1U << ((mmDMA3_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 3070 mask |= 1U << ((mmDMA3_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 3071 mask |= 1U << ((mmDMA3_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 3072 mask |= 1U << ((mmDMA3_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 3073 mask |= 1U << ((mmDMA3_QM_GLBL_AXCACHE & 0x7F) >> 2); 3074 mask |= 1U << ((mmDMA3_QM_IND_GW_APB_CFG & 0x7F) >> 2); 3075 mask |= 1U << ((mmDMA3_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 3076 mask |= 1U << ((mmDMA3_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 3077 mask |= 1U << ((mmDMA3_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 3078 mask |= 1U << ((mmDMA3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 3079 mask |= 1U << ((mmDMA3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 3080 mask |= 1U << ((mmDMA3_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 3081 3082 WREG32(pb_addr + word_offset, ~mask); 3083 3084 pb_addr = (mmDMA3_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 3085 word_offset = ((mmDMA3_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 3086 << 2; 3087 mask = 1U << ((mmDMA3_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 3088 3089 WREG32(pb_addr + word_offset, ~mask); 3090 3091 pb_addr = (mmDMA4_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 3092 word_offset = ((mmDMA4_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 3093 mask = 1U << ((mmDMA4_QM_GLBL_CFG0 & 0x7F) >> 2); 3094 mask |= 1U << ((mmDMA4_QM_GLBL_CFG1 & 0x7F) >> 2); 3095 mask |= 1U << ((mmDMA4_QM_GLBL_PROT & 0x7F) >> 2); 3096 mask |= 1U << ((mmDMA4_QM_GLBL_ERR_CFG & 0x7F) >> 2); 3097 mask |= 1U << ((mmDMA4_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 3098 mask |= 1U << ((mmDMA4_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 3099 mask |= 1U << ((mmDMA4_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 3100 mask |= 1U << ((mmDMA4_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 3101 mask |= 1U << ((mmDMA4_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 3102 mask |= 1U << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 3103 mask |= 1U << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 3104 mask |= 1U << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 3105 mask |= 1U << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 3106 mask |= 1U << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 3107 mask |= 1U << ((mmDMA4_QM_GLBL_STS0 & 0x7F) >> 2); 3108 mask |= 1U << ((mmDMA4_QM_GLBL_STS1_0 & 0x7F) >> 2); 3109 mask |= 1U << ((mmDMA4_QM_GLBL_STS1_1 & 0x7F) >> 2); 3110 mask |= 1U << ((mmDMA4_QM_GLBL_STS1_2 & 0x7F) >> 2); 3111 mask |= 1U << ((mmDMA4_QM_GLBL_STS1_3 & 0x7F) >> 2); 3112 mask |= 1U << ((mmDMA4_QM_GLBL_STS1_4 & 0x7F) >> 2); 3113 mask |= 1U << ((mmDMA4_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 3114 mask |= 1U << ((mmDMA4_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 3115 mask |= 1U << ((mmDMA4_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 3116 mask |= 1U << ((mmDMA4_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 3117 mask |= 1U << ((mmDMA4_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 3118 mask |= 1U << ((mmDMA4_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 3119 mask |= 1U << ((mmDMA4_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 3120 mask |= 1U << ((mmDMA4_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 3121 mask |= 1U << ((mmDMA4_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 3122 3123 WREG32(pb_addr + word_offset, ~mask); 3124 3125 pb_addr = (mmDMA4_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 3126 word_offset = ((mmDMA4_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 3127 mask = 1U << ((mmDMA4_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 3128 mask |= 1U << ((mmDMA4_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 3129 mask |= 1U << ((mmDMA4_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 3130 mask |= 1U << ((mmDMA4_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 3131 mask |= 1U << ((mmDMA4_QM_PQ_SIZE_0 & 0x7F) >> 2); 3132 mask |= 1U << ((mmDMA4_QM_PQ_SIZE_1 & 0x7F) >> 2); 3133 mask |= 1U << ((mmDMA4_QM_PQ_SIZE_2 & 0x7F) >> 2); 3134 mask |= 1U << ((mmDMA4_QM_PQ_SIZE_3 & 0x7F) >> 2); 3135 mask |= 1U << ((mmDMA4_QM_PQ_PI_0 & 0x7F) >> 2); 3136 mask |= 1U << ((mmDMA4_QM_PQ_PI_1 & 0x7F) >> 2); 3137 mask |= 1U << ((mmDMA4_QM_PQ_PI_2 & 0x7F) >> 2); 3138 mask |= 1U << ((mmDMA4_QM_PQ_PI_3 & 0x7F) >> 2); 3139 mask |= 1U << ((mmDMA4_QM_PQ_CI_0 & 0x7F) >> 2); 3140 mask |= 1U << ((mmDMA4_QM_PQ_CI_1 & 0x7F) >> 2); 3141 mask |= 1U << ((mmDMA4_QM_PQ_CI_2 & 0x7F) >> 2); 3142 mask |= 1U << ((mmDMA4_QM_PQ_CI_3 & 0x7F) >> 2); 3143 mask |= 1U << ((mmDMA4_QM_PQ_CFG0_0 & 0x7F) >> 2); 3144 mask |= 1U << ((mmDMA4_QM_PQ_CFG0_1 & 0x7F) >> 2); 3145 mask |= 1U << ((mmDMA4_QM_PQ_CFG0_2 & 0x7F) >> 2); 3146 mask |= 1U << ((mmDMA4_QM_PQ_CFG0_3 & 0x7F) >> 2); 3147 mask |= 1U << ((mmDMA4_QM_PQ_CFG1_0 & 0x7F) >> 2); 3148 mask |= 1U << ((mmDMA4_QM_PQ_CFG1_1 & 0x7F) >> 2); 3149 mask |= 1U << ((mmDMA4_QM_PQ_CFG1_2 & 0x7F) >> 2); 3150 mask |= 1U << ((mmDMA4_QM_PQ_CFG1_3 & 0x7F) >> 2); 3151 mask |= 1U << ((mmDMA4_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 3152 mask |= 1U << ((mmDMA4_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 3153 mask |= 1U << ((mmDMA4_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 3154 mask |= 1U << ((mmDMA4_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 3155 mask |= 1U << ((mmDMA4_QM_PQ_STS0_0 & 0x7F) >> 2); 3156 mask |= 1U << ((mmDMA4_QM_PQ_STS0_1 & 0x7F) >> 2); 3157 mask |= 1U << ((mmDMA4_QM_PQ_STS0_2 & 0x7F) >> 2); 3158 mask |= 1U << ((mmDMA4_QM_PQ_STS0_3 & 0x7F) >> 2); 3159 3160 WREG32(pb_addr + word_offset, ~mask); 3161 3162 pb_addr = (mmDMA4_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 3163 word_offset = ((mmDMA4_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 3164 mask = 1U << ((mmDMA4_QM_PQ_STS1_0 & 0x7F) >> 2); 3165 mask |= 1U << ((mmDMA4_QM_PQ_STS1_1 & 0x7F) >> 2); 3166 mask |= 1U << ((mmDMA4_QM_PQ_STS1_2 & 0x7F) >> 2); 3167 mask |= 1U << ((mmDMA4_QM_PQ_STS1_3 & 0x7F) >> 2); 3168 mask |= 1U << ((mmDMA4_QM_CQ_STS0_0 & 0x7F) >> 2); 3169 mask |= 1U << ((mmDMA4_QM_CQ_STS0_1 & 0x7F) >> 2); 3170 mask |= 1U << ((mmDMA4_QM_CQ_STS0_2 & 0x7F) >> 2); 3171 mask |= 1U << ((mmDMA4_QM_CQ_STS0_3 & 0x7F) >> 2); 3172 mask |= 1U << ((mmDMA4_QM_CQ_STS1_0 & 0x7F) >> 2); 3173 mask |= 1U << ((mmDMA4_QM_CQ_STS1_1 & 0x7F) >> 2); 3174 mask |= 1U << ((mmDMA4_QM_CQ_STS1_2 & 0x7F) >> 2); 3175 mask |= 1U << ((mmDMA4_QM_CQ_STS1_3 & 0x7F) >> 2); 3176 mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 3177 mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 3178 mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_0 & 0x7F) >> 2); 3179 3180 WREG32(pb_addr + word_offset, ~mask); 3181 3182 pb_addr = (mmDMA4_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 3183 word_offset = ((mmDMA4_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 3184 mask = 1U << ((mmDMA4_QM_CQ_CTL_0 & 0x7F) >> 2); 3185 mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 3186 mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 3187 mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_1 & 0x7F) >> 2); 3188 mask |= 1U << ((mmDMA4_QM_CQ_CTL_1 & 0x7F) >> 2); 3189 mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 3190 mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 3191 mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_2 & 0x7F) >> 2); 3192 mask |= 1U << ((mmDMA4_QM_CQ_CTL_2 & 0x7F) >> 2); 3193 mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 3194 mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 3195 mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_3 & 0x7F) >> 2); 3196 mask |= 1U << ((mmDMA4_QM_CQ_CTL_3 & 0x7F) >> 2); 3197 mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 3198 mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 3199 mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 3200 mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 3201 mask |= 1U << ((mmDMA4_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 3202 mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 3203 mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 3204 mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 3205 mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 3206 mask |= 1U << ((mmDMA4_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 3207 mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 3208 mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 3209 mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 3210 mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 3211 mask |= 1U << ((mmDMA4_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 3212 3213 WREG32(pb_addr + word_offset, ~mask); 3214 3215 pb_addr = (mmDMA4_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 3216 word_offset = ((mmDMA4_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 3217 mask = 1U << ((mmDMA4_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 3218 mask |= 1U << ((mmDMA4_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 3219 mask |= 1U << ((mmDMA4_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 3220 mask |= 1U << ((mmDMA4_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 3221 mask |= 1U << ((mmDMA4_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 3222 mask |= 1U << ((mmDMA4_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 3223 mask |= 1U << ((mmDMA4_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 3224 mask |= 1U << ((mmDMA4_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 3225 mask |= 1U << ((mmDMA4_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 3226 mask |= 1U << ((mmDMA4_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 3227 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 3228 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 3229 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 3230 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 3231 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 3232 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 3233 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 3234 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 3235 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 3236 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 3237 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 3238 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 3239 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 3240 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 3241 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 3242 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 3243 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 3244 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 3245 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 3246 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 3247 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 3248 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 3249 3250 WREG32(pb_addr + word_offset, ~mask); 3251 3252 pb_addr = (mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 3253 word_offset = ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 3254 << 2; 3255 mask = 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 3256 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 3257 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 3258 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 3259 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 3260 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 3261 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 3262 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 3263 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 3264 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 3265 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 3266 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 3267 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 3268 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 3269 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 3270 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 3271 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 3272 mask |= 1U << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 3273 mask |= 1U << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 3274 mask |= 1U << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 3275 mask |= 1U << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 3276 mask |= 1U << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 3277 mask |= 1U << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 3278 mask |= 1U << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 3279 mask |= 1U << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 3280 mask |= 1U << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 3281 mask |= 1U << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 3282 mask |= 1U << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 3283 mask |= 1U << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 3284 mask |= 1U << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 3285 mask |= 1U << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 3286 3287 WREG32(pb_addr + word_offset, ~mask); 3288 3289 pb_addr = (mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 3290 PROT_BITS_OFFS; 3291 word_offset = 3292 ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) 3293 << 2; 3294 mask = 1U << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 3295 mask |= 1U << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 3296 3297 WREG32(pb_addr + word_offset, ~mask); 3298 3299 pb_addr = (mmDMA4_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 3300 word_offset = ((mmDMA4_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 3301 mask = 1U << ((mmDMA4_QM_CP_STS_0 & 0x7F) >> 2); 3302 mask |= 1U << ((mmDMA4_QM_CP_STS_1 & 0x7F) >> 2); 3303 mask |= 1U << ((mmDMA4_QM_CP_STS_2 & 0x7F) >> 2); 3304 mask |= 1U << ((mmDMA4_QM_CP_STS_3 & 0x7F) >> 2); 3305 mask |= 1U << ((mmDMA4_QM_CP_STS_4 & 0x7F) >> 2); 3306 mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 3307 mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 3308 mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 3309 mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 3310 mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 3311 mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 3312 mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 3313 mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 3314 mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 3315 mask |= 1U << ((mmDMA4_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 3316 mask |= 1U << ((mmDMA4_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 3317 mask |= 1U << ((mmDMA4_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 3318 mask |= 1U << ((mmDMA4_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 3319 3320 WREG32(pb_addr + word_offset, ~mask); 3321 3322 pb_addr = (mmDMA4_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 3323 word_offset = ((mmDMA4_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 3324 mask = 1U << ((mmDMA4_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 3325 mask |= 1U << ((mmDMA4_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 3326 mask |= 1U << ((mmDMA4_QM_CP_DBG_0_0 & 0x7F) >> 2); 3327 mask |= 1U << ((mmDMA4_QM_CP_DBG_0_1 & 0x7F) >> 2); 3328 3329 WREG32(pb_addr + word_offset, ~mask); 3330 3331 pb_addr = (mmDMA4_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 3332 word_offset = ((mmDMA4_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 3333 mask = 1U << ((mmDMA4_QM_CP_DBG_0_2 & 0x7F) >> 2); 3334 mask |= 1U << ((mmDMA4_QM_CP_DBG_0_3 & 0x7F) >> 2); 3335 mask |= 1U << ((mmDMA4_QM_CP_DBG_0_4 & 0x7F) >> 2); 3336 mask |= 1U << ((mmDMA4_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 3337 mask |= 1U << ((mmDMA4_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 3338 mask |= 1U << ((mmDMA4_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 3339 mask |= 1U << ((mmDMA4_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 3340 mask |= 1U << ((mmDMA4_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 3341 mask |= 1U << ((mmDMA4_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 3342 mask |= 1U << ((mmDMA4_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 3343 mask |= 1U << ((mmDMA4_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 3344 mask |= 1U << ((mmDMA4_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 3345 mask |= 1U << ((mmDMA4_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 3346 3347 WREG32(pb_addr + word_offset, ~mask); 3348 3349 pb_addr = (mmDMA4_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 3350 word_offset = ((mmDMA4_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 3351 mask = 1U << ((mmDMA4_QM_ARB_CFG_1 & 0x7F) >> 2); 3352 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 3353 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 3354 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 3355 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 3356 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 3357 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 3358 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 3359 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 3360 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 3361 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 3362 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 3363 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 3364 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 3365 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 3366 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 3367 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 3368 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 3369 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 3370 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 3371 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 3372 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 3373 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 3374 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 3375 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 3376 3377 WREG32(pb_addr + word_offset, ~mask); 3378 3379 pb_addr = (mmDMA4_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 3380 word_offset = ((mmDMA4_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 3381 << 2; 3382 mask = 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 3383 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 3384 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 3385 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 3386 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 3387 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 3388 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 3389 mask |= 1U << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 3390 3391 WREG32(pb_addr + word_offset, ~mask); 3392 3393 pb_addr = (mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 3394 PROT_BITS_OFFS; 3395 word_offset = 3396 ((mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) 3397 << 2; 3398 mask = 1U << ((mmDMA4_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 3399 mask |= 1U << ((mmDMA4_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 3400 mask |= 1U << ((mmDMA4_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 3401 mask |= 1U << ((mmDMA4_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 3402 mask |= 1U << ((mmDMA4_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 3403 3404 WREG32(pb_addr + word_offset, ~mask); 3405 3406 pb_addr = (mmDMA4_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 3407 word_offset = ((mmDMA4_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 3408 mask = 1U << ((mmDMA4_QM_ARB_STATE_STS & 0x7F) >> 2); 3409 mask |= 1U << ((mmDMA4_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 3410 mask |= 1U << ((mmDMA4_QM_ARB_MSG_STS & 0x7F) >> 2); 3411 mask |= 1U << ((mmDMA4_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 3412 mask |= 1U << ((mmDMA4_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 3413 mask |= 1U << ((mmDMA4_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 3414 mask |= 1U << ((mmDMA4_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 3415 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 3416 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 3417 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 3418 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 3419 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 3420 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 3421 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 3422 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 3423 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 3424 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 3425 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 3426 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 3427 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 3428 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 3429 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 3430 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 3431 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 3432 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 3433 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 3434 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 3435 3436 WREG32(pb_addr + word_offset, ~mask); 3437 3438 pb_addr = (mmDMA4_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 3439 word_offset = ((mmDMA4_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 3440 << 2; 3441 mask = 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 3442 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 3443 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 3444 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 3445 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 3446 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 3447 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 3448 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 3449 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 3450 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 3451 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 3452 mask |= 1U << ((mmDMA4_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 3453 mask |= 1U << ((mmDMA4_QM_CGM_CFG & 0x7F) >> 2); 3454 mask |= 1U << ((mmDMA4_QM_CGM_STS & 0x7F) >> 2); 3455 mask |= 1U << ((mmDMA4_QM_CGM_CFG1 & 0x7F) >> 2); 3456 3457 WREG32(pb_addr + word_offset, ~mask); 3458 3459 pb_addr = (mmDMA4_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 3460 word_offset = ((mmDMA4_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 3461 mask = 1U << ((mmDMA4_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 3462 mask |= 1U << ((mmDMA4_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 3463 mask |= 1U << ((mmDMA4_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 3464 mask |= 1U << ((mmDMA4_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 3465 mask |= 1U << ((mmDMA4_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 3466 mask |= 1U << ((mmDMA4_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 3467 mask |= 1U << ((mmDMA4_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 3468 mask |= 1U << ((mmDMA4_QM_GLBL_AXCACHE & 0x7F) >> 2); 3469 mask |= 1U << ((mmDMA4_QM_IND_GW_APB_CFG & 0x7F) >> 2); 3470 mask |= 1U << ((mmDMA4_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 3471 mask |= 1U << ((mmDMA4_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 3472 mask |= 1U << ((mmDMA4_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 3473 mask |= 1U << ((mmDMA4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 3474 mask |= 1U << ((mmDMA4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 3475 mask |= 1U << ((mmDMA4_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 3476 3477 WREG32(pb_addr + word_offset, ~mask); 3478 3479 pb_addr = (mmDMA4_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 3480 word_offset = ((mmDMA4_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 3481 << 2; 3482 mask = 1U << ((mmDMA4_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 3483 3484 WREG32(pb_addr + word_offset, ~mask); 3485 3486 pb_addr = (mmDMA5_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 3487 word_offset = ((mmDMA5_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 3488 mask = 1U << ((mmDMA5_QM_GLBL_CFG0 & 0x7F) >> 2); 3489 mask |= 1U << ((mmDMA5_QM_GLBL_CFG1 & 0x7F) >> 2); 3490 mask |= 1U << ((mmDMA5_QM_GLBL_PROT & 0x7F) >> 2); 3491 mask |= 1U << ((mmDMA5_QM_GLBL_ERR_CFG & 0x7F) >> 2); 3492 mask |= 1U << ((mmDMA5_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 3493 mask |= 1U << ((mmDMA5_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 3494 mask |= 1U << ((mmDMA5_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 3495 mask |= 1U << ((mmDMA5_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 3496 mask |= 1U << ((mmDMA5_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 3497 mask |= 1U << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 3498 mask |= 1U << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 3499 mask |= 1U << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 3500 mask |= 1U << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 3501 mask |= 1U << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 3502 mask |= 1U << ((mmDMA5_QM_GLBL_STS0 & 0x7F) >> 2); 3503 mask |= 1U << ((mmDMA5_QM_GLBL_STS1_0 & 0x7F) >> 2); 3504 mask |= 1U << ((mmDMA5_QM_GLBL_STS1_1 & 0x7F) >> 2); 3505 mask |= 1U << ((mmDMA5_QM_GLBL_STS1_2 & 0x7F) >> 2); 3506 mask |= 1U << ((mmDMA5_QM_GLBL_STS1_3 & 0x7F) >> 2); 3507 mask |= 1U << ((mmDMA5_QM_GLBL_STS1_4 & 0x7F) >> 2); 3508 mask |= 1U << ((mmDMA5_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 3509 mask |= 1U << ((mmDMA5_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 3510 mask |= 1U << ((mmDMA5_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 3511 mask |= 1U << ((mmDMA5_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 3512 mask |= 1U << ((mmDMA5_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 3513 mask |= 1U << ((mmDMA5_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 3514 mask |= 1U << ((mmDMA5_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 3515 mask |= 1U << ((mmDMA5_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 3516 mask |= 1U << ((mmDMA5_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 3517 3518 WREG32(pb_addr + word_offset, ~mask); 3519 3520 pb_addr = (mmDMA5_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 3521 word_offset = ((mmDMA5_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 3522 mask = 1U << ((mmDMA5_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 3523 mask |= 1U << ((mmDMA5_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 3524 mask |= 1U << ((mmDMA5_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 3525 mask |= 1U << ((mmDMA5_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 3526 mask |= 1U << ((mmDMA5_QM_PQ_SIZE_0 & 0x7F) >> 2); 3527 mask |= 1U << ((mmDMA5_QM_PQ_SIZE_1 & 0x7F) >> 2); 3528 mask |= 1U << ((mmDMA5_QM_PQ_SIZE_2 & 0x7F) >> 2); 3529 mask |= 1U << ((mmDMA5_QM_PQ_SIZE_3 & 0x7F) >> 2); 3530 mask |= 1U << ((mmDMA5_QM_PQ_PI_0 & 0x7F) >> 2); 3531 mask |= 1U << ((mmDMA5_QM_PQ_PI_1 & 0x7F) >> 2); 3532 mask |= 1U << ((mmDMA5_QM_PQ_PI_2 & 0x7F) >> 2); 3533 mask |= 1U << ((mmDMA5_QM_PQ_PI_3 & 0x7F) >> 2); 3534 mask |= 1U << ((mmDMA5_QM_PQ_CI_0 & 0x7F) >> 2); 3535 mask |= 1U << ((mmDMA5_QM_PQ_CI_1 & 0x7F) >> 2); 3536 mask |= 1U << ((mmDMA5_QM_PQ_CI_2 & 0x7F) >> 2); 3537 mask |= 1U << ((mmDMA5_QM_PQ_CI_3 & 0x7F) >> 2); 3538 mask |= 1U << ((mmDMA5_QM_PQ_CFG0_0 & 0x7F) >> 2); 3539 mask |= 1U << ((mmDMA5_QM_PQ_CFG0_1 & 0x7F) >> 2); 3540 mask |= 1U << ((mmDMA5_QM_PQ_CFG0_2 & 0x7F) >> 2); 3541 mask |= 1U << ((mmDMA5_QM_PQ_CFG0_3 & 0x7F) >> 2); 3542 mask |= 1U << ((mmDMA5_QM_PQ_CFG1_0 & 0x7F) >> 2); 3543 mask |= 1U << ((mmDMA5_QM_PQ_CFG1_1 & 0x7F) >> 2); 3544 mask |= 1U << ((mmDMA5_QM_PQ_CFG1_2 & 0x7F) >> 2); 3545 mask |= 1U << ((mmDMA5_QM_PQ_CFG1_3 & 0x7F) >> 2); 3546 mask |= 1U << ((mmDMA5_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 3547 mask |= 1U << ((mmDMA5_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 3548 mask |= 1U << ((mmDMA5_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 3549 mask |= 1U << ((mmDMA5_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 3550 mask |= 1U << ((mmDMA5_QM_PQ_STS0_0 & 0x7F) >> 2); 3551 mask |= 1U << ((mmDMA5_QM_PQ_STS0_1 & 0x7F) >> 2); 3552 mask |= 1U << ((mmDMA5_QM_PQ_STS0_2 & 0x7F) >> 2); 3553 mask |= 1U << ((mmDMA5_QM_PQ_STS0_3 & 0x7F) >> 2); 3554 3555 WREG32(pb_addr + word_offset, ~mask); 3556 3557 pb_addr = (mmDMA5_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 3558 word_offset = ((mmDMA5_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 3559 mask = 1U << ((mmDMA5_QM_PQ_STS1_0 & 0x7F) >> 2); 3560 mask |= 1U << ((mmDMA5_QM_PQ_STS1_1 & 0x7F) >> 2); 3561 mask |= 1U << ((mmDMA5_QM_PQ_STS1_2 & 0x7F) >> 2); 3562 mask |= 1U << ((mmDMA5_QM_PQ_STS1_3 & 0x7F) >> 2); 3563 mask |= 1U << ((mmDMA5_QM_CQ_STS0_0 & 0x7F) >> 2); 3564 mask |= 1U << ((mmDMA5_QM_CQ_STS0_1 & 0x7F) >> 2); 3565 mask |= 1U << ((mmDMA5_QM_CQ_STS0_2 & 0x7F) >> 2); 3566 mask |= 1U << ((mmDMA5_QM_CQ_STS0_3 & 0x7F) >> 2); 3567 mask |= 1U << ((mmDMA5_QM_CQ_STS1_0 & 0x7F) >> 2); 3568 mask |= 1U << ((mmDMA5_QM_CQ_STS1_1 & 0x7F) >> 2); 3569 mask |= 1U << ((mmDMA5_QM_CQ_STS1_2 & 0x7F) >> 2); 3570 mask |= 1U << ((mmDMA5_QM_CQ_STS1_3 & 0x7F) >> 2); 3571 mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 3572 mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 3573 mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_0 & 0x7F) >> 2); 3574 3575 WREG32(pb_addr + word_offset, ~mask); 3576 3577 pb_addr = (mmDMA5_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 3578 word_offset = ((mmDMA5_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 3579 mask = 1U << ((mmDMA5_QM_CQ_CTL_0 & 0x7F) >> 2); 3580 mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 3581 mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 3582 mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_1 & 0x7F) >> 2); 3583 mask |= 1U << ((mmDMA5_QM_CQ_CTL_1 & 0x7F) >> 2); 3584 mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 3585 mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 3586 mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_2 & 0x7F) >> 2); 3587 mask |= 1U << ((mmDMA5_QM_CQ_CTL_2 & 0x7F) >> 2); 3588 mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 3589 mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 3590 mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_3 & 0x7F) >> 2); 3591 mask |= 1U << ((mmDMA5_QM_CQ_CTL_3 & 0x7F) >> 2); 3592 mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 3593 mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 3594 mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 3595 mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 3596 mask |= 1U << ((mmDMA5_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 3597 mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 3598 mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 3599 mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 3600 mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 3601 mask |= 1U << ((mmDMA5_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 3602 mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 3603 mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 3604 mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 3605 mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 3606 mask |= 1U << ((mmDMA5_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 3607 3608 WREG32(pb_addr + word_offset, ~mask); 3609 3610 pb_addr = (mmDMA5_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 3611 word_offset = ((mmDMA5_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 3612 mask = 1U << ((mmDMA5_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 3613 mask |= 1U << ((mmDMA5_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 3614 mask |= 1U << ((mmDMA5_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 3615 mask |= 1U << ((mmDMA5_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 3616 mask |= 1U << ((mmDMA5_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 3617 mask |= 1U << ((mmDMA5_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 3618 mask |= 1U << ((mmDMA5_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 3619 mask |= 1U << ((mmDMA5_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 3620 mask |= 1U << ((mmDMA5_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 3621 mask |= 1U << ((mmDMA5_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 3622 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 3623 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 3624 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 3625 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 3626 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 3627 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 3628 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 3629 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 3630 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 3631 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 3632 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 3633 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 3634 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 3635 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 3636 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 3637 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 3638 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 3639 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 3640 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 3641 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 3642 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 3643 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 3644 3645 WREG32(pb_addr + word_offset, ~mask); 3646 3647 pb_addr = (mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 3648 word_offset = ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 3649 << 2; 3650 mask = 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 3651 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 3652 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 3653 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 3654 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 3655 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 3656 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 3657 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 3658 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 3659 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 3660 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 3661 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 3662 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 3663 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 3664 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 3665 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 3666 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 3667 mask |= 1U << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 3668 mask |= 1U << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 3669 mask |= 1U << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 3670 mask |= 1U << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 3671 mask |= 1U << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 3672 mask |= 1U << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 3673 mask |= 1U << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 3674 mask |= 1U << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 3675 mask |= 1U << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 3676 mask |= 1U << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 3677 mask |= 1U << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 3678 mask |= 1U << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 3679 mask |= 1U << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 3680 mask |= 1U << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 3681 3682 WREG32(pb_addr + word_offset, ~mask); 3683 3684 pb_addr = (mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 3685 PROT_BITS_OFFS; 3686 word_offset = 3687 ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) 3688 << 2; 3689 mask = 1U << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 3690 mask |= 1U << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 3691 3692 WREG32(pb_addr + word_offset, ~mask); 3693 3694 pb_addr = (mmDMA5_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 3695 word_offset = ((mmDMA5_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 3696 mask = 1U << ((mmDMA5_QM_CP_STS_0 & 0x7F) >> 2); 3697 mask |= 1U << ((mmDMA5_QM_CP_STS_1 & 0x7F) >> 2); 3698 mask |= 1U << ((mmDMA5_QM_CP_STS_2 & 0x7F) >> 2); 3699 mask |= 1U << ((mmDMA5_QM_CP_STS_3 & 0x7F) >> 2); 3700 mask |= 1U << ((mmDMA5_QM_CP_STS_4 & 0x7F) >> 2); 3701 mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 3702 mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 3703 mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 3704 mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 3705 mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 3706 mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 3707 mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 3708 mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 3709 mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 3710 mask |= 1U << ((mmDMA5_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 3711 mask |= 1U << ((mmDMA5_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 3712 mask |= 1U << ((mmDMA5_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 3713 mask |= 1U << ((mmDMA5_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 3714 3715 WREG32(pb_addr + word_offset, ~mask); 3716 3717 pb_addr = (mmDMA5_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 3718 word_offset = ((mmDMA5_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 3719 mask = 1U << ((mmDMA5_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 3720 mask |= 1U << ((mmDMA5_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 3721 mask |= 1U << ((mmDMA5_QM_CP_DBG_0_0 & 0x7F) >> 2); 3722 mask |= 1U << ((mmDMA5_QM_CP_DBG_0_1 & 0x7F) >> 2); 3723 3724 WREG32(pb_addr + word_offset, ~mask); 3725 3726 pb_addr = (mmDMA5_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 3727 word_offset = ((mmDMA5_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 3728 mask = 1U << ((mmDMA5_QM_CP_DBG_0_2 & 0x7F) >> 2); 3729 mask |= 1U << ((mmDMA5_QM_CP_DBG_0_3 & 0x7F) >> 2); 3730 mask |= 1U << ((mmDMA5_QM_CP_DBG_0_4 & 0x7F) >> 2); 3731 mask |= 1U << ((mmDMA5_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 3732 mask |= 1U << ((mmDMA5_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 3733 mask |= 1U << ((mmDMA5_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 3734 mask |= 1U << ((mmDMA5_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 3735 mask |= 1U << ((mmDMA5_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 3736 mask |= 1U << ((mmDMA5_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 3737 mask |= 1U << ((mmDMA5_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 3738 mask |= 1U << ((mmDMA5_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 3739 mask |= 1U << ((mmDMA5_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 3740 mask |= 1U << ((mmDMA5_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 3741 3742 WREG32(pb_addr + word_offset, ~mask); 3743 3744 pb_addr = (mmDMA5_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 3745 word_offset = ((mmDMA5_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 3746 mask = 1U << ((mmDMA5_QM_ARB_CFG_1 & 0x7F) >> 2); 3747 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 3748 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 3749 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 3750 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 3751 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 3752 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 3753 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 3754 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 3755 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 3756 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 3757 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 3758 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 3759 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 3760 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 3761 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 3762 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 3763 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 3764 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 3765 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 3766 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 3767 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 3768 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 3769 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 3770 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 3771 3772 WREG32(pb_addr + word_offset, ~mask); 3773 3774 pb_addr = (mmDMA5_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 3775 word_offset = ((mmDMA5_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 3776 << 2; 3777 mask = 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 3778 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 3779 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 3780 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 3781 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 3782 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 3783 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 3784 mask |= 1U << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 3785 3786 WREG32(pb_addr + word_offset, ~mask); 3787 3788 pb_addr = (mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 3789 PROT_BITS_OFFS; 3790 word_offset = 3791 ((mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) 3792 << 2; 3793 mask = 1U << ((mmDMA5_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 3794 mask |= 1U << ((mmDMA5_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 3795 mask |= 1U << ((mmDMA5_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 3796 mask |= 1U << ((mmDMA5_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 3797 mask |= 1U << ((mmDMA5_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 3798 3799 WREG32(pb_addr + word_offset, ~mask); 3800 3801 pb_addr = (mmDMA5_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 3802 word_offset = ((mmDMA5_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 3803 mask = 1U << ((mmDMA5_QM_ARB_STATE_STS & 0x7F) >> 2); 3804 mask |= 1U << ((mmDMA5_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 3805 mask |= 1U << ((mmDMA5_QM_ARB_MSG_STS & 0x7F) >> 2); 3806 mask |= 1U << ((mmDMA5_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 3807 mask |= 1U << ((mmDMA5_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 3808 mask |= 1U << ((mmDMA5_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 3809 mask |= 1U << ((mmDMA5_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 3810 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 3811 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 3812 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 3813 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 3814 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 3815 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 3816 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 3817 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 3818 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 3819 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 3820 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 3821 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 3822 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 3823 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 3824 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 3825 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 3826 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 3827 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 3828 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 3829 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 3830 3831 WREG32(pb_addr + word_offset, ~mask); 3832 3833 pb_addr = (mmDMA5_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 3834 word_offset = ((mmDMA5_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 3835 << 2; 3836 mask = 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 3837 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 3838 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 3839 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 3840 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 3841 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 3842 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 3843 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 3844 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 3845 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 3846 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 3847 mask |= 1U << ((mmDMA5_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 3848 mask |= 1U << ((mmDMA5_QM_CGM_CFG & 0x7F) >> 2); 3849 mask |= 1U << ((mmDMA5_QM_CGM_STS & 0x7F) >> 2); 3850 mask |= 1U << ((mmDMA5_QM_CGM_CFG1 & 0x7F) >> 2); 3851 3852 WREG32(pb_addr + word_offset, ~mask); 3853 3854 pb_addr = (mmDMA5_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 3855 word_offset = ((mmDMA5_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 3856 mask = 1U << ((mmDMA5_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 3857 mask |= 1U << ((mmDMA5_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 3858 mask |= 1U << ((mmDMA5_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 3859 mask |= 1U << ((mmDMA5_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 3860 mask |= 1U << ((mmDMA5_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 3861 mask |= 1U << ((mmDMA5_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 3862 mask |= 1U << ((mmDMA5_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 3863 mask |= 1U << ((mmDMA5_QM_GLBL_AXCACHE & 0x7F) >> 2); 3864 mask |= 1U << ((mmDMA5_QM_IND_GW_APB_CFG & 0x7F) >> 2); 3865 mask |= 1U << ((mmDMA5_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 3866 mask |= 1U << ((mmDMA5_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 3867 mask |= 1U << ((mmDMA5_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 3868 mask |= 1U << ((mmDMA5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 3869 mask |= 1U << ((mmDMA5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 3870 mask |= 1U << ((mmDMA5_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 3871 3872 WREG32(pb_addr + word_offset, ~mask); 3873 3874 pb_addr = (mmDMA5_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 3875 word_offset = ((mmDMA5_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 3876 << 2; 3877 mask = 1U << ((mmDMA5_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 3878 3879 WREG32(pb_addr + word_offset, ~mask); 3880 3881 pb_addr = (mmDMA6_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 3882 word_offset = ((mmDMA6_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 3883 mask = 1U << ((mmDMA6_QM_GLBL_CFG0 & 0x7F) >> 2); 3884 mask |= 1U << ((mmDMA6_QM_GLBL_CFG1 & 0x7F) >> 2); 3885 mask |= 1U << ((mmDMA6_QM_GLBL_PROT & 0x7F) >> 2); 3886 mask |= 1U << ((mmDMA6_QM_GLBL_ERR_CFG & 0x7F) >> 2); 3887 mask |= 1U << ((mmDMA6_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 3888 mask |= 1U << ((mmDMA6_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 3889 mask |= 1U << ((mmDMA6_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 3890 mask |= 1U << ((mmDMA6_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 3891 mask |= 1U << ((mmDMA6_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 3892 mask |= 1U << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 3893 mask |= 1U << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 3894 mask |= 1U << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 3895 mask |= 1U << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 3896 mask |= 1U << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 3897 mask |= 1U << ((mmDMA6_QM_GLBL_STS0 & 0x7F) >> 2); 3898 mask |= 1U << ((mmDMA6_QM_GLBL_STS1_0 & 0x7F) >> 2); 3899 mask |= 1U << ((mmDMA6_QM_GLBL_STS1_1 & 0x7F) >> 2); 3900 mask |= 1U << ((mmDMA6_QM_GLBL_STS1_2 & 0x7F) >> 2); 3901 mask |= 1U << ((mmDMA6_QM_GLBL_STS1_3 & 0x7F) >> 2); 3902 mask |= 1U << ((mmDMA6_QM_GLBL_STS1_4 & 0x7F) >> 2); 3903 mask |= 1U << ((mmDMA6_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 3904 mask |= 1U << ((mmDMA6_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 3905 mask |= 1U << ((mmDMA6_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 3906 mask |= 1U << ((mmDMA6_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 3907 mask |= 1U << ((mmDMA6_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 3908 mask |= 1U << ((mmDMA6_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 3909 mask |= 1U << ((mmDMA6_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 3910 mask |= 1U << ((mmDMA6_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 3911 mask |= 1U << ((mmDMA6_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 3912 3913 WREG32(pb_addr + word_offset, ~mask); 3914 3915 pb_addr = (mmDMA6_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 3916 word_offset = ((mmDMA6_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 3917 mask = 1U << ((mmDMA6_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 3918 mask |= 1U << ((mmDMA6_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 3919 mask |= 1U << ((mmDMA6_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 3920 mask |= 1U << ((mmDMA6_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 3921 mask |= 1U << ((mmDMA6_QM_PQ_SIZE_0 & 0x7F) >> 2); 3922 mask |= 1U << ((mmDMA6_QM_PQ_SIZE_1 & 0x7F) >> 2); 3923 mask |= 1U << ((mmDMA6_QM_PQ_SIZE_2 & 0x7F) >> 2); 3924 mask |= 1U << ((mmDMA6_QM_PQ_SIZE_3 & 0x7F) >> 2); 3925 mask |= 1U << ((mmDMA6_QM_PQ_PI_0 & 0x7F) >> 2); 3926 mask |= 1U << ((mmDMA6_QM_PQ_PI_1 & 0x7F) >> 2); 3927 mask |= 1U << ((mmDMA6_QM_PQ_PI_2 & 0x7F) >> 2); 3928 mask |= 1U << ((mmDMA6_QM_PQ_PI_3 & 0x7F) >> 2); 3929 mask |= 1U << ((mmDMA6_QM_PQ_CI_0 & 0x7F) >> 2); 3930 mask |= 1U << ((mmDMA6_QM_PQ_CI_1 & 0x7F) >> 2); 3931 mask |= 1U << ((mmDMA6_QM_PQ_CI_2 & 0x7F) >> 2); 3932 mask |= 1U << ((mmDMA6_QM_PQ_CI_3 & 0x7F) >> 2); 3933 mask |= 1U << ((mmDMA6_QM_PQ_CFG0_0 & 0x7F) >> 2); 3934 mask |= 1U << ((mmDMA6_QM_PQ_CFG0_1 & 0x7F) >> 2); 3935 mask |= 1U << ((mmDMA6_QM_PQ_CFG0_2 & 0x7F) >> 2); 3936 mask |= 1U << ((mmDMA6_QM_PQ_CFG0_3 & 0x7F) >> 2); 3937 mask |= 1U << ((mmDMA6_QM_PQ_CFG1_0 & 0x7F) >> 2); 3938 mask |= 1U << ((mmDMA6_QM_PQ_CFG1_1 & 0x7F) >> 2); 3939 mask |= 1U << ((mmDMA6_QM_PQ_CFG1_2 & 0x7F) >> 2); 3940 mask |= 1U << ((mmDMA6_QM_PQ_CFG1_3 & 0x7F) >> 2); 3941 mask |= 1U << ((mmDMA6_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 3942 mask |= 1U << ((mmDMA6_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 3943 mask |= 1U << ((mmDMA6_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 3944 mask |= 1U << ((mmDMA6_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 3945 mask |= 1U << ((mmDMA6_QM_PQ_STS0_0 & 0x7F) >> 2); 3946 mask |= 1U << ((mmDMA6_QM_PQ_STS0_1 & 0x7F) >> 2); 3947 mask |= 1U << ((mmDMA6_QM_PQ_STS0_2 & 0x7F) >> 2); 3948 mask |= 1U << ((mmDMA6_QM_PQ_STS0_3 & 0x7F) >> 2); 3949 3950 WREG32(pb_addr + word_offset, ~mask); 3951 3952 pb_addr = (mmDMA6_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 3953 word_offset = ((mmDMA6_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 3954 mask = 1U << ((mmDMA6_QM_PQ_STS1_0 & 0x7F) >> 2); 3955 mask |= 1U << ((mmDMA6_QM_PQ_STS1_1 & 0x7F) >> 2); 3956 mask |= 1U << ((mmDMA6_QM_PQ_STS1_2 & 0x7F) >> 2); 3957 mask |= 1U << ((mmDMA6_QM_PQ_STS1_3 & 0x7F) >> 2); 3958 mask |= 1U << ((mmDMA6_QM_CQ_STS0_0 & 0x7F) >> 2); 3959 mask |= 1U << ((mmDMA6_QM_CQ_STS0_1 & 0x7F) >> 2); 3960 mask |= 1U << ((mmDMA6_QM_CQ_STS0_2 & 0x7F) >> 2); 3961 mask |= 1U << ((mmDMA6_QM_CQ_STS0_3 & 0x7F) >> 2); 3962 mask |= 1U << ((mmDMA6_QM_CQ_STS1_0 & 0x7F) >> 2); 3963 mask |= 1U << ((mmDMA6_QM_CQ_STS1_1 & 0x7F) >> 2); 3964 mask |= 1U << ((mmDMA6_QM_CQ_STS1_2 & 0x7F) >> 2); 3965 mask |= 1U << ((mmDMA6_QM_CQ_STS1_3 & 0x7F) >> 2); 3966 mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 3967 mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 3968 mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_0 & 0x7F) >> 2); 3969 3970 WREG32(pb_addr + word_offset, ~mask); 3971 3972 pb_addr = (mmDMA6_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 3973 word_offset = ((mmDMA6_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 3974 mask = 1U << ((mmDMA6_QM_CQ_CTL_0 & 0x7F) >> 2); 3975 mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 3976 mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 3977 mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_1 & 0x7F) >> 2); 3978 mask |= 1U << ((mmDMA6_QM_CQ_CTL_1 & 0x7F) >> 2); 3979 mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 3980 mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 3981 mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_2 & 0x7F) >> 2); 3982 mask |= 1U << ((mmDMA6_QM_CQ_CTL_2 & 0x7F) >> 2); 3983 mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 3984 mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 3985 mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_3 & 0x7F) >> 2); 3986 mask |= 1U << ((mmDMA6_QM_CQ_CTL_3 & 0x7F) >> 2); 3987 mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 3988 mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 3989 mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 3990 mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 3991 mask |= 1U << ((mmDMA6_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 3992 mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 3993 mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 3994 mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 3995 mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 3996 mask |= 1U << ((mmDMA6_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 3997 mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 3998 mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 3999 mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 4000 mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 4001 mask |= 1U << ((mmDMA6_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 4002 4003 WREG32(pb_addr + word_offset, ~mask); 4004 4005 pb_addr = (mmDMA6_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 4006 word_offset = ((mmDMA6_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 4007 mask = 1U << ((mmDMA6_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 4008 mask |= 1U << ((mmDMA6_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 4009 mask |= 1U << ((mmDMA6_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 4010 mask |= 1U << ((mmDMA6_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 4011 mask |= 1U << ((mmDMA6_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 4012 mask |= 1U << ((mmDMA6_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 4013 mask |= 1U << ((mmDMA6_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 4014 mask |= 1U << ((mmDMA6_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 4015 mask |= 1U << ((mmDMA6_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 4016 mask |= 1U << ((mmDMA6_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 4017 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 4018 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 4019 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 4020 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 4021 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 4022 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 4023 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 4024 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 4025 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 4026 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 4027 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 4028 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 4029 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 4030 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 4031 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 4032 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 4033 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 4034 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 4035 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 4036 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 4037 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 4038 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 4039 4040 WREG32(pb_addr + word_offset, ~mask); 4041 4042 pb_addr = (mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 4043 word_offset = ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 4044 << 2; 4045 mask = 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 4046 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 4047 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 4048 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 4049 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 4050 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 4051 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 4052 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 4053 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 4054 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 4055 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 4056 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 4057 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 4058 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 4059 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 4060 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 4061 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 4062 mask |= 1U << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 4063 mask |= 1U << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 4064 mask |= 1U << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 4065 mask |= 1U << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 4066 mask |= 1U << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 4067 mask |= 1U << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 4068 mask |= 1U << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 4069 mask |= 1U << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 4070 mask |= 1U << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 4071 mask |= 1U << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 4072 mask |= 1U << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 4073 mask |= 1U << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 4074 mask |= 1U << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 4075 mask |= 1U << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 4076 4077 WREG32(pb_addr + word_offset, ~mask); 4078 4079 pb_addr = (mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 4080 PROT_BITS_OFFS; 4081 word_offset = 4082 ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) 4083 << 2; 4084 mask = 1U << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 4085 mask |= 1U << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 4086 4087 WREG32(pb_addr + word_offset, ~mask); 4088 4089 pb_addr = (mmDMA6_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 4090 word_offset = ((mmDMA6_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 4091 mask = 1U << ((mmDMA6_QM_CP_STS_0 & 0x7F) >> 2); 4092 mask |= 1U << ((mmDMA6_QM_CP_STS_1 & 0x7F) >> 2); 4093 mask |= 1U << ((mmDMA6_QM_CP_STS_2 & 0x7F) >> 2); 4094 mask |= 1U << ((mmDMA6_QM_CP_STS_3 & 0x7F) >> 2); 4095 mask |= 1U << ((mmDMA6_QM_CP_STS_4 & 0x7F) >> 2); 4096 mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 4097 mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 4098 mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 4099 mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 4100 mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 4101 mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 4102 mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 4103 mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 4104 mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 4105 mask |= 1U << ((mmDMA6_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 4106 mask |= 1U << ((mmDMA6_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 4107 mask |= 1U << ((mmDMA6_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 4108 mask |= 1U << ((mmDMA6_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 4109 4110 WREG32(pb_addr + word_offset, ~mask); 4111 4112 pb_addr = (mmDMA6_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 4113 word_offset = ((mmDMA6_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 4114 mask = 1U << ((mmDMA6_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 4115 mask |= 1U << ((mmDMA6_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 4116 mask |= 1U << ((mmDMA6_QM_CP_DBG_0_0 & 0x7F) >> 2); 4117 mask |= 1U << ((mmDMA6_QM_CP_DBG_0_1 & 0x7F) >> 2); 4118 4119 WREG32(pb_addr + word_offset, ~mask); 4120 4121 pb_addr = (mmDMA6_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 4122 word_offset = ((mmDMA6_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 4123 mask = 1U << ((mmDMA6_QM_CP_DBG_0_2 & 0x7F) >> 2); 4124 mask |= 1U << ((mmDMA6_QM_CP_DBG_0_3 & 0x7F) >> 2); 4125 mask |= 1U << ((mmDMA6_QM_CP_DBG_0_4 & 0x7F) >> 2); 4126 mask |= 1U << ((mmDMA6_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 4127 mask |= 1U << ((mmDMA6_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 4128 mask |= 1U << ((mmDMA6_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 4129 mask |= 1U << ((mmDMA6_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 4130 mask |= 1U << ((mmDMA6_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 4131 mask |= 1U << ((mmDMA6_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 4132 mask |= 1U << ((mmDMA6_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 4133 mask |= 1U << ((mmDMA6_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 4134 mask |= 1U << ((mmDMA6_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 4135 mask |= 1U << ((mmDMA6_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 4136 4137 WREG32(pb_addr + word_offset, ~mask); 4138 4139 pb_addr = (mmDMA6_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 4140 word_offset = ((mmDMA6_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 4141 mask = 1U << ((mmDMA6_QM_ARB_CFG_1 & 0x7F) >> 2); 4142 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 4143 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 4144 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 4145 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 4146 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 4147 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 4148 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 4149 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 4150 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 4151 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 4152 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 4153 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 4154 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 4155 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 4156 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 4157 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 4158 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 4159 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 4160 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 4161 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 4162 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 4163 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 4164 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 4165 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 4166 4167 WREG32(pb_addr + word_offset, ~mask); 4168 4169 pb_addr = (mmDMA6_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 4170 word_offset = ((mmDMA6_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 4171 << 2; 4172 mask = 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 4173 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 4174 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 4175 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 4176 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 4177 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 4178 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 4179 mask |= 1U << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 4180 4181 WREG32(pb_addr + word_offset, ~mask); 4182 4183 pb_addr = (mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 4184 PROT_BITS_OFFS; 4185 word_offset = 4186 ((mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) 4187 << 2; 4188 4189 mask = 1U << ((mmDMA6_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 4190 mask |= 1U << ((mmDMA6_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 4191 mask |= 1U << ((mmDMA6_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 4192 mask |= 1U << ((mmDMA6_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 4193 mask |= 1U << ((mmDMA6_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 4194 4195 WREG32(pb_addr + word_offset, ~mask); 4196 4197 pb_addr = (mmDMA6_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 4198 word_offset = ((mmDMA6_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 4199 mask = 1U << ((mmDMA6_QM_ARB_STATE_STS & 0x7F) >> 2); 4200 mask |= 1U << ((mmDMA6_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 4201 mask |= 1U << ((mmDMA6_QM_ARB_MSG_STS & 0x7F) >> 2); 4202 mask |= 1U << ((mmDMA6_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 4203 mask |= 1U << ((mmDMA6_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 4204 mask |= 1U << ((mmDMA6_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 4205 mask |= 1U << ((mmDMA6_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 4206 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 4207 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 4208 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 4209 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 4210 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 4211 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 4212 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 4213 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 4214 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 4215 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 4216 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 4217 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 4218 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 4219 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 4220 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 4221 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 4222 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 4223 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 4224 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 4225 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 4226 4227 WREG32(pb_addr + word_offset, ~mask); 4228 4229 pb_addr = (mmDMA6_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 4230 word_offset = ((mmDMA6_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 4231 << 2; 4232 mask = 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 4233 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 4234 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 4235 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 4236 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 4237 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 4238 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 4239 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 4240 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 4241 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 4242 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 4243 mask |= 1U << ((mmDMA6_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 4244 mask |= 1U << ((mmDMA6_QM_CGM_CFG & 0x7F) >> 2); 4245 mask |= 1U << ((mmDMA6_QM_CGM_STS & 0x7F) >> 2); 4246 mask |= 1U << ((mmDMA6_QM_CGM_CFG1 & 0x7F) >> 2); 4247 4248 WREG32(pb_addr + word_offset, ~mask); 4249 4250 pb_addr = (mmDMA6_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 4251 word_offset = ((mmDMA6_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 4252 mask = 1U << ((mmDMA6_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 4253 mask |= 1U << ((mmDMA6_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 4254 mask |= 1U << ((mmDMA6_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 4255 mask |= 1U << ((mmDMA6_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 4256 mask |= 1U << ((mmDMA6_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 4257 mask |= 1U << ((mmDMA6_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 4258 mask |= 1U << ((mmDMA6_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 4259 mask |= 1U << ((mmDMA6_QM_GLBL_AXCACHE & 0x7F) >> 2); 4260 mask |= 1U << ((mmDMA6_QM_IND_GW_APB_CFG & 0x7F) >> 2); 4261 mask |= 1U << ((mmDMA6_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 4262 mask |= 1U << ((mmDMA6_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 4263 mask |= 1U << ((mmDMA6_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 4264 mask |= 1U << ((mmDMA6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 4265 mask |= 1U << ((mmDMA6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 4266 mask |= 1U << ((mmDMA6_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 4267 4268 WREG32(pb_addr + word_offset, ~mask); 4269 4270 pb_addr = (mmDMA6_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 4271 word_offset = ((mmDMA6_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 4272 << 2; 4273 mask = 1U << ((mmDMA6_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 4274 4275 WREG32(pb_addr + word_offset, ~mask); 4276 4277 pb_addr = (mmDMA7_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 4278 word_offset = ((mmDMA7_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 4279 mask = 1U << ((mmDMA7_QM_GLBL_CFG0 & 0x7F) >> 2); 4280 mask |= 1U << ((mmDMA7_QM_GLBL_CFG1 & 0x7F) >> 2); 4281 mask |= 1U << ((mmDMA7_QM_GLBL_PROT & 0x7F) >> 2); 4282 mask |= 1U << ((mmDMA7_QM_GLBL_ERR_CFG & 0x7F) >> 2); 4283 mask |= 1U << ((mmDMA7_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 4284 mask |= 1U << ((mmDMA7_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 4285 mask |= 1U << ((mmDMA7_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 4286 mask |= 1U << ((mmDMA7_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 4287 mask |= 1U << ((mmDMA7_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 4288 mask |= 1U << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 4289 mask |= 1U << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 4290 mask |= 1U << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 4291 mask |= 1U << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 4292 mask |= 1U << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 4293 mask |= 1U << ((mmDMA7_QM_GLBL_STS0 & 0x7F) >> 2); 4294 mask |= 1U << ((mmDMA7_QM_GLBL_STS1_0 & 0x7F) >> 2); 4295 mask |= 1U << ((mmDMA7_QM_GLBL_STS1_1 & 0x7F) >> 2); 4296 mask |= 1U << ((mmDMA7_QM_GLBL_STS1_2 & 0x7F) >> 2); 4297 mask |= 1U << ((mmDMA7_QM_GLBL_STS1_3 & 0x7F) >> 2); 4298 mask |= 1U << ((mmDMA7_QM_GLBL_STS1_4 & 0x7F) >> 2); 4299 mask |= 1U << ((mmDMA7_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 4300 mask |= 1U << ((mmDMA7_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 4301 mask |= 1U << ((mmDMA7_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 4302 mask |= 1U << ((mmDMA7_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 4303 mask |= 1U << ((mmDMA7_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 4304 mask |= 1U << ((mmDMA7_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 4305 mask |= 1U << ((mmDMA7_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 4306 mask |= 1U << ((mmDMA7_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 4307 mask |= 1U << ((mmDMA7_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 4308 4309 WREG32(pb_addr + word_offset, ~mask); 4310 4311 pb_addr = (mmDMA7_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 4312 word_offset = ((mmDMA7_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 4313 mask = 1U << ((mmDMA7_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 4314 mask |= 1U << ((mmDMA7_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 4315 mask |= 1U << ((mmDMA7_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 4316 mask |= 1U << ((mmDMA7_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 4317 mask |= 1U << ((mmDMA7_QM_PQ_SIZE_0 & 0x7F) >> 2); 4318 mask |= 1U << ((mmDMA7_QM_PQ_SIZE_1 & 0x7F) >> 2); 4319 mask |= 1U << ((mmDMA7_QM_PQ_SIZE_2 & 0x7F) >> 2); 4320 mask |= 1U << ((mmDMA7_QM_PQ_SIZE_3 & 0x7F) >> 2); 4321 mask |= 1U << ((mmDMA7_QM_PQ_PI_0 & 0x7F) >> 2); 4322 mask |= 1U << ((mmDMA7_QM_PQ_PI_1 & 0x7F) >> 2); 4323 mask |= 1U << ((mmDMA7_QM_PQ_PI_2 & 0x7F) >> 2); 4324 mask |= 1U << ((mmDMA7_QM_PQ_PI_3 & 0x7F) >> 2); 4325 mask |= 1U << ((mmDMA7_QM_PQ_CI_0 & 0x7F) >> 2); 4326 mask |= 1U << ((mmDMA7_QM_PQ_CI_1 & 0x7F) >> 2); 4327 mask |= 1U << ((mmDMA7_QM_PQ_CI_2 & 0x7F) >> 2); 4328 mask |= 1U << ((mmDMA7_QM_PQ_CI_3 & 0x7F) >> 2); 4329 mask |= 1U << ((mmDMA7_QM_PQ_CFG0_0 & 0x7F) >> 2); 4330 mask |= 1U << ((mmDMA7_QM_PQ_CFG0_1 & 0x7F) >> 2); 4331 mask |= 1U << ((mmDMA7_QM_PQ_CFG0_2 & 0x7F) >> 2); 4332 mask |= 1U << ((mmDMA7_QM_PQ_CFG0_3 & 0x7F) >> 2); 4333 mask |= 1U << ((mmDMA7_QM_PQ_CFG1_0 & 0x7F) >> 2); 4334 mask |= 1U << ((mmDMA7_QM_PQ_CFG1_1 & 0x7F) >> 2); 4335 mask |= 1U << ((mmDMA7_QM_PQ_CFG1_2 & 0x7F) >> 2); 4336 mask |= 1U << ((mmDMA7_QM_PQ_CFG1_3 & 0x7F) >> 2); 4337 mask |= 1U << ((mmDMA7_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 4338 mask |= 1U << ((mmDMA7_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 4339 mask |= 1U << ((mmDMA7_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 4340 mask |= 1U << ((mmDMA7_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 4341 mask |= 1U << ((mmDMA7_QM_PQ_STS0_0 & 0x7F) >> 2); 4342 mask |= 1U << ((mmDMA7_QM_PQ_STS0_1 & 0x7F) >> 2); 4343 mask |= 1U << ((mmDMA7_QM_PQ_STS0_2 & 0x7F) >> 2); 4344 mask |= 1U << ((mmDMA7_QM_PQ_STS0_3 & 0x7F) >> 2); 4345 4346 WREG32(pb_addr + word_offset, ~mask); 4347 4348 pb_addr = (mmDMA7_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 4349 word_offset = ((mmDMA7_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 4350 mask = 1U << ((mmDMA7_QM_PQ_STS1_0 & 0x7F) >> 2); 4351 mask |= 1U << ((mmDMA7_QM_PQ_STS1_1 & 0x7F) >> 2); 4352 mask |= 1U << ((mmDMA7_QM_PQ_STS1_2 & 0x7F) >> 2); 4353 mask |= 1U << ((mmDMA7_QM_PQ_STS1_3 & 0x7F) >> 2); 4354 mask |= 1U << ((mmDMA7_QM_CQ_STS0_0 & 0x7F) >> 2); 4355 mask |= 1U << ((mmDMA7_QM_CQ_STS0_1 & 0x7F) >> 2); 4356 mask |= 1U << ((mmDMA7_QM_CQ_STS0_2 & 0x7F) >> 2); 4357 mask |= 1U << ((mmDMA7_QM_CQ_STS0_3 & 0x7F) >> 2); 4358 mask |= 1U << ((mmDMA7_QM_CQ_STS1_0 & 0x7F) >> 2); 4359 mask |= 1U << ((mmDMA7_QM_CQ_STS1_1 & 0x7F) >> 2); 4360 mask |= 1U << ((mmDMA7_QM_CQ_STS1_2 & 0x7F) >> 2); 4361 mask |= 1U << ((mmDMA7_QM_CQ_STS1_3 & 0x7F) >> 2); 4362 mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 4363 mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 4364 mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_0 & 0x7F) >> 2); 4365 4366 WREG32(pb_addr + word_offset, ~mask); 4367 4368 pb_addr = (mmDMA7_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 4369 word_offset = ((mmDMA7_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 4370 mask = 1U << ((mmDMA7_QM_CQ_CTL_0 & 0x7F) >> 2); 4371 mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 4372 mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 4373 mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_1 & 0x7F) >> 2); 4374 mask |= 1U << ((mmDMA7_QM_CQ_CTL_1 & 0x7F) >> 2); 4375 mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 4376 mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 4377 mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_2 & 0x7F) >> 2); 4378 mask |= 1U << ((mmDMA7_QM_CQ_CTL_2 & 0x7F) >> 2); 4379 mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 4380 mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 4381 mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_3 & 0x7F) >> 2); 4382 mask |= 1U << ((mmDMA7_QM_CQ_CTL_3 & 0x7F) >> 2); 4383 mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 4384 mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 4385 mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 4386 mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 4387 mask |= 1U << ((mmDMA7_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 4388 mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 4389 mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 4390 mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 4391 mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 4392 mask |= 1U << ((mmDMA7_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 4393 mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 4394 mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 4395 mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 4396 mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 4397 mask |= 1U << ((mmDMA7_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 4398 4399 WREG32(pb_addr + word_offset, ~mask); 4400 4401 pb_addr = (mmDMA7_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 4402 word_offset = ((mmDMA7_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 4403 mask = 1U << ((mmDMA7_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 4404 mask |= 1U << ((mmDMA7_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 4405 mask |= 1U << ((mmDMA7_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 4406 mask |= 1U << ((mmDMA7_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 4407 mask |= 1U << ((mmDMA7_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 4408 mask |= 1U << ((mmDMA7_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 4409 mask |= 1U << ((mmDMA7_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 4410 mask |= 1U << ((mmDMA7_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 4411 mask |= 1U << ((mmDMA7_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 4412 mask |= 1U << ((mmDMA7_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 4413 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 4414 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 4415 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 4416 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 4417 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 4418 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 4419 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 4420 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 4421 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 4422 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 4423 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 4424 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 4425 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 4426 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 4427 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 4428 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 4429 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 4430 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 4431 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 4432 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 4433 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 4434 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 4435 4436 WREG32(pb_addr + word_offset, ~mask); 4437 4438 pb_addr = (mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 4439 word_offset = ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 4440 << 2; 4441 mask = 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 4442 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 4443 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 4444 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 4445 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 4446 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 4447 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 4448 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 4449 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 4450 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 4451 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 4452 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 4453 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 4454 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 4455 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 4456 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 4457 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 4458 mask |= 1U << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 4459 mask |= 1U << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 4460 mask |= 1U << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 4461 mask |= 1U << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 4462 mask |= 1U << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 4463 mask |= 1U << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 4464 mask |= 1U << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 4465 mask |= 1U << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 4466 mask |= 1U << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 4467 mask |= 1U << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 4468 mask |= 1U << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 4469 mask |= 1U << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 4470 mask |= 1U << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 4471 mask |= 1U << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 4472 4473 WREG32(pb_addr + word_offset, ~mask); 4474 4475 pb_addr = (mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 4476 PROT_BITS_OFFS; 4477 word_offset = 4478 ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) 4479 << 2; 4480 mask = 1U << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 4481 mask |= 1U << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 4482 4483 WREG32(pb_addr + word_offset, ~mask); 4484 4485 pb_addr = (mmDMA7_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 4486 word_offset = ((mmDMA7_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 4487 mask = 1U << ((mmDMA7_QM_CP_STS_0 & 0x7F) >> 2); 4488 mask |= 1U << ((mmDMA7_QM_CP_STS_1 & 0x7F) >> 2); 4489 mask |= 1U << ((mmDMA7_QM_CP_STS_2 & 0x7F) >> 2); 4490 mask |= 1U << ((mmDMA7_QM_CP_STS_3 & 0x7F) >> 2); 4491 mask |= 1U << ((mmDMA7_QM_CP_STS_4 & 0x7F) >> 2); 4492 mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 4493 mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 4494 mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 4495 mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 4496 mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 4497 mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 4498 mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 4499 mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 4500 mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 4501 mask |= 1U << ((mmDMA7_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 4502 mask |= 1U << ((mmDMA7_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 4503 mask |= 1U << ((mmDMA7_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 4504 mask |= 1U << ((mmDMA7_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 4505 4506 WREG32(pb_addr + word_offset, ~mask); 4507 4508 pb_addr = (mmDMA7_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 4509 word_offset = ((mmDMA7_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 4510 mask = 1U << ((mmDMA7_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 4511 mask |= 1U << ((mmDMA7_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 4512 mask |= 1U << ((mmDMA7_QM_CP_DBG_0_0 & 0x7F) >> 2); 4513 mask |= 1U << ((mmDMA7_QM_CP_DBG_0_1 & 0x7F) >> 2); 4514 4515 WREG32(pb_addr + word_offset, ~mask); 4516 4517 pb_addr = (mmDMA7_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 4518 word_offset = ((mmDMA7_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 4519 mask = 1U << ((mmDMA7_QM_CP_DBG_0_2 & 0x7F) >> 2); 4520 mask |= 1U << ((mmDMA7_QM_CP_DBG_0_3 & 0x7F) >> 2); 4521 mask |= 1U << ((mmDMA7_QM_CP_DBG_0_4 & 0x7F) >> 2); 4522 mask |= 1U << ((mmDMA7_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 4523 mask |= 1U << ((mmDMA7_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 4524 mask |= 1U << ((mmDMA7_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 4525 mask |= 1U << ((mmDMA7_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 4526 mask |= 1U << ((mmDMA7_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 4527 mask |= 1U << ((mmDMA7_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 4528 mask |= 1U << ((mmDMA7_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 4529 mask |= 1U << ((mmDMA7_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 4530 mask |= 1U << ((mmDMA7_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 4531 mask |= 1U << ((mmDMA7_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 4532 4533 WREG32(pb_addr + word_offset, ~mask); 4534 4535 pb_addr = (mmDMA7_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 4536 word_offset = ((mmDMA7_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 4537 mask = 1U << ((mmDMA7_QM_ARB_CFG_1 & 0x7F) >> 2); 4538 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 4539 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 4540 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 4541 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 4542 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 4543 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 4544 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 4545 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 4546 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 4547 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 4548 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 4549 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 4550 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 4551 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 4552 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 4553 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 4554 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 4555 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 4556 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 4557 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 4558 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 4559 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 4560 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 4561 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 4562 4563 WREG32(pb_addr + word_offset, ~mask); 4564 4565 pb_addr = (mmDMA7_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 4566 word_offset = ((mmDMA7_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 4567 << 2; 4568 mask = 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 4569 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 4570 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 4571 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 4572 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 4573 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 4574 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 4575 mask |= 1U << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 4576 4577 WREG32(pb_addr + word_offset, ~mask); 4578 4579 pb_addr = (mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 4580 PROT_BITS_OFFS; 4581 word_offset = 4582 ((mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) 4583 << 2; 4584 mask = 1U << ((mmDMA7_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 4585 mask |= 1U << ((mmDMA7_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 4586 mask |= 1U << ((mmDMA7_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 4587 mask |= 1U << ((mmDMA7_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 4588 mask |= 1U << ((mmDMA7_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 4589 4590 WREG32(pb_addr + word_offset, ~mask); 4591 4592 pb_addr = (mmDMA7_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 4593 word_offset = ((mmDMA7_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 4594 mask = 1U << ((mmDMA7_QM_ARB_STATE_STS & 0x7F) >> 2); 4595 mask |= 1U << ((mmDMA7_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 4596 mask |= 1U << ((mmDMA7_QM_ARB_MSG_STS & 0x7F) >> 2); 4597 mask |= 1U << ((mmDMA7_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 4598 mask |= 1U << ((mmDMA7_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 4599 mask |= 1U << ((mmDMA7_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 4600 mask |= 1U << ((mmDMA7_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 4601 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 4602 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 4603 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 4604 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 4605 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 4606 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 4607 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 4608 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 4609 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 4610 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 4611 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 4612 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 4613 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 4614 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 4615 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 4616 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 4617 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 4618 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 4619 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 4620 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 4621 4622 WREG32(pb_addr + word_offset, ~mask); 4623 4624 pb_addr = (mmDMA7_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 4625 word_offset = ((mmDMA7_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 4626 << 2; 4627 mask = 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 4628 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 4629 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 4630 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 4631 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 4632 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 4633 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 4634 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 4635 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 4636 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 4637 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 4638 mask |= 1U << ((mmDMA7_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 4639 mask |= 1U << ((mmDMA7_QM_CGM_CFG & 0x7F) >> 2); 4640 mask |= 1U << ((mmDMA7_QM_CGM_STS & 0x7F) >> 2); 4641 mask |= 1U << ((mmDMA7_QM_CGM_CFG1 & 0x7F) >> 2); 4642 4643 WREG32(pb_addr + word_offset, ~mask); 4644 4645 pb_addr = (mmDMA7_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 4646 word_offset = ((mmDMA7_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 4647 mask = 1U << ((mmDMA7_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 4648 mask |= 1U << ((mmDMA7_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 4649 mask |= 1U << ((mmDMA7_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 4650 mask |= 1U << ((mmDMA7_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 4651 mask |= 1U << ((mmDMA7_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 4652 mask |= 1U << ((mmDMA7_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 4653 mask |= 1U << ((mmDMA7_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 4654 mask |= 1U << ((mmDMA7_QM_GLBL_AXCACHE & 0x7F) >> 2); 4655 mask |= 1U << ((mmDMA7_QM_IND_GW_APB_CFG & 0x7F) >> 2); 4656 mask |= 1U << ((mmDMA7_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 4657 mask |= 1U << ((mmDMA7_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 4658 mask |= 1U << ((mmDMA7_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 4659 mask |= 1U << ((mmDMA7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 4660 mask |= 1U << ((mmDMA7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 4661 mask |= 1U << ((mmDMA7_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 4662 4663 WREG32(pb_addr + word_offset, ~mask); 4664 4665 pb_addr = (mmDMA7_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 4666 word_offset = ((mmDMA7_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 4667 << 2; 4668 mask = 1U << ((mmDMA7_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 4669 4670 WREG32(pb_addr + word_offset, ~mask); 4671 4672 pb_addr = (mmDMA0_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 4673 word_offset = ((mmDMA0_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 4674 mask = 1U << ((mmDMA0_CORE_CFG_0 & 0x7F) >> 2); 4675 mask |= 1U << ((mmDMA0_CORE_CFG_1 & 0x7F) >> 2); 4676 mask |= 1U << ((mmDMA0_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); 4677 4678 WREG32(pb_addr + word_offset, ~mask); 4679 4680 pb_addr = (mmDMA0_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; 4681 word_offset = ((mmDMA0_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; 4682 mask = 1U << ((mmDMA0_CORE_PROT & 0x7F) >> 2); 4683 mask |= 1U << ((mmDMA0_CORE_SECURE_PROPS & 0x7F) >> 2); 4684 mask |= 1U << ((mmDMA0_CORE_NON_SECURE_PROPS & 0x7F) >> 2); 4685 4686 WREG32(pb_addr + word_offset, ~mask); 4687 4688 pb_addr = (mmDMA0_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; 4689 word_offset = ((mmDMA0_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) 4690 << 2; 4691 mask = 1U << ((mmDMA0_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); 4692 mask |= 1U << ((mmDMA0_CORE_RD_MAX_SIZE & 0x7F) >> 2); 4693 mask |= 1U << ((mmDMA0_CORE_RD_ARCACHE & 0x7F) >> 2); 4694 mask |= 1U << ((mmDMA0_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); 4695 mask |= 1U << ((mmDMA0_CORE_RD_INFLIGHTS & 0x7F) >> 2); 4696 mask |= 1U << ((mmDMA0_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); 4697 mask |= 1U << ((mmDMA0_CORE_WR_MAX_AWID & 0x7F) >> 2); 4698 mask |= 1U << ((mmDMA0_CORE_WR_AWCACHE & 0x7F) >> 2); 4699 mask |= 1U << ((mmDMA0_CORE_WR_AWUSER_31_11 & 0x7F) >> 2); 4700 mask |= 1U << ((mmDMA0_CORE_WR_INFLIGHTS & 0x7F) >> 2); 4701 mask |= 1U << ((mmDMA0_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 4702 mask |= 1U << ((mmDMA0_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 4703 mask |= 1U << ((mmDMA0_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 4704 mask |= 1U << ((mmDMA0_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 4705 mask |= 1U << ((mmDMA0_CORE_ERR_CFG & 0x7F) >> 2); 4706 mask |= 1U << ((mmDMA0_CORE_ERR_CAUSE & 0x7F) >> 2); 4707 mask |= 1U << ((mmDMA0_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); 4708 mask |= 1U << ((mmDMA0_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); 4709 mask |= 1U << ((mmDMA0_CORE_ERRMSG_WDATA & 0x7F) >> 2); 4710 4711 WREG32(pb_addr + word_offset, ~mask); 4712 4713 pb_addr = (mmDMA0_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; 4714 word_offset = ((mmDMA0_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; 4715 mask = 1U << ((mmDMA0_CORE_STS0 & 0x7F) >> 2); 4716 mask |= 1U << ((mmDMA0_CORE_STS1 & 0x7F) >> 2); 4717 4718 WREG32(pb_addr + word_offset, ~mask); 4719 4720 pb_addr = (mmDMA0_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; 4721 word_offset = ((mmDMA0_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; 4722 mask = 1U << ((mmDMA0_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); 4723 mask |= 1U << ((mmDMA0_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); 4724 mask |= 1U << ((mmDMA0_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); 4725 mask |= 1U << ((mmDMA0_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); 4726 mask |= 1U << ((mmDMA0_CORE_RD_DBGMEM_RC & 0x7F) >> 2); 4727 mask |= 1U << ((mmDMA0_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); 4728 mask |= 1U << ((mmDMA0_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); 4729 mask |= 1U << ((mmDMA0_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); 4730 mask |= 1U << ((mmDMA0_CORE_DBG_DESC_CNT & 0x7F) >> 2); 4731 mask |= 1U << ((mmDMA0_CORE_DBG_STS & 0x7F) >> 2); 4732 mask |= 1U << ((mmDMA0_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); 4733 mask |= 1U << ((mmDMA0_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); 4734 4735 WREG32(pb_addr + word_offset, ~mask); 4736 4737 pb_addr = (mmDMA1_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 4738 word_offset = ((mmDMA1_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 4739 mask = 1U << ((mmDMA1_CORE_CFG_0 & 0x7F) >> 2); 4740 mask |= 1U << ((mmDMA1_CORE_CFG_1 & 0x7F) >> 2); 4741 mask |= 1U << ((mmDMA1_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); 4742 4743 WREG32(pb_addr + word_offset, ~mask); 4744 4745 pb_addr = (mmDMA1_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; 4746 word_offset = ((mmDMA1_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; 4747 mask = 1U << ((mmDMA1_CORE_PROT & 0x7F) >> 2); 4748 mask |= 1U << ((mmDMA1_CORE_SECURE_PROPS & 0x7F) >> 2); 4749 mask |= 1U << ((mmDMA1_CORE_NON_SECURE_PROPS & 0x7F) >> 2); 4750 4751 WREG32(pb_addr + word_offset, ~mask); 4752 4753 pb_addr = (mmDMA1_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; 4754 word_offset = ((mmDMA1_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) 4755 << 2; 4756 mask = 1U << ((mmDMA1_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); 4757 mask |= 1U << ((mmDMA1_CORE_RD_MAX_SIZE & 0x7F) >> 2); 4758 mask |= 1U << ((mmDMA1_CORE_RD_ARCACHE & 0x7F) >> 2); 4759 mask |= 1U << ((mmDMA1_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); 4760 mask |= 1U << ((mmDMA1_CORE_RD_INFLIGHTS & 0x7F) >> 2); 4761 mask |= 1U << ((mmDMA1_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); 4762 mask |= 1U << ((mmDMA1_CORE_WR_MAX_AWID & 0x7F) >> 2); 4763 mask |= 1U << ((mmDMA1_CORE_WR_AWCACHE & 0x7F) >> 2); 4764 mask |= 1U << ((mmDMA1_CORE_WR_AWUSER_31_11 & 0x7F) >> 2); 4765 mask |= 1U << ((mmDMA1_CORE_WR_INFLIGHTS & 0x7F) >> 2); 4766 mask |= 1U << ((mmDMA1_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 4767 mask |= 1U << ((mmDMA1_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 4768 mask |= 1U << ((mmDMA1_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 4769 mask |= 1U << ((mmDMA1_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 4770 mask |= 1U << ((mmDMA1_CORE_ERR_CFG & 0x7F) >> 2); 4771 mask |= 1U << ((mmDMA1_CORE_ERR_CAUSE & 0x7F) >> 2); 4772 mask |= 1U << ((mmDMA1_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); 4773 mask |= 1U << ((mmDMA1_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); 4774 mask |= 1U << ((mmDMA1_CORE_ERRMSG_WDATA & 0x7F) >> 2); 4775 4776 WREG32(pb_addr + word_offset, ~mask); 4777 4778 pb_addr = (mmDMA1_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; 4779 word_offset = ((mmDMA1_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; 4780 mask = 1U << ((mmDMA1_CORE_STS0 & 0x7F) >> 2); 4781 mask |= 1U << ((mmDMA1_CORE_STS1 & 0x7F) >> 2); 4782 4783 WREG32(pb_addr + word_offset, ~mask); 4784 4785 pb_addr = (mmDMA1_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; 4786 word_offset = ((mmDMA1_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; 4787 mask = 1U << ((mmDMA1_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); 4788 mask |= 1U << ((mmDMA1_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); 4789 mask |= 1U << ((mmDMA1_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); 4790 mask |= 1U << ((mmDMA1_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); 4791 mask |= 1U << ((mmDMA1_CORE_RD_DBGMEM_RC & 0x7F) >> 2); 4792 mask |= 1U << ((mmDMA1_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); 4793 mask |= 1U << ((mmDMA1_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); 4794 mask |= 1U << ((mmDMA1_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); 4795 mask |= 1U << ((mmDMA1_CORE_DBG_DESC_CNT & 0x7F) >> 2); 4796 mask |= 1U << ((mmDMA1_CORE_DBG_STS & 0x7F) >> 2); 4797 mask |= 1U << ((mmDMA1_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); 4798 mask |= 1U << ((mmDMA1_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); 4799 4800 WREG32(pb_addr + word_offset, ~mask); 4801 4802 pb_addr = (mmDMA2_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 4803 word_offset = ((mmDMA2_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 4804 mask = 1U << ((mmDMA2_CORE_CFG_0 & 0x7F) >> 2); 4805 mask |= 1U << ((mmDMA2_CORE_CFG_1 & 0x7F) >> 2); 4806 mask |= 1U << ((mmDMA2_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); 4807 4808 WREG32(pb_addr + word_offset, ~mask); 4809 4810 pb_addr = (mmDMA2_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; 4811 word_offset = ((mmDMA2_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; 4812 mask = 1U << ((mmDMA2_CORE_PROT & 0x7F) >> 2); 4813 mask |= 1U << ((mmDMA2_CORE_SECURE_PROPS & 0x7F) >> 2); 4814 mask |= 1U << ((mmDMA2_CORE_NON_SECURE_PROPS & 0x7F) >> 2); 4815 4816 WREG32(pb_addr + word_offset, ~mask); 4817 4818 pb_addr = (mmDMA2_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; 4819 word_offset = ((mmDMA2_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) 4820 << 2; 4821 mask = 1U << ((mmDMA2_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); 4822 mask |= 1U << ((mmDMA2_CORE_RD_MAX_SIZE & 0x7F) >> 2); 4823 mask |= 1U << ((mmDMA2_CORE_RD_ARCACHE & 0x7F) >> 2); 4824 mask |= 1U << ((mmDMA2_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); 4825 mask |= 1U << ((mmDMA2_CORE_RD_INFLIGHTS & 0x7F) >> 2); 4826 mask |= 1U << ((mmDMA2_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); 4827 mask |= 1U << ((mmDMA2_CORE_WR_MAX_AWID & 0x7F) >> 2); 4828 mask |= 1U << ((mmDMA2_CORE_WR_AWCACHE & 0x7F) >> 2); 4829 mask |= 1U << ((mmDMA2_CORE_WR_INFLIGHTS & 0x7F) >> 2); 4830 mask |= 1U << ((mmDMA2_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 4831 mask |= 1U << ((mmDMA2_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 4832 mask |= 1U << ((mmDMA2_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 4833 mask |= 1U << ((mmDMA2_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 4834 mask |= 1U << ((mmDMA2_CORE_ERR_CFG & 0x7F) >> 2); 4835 mask |= 1U << ((mmDMA2_CORE_ERR_CAUSE & 0x7F) >> 2); 4836 mask |= 1U << ((mmDMA2_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); 4837 mask |= 1U << ((mmDMA2_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); 4838 mask |= 1U << ((mmDMA2_CORE_ERRMSG_WDATA & 0x7F) >> 2); 4839 4840 WREG32(pb_addr + word_offset, ~mask); 4841 4842 pb_addr = (mmDMA2_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; 4843 word_offset = ((mmDMA2_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; 4844 mask = 1U << ((mmDMA2_CORE_STS0 & 0x7F) >> 2); 4845 mask |= 1U << ((mmDMA2_CORE_STS1 & 0x7F) >> 2); 4846 4847 WREG32(pb_addr + word_offset, ~mask); 4848 4849 pb_addr = (mmDMA2_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; 4850 word_offset = ((mmDMA2_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; 4851 mask = 1U << ((mmDMA2_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); 4852 mask |= 1U << ((mmDMA2_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); 4853 mask |= 1U << ((mmDMA2_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); 4854 mask |= 1U << ((mmDMA2_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); 4855 mask |= 1U << ((mmDMA2_CORE_RD_DBGMEM_RC & 0x7F) >> 2); 4856 mask |= 1U << ((mmDMA2_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); 4857 mask |= 1U << ((mmDMA2_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); 4858 mask |= 1U << ((mmDMA2_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); 4859 mask |= 1U << ((mmDMA2_CORE_DBG_DESC_CNT & 0x7F) >> 2); 4860 mask |= 1U << ((mmDMA2_CORE_DBG_STS & 0x7F) >> 2); 4861 mask |= 1U << ((mmDMA2_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); 4862 mask |= 1U << ((mmDMA2_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); 4863 4864 WREG32(pb_addr + word_offset, ~mask); 4865 4866 pb_addr = (mmDMA3_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 4867 word_offset = ((mmDMA3_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 4868 mask = 1U << ((mmDMA3_CORE_CFG_0 & 0x7F) >> 2); 4869 mask |= 1U << ((mmDMA3_CORE_CFG_1 & 0x7F) >> 2); 4870 mask |= 1U << ((mmDMA3_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); 4871 4872 WREG32(pb_addr + word_offset, ~mask); 4873 4874 pb_addr = (mmDMA3_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; 4875 word_offset = ((mmDMA3_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; 4876 mask = 1U << ((mmDMA3_CORE_PROT & 0x7F) >> 2); 4877 mask |= 1U << ((mmDMA3_CORE_SECURE_PROPS & 0x7F) >> 2); 4878 mask |= 1U << ((mmDMA3_CORE_NON_SECURE_PROPS & 0x7F) >> 2); 4879 4880 WREG32(pb_addr + word_offset, ~mask); 4881 4882 pb_addr = (mmDMA3_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; 4883 word_offset = ((mmDMA3_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) 4884 << 2; 4885 mask = 1U << ((mmDMA3_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); 4886 mask |= 1U << ((mmDMA3_CORE_RD_MAX_SIZE & 0x7F) >> 2); 4887 mask |= 1U << ((mmDMA3_CORE_RD_ARCACHE & 0x7F) >> 2); 4888 mask |= 1U << ((mmDMA3_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); 4889 mask |= 1U << ((mmDMA3_CORE_RD_INFLIGHTS & 0x7F) >> 2); 4890 mask |= 1U << ((mmDMA3_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); 4891 mask |= 1U << ((mmDMA3_CORE_WR_MAX_AWID & 0x7F) >> 2); 4892 mask |= 1U << ((mmDMA3_CORE_WR_AWCACHE & 0x7F) >> 2); 4893 mask |= 1U << ((mmDMA3_CORE_WR_INFLIGHTS & 0x7F) >> 2); 4894 mask |= 1U << ((mmDMA3_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 4895 mask |= 1U << ((mmDMA3_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 4896 mask |= 1U << ((mmDMA3_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 4897 mask |= 1U << ((mmDMA3_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 4898 mask |= 1U << ((mmDMA3_CORE_ERR_CFG & 0x7F) >> 2); 4899 mask |= 1U << ((mmDMA3_CORE_ERR_CAUSE & 0x7F) >> 2); 4900 mask |= 1U << ((mmDMA3_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); 4901 mask |= 1U << ((mmDMA3_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); 4902 mask |= 1U << ((mmDMA3_CORE_ERRMSG_WDATA & 0x7F) >> 2); 4903 4904 WREG32(pb_addr + word_offset, ~mask); 4905 4906 pb_addr = (mmDMA3_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; 4907 word_offset = ((mmDMA3_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; 4908 mask = 1U << ((mmDMA3_CORE_STS0 & 0x7F) >> 2); 4909 mask |= 1U << ((mmDMA3_CORE_STS1 & 0x7F) >> 2); 4910 4911 WREG32(pb_addr + word_offset, ~mask); 4912 4913 pb_addr = (mmDMA3_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; 4914 word_offset = ((mmDMA3_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; 4915 mask = 1U << ((mmDMA3_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); 4916 mask |= 1U << ((mmDMA3_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); 4917 mask |= 1U << ((mmDMA3_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); 4918 mask |= 1U << ((mmDMA3_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); 4919 mask |= 1U << ((mmDMA3_CORE_RD_DBGMEM_RC & 0x7F) >> 2); 4920 mask |= 1U << ((mmDMA3_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); 4921 mask |= 1U << ((mmDMA3_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); 4922 mask |= 1U << ((mmDMA3_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); 4923 mask |= 1U << ((mmDMA3_CORE_DBG_DESC_CNT & 0x7F) >> 2); 4924 mask |= 1U << ((mmDMA3_CORE_DBG_STS & 0x7F) >> 2); 4925 mask |= 1U << ((mmDMA3_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); 4926 mask |= 1U << ((mmDMA3_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); 4927 4928 WREG32(pb_addr + word_offset, ~mask); 4929 4930 pb_addr = (mmDMA4_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 4931 word_offset = ((mmDMA4_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 4932 mask = 1U << ((mmDMA4_CORE_CFG_0 & 0x7F) >> 2); 4933 mask |= 1U << ((mmDMA4_CORE_CFG_1 & 0x7F) >> 2); 4934 mask |= 1U << ((mmDMA4_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); 4935 4936 WREG32(pb_addr + word_offset, ~mask); 4937 4938 pb_addr = (mmDMA4_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; 4939 word_offset = ((mmDMA4_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; 4940 mask = 1U << ((mmDMA4_CORE_PROT & 0x7F) >> 2); 4941 mask |= 1U << ((mmDMA4_CORE_SECURE_PROPS & 0x7F) >> 2); 4942 mask |= 1U << ((mmDMA4_CORE_NON_SECURE_PROPS & 0x7F) >> 2); 4943 4944 WREG32(pb_addr + word_offset, ~mask); 4945 4946 pb_addr = (mmDMA4_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; 4947 word_offset = ((mmDMA4_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) 4948 << 2; 4949 mask = 1U << ((mmDMA4_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); 4950 mask |= 1U << ((mmDMA4_CORE_RD_MAX_SIZE & 0x7F) >> 2); 4951 mask |= 1U << ((mmDMA4_CORE_RD_ARCACHE & 0x7F) >> 2); 4952 mask |= 1U << ((mmDMA4_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); 4953 mask |= 1U << ((mmDMA4_CORE_RD_INFLIGHTS & 0x7F) >> 2); 4954 mask |= 1U << ((mmDMA4_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); 4955 mask |= 1U << ((mmDMA4_CORE_WR_MAX_AWID & 0x7F) >> 2); 4956 mask |= 1U << ((mmDMA4_CORE_WR_AWCACHE & 0x7F) >> 2); 4957 mask |= 1U << ((mmDMA4_CORE_WR_INFLIGHTS & 0x7F) >> 2); 4958 mask |= 1U << ((mmDMA4_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 4959 mask |= 1U << ((mmDMA4_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 4960 mask |= 1U << ((mmDMA4_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 4961 mask |= 1U << ((mmDMA4_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 4962 mask |= 1U << ((mmDMA4_CORE_ERR_CFG & 0x7F) >> 2); 4963 mask |= 1U << ((mmDMA4_CORE_ERR_CAUSE & 0x7F) >> 2); 4964 mask |= 1U << ((mmDMA4_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); 4965 mask |= 1U << ((mmDMA4_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); 4966 mask |= 1U << ((mmDMA4_CORE_ERRMSG_WDATA & 0x7F) >> 2); 4967 4968 WREG32(pb_addr + word_offset, ~mask); 4969 4970 pb_addr = (mmDMA4_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; 4971 word_offset = ((mmDMA4_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; 4972 mask = 1U << ((mmDMA4_CORE_STS0 & 0x7F) >> 2); 4973 mask |= 1U << ((mmDMA4_CORE_STS1 & 0x7F) >> 2); 4974 4975 WREG32(pb_addr + word_offset, ~mask); 4976 4977 pb_addr = (mmDMA4_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; 4978 word_offset = ((mmDMA4_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; 4979 mask = 1U << ((mmDMA4_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); 4980 mask |= 1U << ((mmDMA4_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); 4981 mask |= 1U << ((mmDMA4_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); 4982 mask |= 1U << ((mmDMA4_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); 4983 mask |= 1U << ((mmDMA4_CORE_RD_DBGMEM_RC & 0x7F) >> 2); 4984 mask |= 1U << ((mmDMA4_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); 4985 mask |= 1U << ((mmDMA4_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); 4986 mask |= 1U << ((mmDMA4_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); 4987 mask |= 1U << ((mmDMA4_CORE_DBG_DESC_CNT & 0x7F) >> 2); 4988 mask |= 1U << ((mmDMA4_CORE_DBG_STS & 0x7F) >> 2); 4989 mask |= 1U << ((mmDMA4_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); 4990 mask |= 1U << ((mmDMA4_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); 4991 4992 WREG32(pb_addr + word_offset, ~mask); 4993 4994 pb_addr = (mmDMA5_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 4995 word_offset = ((mmDMA5_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 4996 mask = 1U << ((mmDMA5_CORE_CFG_0 & 0x7F) >> 2); 4997 mask |= 1U << ((mmDMA5_CORE_CFG_1 & 0x7F) >> 2); 4998 mask |= 1U << ((mmDMA5_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); 4999 5000 WREG32(pb_addr + word_offset, ~mask); 5001 5002 pb_addr = (mmDMA5_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; 5003 word_offset = ((mmDMA5_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; 5004 mask = 1U << ((mmDMA5_CORE_PROT & 0x7F) >> 2); 5005 mask |= 1U << ((mmDMA5_CORE_SECURE_PROPS & 0x7F) >> 2); 5006 mask |= 1U << ((mmDMA5_CORE_NON_SECURE_PROPS & 0x7F) >> 2); 5007 5008 WREG32(pb_addr + word_offset, ~mask); 5009 5010 pb_addr = (mmDMA5_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; 5011 word_offset = ((mmDMA5_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) 5012 << 2; 5013 mask = 1U << ((mmDMA5_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); 5014 mask |= 1U << ((mmDMA5_CORE_RD_MAX_SIZE & 0x7F) >> 2); 5015 mask |= 1U << ((mmDMA5_CORE_RD_ARCACHE & 0x7F) >> 2); 5016 mask |= 1U << ((mmDMA5_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); 5017 mask |= 1U << ((mmDMA5_CORE_RD_INFLIGHTS & 0x7F) >> 2); 5018 mask |= 1U << ((mmDMA5_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); 5019 mask |= 1U << ((mmDMA5_CORE_WR_MAX_AWID & 0x7F) >> 2); 5020 mask |= 1U << ((mmDMA5_CORE_WR_AWCACHE & 0x7F) >> 2); 5021 mask |= 1U << ((mmDMA5_CORE_WR_INFLIGHTS & 0x7F) >> 2); 5022 mask |= 1U << ((mmDMA5_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 5023 mask |= 1U << ((mmDMA5_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 5024 mask |= 1U << ((mmDMA5_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 5025 mask |= 1U << ((mmDMA5_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 5026 mask |= 1U << ((mmDMA5_CORE_ERR_CFG & 0x7F) >> 2); 5027 mask |= 1U << ((mmDMA5_CORE_ERR_CAUSE & 0x7F) >> 2); 5028 mask |= 1U << ((mmDMA5_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); 5029 mask |= 1U << ((mmDMA5_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); 5030 mask |= 1U << ((mmDMA5_CORE_ERRMSG_WDATA & 0x7F) >> 2); 5031 5032 WREG32(pb_addr + word_offset, ~mask); 5033 5034 pb_addr = (mmDMA5_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; 5035 word_offset = ((mmDMA5_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; 5036 mask = 1U << ((mmDMA5_CORE_STS0 & 0x7F) >> 2); 5037 mask |= 1U << ((mmDMA5_CORE_STS1 & 0x7F) >> 2); 5038 5039 WREG32(pb_addr + word_offset, ~mask); 5040 5041 pb_addr = (mmDMA5_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; 5042 word_offset = ((mmDMA5_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; 5043 mask = 1U << ((mmDMA5_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); 5044 mask |= 1U << ((mmDMA5_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); 5045 mask |= 1U << ((mmDMA5_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); 5046 mask |= 1U << ((mmDMA5_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); 5047 mask |= 1U << ((mmDMA5_CORE_RD_DBGMEM_RC & 0x7F) >> 2); 5048 mask |= 1U << ((mmDMA5_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); 5049 mask |= 1U << ((mmDMA5_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); 5050 mask |= 1U << ((mmDMA5_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); 5051 mask |= 1U << ((mmDMA5_CORE_DBG_DESC_CNT & 0x7F) >> 2); 5052 mask |= 1U << ((mmDMA5_CORE_DBG_STS & 0x7F) >> 2); 5053 mask |= 1U << ((mmDMA5_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); 5054 mask |= 1U << ((mmDMA5_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); 5055 5056 WREG32(pb_addr + word_offset, ~mask); 5057 5058 pb_addr = (mmDMA6_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 5059 word_offset = ((mmDMA6_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 5060 mask = 1U << ((mmDMA6_CORE_CFG_0 & 0x7F) >> 2); 5061 mask |= 1U << ((mmDMA6_CORE_CFG_1 & 0x7F) >> 2); 5062 mask |= 1U << ((mmDMA6_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); 5063 5064 WREG32(pb_addr + word_offset, ~mask); 5065 5066 pb_addr = (mmDMA6_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; 5067 word_offset = ((mmDMA6_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; 5068 mask = 1U << ((mmDMA6_CORE_PROT & 0x7F) >> 2); 5069 mask |= 1U << ((mmDMA6_CORE_SECURE_PROPS & 0x7F) >> 2); 5070 mask |= 1U << ((mmDMA6_CORE_NON_SECURE_PROPS & 0x7F) >> 2); 5071 5072 WREG32(pb_addr + word_offset, ~mask); 5073 5074 pb_addr = (mmDMA6_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; 5075 word_offset = ((mmDMA6_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) 5076 << 2; 5077 mask = 1U << ((mmDMA6_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); 5078 mask |= 1U << ((mmDMA6_CORE_RD_MAX_SIZE & 0x7F) >> 2); 5079 mask |= 1U << ((mmDMA6_CORE_RD_ARCACHE & 0x7F) >> 2); 5080 mask |= 1U << ((mmDMA6_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); 5081 mask |= 1U << ((mmDMA6_CORE_RD_INFLIGHTS & 0x7F) >> 2); 5082 mask |= 1U << ((mmDMA6_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); 5083 mask |= 1U << ((mmDMA6_CORE_WR_MAX_AWID & 0x7F) >> 2); 5084 mask |= 1U << ((mmDMA6_CORE_WR_AWCACHE & 0x7F) >> 2); 5085 mask |= 1U << ((mmDMA6_CORE_WR_INFLIGHTS & 0x7F) >> 2); 5086 mask |= 1U << ((mmDMA6_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 5087 mask |= 1U << ((mmDMA6_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 5088 mask |= 1U << ((mmDMA6_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 5089 mask |= 1U << ((mmDMA6_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 5090 mask |= 1U << ((mmDMA6_CORE_ERR_CFG & 0x7F) >> 2); 5091 mask |= 1U << ((mmDMA6_CORE_ERR_CAUSE & 0x7F) >> 2); 5092 mask |= 1U << ((mmDMA6_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); 5093 mask |= 1U << ((mmDMA6_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); 5094 mask |= 1U << ((mmDMA6_CORE_ERRMSG_WDATA & 0x7F) >> 2); 5095 5096 WREG32(pb_addr + word_offset, ~mask); 5097 5098 pb_addr = (mmDMA6_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; 5099 word_offset = ((mmDMA6_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; 5100 mask = 1U << ((mmDMA6_CORE_STS0 & 0x7F) >> 2); 5101 mask |= 1U << ((mmDMA6_CORE_STS1 & 0x7F) >> 2); 5102 5103 WREG32(pb_addr + word_offset, ~mask); 5104 5105 pb_addr = (mmDMA6_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; 5106 word_offset = ((mmDMA6_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; 5107 mask = 1U << ((mmDMA6_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); 5108 mask |= 1U << ((mmDMA6_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); 5109 mask |= 1U << ((mmDMA6_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); 5110 mask |= 1U << ((mmDMA6_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); 5111 mask |= 1U << ((mmDMA6_CORE_RD_DBGMEM_RC & 0x7F) >> 2); 5112 mask |= 1U << ((mmDMA6_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); 5113 mask |= 1U << ((mmDMA6_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); 5114 mask |= 1U << ((mmDMA6_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); 5115 mask |= 1U << ((mmDMA6_CORE_DBG_DESC_CNT & 0x7F) >> 2); 5116 mask |= 1U << ((mmDMA6_CORE_DBG_STS & 0x7F) >> 2); 5117 mask |= 1U << ((mmDMA6_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); 5118 mask |= 1U << ((mmDMA6_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); 5119 5120 WREG32(pb_addr + word_offset, ~mask); 5121 5122 pb_addr = (mmDMA7_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 5123 word_offset = ((mmDMA7_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 5124 mask = 1U << ((mmDMA7_CORE_CFG_0 & 0x7F) >> 2); 5125 mask |= 1U << ((mmDMA7_CORE_CFG_1 & 0x7F) >> 2); 5126 mask |= 1U << ((mmDMA7_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); 5127 5128 WREG32(pb_addr + word_offset, ~mask); 5129 5130 pb_addr = (mmDMA7_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; 5131 word_offset = ((mmDMA7_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; 5132 mask = 1U << ((mmDMA7_CORE_PROT & 0x7F) >> 2); 5133 mask |= 1U << ((mmDMA7_CORE_SECURE_PROPS & 0x7F) >> 2); 5134 mask |= 1U << ((mmDMA7_CORE_NON_SECURE_PROPS & 0x7F) >> 2); 5135 5136 WREG32(pb_addr + word_offset, ~mask); 5137 5138 pb_addr = (mmDMA7_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; 5139 word_offset = ((mmDMA7_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) 5140 << 2; 5141 mask = 1U << ((mmDMA7_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); 5142 mask |= 1U << ((mmDMA7_CORE_RD_MAX_SIZE & 0x7F) >> 2); 5143 mask |= 1U << ((mmDMA7_CORE_RD_ARCACHE & 0x7F) >> 2); 5144 mask |= 1U << ((mmDMA7_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); 5145 mask |= 1U << ((mmDMA7_CORE_RD_INFLIGHTS & 0x7F) >> 2); 5146 mask |= 1U << ((mmDMA7_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); 5147 mask |= 1U << ((mmDMA7_CORE_WR_MAX_AWID & 0x7F) >> 2); 5148 mask |= 1U << ((mmDMA7_CORE_WR_AWCACHE & 0x7F) >> 2); 5149 mask |= 1U << ((mmDMA7_CORE_WR_INFLIGHTS & 0x7F) >> 2); 5150 mask |= 1U << ((mmDMA7_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 5151 mask |= 1U << ((mmDMA7_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 5152 mask |= 1U << ((mmDMA7_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 5153 mask |= 1U << ((mmDMA7_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 5154 mask |= 1U << ((mmDMA7_CORE_ERR_CFG & 0x7F) >> 2); 5155 mask |= 1U << ((mmDMA7_CORE_ERR_CAUSE & 0x7F) >> 2); 5156 mask |= 1U << ((mmDMA7_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); 5157 mask |= 1U << ((mmDMA7_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); 5158 mask |= 1U << ((mmDMA7_CORE_ERRMSG_WDATA & 0x7F) >> 2); 5159 5160 WREG32(pb_addr + word_offset, ~mask); 5161 5162 pb_addr = (mmDMA7_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; 5163 word_offset = ((mmDMA7_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; 5164 mask = 1U << ((mmDMA7_CORE_STS0 & 0x7F) >> 2); 5165 mask |= 1U << ((mmDMA7_CORE_STS1 & 0x7F) >> 2); 5166 5167 WREG32(pb_addr + word_offset, ~mask); 5168 5169 pb_addr = (mmDMA7_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; 5170 word_offset = ((mmDMA7_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; 5171 mask = 1U << ((mmDMA7_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); 5172 mask |= 1U << ((mmDMA7_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); 5173 mask |= 1U << ((mmDMA7_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); 5174 mask |= 1U << ((mmDMA7_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); 5175 mask |= 1U << ((mmDMA7_CORE_RD_DBGMEM_RC & 0x7F) >> 2); 5176 mask |= 1U << ((mmDMA7_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); 5177 mask |= 1U << ((mmDMA7_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); 5178 mask |= 1U << ((mmDMA7_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); 5179 mask |= 1U << ((mmDMA7_CORE_DBG_DESC_CNT & 0x7F) >> 2); 5180 mask |= 1U << ((mmDMA7_CORE_DBG_STS & 0x7F) >> 2); 5181 mask |= 1U << ((mmDMA7_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); 5182 mask |= 1U << ((mmDMA7_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); 5183 5184 WREG32(pb_addr + word_offset, ~mask); 5185} 5186 5187static void gaudi_init_nic_protection_bits(struct hl_device *hdev) 5188{ 5189 u32 pb_addr, mask; 5190 u8 word_offset; 5191 5192 WREG32(mmNIC0_QM0_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 5193 WREG32(mmNIC0_QM1_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 5194 5195 pb_addr = (mmNIC0_QM0_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 5196 word_offset = ((mmNIC0_QM0_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 5197 mask = 1U << ((mmNIC0_QM0_GLBL_CFG0 & 0x7F) >> 2); 5198 mask |= 1U << ((mmNIC0_QM0_GLBL_CFG1 & 0x7F) >> 2); 5199 mask |= 1U << ((mmNIC0_QM0_GLBL_PROT & 0x7F) >> 2); 5200 mask |= 1U << ((mmNIC0_QM0_GLBL_ERR_CFG & 0x7F) >> 2); 5201 mask |= 1U << ((mmNIC0_QM0_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 5202 mask |= 1U << ((mmNIC0_QM0_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 5203 mask |= 1U << ((mmNIC0_QM0_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 5204 mask |= 1U << ((mmNIC0_QM0_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 5205 mask |= 1U << ((mmNIC0_QM0_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 5206 mask |= 1U << ((mmNIC0_QM0_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 5207 mask |= 1U << ((mmNIC0_QM0_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 5208 mask |= 1U << ((mmNIC0_QM0_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 5209 mask |= 1U << ((mmNIC0_QM0_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 5210 mask |= 1U << ((mmNIC0_QM0_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 5211 mask |= 1U << ((mmNIC0_QM0_GLBL_STS0 & 0x7F) >> 2); 5212 mask |= 1U << ((mmNIC0_QM0_GLBL_STS1_0 & 0x7F) >> 2); 5213 mask |= 1U << ((mmNIC0_QM0_GLBL_STS1_1 & 0x7F) >> 2); 5214 mask |= 1U << ((mmNIC0_QM0_GLBL_STS1_2 & 0x7F) >> 2); 5215 mask |= 1U << ((mmNIC0_QM0_GLBL_STS1_3 & 0x7F) >> 2); 5216 mask |= 1U << ((mmNIC0_QM0_GLBL_STS1_4 & 0x7F) >> 2); 5217 mask |= 1U << ((mmNIC0_QM0_GLBL_MSG_EN_0 & 0x7F) >> 2); 5218 mask |= 1U << ((mmNIC0_QM0_GLBL_MSG_EN_1 & 0x7F) >> 2); 5219 mask |= 1U << ((mmNIC0_QM0_GLBL_MSG_EN_2 & 0x7F) >> 2); 5220 mask |= 1U << ((mmNIC0_QM0_GLBL_MSG_EN_3 & 0x7F) >> 2); 5221 mask |= 1U << ((mmNIC0_QM0_GLBL_MSG_EN_4 & 0x7F) >> 2); 5222 mask |= 1U << ((mmNIC0_QM0_PQ_BASE_LO_0 & 0x7F) >> 2); 5223 mask |= 1U << ((mmNIC0_QM0_PQ_BASE_LO_1 & 0x7F) >> 2); 5224 mask |= 1U << ((mmNIC0_QM0_PQ_BASE_LO_2 & 0x7F) >> 2); 5225 mask |= 1U << ((mmNIC0_QM0_PQ_BASE_LO_3 & 0x7F) >> 2); 5226 5227 WREG32(pb_addr + word_offset, ~mask); 5228 5229 pb_addr = (mmNIC0_QM0_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 5230 word_offset = ((mmNIC0_QM0_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 5231 mask = 1U << ((mmNIC0_QM0_PQ_BASE_HI_0 & 0x7F) >> 2); 5232 mask |= 1U << ((mmNIC0_QM0_PQ_BASE_HI_1 & 0x7F) >> 2); 5233 mask |= 1U << ((mmNIC0_QM0_PQ_BASE_HI_2 & 0x7F) >> 2); 5234 mask |= 1U << ((mmNIC0_QM0_PQ_BASE_HI_3 & 0x7F) >> 2); 5235 mask |= 1U << ((mmNIC0_QM0_PQ_SIZE_0 & 0x7F) >> 2); 5236 mask |= 1U << ((mmNIC0_QM0_PQ_SIZE_1 & 0x7F) >> 2); 5237 mask |= 1U << ((mmNIC0_QM0_PQ_SIZE_2 & 0x7F) >> 2); 5238 mask |= 1U << ((mmNIC0_QM0_PQ_SIZE_3 & 0x7F) >> 2); 5239 mask |= 1U << ((mmNIC0_QM0_PQ_PI_0 & 0x7F) >> 2); 5240 mask |= 1U << ((mmNIC0_QM0_PQ_PI_1 & 0x7F) >> 2); 5241 mask |= 1U << ((mmNIC0_QM0_PQ_PI_2 & 0x7F) >> 2); 5242 mask |= 1U << ((mmNIC0_QM0_PQ_PI_3 & 0x7F) >> 2); 5243 mask |= 1U << ((mmNIC0_QM0_PQ_CI_0 & 0x7F) >> 2); 5244 mask |= 1U << ((mmNIC0_QM0_PQ_CI_1 & 0x7F) >> 2); 5245 mask |= 1U << ((mmNIC0_QM0_PQ_CI_2 & 0x7F) >> 2); 5246 mask |= 1U << ((mmNIC0_QM0_PQ_CI_3 & 0x7F) >> 2); 5247 mask |= 1U << ((mmNIC0_QM0_PQ_CFG0_0 & 0x7F) >> 2); 5248 mask |= 1U << ((mmNIC0_QM0_PQ_CFG0_1 & 0x7F) >> 2); 5249 mask |= 1U << ((mmNIC0_QM0_PQ_CFG0_2 & 0x7F) >> 2); 5250 mask |= 1U << ((mmNIC0_QM0_PQ_CFG0_3 & 0x7F) >> 2); 5251 mask |= 1U << ((mmNIC0_QM0_PQ_CFG1_0 & 0x7F) >> 2); 5252 mask |= 1U << ((mmNIC0_QM0_PQ_CFG1_1 & 0x7F) >> 2); 5253 mask |= 1U << ((mmNIC0_QM0_PQ_CFG1_2 & 0x7F) >> 2); 5254 mask |= 1U << ((mmNIC0_QM0_PQ_CFG1_3 & 0x7F) >> 2); 5255 mask |= 1U << ((mmNIC0_QM0_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 5256 mask |= 1U << ((mmNIC0_QM0_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 5257 mask |= 1U << ((mmNIC0_QM0_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 5258 mask |= 1U << ((mmNIC0_QM0_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 5259 mask |= 1U << ((mmNIC0_QM0_PQ_STS0_0 & 0x7F) >> 2); 5260 mask |= 1U << ((mmNIC0_QM0_PQ_STS0_1 & 0x7F) >> 2); 5261 mask |= 1U << ((mmNIC0_QM0_PQ_STS0_2 & 0x7F) >> 2); 5262 mask |= 1U << ((mmNIC0_QM0_PQ_STS0_3 & 0x7F) >> 2); 5263 5264 WREG32(pb_addr + word_offset, ~mask); 5265 5266 pb_addr = (mmNIC0_QM0_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 5267 word_offset = ((mmNIC0_QM0_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 5268 mask = 1U << ((mmNIC0_QM0_PQ_STS1_0 & 0x7F) >> 2); 5269 mask |= 1U << ((mmNIC0_QM0_PQ_STS1_1 & 0x7F) >> 2); 5270 mask |= 1U << ((mmNIC0_QM0_PQ_STS1_2 & 0x7F) >> 2); 5271 mask |= 1U << ((mmNIC0_QM0_PQ_STS1_3 & 0x7F) >> 2); 5272 mask |= 1U << ((mmNIC0_QM0_CQ_STS0_0 & 0x7F) >> 2); 5273 mask |= 1U << ((mmNIC0_QM0_CQ_STS0_1 & 0x7F) >> 2); 5274 mask |= 1U << ((mmNIC0_QM0_CQ_STS0_2 & 0x7F) >> 2); 5275 mask |= 1U << ((mmNIC0_QM0_CQ_STS0_3 & 0x7F) >> 2); 5276 mask |= 1U << ((mmNIC0_QM0_CQ_STS1_0 & 0x7F) >> 2); 5277 mask |= 1U << ((mmNIC0_QM0_CQ_STS1_1 & 0x7F) >> 2); 5278 mask |= 1U << ((mmNIC0_QM0_CQ_STS1_2 & 0x7F) >> 2); 5279 mask |= 1U << ((mmNIC0_QM0_CQ_STS1_3 & 0x7F) >> 2); 5280 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_0 & 0x7F) >> 2); 5281 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_0 & 0x7F) >> 2); 5282 mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_0 & 0x7F) >> 2); 5283 5284 WREG32(pb_addr + word_offset, ~mask); 5285 5286 pb_addr = (mmNIC0_QM0_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 5287 word_offset = ((mmNIC0_QM0_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 5288 mask = 1U << ((mmNIC0_QM0_CQ_CTL_0 & 0x7F) >> 2); 5289 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_1 & 0x7F) >> 2); 5290 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_1 & 0x7F) >> 2); 5291 mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_1 & 0x7F) >> 2); 5292 mask |= 1U << ((mmNIC0_QM0_CQ_CTL_1 & 0x7F) >> 2); 5293 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_2 & 0x7F) >> 2); 5294 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_2 & 0x7F) >> 2); 5295 mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_2 & 0x7F) >> 2); 5296 mask |= 1U << ((mmNIC0_QM0_CQ_CTL_2 & 0x7F) >> 2); 5297 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_3 & 0x7F) >> 2); 5298 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_3 & 0x7F) >> 2); 5299 mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_3 & 0x7F) >> 2); 5300 mask |= 1U << ((mmNIC0_QM0_CQ_CTL_3 & 0x7F) >> 2); 5301 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 5302 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 5303 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 5304 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 5305 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 5306 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 5307 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 5308 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 5309 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 5310 mask |= 1U << ((mmNIC0_QM0_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 5311 mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_STS_0 & 0x7F) >> 2); 5312 mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_STS_1 & 0x7F) >> 2); 5313 mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_STS_2 & 0x7F) >> 2); 5314 mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_STS_3 & 0x7F) >> 2); 5315 mask |= 1U << ((mmNIC0_QM0_CQ_TSIZE_STS_4 & 0x7F) >> 2); 5316 5317 WREG32(pb_addr + word_offset, ~mask); 5318 5319 pb_addr = (mmNIC0_QM0_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 5320 word_offset = ((mmNIC0_QM0_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 5321 mask = 1U << ((mmNIC0_QM0_CQ_CTL_STS_0 & 0x7F) >> 2); 5322 mask |= 1U << ((mmNIC0_QM0_CQ_CTL_STS_1 & 0x7F) >> 2); 5323 mask |= 1U << ((mmNIC0_QM0_CQ_CTL_STS_2 & 0x7F) >> 2); 5324 mask |= 1U << ((mmNIC0_QM0_CQ_CTL_STS_3 & 0x7F) >> 2); 5325 mask |= 1U << ((mmNIC0_QM0_CQ_CTL_STS_4 & 0x7F) >> 2); 5326 mask |= 1U << ((mmNIC0_QM0_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 5327 mask |= 1U << ((mmNIC0_QM0_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 5328 mask |= 1U << ((mmNIC0_QM0_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 5329 mask |= 1U << ((mmNIC0_QM0_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 5330 mask |= 1U << ((mmNIC0_QM0_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 5331 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 5332 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 5333 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 5334 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 5335 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 5336 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 5337 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 5338 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 5339 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 5340 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 5341 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 5342 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 5343 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 5344 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 5345 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 5346 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 5347 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 5348 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 5349 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 5350 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 5351 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 5352 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 5353 5354 WREG32(pb_addr + word_offset, ~mask); 5355 5356 pb_addr = (mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 5357 word_offset = ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2 & 5358 PROT_BITS_OFFS) >> 7) << 2; 5359 mask = 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 5360 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 5361 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 5362 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 5363 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 5364 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 5365 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 5366 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 5367 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 5368 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 5369 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 5370 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 5371 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 5372 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 5373 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 5374 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 5375 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 5376 mask |= 1U << ((mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 5377 mask |= 1U << ((mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 5378 mask |= 1U << ((mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 5379 mask |= 1U << ((mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 5380 mask |= 1U << ((mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 5381 mask |= 1U << ((mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 5382 mask |= 1U << ((mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 5383 mask |= 1U << ((mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 5384 mask |= 1U << ((mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 5385 mask |= 1U << ((mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 5386 mask |= 1U << ((mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 5387 mask |= 1U << ((mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 5388 mask |= 1U << ((mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 5389 mask |= 1U << ((mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 5390 5391 WREG32(pb_addr + word_offset, ~mask); 5392 5393 pb_addr = (mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 5394 PROT_BITS_OFFS; 5395 word_offset = ((mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & 5396 PROT_BITS_OFFS) >> 7) << 2; 5397 mask = 1U << ((mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 5398 mask |= 1U << ((mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 5399 5400 WREG32(pb_addr + word_offset, ~mask); 5401 5402 pb_addr = (mmNIC0_QM0_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 5403 word_offset = ((mmNIC0_QM0_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 5404 mask = 1U << ((mmNIC0_QM0_CP_STS_0 & 0x7F) >> 2); 5405 mask |= 1U << ((mmNIC0_QM0_CP_STS_1 & 0x7F) >> 2); 5406 mask |= 1U << ((mmNIC0_QM0_CP_STS_2 & 0x7F) >> 2); 5407 mask |= 1U << ((mmNIC0_QM0_CP_STS_3 & 0x7F) >> 2); 5408 mask |= 1U << ((mmNIC0_QM0_CP_STS_4 & 0x7F) >> 2); 5409 mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 5410 mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 5411 mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 5412 mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 5413 mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 5414 mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 5415 mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 5416 mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 5417 mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 5418 mask |= 1U << ((mmNIC0_QM0_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 5419 mask |= 1U << ((mmNIC0_QM0_CP_BARRIER_CFG_0 & 0x7F) >> 2); 5420 mask |= 1U << ((mmNIC0_QM0_CP_BARRIER_CFG_1 & 0x7F) >> 2); 5421 mask |= 1U << ((mmNIC0_QM0_CP_BARRIER_CFG_2 & 0x7F) >> 2); 5422 5423 WREG32(pb_addr + word_offset, ~mask); 5424 5425 pb_addr = (mmNIC0_QM0_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 5426 word_offset = ((mmNIC0_QM0_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) 5427 >> 7) << 2; 5428 mask = 1U << ((mmNIC0_QM0_CP_BARRIER_CFG_3 & 0x7F) >> 2); 5429 mask |= 1U << ((mmNIC0_QM0_CP_BARRIER_CFG_4 & 0x7F) >> 2); 5430 mask |= 1U << ((mmNIC0_QM0_CP_DBG_0_0 & 0x7F) >> 2); 5431 mask |= 1U << ((mmNIC0_QM0_CP_DBG_0_1 & 0x7F) >> 2); 5432 5433 WREG32(pb_addr + word_offset, ~mask); 5434 5435 pb_addr = (mmNIC0_QM0_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 5436 word_offset = ((mmNIC0_QM0_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 5437 mask = 1U << ((mmNIC0_QM0_CP_DBG_0_2 & 0x7F) >> 2); 5438 mask |= 1U << ((mmNIC0_QM0_CP_DBG_0_3 & 0x7F) >> 2); 5439 mask |= 1U << ((mmNIC0_QM0_CP_DBG_0_4 & 0x7F) >> 2); 5440 mask |= 1U << ((mmNIC0_QM0_CP_ARUSER_31_11_0 & 0x7F) >> 2); 5441 mask |= 1U << ((mmNIC0_QM0_CP_ARUSER_31_11_1 & 0x7F) >> 2); 5442 mask |= 1U << ((mmNIC0_QM0_CP_ARUSER_31_11_2 & 0x7F) >> 2); 5443 mask |= 1U << ((mmNIC0_QM0_CP_ARUSER_31_11_3 & 0x7F) >> 2); 5444 mask |= 1U << ((mmNIC0_QM0_CP_ARUSER_31_11_4 & 0x7F) >> 2); 5445 mask |= 1U << ((mmNIC0_QM0_CP_AWUSER_31_11_0 & 0x7F) >> 2); 5446 mask |= 1U << ((mmNIC0_QM0_CP_AWUSER_31_11_1 & 0x7F) >> 2); 5447 mask |= 1U << ((mmNIC0_QM0_CP_AWUSER_31_11_2 & 0x7F) >> 2); 5448 mask |= 1U << ((mmNIC0_QM0_CP_AWUSER_31_11_3 & 0x7F) >> 2); 5449 mask |= 1U << ((mmNIC0_QM0_CP_AWUSER_31_11_4 & 0x7F) >> 2); 5450 5451 WREG32(pb_addr + word_offset, ~mask); 5452 5453 pb_addr = (mmNIC0_QM0_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 5454 word_offset = ((mmNIC0_QM0_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 5455 mask = 1U << ((mmNIC0_QM0_ARB_CFG_1 & 0x7F) >> 2); 5456 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 5457 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 5458 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 5459 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 5460 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 5461 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 5462 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 5463 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 5464 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 5465 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 5466 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 5467 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 5468 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 5469 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 5470 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 5471 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 5472 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 5473 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 5474 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 5475 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 5476 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 5477 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 5478 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 5479 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 5480 5481 WREG32(pb_addr + word_offset, ~mask); 5482 5483 pb_addr = (mmNIC0_QM0_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 5484 word_offset = ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_24 & 5485 PROT_BITS_OFFS) >> 7) << 2; 5486 mask = 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 5487 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 5488 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 5489 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 5490 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 5491 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 5492 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 5493 mask |= 1U << ((mmNIC0_QM0_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 5494 5495 WREG32(pb_addr + word_offset, ~mask); 5496 5497 pb_addr = (mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 5498 PROT_BITS_OFFS; 5499 word_offset = ((mmNIC0_QM0_ARB_MST_CHOISE_PUSH_OFST_23 & 5500 PROT_BITS_OFFS) >> 7) << 2; 5501 mask = 1U << ((mmNIC0_QM0_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 5502 mask |= 1U << ((mmNIC0_QM0_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 5503 mask |= 1U << ((mmNIC0_QM0_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 5504 mask |= 1U << ((mmNIC0_QM0_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 5505 mask |= 1U << ((mmNIC0_QM0_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 5506 5507 WREG32(pb_addr + word_offset, ~mask); 5508 5509 pb_addr = (mmNIC0_QM0_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 5510 word_offset = ((mmNIC0_QM0_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 5511 mask = 1U << ((mmNIC0_QM0_ARB_STATE_STS & 0x7F) >> 2); 5512 mask |= 1U << ((mmNIC0_QM0_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 5513 mask |= 1U << ((mmNIC0_QM0_ARB_MSG_STS & 0x7F) >> 2); 5514 mask |= 1U << ((mmNIC0_QM0_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 5515 mask |= 1U << ((mmNIC0_QM0_ARB_ERR_CAUSE & 0x7F) >> 2); 5516 mask |= 1U << ((mmNIC0_QM0_ARB_ERR_MSG_EN & 0x7F) >> 2); 5517 mask |= 1U << ((mmNIC0_QM0_ARB_ERR_STS_DRP & 0x7F) >> 2); 5518 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 5519 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 5520 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 5521 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 5522 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 5523 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 5524 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 5525 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 5526 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 5527 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 5528 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 5529 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 5530 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 5531 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 5532 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 5533 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 5534 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 5535 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 5536 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 5537 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 5538 5539 WREG32(pb_addr + word_offset, ~mask); 5540 5541 pb_addr = (mmNIC0_QM0_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 5542 word_offset = ((mmNIC0_QM0_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) 5543 >> 7) << 2; 5544 mask = 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 5545 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 5546 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 5547 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 5548 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 5549 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 5550 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 5551 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 5552 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 5553 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 5554 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 5555 mask |= 1U << ((mmNIC0_QM0_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 5556 mask |= 1U << ((mmNIC0_QM0_CGM_CFG & 0x7F) >> 2); 5557 mask |= 1U << ((mmNIC0_QM0_CGM_STS & 0x7F) >> 2); 5558 mask |= 1U << ((mmNIC0_QM0_CGM_CFG1 & 0x7F) >> 2); 5559 5560 WREG32(pb_addr + word_offset, ~mask); 5561 5562 pb_addr = (mmNIC0_QM0_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 5563 word_offset = ((mmNIC0_QM0_LOCAL_RANGE_BASE & PROT_BITS_OFFS) 5564 >> 7) << 2; 5565 mask = 1U << ((mmNIC0_QM0_LOCAL_RANGE_BASE & 0x7F) >> 2); 5566 mask |= 1U << ((mmNIC0_QM0_LOCAL_RANGE_SIZE & 0x7F) >> 2); 5567 mask |= 1U << ((mmNIC0_QM0_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 5568 mask |= 1U << ((mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 5569 mask |= 1U << ((mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 5570 mask |= 1U << ((mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 5571 mask |= 1U << ((mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 5572 mask |= 1U << ((mmNIC0_QM0_GLBL_AXCACHE & 0x7F) >> 2); 5573 mask |= 1U << ((mmNIC0_QM0_IND_GW_APB_CFG & 0x7F) >> 2); 5574 mask |= 1U << ((mmNIC0_QM0_IND_GW_APB_WDATA & 0x7F) >> 2); 5575 mask |= 1U << ((mmNIC0_QM0_IND_GW_APB_RDATA & 0x7F) >> 2); 5576 mask |= 1U << ((mmNIC0_QM0_IND_GW_APB_STATUS & 0x7F) >> 2); 5577 mask |= 1U << ((mmNIC0_QM0_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 5578 mask |= 1U << ((mmNIC0_QM0_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 5579 mask |= 1U << ((mmNIC0_QM0_GLBL_ERR_WDATA & 0x7F) >> 2); 5580 5581 WREG32(pb_addr + word_offset, ~mask); 5582 5583 pb_addr = (mmNIC0_QM0_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 5584 word_offset = ((mmNIC0_QM0_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) 5585 >> 7) << 2; 5586 mask = 1U << ((mmNIC0_QM0_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 5587 5588 WREG32(pb_addr + word_offset, ~mask); 5589 5590 pb_addr = (mmNIC0_QM1_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 5591 word_offset = ((mmNIC0_QM1_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 5592 mask = 1U << ((mmNIC0_QM1_GLBL_CFG0 & 0x7F) >> 2); 5593 mask |= 1U << ((mmNIC0_QM1_GLBL_CFG1 & 0x7F) >> 2); 5594 mask |= 1U << ((mmNIC0_QM1_GLBL_PROT & 0x7F) >> 2); 5595 mask |= 1U << ((mmNIC0_QM1_GLBL_ERR_CFG & 0x7F) >> 2); 5596 mask |= 1U << ((mmNIC0_QM1_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 5597 mask |= 1U << ((mmNIC0_QM1_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 5598 mask |= 1U << ((mmNIC0_QM1_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 5599 mask |= 1U << ((mmNIC0_QM1_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 5600 mask |= 1U << ((mmNIC0_QM1_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 5601 mask |= 1U << ((mmNIC0_QM1_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 5602 mask |= 1U << ((mmNIC0_QM1_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 5603 mask |= 1U << ((mmNIC0_QM1_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 5604 mask |= 1U << ((mmNIC0_QM1_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 5605 mask |= 1U << ((mmNIC0_QM1_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 5606 mask |= 1U << ((mmNIC0_QM1_GLBL_STS0 & 0x7F) >> 2); 5607 mask |= 1U << ((mmNIC0_QM1_GLBL_STS1_0 & 0x7F) >> 2); 5608 mask |= 1U << ((mmNIC0_QM1_GLBL_STS1_1 & 0x7F) >> 2); 5609 mask |= 1U << ((mmNIC0_QM1_GLBL_STS1_2 & 0x7F) >> 2); 5610 mask |= 1U << ((mmNIC0_QM1_GLBL_STS1_3 & 0x7F) >> 2); 5611 mask |= 1U << ((mmNIC0_QM1_GLBL_STS1_4 & 0x7F) >> 2); 5612 mask |= 1U << ((mmNIC0_QM1_GLBL_MSG_EN_0 & 0x7F) >> 2); 5613 mask |= 1U << ((mmNIC0_QM1_GLBL_MSG_EN_1 & 0x7F) >> 2); 5614 mask |= 1U << ((mmNIC0_QM1_GLBL_MSG_EN_2 & 0x7F) >> 2); 5615 mask |= 1U << ((mmNIC0_QM1_GLBL_MSG_EN_3 & 0x7F) >> 2); 5616 mask |= 1U << ((mmNIC0_QM1_GLBL_MSG_EN_4 & 0x7F) >> 2); 5617 mask |= 1U << ((mmNIC0_QM1_PQ_BASE_LO_0 & 0x7F) >> 2); 5618 mask |= 1U << ((mmNIC0_QM1_PQ_BASE_LO_1 & 0x7F) >> 2); 5619 mask |= 1U << ((mmNIC0_QM1_PQ_BASE_LO_2 & 0x7F) >> 2); 5620 mask |= 1U << ((mmNIC0_QM1_PQ_BASE_LO_3 & 0x7F) >> 2); 5621 5622 WREG32(pb_addr + word_offset, ~mask); 5623 5624 pb_addr = (mmNIC0_QM1_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 5625 word_offset = ((mmNIC0_QM1_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 5626 mask = 1U << ((mmNIC0_QM1_PQ_BASE_HI_0 & 0x7F) >> 2); 5627 mask |= 1U << ((mmNIC0_QM1_PQ_BASE_HI_1 & 0x7F) >> 2); 5628 mask |= 1U << ((mmNIC0_QM1_PQ_BASE_HI_2 & 0x7F) >> 2); 5629 mask |= 1U << ((mmNIC0_QM1_PQ_BASE_HI_3 & 0x7F) >> 2); 5630 mask |= 1U << ((mmNIC0_QM1_PQ_SIZE_0 & 0x7F) >> 2); 5631 mask |= 1U << ((mmNIC0_QM1_PQ_SIZE_1 & 0x7F) >> 2); 5632 mask |= 1U << ((mmNIC0_QM1_PQ_SIZE_2 & 0x7F) >> 2); 5633 mask |= 1U << ((mmNIC0_QM1_PQ_SIZE_3 & 0x7F) >> 2); 5634 mask |= 1U << ((mmNIC0_QM1_PQ_PI_0 & 0x7F) >> 2); 5635 mask |= 1U << ((mmNIC0_QM1_PQ_PI_1 & 0x7F) >> 2); 5636 mask |= 1U << ((mmNIC0_QM1_PQ_PI_2 & 0x7F) >> 2); 5637 mask |= 1U << ((mmNIC0_QM1_PQ_PI_3 & 0x7F) >> 2); 5638 mask |= 1U << ((mmNIC0_QM1_PQ_CI_0 & 0x7F) >> 2); 5639 mask |= 1U << ((mmNIC0_QM1_PQ_CI_1 & 0x7F) >> 2); 5640 mask |= 1U << ((mmNIC0_QM1_PQ_CI_2 & 0x7F) >> 2); 5641 mask |= 1U << ((mmNIC0_QM1_PQ_CI_3 & 0x7F) >> 2); 5642 mask |= 1U << ((mmNIC0_QM1_PQ_CFG0_0 & 0x7F) >> 2); 5643 mask |= 1U << ((mmNIC0_QM1_PQ_CFG0_1 & 0x7F) >> 2); 5644 mask |= 1U << ((mmNIC0_QM1_PQ_CFG0_2 & 0x7F) >> 2); 5645 mask |= 1U << ((mmNIC0_QM1_PQ_CFG0_3 & 0x7F) >> 2); 5646 mask |= 1U << ((mmNIC0_QM1_PQ_CFG1_0 & 0x7F) >> 2); 5647 mask |= 1U << ((mmNIC0_QM1_PQ_CFG1_1 & 0x7F) >> 2); 5648 mask |= 1U << ((mmNIC0_QM1_PQ_CFG1_2 & 0x7F) >> 2); 5649 mask |= 1U << ((mmNIC0_QM1_PQ_CFG1_3 & 0x7F) >> 2); 5650 mask |= 1U << ((mmNIC0_QM1_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 5651 mask |= 1U << ((mmNIC0_QM1_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 5652 mask |= 1U << ((mmNIC0_QM1_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 5653 mask |= 1U << ((mmNIC0_QM1_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 5654 mask |= 1U << ((mmNIC0_QM1_PQ_STS0_0 & 0x7F) >> 2); 5655 mask |= 1U << ((mmNIC0_QM1_PQ_STS0_1 & 0x7F) >> 2); 5656 mask |= 1U << ((mmNIC0_QM1_PQ_STS0_2 & 0x7F) >> 2); 5657 mask |= 1U << ((mmNIC0_QM1_PQ_STS0_3 & 0x7F) >> 2); 5658 5659 WREG32(pb_addr + word_offset, ~mask); 5660 5661 pb_addr = (mmNIC0_QM1_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 5662 word_offset = ((mmNIC0_QM1_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 5663 mask = 1U << ((mmNIC0_QM1_PQ_STS1_0 & 0x7F) >> 2); 5664 mask |= 1U << ((mmNIC0_QM1_PQ_STS1_1 & 0x7F) >> 2); 5665 mask |= 1U << ((mmNIC0_QM1_PQ_STS1_2 & 0x7F) >> 2); 5666 mask |= 1U << ((mmNIC0_QM1_PQ_STS1_3 & 0x7F) >> 2); 5667 mask |= 1U << ((mmNIC0_QM1_CQ_STS0_0 & 0x7F) >> 2); 5668 mask |= 1U << ((mmNIC0_QM1_CQ_STS0_1 & 0x7F) >> 2); 5669 mask |= 1U << ((mmNIC0_QM1_CQ_STS0_2 & 0x7F) >> 2); 5670 mask |= 1U << ((mmNIC0_QM1_CQ_STS0_3 & 0x7F) >> 2); 5671 mask |= 1U << ((mmNIC0_QM1_CQ_STS1_0 & 0x7F) >> 2); 5672 mask |= 1U << ((mmNIC0_QM1_CQ_STS1_1 & 0x7F) >> 2); 5673 mask |= 1U << ((mmNIC0_QM1_CQ_STS1_2 & 0x7F) >> 2); 5674 mask |= 1U << ((mmNIC0_QM1_CQ_STS1_3 & 0x7F) >> 2); 5675 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_0 & 0x7F) >> 2); 5676 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_0 & 0x7F) >> 2); 5677 mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_0 & 0x7F) >> 2); 5678 5679 WREG32(pb_addr + word_offset, ~mask); 5680 5681 pb_addr = (mmNIC0_QM1_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 5682 word_offset = ((mmNIC0_QM1_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 5683 mask = 1U << ((mmNIC0_QM1_CQ_CTL_0 & 0x7F) >> 2); 5684 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_1 & 0x7F) >> 2); 5685 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_1 & 0x7F) >> 2); 5686 mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_1 & 0x7F) >> 2); 5687 mask |= 1U << ((mmNIC0_QM1_CQ_CTL_1 & 0x7F) >> 2); 5688 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_2 & 0x7F) >> 2); 5689 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_2 & 0x7F) >> 2); 5690 mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_2 & 0x7F) >> 2); 5691 mask |= 1U << ((mmNIC0_QM1_CQ_CTL_2 & 0x7F) >> 2); 5692 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_3 & 0x7F) >> 2); 5693 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_3 & 0x7F) >> 2); 5694 mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_3 & 0x7F) >> 2); 5695 mask |= 1U << ((mmNIC0_QM1_CQ_CTL_3 & 0x7F) >> 2); 5696 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 5697 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 5698 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 5699 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 5700 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 5701 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 5702 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 5703 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 5704 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 5705 mask |= 1U << ((mmNIC0_QM1_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 5706 mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_STS_0 & 0x7F) >> 2); 5707 mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_STS_1 & 0x7F) >> 2); 5708 mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_STS_2 & 0x7F) >> 2); 5709 mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_STS_3 & 0x7F) >> 2); 5710 mask |= 1U << ((mmNIC0_QM1_CQ_TSIZE_STS_4 & 0x7F) >> 2); 5711 5712 WREG32(pb_addr + word_offset, ~mask); 5713 5714 pb_addr = (mmNIC0_QM1_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 5715 word_offset = ((mmNIC0_QM1_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 5716 mask = 1U << ((mmNIC0_QM1_CQ_CTL_STS_0 & 0x7F) >> 2); 5717 mask |= 1U << ((mmNIC0_QM1_CQ_CTL_STS_1 & 0x7F) >> 2); 5718 mask |= 1U << ((mmNIC0_QM1_CQ_CTL_STS_2 & 0x7F) >> 2); 5719 mask |= 1U << ((mmNIC0_QM1_CQ_CTL_STS_3 & 0x7F) >> 2); 5720 mask |= 1U << ((mmNIC0_QM1_CQ_CTL_STS_4 & 0x7F) >> 2); 5721 mask |= 1U << ((mmNIC0_QM1_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 5722 mask |= 1U << ((mmNIC0_QM1_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 5723 mask |= 1U << ((mmNIC0_QM1_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 5724 mask |= 1U << ((mmNIC0_QM1_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 5725 mask |= 1U << ((mmNIC0_QM1_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 5726 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 5727 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 5728 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 5729 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 5730 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 5731 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 5732 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 5733 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 5734 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 5735 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 5736 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 5737 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 5738 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 5739 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 5740 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 5741 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 5742 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 5743 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 5744 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 5745 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 5746 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 5747 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 5748 5749 WREG32(pb_addr + word_offset, ~mask); 5750 5751 pb_addr = (mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 5752 word_offset = ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_2 & 5753 PROT_BITS_OFFS) >> 7) << 2; 5754 mask = 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 5755 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 5756 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 5757 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 5758 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 5759 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 5760 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 5761 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 5762 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 5763 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 5764 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 5765 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 5766 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 5767 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 5768 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 5769 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 5770 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 5771 mask |= 1U << ((mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 5772 mask |= 1U << ((mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 5773 mask |= 1U << ((mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 5774 mask |= 1U << ((mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 5775 mask |= 1U << ((mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 5776 mask |= 1U << ((mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 5777 mask |= 1U << ((mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 5778 mask |= 1U << ((mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 5779 mask |= 1U << ((mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 5780 mask |= 1U << ((mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 5781 mask |= 1U << ((mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 5782 mask |= 1U << ((mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 5783 mask |= 1U << ((mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 5784 mask |= 1U << ((mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 5785 5786 WREG32(pb_addr + word_offset, ~mask); 5787 5788 pb_addr = (mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 5789 PROT_BITS_OFFS; 5790 word_offset = ((mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & 5791 PROT_BITS_OFFS) >> 7) << 2; 5792 mask = 1U << ((mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 5793 mask |= 1U << ((mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 5794 5795 WREG32(pb_addr + word_offset, ~mask); 5796 5797 pb_addr = (mmNIC0_QM1_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 5798 word_offset = ((mmNIC0_QM1_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 5799 mask = 1U << ((mmNIC0_QM1_CP_STS_0 & 0x7F) >> 2); 5800 mask |= 1U << ((mmNIC0_QM1_CP_STS_1 & 0x7F) >> 2); 5801 mask |= 1U << ((mmNIC0_QM1_CP_STS_2 & 0x7F) >> 2); 5802 mask |= 1U << ((mmNIC0_QM1_CP_STS_3 & 0x7F) >> 2); 5803 mask |= 1U << ((mmNIC0_QM1_CP_STS_4 & 0x7F) >> 2); 5804 mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 5805 mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 5806 mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 5807 mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 5808 mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 5809 mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 5810 mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 5811 mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 5812 mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 5813 mask |= 1U << ((mmNIC0_QM1_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 5814 mask |= 1U << ((mmNIC0_QM1_CP_BARRIER_CFG_0 & 0x7F) >> 2); 5815 mask |= 1U << ((mmNIC0_QM1_CP_BARRIER_CFG_1 & 0x7F) >> 2); 5816 mask |= 1U << ((mmNIC0_QM1_CP_BARRIER_CFG_2 & 0x7F) >> 2); 5817 5818 WREG32(pb_addr + word_offset, ~mask); 5819 5820 pb_addr = (mmNIC0_QM1_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 5821 word_offset = ((mmNIC0_QM1_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) 5822 >> 7) << 2; 5823 mask = 1U << ((mmNIC0_QM1_CP_BARRIER_CFG_3 & 0x7F) >> 2); 5824 mask |= 1U << ((mmNIC0_QM1_CP_BARRIER_CFG_4 & 0x7F) >> 2); 5825 mask |= 1U << ((mmNIC0_QM1_CP_DBG_0_0 & 0x7F) >> 2); 5826 mask |= 1U << ((mmNIC0_QM1_CP_DBG_0_1 & 0x7F) >> 2); 5827 5828 WREG32(pb_addr + word_offset, ~mask); 5829 5830 pb_addr = (mmNIC0_QM1_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 5831 word_offset = ((mmNIC0_QM1_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 5832 mask = 1U << ((mmNIC0_QM1_CP_DBG_0_2 & 0x7F) >> 2); 5833 mask |= 1U << ((mmNIC0_QM1_CP_DBG_0_3 & 0x7F) >> 2); 5834 mask |= 1U << ((mmNIC0_QM1_CP_DBG_0_4 & 0x7F) >> 2); 5835 mask |= 1U << ((mmNIC0_QM1_CP_ARUSER_31_11_0 & 0x7F) >> 2); 5836 mask |= 1U << ((mmNIC0_QM1_CP_ARUSER_31_11_1 & 0x7F) >> 2); 5837 mask |= 1U << ((mmNIC0_QM1_CP_ARUSER_31_11_2 & 0x7F) >> 2); 5838 mask |= 1U << ((mmNIC0_QM1_CP_ARUSER_31_11_3 & 0x7F) >> 2); 5839 mask |= 1U << ((mmNIC0_QM1_CP_ARUSER_31_11_4 & 0x7F) >> 2); 5840 mask |= 1U << ((mmNIC0_QM1_CP_AWUSER_31_11_0 & 0x7F) >> 2); 5841 mask |= 1U << ((mmNIC0_QM1_CP_AWUSER_31_11_1 & 0x7F) >> 2); 5842 mask |= 1U << ((mmNIC0_QM1_CP_AWUSER_31_11_2 & 0x7F) >> 2); 5843 mask |= 1U << ((mmNIC0_QM1_CP_AWUSER_31_11_3 & 0x7F) >> 2); 5844 mask |= 1U << ((mmNIC0_QM1_CP_AWUSER_31_11_4 & 0x7F) >> 2); 5845 5846 WREG32(pb_addr + word_offset, ~mask); 5847 5848 pb_addr = (mmNIC0_QM1_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 5849 word_offset = ((mmNIC0_QM1_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 5850 mask = 1U << ((mmNIC0_QM1_ARB_CFG_1 & 0x7F) >> 2); 5851 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 5852 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 5853 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 5854 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 5855 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 5856 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 5857 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 5858 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 5859 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 5860 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 5861 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 5862 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 5863 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 5864 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 5865 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 5866 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 5867 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 5868 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 5869 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 5870 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 5871 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 5872 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 5873 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 5874 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 5875 5876 WREG32(pb_addr + word_offset, ~mask); 5877 5878 pb_addr = (mmNIC0_QM1_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 5879 word_offset = ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_24 & 5880 PROT_BITS_OFFS) >> 7) << 2; 5881 mask = 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 5882 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 5883 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 5884 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 5885 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 5886 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 5887 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 5888 mask |= 1U << ((mmNIC0_QM1_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 5889 5890 WREG32(pb_addr + word_offset, ~mask); 5891 5892 pb_addr = (mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 5893 PROT_BITS_OFFS; 5894 word_offset = ((mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_23 & 5895 PROT_BITS_OFFS) >> 7) << 2; 5896 mask = 1U << ((mmNIC0_QM1_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 5897 mask |= 1U << ((mmNIC0_QM1_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 5898 mask |= 1U << ((mmNIC0_QM1_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 5899 mask |= 1U << ((mmNIC0_QM1_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 5900 mask |= 1U << ((mmNIC0_QM1_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 5901 5902 WREG32(pb_addr + word_offset, ~mask); 5903 5904 pb_addr = (mmNIC0_QM1_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 5905 word_offset = ((mmNIC0_QM1_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 5906 mask = 1U << ((mmNIC0_QM1_ARB_STATE_STS & 0x7F) >> 2); 5907 mask |= 1U << ((mmNIC0_QM1_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 5908 mask |= 1U << ((mmNIC0_QM1_ARB_MSG_STS & 0x7F) >> 2); 5909 mask |= 1U << ((mmNIC0_QM1_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 5910 mask |= 1U << ((mmNIC0_QM1_ARB_ERR_CAUSE & 0x7F) >> 2); 5911 mask |= 1U << ((mmNIC0_QM1_ARB_ERR_MSG_EN & 0x7F) >> 2); 5912 mask |= 1U << ((mmNIC0_QM1_ARB_ERR_STS_DRP & 0x7F) >> 2); 5913 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 5914 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 5915 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 5916 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 5917 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 5918 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 5919 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 5920 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 5921 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 5922 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 5923 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 5924 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 5925 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 5926 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 5927 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 5928 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 5929 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 5930 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 5931 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 5932 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 5933 5934 WREG32(pb_addr + word_offset, ~mask); 5935 5936 pb_addr = (mmNIC0_QM1_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 5937 word_offset = ((mmNIC0_QM1_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) 5938 >> 7) << 2; 5939 mask = 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 5940 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 5941 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 5942 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 5943 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 5944 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 5945 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 5946 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 5947 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 5948 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 5949 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 5950 mask |= 1U << ((mmNIC0_QM1_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 5951 mask |= 1U << ((mmNIC0_QM1_CGM_CFG & 0x7F) >> 2); 5952 mask |= 1U << ((mmNIC0_QM1_CGM_STS & 0x7F) >> 2); 5953 mask |= 1U << ((mmNIC0_QM1_CGM_CFG1 & 0x7F) >> 2); 5954 5955 WREG32(pb_addr + word_offset, ~mask); 5956 5957 pb_addr = (mmNIC0_QM1_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 5958 word_offset = ((mmNIC0_QM1_LOCAL_RANGE_BASE & PROT_BITS_OFFS) 5959 >> 7) << 2; 5960 mask = 1U << ((mmNIC0_QM1_LOCAL_RANGE_BASE & 0x7F) >> 2); 5961 mask |= 1U << ((mmNIC0_QM1_LOCAL_RANGE_SIZE & 0x7F) >> 2); 5962 mask |= 1U << ((mmNIC0_QM1_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 5963 mask |= 1U << ((mmNIC0_QM1_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 5964 mask |= 1U << ((mmNIC0_QM1_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 5965 mask |= 1U << ((mmNIC0_QM1_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 5966 mask |= 1U << ((mmNIC0_QM1_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 5967 mask |= 1U << ((mmNIC0_QM1_GLBL_AXCACHE & 0x7F) >> 2); 5968 mask |= 1U << ((mmNIC0_QM1_IND_GW_APB_CFG & 0x7F) >> 2); 5969 mask |= 1U << ((mmNIC0_QM1_IND_GW_APB_WDATA & 0x7F) >> 2); 5970 mask |= 1U << ((mmNIC0_QM1_IND_GW_APB_RDATA & 0x7F) >> 2); 5971 mask |= 1U << ((mmNIC0_QM1_IND_GW_APB_STATUS & 0x7F) >> 2); 5972 mask |= 1U << ((mmNIC0_QM1_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 5973 mask |= 1U << ((mmNIC0_QM1_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 5974 mask |= 1U << ((mmNIC0_QM1_GLBL_ERR_WDATA & 0x7F) >> 2); 5975 5976 WREG32(pb_addr + word_offset, ~mask); 5977 5978 pb_addr = (mmNIC0_QM1_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 5979 word_offset = ((mmNIC0_QM1_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) 5980 >> 7) << 2; 5981 mask = 1U << ((mmNIC0_QM1_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 5982 5983 WREG32(pb_addr + word_offset, ~mask); 5984 5985 WREG32(mmNIC1_QM0_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 5986 WREG32(mmNIC1_QM1_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 5987 5988 pb_addr = (mmNIC1_QM0_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 5989 word_offset = ((mmNIC1_QM0_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 5990 mask = 1U << ((mmNIC1_QM0_GLBL_CFG0 & 0x7F) >> 2); 5991 mask |= 1U << ((mmNIC1_QM0_GLBL_CFG1 & 0x7F) >> 2); 5992 mask |= 1U << ((mmNIC1_QM0_GLBL_PROT & 0x7F) >> 2); 5993 mask |= 1U << ((mmNIC1_QM0_GLBL_ERR_CFG & 0x7F) >> 2); 5994 mask |= 1U << ((mmNIC1_QM0_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 5995 mask |= 1U << ((mmNIC1_QM0_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 5996 mask |= 1U << ((mmNIC1_QM0_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 5997 mask |= 1U << ((mmNIC1_QM0_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 5998 mask |= 1U << ((mmNIC1_QM0_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 5999 mask |= 1U << ((mmNIC1_QM0_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 6000 mask |= 1U << ((mmNIC1_QM0_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 6001 mask |= 1U << ((mmNIC1_QM0_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 6002 mask |= 1U << ((mmNIC1_QM0_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 6003 mask |= 1U << ((mmNIC1_QM0_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 6004 mask |= 1U << ((mmNIC1_QM0_GLBL_STS0 & 0x7F) >> 2); 6005 mask |= 1U << ((mmNIC1_QM0_GLBL_STS1_0 & 0x7F) >> 2); 6006 mask |= 1U << ((mmNIC1_QM0_GLBL_STS1_1 & 0x7F) >> 2); 6007 mask |= 1U << ((mmNIC1_QM0_GLBL_STS1_2 & 0x7F) >> 2); 6008 mask |= 1U << ((mmNIC1_QM0_GLBL_STS1_3 & 0x7F) >> 2); 6009 mask |= 1U << ((mmNIC1_QM0_GLBL_STS1_4 & 0x7F) >> 2); 6010 mask |= 1U << ((mmNIC1_QM0_GLBL_MSG_EN_0 & 0x7F) >> 2); 6011 mask |= 1U << ((mmNIC1_QM0_GLBL_MSG_EN_1 & 0x7F) >> 2); 6012 mask |= 1U << ((mmNIC1_QM0_GLBL_MSG_EN_2 & 0x7F) >> 2); 6013 mask |= 1U << ((mmNIC1_QM0_GLBL_MSG_EN_3 & 0x7F) >> 2); 6014 mask |= 1U << ((mmNIC1_QM0_GLBL_MSG_EN_4 & 0x7F) >> 2); 6015 mask |= 1U << ((mmNIC1_QM0_PQ_BASE_LO_0 & 0x7F) >> 2); 6016 mask |= 1U << ((mmNIC1_QM0_PQ_BASE_LO_1 & 0x7F) >> 2); 6017 mask |= 1U << ((mmNIC1_QM0_PQ_BASE_LO_2 & 0x7F) >> 2); 6018 mask |= 1U << ((mmNIC1_QM0_PQ_BASE_LO_3 & 0x7F) >> 2); 6019 6020 WREG32(pb_addr + word_offset, ~mask); 6021 6022 pb_addr = (mmNIC1_QM0_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 6023 word_offset = ((mmNIC1_QM0_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 6024 mask = 1U << ((mmNIC1_QM0_PQ_BASE_HI_0 & 0x7F) >> 2); 6025 mask |= 1U << ((mmNIC1_QM0_PQ_BASE_HI_1 & 0x7F) >> 2); 6026 mask |= 1U << ((mmNIC1_QM0_PQ_BASE_HI_2 & 0x7F) >> 2); 6027 mask |= 1U << ((mmNIC1_QM0_PQ_BASE_HI_3 & 0x7F) >> 2); 6028 mask |= 1U << ((mmNIC1_QM0_PQ_SIZE_0 & 0x7F) >> 2); 6029 mask |= 1U << ((mmNIC1_QM0_PQ_SIZE_1 & 0x7F) >> 2); 6030 mask |= 1U << ((mmNIC1_QM0_PQ_SIZE_2 & 0x7F) >> 2); 6031 mask |= 1U << ((mmNIC1_QM0_PQ_SIZE_3 & 0x7F) >> 2); 6032 mask |= 1U << ((mmNIC1_QM0_PQ_PI_0 & 0x7F) >> 2); 6033 mask |= 1U << ((mmNIC1_QM0_PQ_PI_1 & 0x7F) >> 2); 6034 mask |= 1U << ((mmNIC1_QM0_PQ_PI_2 & 0x7F) >> 2); 6035 mask |= 1U << ((mmNIC1_QM0_PQ_PI_3 & 0x7F) >> 2); 6036 mask |= 1U << ((mmNIC1_QM0_PQ_CI_0 & 0x7F) >> 2); 6037 mask |= 1U << ((mmNIC1_QM0_PQ_CI_1 & 0x7F) >> 2); 6038 mask |= 1U << ((mmNIC1_QM0_PQ_CI_2 & 0x7F) >> 2); 6039 mask |= 1U << ((mmNIC1_QM0_PQ_CI_3 & 0x7F) >> 2); 6040 mask |= 1U << ((mmNIC1_QM0_PQ_CFG0_0 & 0x7F) >> 2); 6041 mask |= 1U << ((mmNIC1_QM0_PQ_CFG0_1 & 0x7F) >> 2); 6042 mask |= 1U << ((mmNIC1_QM0_PQ_CFG0_2 & 0x7F) >> 2); 6043 mask |= 1U << ((mmNIC1_QM0_PQ_CFG0_3 & 0x7F) >> 2); 6044 mask |= 1U << ((mmNIC1_QM0_PQ_CFG1_0 & 0x7F) >> 2); 6045 mask |= 1U << ((mmNIC1_QM0_PQ_CFG1_1 & 0x7F) >> 2); 6046 mask |= 1U << ((mmNIC1_QM0_PQ_CFG1_2 & 0x7F) >> 2); 6047 mask |= 1U << ((mmNIC1_QM0_PQ_CFG1_3 & 0x7F) >> 2); 6048 mask |= 1U << ((mmNIC1_QM0_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 6049 mask |= 1U << ((mmNIC1_QM0_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 6050 mask |= 1U << ((mmNIC1_QM0_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 6051 mask |= 1U << ((mmNIC1_QM0_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 6052 mask |= 1U << ((mmNIC1_QM0_PQ_STS0_0 & 0x7F) >> 2); 6053 mask |= 1U << ((mmNIC1_QM0_PQ_STS0_1 & 0x7F) >> 2); 6054 mask |= 1U << ((mmNIC1_QM0_PQ_STS0_2 & 0x7F) >> 2); 6055 mask |= 1U << ((mmNIC1_QM0_PQ_STS0_3 & 0x7F) >> 2); 6056 6057 WREG32(pb_addr + word_offset, ~mask); 6058 6059 pb_addr = (mmNIC1_QM0_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 6060 word_offset = ((mmNIC1_QM0_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 6061 mask = 1U << ((mmNIC1_QM0_PQ_STS1_0 & 0x7F) >> 2); 6062 mask |= 1U << ((mmNIC1_QM0_PQ_STS1_1 & 0x7F) >> 2); 6063 mask |= 1U << ((mmNIC1_QM0_PQ_STS1_2 & 0x7F) >> 2); 6064 mask |= 1U << ((mmNIC1_QM0_PQ_STS1_3 & 0x7F) >> 2); 6065 mask |= 1U << ((mmNIC1_QM0_CQ_STS0_0 & 0x7F) >> 2); 6066 mask |= 1U << ((mmNIC1_QM0_CQ_STS0_1 & 0x7F) >> 2); 6067 mask |= 1U << ((mmNIC1_QM0_CQ_STS0_2 & 0x7F) >> 2); 6068 mask |= 1U << ((mmNIC1_QM0_CQ_STS0_3 & 0x7F) >> 2); 6069 mask |= 1U << ((mmNIC1_QM0_CQ_STS1_0 & 0x7F) >> 2); 6070 mask |= 1U << ((mmNIC1_QM0_CQ_STS1_1 & 0x7F) >> 2); 6071 mask |= 1U << ((mmNIC1_QM0_CQ_STS1_2 & 0x7F) >> 2); 6072 mask |= 1U << ((mmNIC1_QM0_CQ_STS1_3 & 0x7F) >> 2); 6073 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_0 & 0x7F) >> 2); 6074 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_0 & 0x7F) >> 2); 6075 mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_0 & 0x7F) >> 2); 6076 6077 WREG32(pb_addr + word_offset, ~mask); 6078 6079 pb_addr = (mmNIC1_QM0_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 6080 word_offset = ((mmNIC1_QM0_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 6081 mask = 1U << ((mmNIC1_QM0_CQ_CTL_0 & 0x7F) >> 2); 6082 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_1 & 0x7F) >> 2); 6083 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_1 & 0x7F) >> 2); 6084 mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_1 & 0x7F) >> 2); 6085 mask |= 1U << ((mmNIC1_QM0_CQ_CTL_1 & 0x7F) >> 2); 6086 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_2 & 0x7F) >> 2); 6087 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_2 & 0x7F) >> 2); 6088 mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_2 & 0x7F) >> 2); 6089 mask |= 1U << ((mmNIC1_QM0_CQ_CTL_2 & 0x7F) >> 2); 6090 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_3 & 0x7F) >> 2); 6091 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_3 & 0x7F) >> 2); 6092 mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_3 & 0x7F) >> 2); 6093 mask |= 1U << ((mmNIC1_QM0_CQ_CTL_3 & 0x7F) >> 2); 6094 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 6095 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 6096 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 6097 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 6098 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 6099 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 6100 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 6101 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 6102 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 6103 mask |= 1U << ((mmNIC1_QM0_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 6104 mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_STS_0 & 0x7F) >> 2); 6105 mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_STS_1 & 0x7F) >> 2); 6106 mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_STS_2 & 0x7F) >> 2); 6107 mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_STS_3 & 0x7F) >> 2); 6108 mask |= 1U << ((mmNIC1_QM0_CQ_TSIZE_STS_4 & 0x7F) >> 2); 6109 6110 WREG32(pb_addr + word_offset, ~mask); 6111 6112 pb_addr = (mmNIC1_QM0_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 6113 word_offset = ((mmNIC1_QM0_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 6114 mask = 1U << ((mmNIC1_QM0_CQ_CTL_STS_0 & 0x7F) >> 2); 6115 mask |= 1U << ((mmNIC1_QM0_CQ_CTL_STS_1 & 0x7F) >> 2); 6116 mask |= 1U << ((mmNIC1_QM0_CQ_CTL_STS_2 & 0x7F) >> 2); 6117 mask |= 1U << ((mmNIC1_QM0_CQ_CTL_STS_3 & 0x7F) >> 2); 6118 mask |= 1U << ((mmNIC1_QM0_CQ_CTL_STS_4 & 0x7F) >> 2); 6119 mask |= 1U << ((mmNIC1_QM0_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 6120 mask |= 1U << ((mmNIC1_QM0_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 6121 mask |= 1U << ((mmNIC1_QM0_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 6122 mask |= 1U << ((mmNIC1_QM0_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 6123 mask |= 1U << ((mmNIC1_QM0_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 6124 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 6125 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 6126 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 6127 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 6128 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 6129 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 6130 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 6131 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 6132 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 6133 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 6134 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 6135 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 6136 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 6137 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 6138 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 6139 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 6140 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 6141 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 6142 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 6143 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 6144 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 6145 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 6146 6147 WREG32(pb_addr + word_offset, ~mask); 6148 6149 pb_addr = (mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 6150 word_offset = ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_2 & 6151 PROT_BITS_OFFS) >> 7) << 2; 6152 mask = 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 6153 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 6154 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 6155 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 6156 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 6157 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 6158 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 6159 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 6160 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 6161 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 6162 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 6163 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 6164 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 6165 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 6166 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 6167 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 6168 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 6169 mask |= 1U << ((mmNIC1_QM0_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 6170 mask |= 1U << ((mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 6171 mask |= 1U << ((mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 6172 mask |= 1U << ((mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 6173 mask |= 1U << ((mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 6174 mask |= 1U << ((mmNIC1_QM0_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 6175 mask |= 1U << ((mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 6176 mask |= 1U << ((mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 6177 mask |= 1U << ((mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 6178 mask |= 1U << ((mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 6179 mask |= 1U << ((mmNIC1_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 6180 mask |= 1U << ((mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 6181 mask |= 1U << ((mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 6182 mask |= 1U << ((mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 6183 6184 WREG32(pb_addr + word_offset, ~mask); 6185 6186 pb_addr = (mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 6187 PROT_BITS_OFFS; 6188 word_offset = ((mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & 6189 PROT_BITS_OFFS) >> 7) << 2; 6190 mask = 1U << ((mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 6191 mask |= 1U << ((mmNIC1_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 6192 6193 WREG32(pb_addr + word_offset, ~mask); 6194 6195 pb_addr = (mmNIC1_QM0_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 6196 word_offset = ((mmNIC1_QM0_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 6197 mask = 1U << ((mmNIC1_QM0_CP_STS_0 & 0x7F) >> 2); 6198 mask |= 1U << ((mmNIC1_QM0_CP_STS_1 & 0x7F) >> 2); 6199 mask |= 1U << ((mmNIC1_QM0_CP_STS_2 & 0x7F) >> 2); 6200 mask |= 1U << ((mmNIC1_QM0_CP_STS_3 & 0x7F) >> 2); 6201 mask |= 1U << ((mmNIC1_QM0_CP_STS_4 & 0x7F) >> 2); 6202 mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 6203 mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 6204 mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 6205 mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 6206 mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 6207 mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 6208 mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 6209 mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 6210 mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 6211 mask |= 1U << ((mmNIC1_QM0_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 6212 mask |= 1U << ((mmNIC1_QM0_CP_BARRIER_CFG_0 & 0x7F) >> 2); 6213 mask |= 1U << ((mmNIC1_QM0_CP_BARRIER_CFG_1 & 0x7F) >> 2); 6214 mask |= 1U << ((mmNIC1_QM0_CP_BARRIER_CFG_2 & 0x7F) >> 2); 6215 6216 WREG32(pb_addr + word_offset, ~mask); 6217 6218 pb_addr = (mmNIC1_QM0_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 6219 word_offset = ((mmNIC1_QM0_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) 6220 >> 7) << 2; 6221 mask = 1U << ((mmNIC1_QM0_CP_BARRIER_CFG_3 & 0x7F) >> 2); 6222 mask |= 1U << ((mmNIC1_QM0_CP_BARRIER_CFG_4 & 0x7F) >> 2); 6223 mask |= 1U << ((mmNIC1_QM0_CP_DBG_0_0 & 0x7F) >> 2); 6224 mask |= 1U << ((mmNIC1_QM0_CP_DBG_0_1 & 0x7F) >> 2); 6225 6226 WREG32(pb_addr + word_offset, ~mask); 6227 6228 pb_addr = (mmNIC1_QM0_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 6229 word_offset = ((mmNIC1_QM0_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 6230 mask = 1U << ((mmNIC1_QM0_CP_DBG_0_2 & 0x7F) >> 2); 6231 mask |= 1U << ((mmNIC1_QM0_CP_DBG_0_3 & 0x7F) >> 2); 6232 mask |= 1U << ((mmNIC1_QM0_CP_DBG_0_4 & 0x7F) >> 2); 6233 mask |= 1U << ((mmNIC1_QM0_CP_ARUSER_31_11_0 & 0x7F) >> 2); 6234 mask |= 1U << ((mmNIC1_QM0_CP_ARUSER_31_11_1 & 0x7F) >> 2); 6235 mask |= 1U << ((mmNIC1_QM0_CP_ARUSER_31_11_2 & 0x7F) >> 2); 6236 mask |= 1U << ((mmNIC1_QM0_CP_ARUSER_31_11_3 & 0x7F) >> 2); 6237 mask |= 1U << ((mmNIC1_QM0_CP_ARUSER_31_11_4 & 0x7F) >> 2); 6238 mask |= 1U << ((mmNIC1_QM0_CP_AWUSER_31_11_0 & 0x7F) >> 2); 6239 mask |= 1U << ((mmNIC1_QM0_CP_AWUSER_31_11_1 & 0x7F) >> 2); 6240 mask |= 1U << ((mmNIC1_QM0_CP_AWUSER_31_11_2 & 0x7F) >> 2); 6241 mask |= 1U << ((mmNIC1_QM0_CP_AWUSER_31_11_3 & 0x7F) >> 2); 6242 mask |= 1U << ((mmNIC1_QM0_CP_AWUSER_31_11_4 & 0x7F) >> 2); 6243 6244 WREG32(pb_addr + word_offset, ~mask); 6245 6246 pb_addr = (mmNIC1_QM0_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 6247 word_offset = ((mmNIC1_QM0_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 6248 mask = 1U << ((mmNIC1_QM0_ARB_CFG_1 & 0x7F) >> 2); 6249 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 6250 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 6251 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 6252 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 6253 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 6254 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 6255 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 6256 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 6257 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 6258 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 6259 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 6260 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 6261 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 6262 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 6263 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 6264 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 6265 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 6266 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 6267 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 6268 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 6269 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 6270 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 6271 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 6272 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 6273 6274 WREG32(pb_addr + word_offset, ~mask); 6275 6276 pb_addr = (mmNIC1_QM0_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 6277 word_offset = ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_24 & 6278 PROT_BITS_OFFS) >> 7) << 2; 6279 mask = 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 6280 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 6281 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 6282 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 6283 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 6284 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 6285 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 6286 mask |= 1U << ((mmNIC1_QM0_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 6287 6288 WREG32(pb_addr + word_offset, ~mask); 6289 6290 pb_addr = (mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 6291 PROT_BITS_OFFS; 6292 word_offset = ((mmNIC1_QM0_ARB_MST_CHOISE_PUSH_OFST_23 & 6293 PROT_BITS_OFFS) >> 7) << 2; 6294 mask = 1U << ((mmNIC1_QM0_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 6295 mask |= 1U << ((mmNIC1_QM0_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 6296 mask |= 1U << ((mmNIC1_QM0_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 6297 mask |= 1U << ((mmNIC1_QM0_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 6298 mask |= 1U << ((mmNIC1_QM0_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 6299 WREG32(pb_addr + word_offset, ~mask); 6300 6301 pb_addr = (mmNIC1_QM0_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 6302 word_offset = ((mmNIC1_QM0_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 6303 mask = 1U << ((mmNIC1_QM0_ARB_STATE_STS & 0x7F) >> 2); 6304 mask |= 1U << ((mmNIC1_QM0_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 6305 mask |= 1U << ((mmNIC1_QM0_ARB_MSG_STS & 0x7F) >> 2); 6306 mask |= 1U << ((mmNIC1_QM0_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 6307 mask |= 1U << ((mmNIC1_QM0_ARB_ERR_CAUSE & 0x7F) >> 2); 6308 mask |= 1U << ((mmNIC1_QM0_ARB_ERR_MSG_EN & 0x7F) >> 2); 6309 mask |= 1U << ((mmNIC1_QM0_ARB_ERR_STS_DRP & 0x7F) >> 2); 6310 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 6311 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 6312 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 6313 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 6314 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 6315 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 6316 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 6317 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 6318 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 6319 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 6320 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 6321 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 6322 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 6323 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 6324 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 6325 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 6326 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 6327 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 6328 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 6329 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 6330 6331 WREG32(pb_addr + word_offset, ~mask); 6332 6333 pb_addr = (mmNIC1_QM0_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 6334 word_offset = ((mmNIC1_QM0_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) 6335 >> 7) << 2; 6336 mask = 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 6337 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 6338 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 6339 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 6340 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 6341 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 6342 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 6343 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 6344 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 6345 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 6346 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 6347 mask |= 1U << ((mmNIC1_QM0_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 6348 mask |= 1U << ((mmNIC1_QM0_CGM_CFG & 0x7F) >> 2); 6349 mask |= 1U << ((mmNIC1_QM0_CGM_STS & 0x7F) >> 2); 6350 mask |= 1U << ((mmNIC1_QM0_CGM_CFG1 & 0x7F) >> 2); 6351 6352 WREG32(pb_addr + word_offset, ~mask); 6353 6354 pb_addr = (mmNIC1_QM0_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 6355 word_offset = ((mmNIC1_QM0_LOCAL_RANGE_BASE & PROT_BITS_OFFS) 6356 >> 7) << 2; 6357 mask = 1U << ((mmNIC1_QM0_LOCAL_RANGE_BASE & 0x7F) >> 2); 6358 mask |= 1U << ((mmNIC1_QM0_LOCAL_RANGE_SIZE & 0x7F) >> 2); 6359 mask |= 1U << ((mmNIC1_QM0_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 6360 mask |= 1U << ((mmNIC1_QM0_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 6361 mask |= 1U << ((mmNIC1_QM0_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 6362 mask |= 1U << ((mmNIC1_QM0_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 6363 mask |= 1U << ((mmNIC1_QM0_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 6364 mask |= 1U << ((mmNIC1_QM0_GLBL_AXCACHE & 0x7F) >> 2); 6365 mask |= 1U << ((mmNIC1_QM0_IND_GW_APB_CFG & 0x7F) >> 2); 6366 mask |= 1U << ((mmNIC1_QM0_IND_GW_APB_WDATA & 0x7F) >> 2); 6367 mask |= 1U << ((mmNIC1_QM0_IND_GW_APB_RDATA & 0x7F) >> 2); 6368 mask |= 1U << ((mmNIC1_QM0_IND_GW_APB_STATUS & 0x7F) >> 2); 6369 mask |= 1U << ((mmNIC1_QM0_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 6370 mask |= 1U << ((mmNIC1_QM0_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 6371 mask |= 1U << ((mmNIC1_QM0_GLBL_ERR_WDATA & 0x7F) >> 2); 6372 6373 WREG32(pb_addr + word_offset, ~mask); 6374 6375 pb_addr = (mmNIC1_QM0_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 6376 word_offset = ((mmNIC1_QM0_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) 6377 >> 7) << 2; 6378 mask = 1U << ((mmNIC1_QM0_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 6379 6380 WREG32(pb_addr + word_offset, ~mask); 6381 6382 pb_addr = (mmNIC1_QM1_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 6383 word_offset = ((mmNIC1_QM1_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 6384 mask = 1U << ((mmNIC1_QM1_GLBL_CFG0 & 0x7F) >> 2); 6385 mask |= 1U << ((mmNIC1_QM1_GLBL_CFG1 & 0x7F) >> 2); 6386 mask |= 1U << ((mmNIC1_QM1_GLBL_PROT & 0x7F) >> 2); 6387 mask |= 1U << ((mmNIC1_QM1_GLBL_ERR_CFG & 0x7F) >> 2); 6388 mask |= 1U << ((mmNIC1_QM1_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 6389 mask |= 1U << ((mmNIC1_QM1_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 6390 mask |= 1U << ((mmNIC1_QM1_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 6391 mask |= 1U << ((mmNIC1_QM1_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 6392 mask |= 1U << ((mmNIC1_QM1_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 6393 mask |= 1U << ((mmNIC1_QM1_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 6394 mask |= 1U << ((mmNIC1_QM1_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 6395 mask |= 1U << ((mmNIC1_QM1_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 6396 mask |= 1U << ((mmNIC1_QM1_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 6397 mask |= 1U << ((mmNIC1_QM1_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 6398 mask |= 1U << ((mmNIC1_QM1_GLBL_STS0 & 0x7F) >> 2); 6399 mask |= 1U << ((mmNIC1_QM1_GLBL_STS1_0 & 0x7F) >> 2); 6400 mask |= 1U << ((mmNIC1_QM1_GLBL_STS1_1 & 0x7F) >> 2); 6401 mask |= 1U << ((mmNIC1_QM1_GLBL_STS1_2 & 0x7F) >> 2); 6402 mask |= 1U << ((mmNIC1_QM1_GLBL_STS1_3 & 0x7F) >> 2); 6403 mask |= 1U << ((mmNIC1_QM1_GLBL_STS1_4 & 0x7F) >> 2); 6404 mask |= 1U << ((mmNIC1_QM1_GLBL_MSG_EN_0 & 0x7F) >> 2); 6405 mask |= 1U << ((mmNIC1_QM1_GLBL_MSG_EN_1 & 0x7F) >> 2); 6406 mask |= 1U << ((mmNIC1_QM1_GLBL_MSG_EN_2 & 0x7F) >> 2); 6407 mask |= 1U << ((mmNIC1_QM1_GLBL_MSG_EN_3 & 0x7F) >> 2); 6408 mask |= 1U << ((mmNIC1_QM1_GLBL_MSG_EN_4 & 0x7F) >> 2); 6409 mask |= 1U << ((mmNIC1_QM1_PQ_BASE_LO_0 & 0x7F) >> 2); 6410 mask |= 1U << ((mmNIC1_QM1_PQ_BASE_LO_1 & 0x7F) >> 2); 6411 mask |= 1U << ((mmNIC1_QM1_PQ_BASE_LO_2 & 0x7F) >> 2); 6412 mask |= 1U << ((mmNIC1_QM1_PQ_BASE_LO_3 & 0x7F) >> 2); 6413 6414 WREG32(pb_addr + word_offset, ~mask); 6415 6416 pb_addr = (mmNIC1_QM1_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 6417 word_offset = ((mmNIC1_QM1_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 6418 mask = 1U << ((mmNIC1_QM1_PQ_BASE_HI_0 & 0x7F) >> 2); 6419 mask |= 1U << ((mmNIC1_QM1_PQ_BASE_HI_1 & 0x7F) >> 2); 6420 mask |= 1U << ((mmNIC1_QM1_PQ_BASE_HI_2 & 0x7F) >> 2); 6421 mask |= 1U << ((mmNIC1_QM1_PQ_BASE_HI_3 & 0x7F) >> 2); 6422 mask |= 1U << ((mmNIC1_QM1_PQ_SIZE_0 & 0x7F) >> 2); 6423 mask |= 1U << ((mmNIC1_QM1_PQ_SIZE_1 & 0x7F) >> 2); 6424 mask |= 1U << ((mmNIC1_QM1_PQ_SIZE_2 & 0x7F) >> 2); 6425 mask |= 1U << ((mmNIC1_QM1_PQ_SIZE_3 & 0x7F) >> 2); 6426 mask |= 1U << ((mmNIC1_QM1_PQ_PI_0 & 0x7F) >> 2); 6427 mask |= 1U << ((mmNIC1_QM1_PQ_PI_1 & 0x7F) >> 2); 6428 mask |= 1U << ((mmNIC1_QM1_PQ_PI_2 & 0x7F) >> 2); 6429 mask |= 1U << ((mmNIC1_QM1_PQ_PI_3 & 0x7F) >> 2); 6430 mask |= 1U << ((mmNIC1_QM1_PQ_CI_0 & 0x7F) >> 2); 6431 mask |= 1U << ((mmNIC1_QM1_PQ_CI_1 & 0x7F) >> 2); 6432 mask |= 1U << ((mmNIC1_QM1_PQ_CI_2 & 0x7F) >> 2); 6433 mask |= 1U << ((mmNIC1_QM1_PQ_CI_3 & 0x7F) >> 2); 6434 mask |= 1U << ((mmNIC1_QM1_PQ_CFG0_0 & 0x7F) >> 2); 6435 mask |= 1U << ((mmNIC1_QM1_PQ_CFG0_1 & 0x7F) >> 2); 6436 mask |= 1U << ((mmNIC1_QM1_PQ_CFG0_2 & 0x7F) >> 2); 6437 mask |= 1U << ((mmNIC1_QM1_PQ_CFG0_3 & 0x7F) >> 2); 6438 mask |= 1U << ((mmNIC1_QM1_PQ_CFG1_0 & 0x7F) >> 2); 6439 mask |= 1U << ((mmNIC1_QM1_PQ_CFG1_1 & 0x7F) >> 2); 6440 mask |= 1U << ((mmNIC1_QM1_PQ_CFG1_2 & 0x7F) >> 2); 6441 mask |= 1U << ((mmNIC1_QM1_PQ_CFG1_3 & 0x7F) >> 2); 6442 mask |= 1U << ((mmNIC1_QM1_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 6443 mask |= 1U << ((mmNIC1_QM1_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 6444 mask |= 1U << ((mmNIC1_QM1_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 6445 mask |= 1U << ((mmNIC1_QM1_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 6446 mask |= 1U << ((mmNIC1_QM1_PQ_STS0_0 & 0x7F) >> 2); 6447 mask |= 1U << ((mmNIC1_QM1_PQ_STS0_1 & 0x7F) >> 2); 6448 mask |= 1U << ((mmNIC1_QM1_PQ_STS0_2 & 0x7F) >> 2); 6449 mask |= 1U << ((mmNIC1_QM1_PQ_STS0_3 & 0x7F) >> 2); 6450 6451 WREG32(pb_addr + word_offset, ~mask); 6452 6453 pb_addr = (mmNIC1_QM1_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 6454 word_offset = ((mmNIC1_QM1_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 6455 mask = 1U << ((mmNIC1_QM1_PQ_STS1_0 & 0x7F) >> 2); 6456 mask |= 1U << ((mmNIC1_QM1_PQ_STS1_1 & 0x7F) >> 2); 6457 mask |= 1U << ((mmNIC1_QM1_PQ_STS1_2 & 0x7F) >> 2); 6458 mask |= 1U << ((mmNIC1_QM1_PQ_STS1_3 & 0x7F) >> 2); 6459 mask |= 1U << ((mmNIC1_QM1_CQ_STS0_0 & 0x7F) >> 2); 6460 mask |= 1U << ((mmNIC1_QM1_CQ_STS0_1 & 0x7F) >> 2); 6461 mask |= 1U << ((mmNIC1_QM1_CQ_STS0_2 & 0x7F) >> 2); 6462 mask |= 1U << ((mmNIC1_QM1_CQ_STS0_3 & 0x7F) >> 2); 6463 mask |= 1U << ((mmNIC1_QM1_CQ_STS1_0 & 0x7F) >> 2); 6464 mask |= 1U << ((mmNIC1_QM1_CQ_STS1_1 & 0x7F) >> 2); 6465 mask |= 1U << ((mmNIC1_QM1_CQ_STS1_2 & 0x7F) >> 2); 6466 mask |= 1U << ((mmNIC1_QM1_CQ_STS1_3 & 0x7F) >> 2); 6467 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_0 & 0x7F) >> 2); 6468 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_0 & 0x7F) >> 2); 6469 mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_0 & 0x7F) >> 2); 6470 6471 WREG32(pb_addr + word_offset, ~mask); 6472 6473 pb_addr = (mmNIC1_QM1_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 6474 word_offset = ((mmNIC1_QM1_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 6475 mask = 1U << ((mmNIC1_QM1_CQ_CTL_0 & 0x7F) >> 2); 6476 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_1 & 0x7F) >> 2); 6477 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_1 & 0x7F) >> 2); 6478 mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_1 & 0x7F) >> 2); 6479 mask |= 1U << ((mmNIC1_QM1_CQ_CTL_1 & 0x7F) >> 2); 6480 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_2 & 0x7F) >> 2); 6481 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_2 & 0x7F) >> 2); 6482 mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_2 & 0x7F) >> 2); 6483 mask |= 1U << ((mmNIC1_QM1_CQ_CTL_2 & 0x7F) >> 2); 6484 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_3 & 0x7F) >> 2); 6485 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_3 & 0x7F) >> 2); 6486 mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_3 & 0x7F) >> 2); 6487 mask |= 1U << ((mmNIC1_QM1_CQ_CTL_3 & 0x7F) >> 2); 6488 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 6489 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 6490 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 6491 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 6492 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 6493 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 6494 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 6495 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 6496 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 6497 mask |= 1U << ((mmNIC1_QM1_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 6498 mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_STS_0 & 0x7F) >> 2); 6499 mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_STS_1 & 0x7F) >> 2); 6500 mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_STS_2 & 0x7F) >> 2); 6501 mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_STS_3 & 0x7F) >> 2); 6502 mask |= 1U << ((mmNIC1_QM1_CQ_TSIZE_STS_4 & 0x7F) >> 2); 6503 6504 WREG32(pb_addr + word_offset, ~mask); 6505 6506 pb_addr = (mmNIC1_QM1_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 6507 word_offset = ((mmNIC1_QM1_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 6508 mask = 1U << ((mmNIC1_QM1_CQ_CTL_STS_0 & 0x7F) >> 2); 6509 mask |= 1U << ((mmNIC1_QM1_CQ_CTL_STS_1 & 0x7F) >> 2); 6510 mask |= 1U << ((mmNIC1_QM1_CQ_CTL_STS_2 & 0x7F) >> 2); 6511 mask |= 1U << ((mmNIC1_QM1_CQ_CTL_STS_3 & 0x7F) >> 2); 6512 mask |= 1U << ((mmNIC1_QM1_CQ_CTL_STS_4 & 0x7F) >> 2); 6513 mask |= 1U << ((mmNIC1_QM1_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 6514 mask |= 1U << ((mmNIC1_QM1_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 6515 mask |= 1U << ((mmNIC1_QM1_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 6516 mask |= 1U << ((mmNIC1_QM1_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 6517 mask |= 1U << ((mmNIC1_QM1_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 6518 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 6519 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 6520 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 6521 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 6522 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 6523 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 6524 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 6525 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 6526 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 6527 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 6528 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 6529 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 6530 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 6531 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 6532 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 6533 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 6534 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 6535 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 6536 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 6537 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 6538 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 6539 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 6540 6541 WREG32(pb_addr + word_offset, ~mask); 6542 6543 pb_addr = (mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 6544 word_offset = ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_2 & 6545 PROT_BITS_OFFS) >> 7) << 2; 6546 mask = 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 6547 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 6548 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 6549 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 6550 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 6551 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 6552 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 6553 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 6554 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 6555 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 6556 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 6557 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 6558 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 6559 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 6560 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 6561 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 6562 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 6563 mask |= 1U << ((mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 6564 mask |= 1U << ((mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 6565 mask |= 1U << ((mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 6566 mask |= 1U << ((mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 6567 mask |= 1U << ((mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 6568 mask |= 1U << ((mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 6569 mask |= 1U << ((mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 6570 mask |= 1U << ((mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 6571 mask |= 1U << ((mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 6572 mask |= 1U << ((mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 6573 mask |= 1U << ((mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 6574 mask |= 1U << ((mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 6575 mask |= 1U << ((mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 6576 mask |= 1U << ((mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 6577 6578 WREG32(pb_addr + word_offset, ~mask); 6579 6580 pb_addr = (mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 6581 PROT_BITS_OFFS; 6582 word_offset = ((mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & 6583 PROT_BITS_OFFS) >> 7) << 2; 6584 mask = 1U << ((mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 6585 mask |= 1U << ((mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 6586 6587 WREG32(pb_addr + word_offset, ~mask); 6588 6589 pb_addr = (mmNIC1_QM1_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 6590 word_offset = ((mmNIC1_QM1_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 6591 mask = 1U << ((mmNIC1_QM1_CP_STS_0 & 0x7F) >> 2); 6592 mask |= 1U << ((mmNIC1_QM1_CP_STS_1 & 0x7F) >> 2); 6593 mask |= 1U << ((mmNIC1_QM1_CP_STS_2 & 0x7F) >> 2); 6594 mask |= 1U << ((mmNIC1_QM1_CP_STS_3 & 0x7F) >> 2); 6595 mask |= 1U << ((mmNIC1_QM1_CP_STS_4 & 0x7F) >> 2); 6596 mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 6597 mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 6598 mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 6599 mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 6600 mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 6601 mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 6602 mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 6603 mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 6604 mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 6605 mask |= 1U << ((mmNIC1_QM1_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 6606 mask |= 1U << ((mmNIC1_QM1_CP_BARRIER_CFG_0 & 0x7F) >> 2); 6607 mask |= 1U << ((mmNIC1_QM1_CP_BARRIER_CFG_1 & 0x7F) >> 2); 6608 mask |= 1U << ((mmNIC1_QM1_CP_BARRIER_CFG_2 & 0x7F) >> 2); 6609 6610 WREG32(pb_addr + word_offset, ~mask); 6611 6612 pb_addr = (mmNIC1_QM1_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 6613 word_offset = ((mmNIC1_QM1_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) 6614 >> 7) << 2; 6615 mask = 1U << ((mmNIC1_QM1_CP_BARRIER_CFG_3 & 0x7F) >> 2); 6616 mask |= 1U << ((mmNIC1_QM1_CP_BARRIER_CFG_4 & 0x7F) >> 2); 6617 mask |= 1U << ((mmNIC1_QM1_CP_DBG_0_0 & 0x7F) >> 2); 6618 mask |= 1U << ((mmNIC1_QM1_CP_DBG_0_1 & 0x7F) >> 2); 6619 6620 WREG32(pb_addr + word_offset, ~mask); 6621 6622 pb_addr = (mmNIC1_QM1_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 6623 word_offset = ((mmNIC1_QM1_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 6624 mask = 1U << ((mmNIC1_QM1_CP_DBG_0_2 & 0x7F) >> 2); 6625 mask |= 1U << ((mmNIC1_QM1_CP_DBG_0_3 & 0x7F) >> 2); 6626 mask |= 1U << ((mmNIC1_QM1_CP_DBG_0_4 & 0x7F) >> 2); 6627 mask |= 1U << ((mmNIC1_QM1_CP_ARUSER_31_11_0 & 0x7F) >> 2); 6628 mask |= 1U << ((mmNIC1_QM1_CP_ARUSER_31_11_1 & 0x7F) >> 2); 6629 mask |= 1U << ((mmNIC1_QM1_CP_ARUSER_31_11_2 & 0x7F) >> 2); 6630 mask |= 1U << ((mmNIC1_QM1_CP_ARUSER_31_11_3 & 0x7F) >> 2); 6631 mask |= 1U << ((mmNIC1_QM1_CP_ARUSER_31_11_4 & 0x7F) >> 2); 6632 mask |= 1U << ((mmNIC1_QM1_CP_AWUSER_31_11_0 & 0x7F) >> 2); 6633 mask |= 1U << ((mmNIC1_QM1_CP_AWUSER_31_11_1 & 0x7F) >> 2); 6634 mask |= 1U << ((mmNIC1_QM1_CP_AWUSER_31_11_2 & 0x7F) >> 2); 6635 mask |= 1U << ((mmNIC1_QM1_CP_AWUSER_31_11_3 & 0x7F) >> 2); 6636 mask |= 1U << ((mmNIC1_QM1_CP_AWUSER_31_11_4 & 0x7F) >> 2); 6637 6638 WREG32(pb_addr + word_offset, ~mask); 6639 6640 pb_addr = (mmNIC1_QM1_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 6641 word_offset = ((mmNIC1_QM1_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 6642 mask = 1U << ((mmNIC1_QM1_ARB_CFG_1 & 0x7F) >> 2); 6643 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 6644 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 6645 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 6646 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 6647 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 6648 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 6649 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 6650 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 6651 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 6652 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 6653 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 6654 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 6655 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 6656 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 6657 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 6658 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 6659 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 6660 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 6661 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 6662 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 6663 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 6664 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 6665 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 6666 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 6667 6668 WREG32(pb_addr + word_offset, ~mask); 6669 6670 pb_addr = (mmNIC1_QM1_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 6671 word_offset = ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_24 & 6672 PROT_BITS_OFFS) >> 7) << 2; 6673 mask = 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 6674 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 6675 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 6676 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 6677 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 6678 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 6679 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 6680 mask |= 1U << ((mmNIC1_QM1_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 6681 6682 WREG32(pb_addr + word_offset, ~mask); 6683 6684 pb_addr = (mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 6685 PROT_BITS_OFFS; 6686 word_offset = ((mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_23 & 6687 PROT_BITS_OFFS) >> 7) << 2; 6688 mask = 1U << ((mmNIC1_QM1_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 6689 mask |= 1U << ((mmNIC1_QM1_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 6690 mask |= 1U << ((mmNIC1_QM1_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 6691 mask |= 1U << ((mmNIC1_QM1_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 6692 mask |= 1U << ((mmNIC1_QM1_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 6693 6694 WREG32(pb_addr + word_offset, ~mask); 6695 6696 pb_addr = (mmNIC1_QM1_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 6697 word_offset = ((mmNIC1_QM1_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 6698 mask = 1U << ((mmNIC1_QM1_ARB_STATE_STS & 0x7F) >> 2); 6699 mask |= 1U << ((mmNIC1_QM1_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 6700 mask |= 1U << ((mmNIC1_QM1_ARB_MSG_STS & 0x7F) >> 2); 6701 mask |= 1U << ((mmNIC1_QM1_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 6702 mask |= 1U << ((mmNIC1_QM1_ARB_ERR_CAUSE & 0x7F) >> 2); 6703 mask |= 1U << ((mmNIC1_QM1_ARB_ERR_MSG_EN & 0x7F) >> 2); 6704 mask |= 1U << ((mmNIC1_QM1_ARB_ERR_STS_DRP & 0x7F) >> 2); 6705 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 6706 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 6707 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 6708 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 6709 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 6710 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 6711 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 6712 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 6713 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 6714 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 6715 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 6716 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 6717 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 6718 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 6719 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 6720 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 6721 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 6722 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 6723 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 6724 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 6725 6726 WREG32(pb_addr + word_offset, ~mask); 6727 6728 pb_addr = (mmNIC1_QM1_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 6729 word_offset = ((mmNIC1_QM1_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) 6730 >> 7) << 2; 6731 mask = 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 6732 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 6733 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 6734 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 6735 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 6736 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 6737 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 6738 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 6739 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 6740 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 6741 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 6742 mask |= 1U << ((mmNIC1_QM1_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 6743 mask |= 1U << ((mmNIC1_QM1_CGM_CFG & 0x7F) >> 2); 6744 mask |= 1U << ((mmNIC1_QM1_CGM_STS & 0x7F) >> 2); 6745 mask |= 1U << ((mmNIC1_QM1_CGM_CFG1 & 0x7F) >> 2); 6746 6747 WREG32(pb_addr + word_offset, ~mask); 6748 6749 pb_addr = (mmNIC1_QM1_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 6750 word_offset = ((mmNIC1_QM1_LOCAL_RANGE_BASE & PROT_BITS_OFFS) 6751 >> 7) << 2; 6752 mask = 1U << ((mmNIC1_QM1_LOCAL_RANGE_BASE & 0x7F) >> 2); 6753 mask |= 1U << ((mmNIC1_QM1_LOCAL_RANGE_SIZE & 0x7F) >> 2); 6754 mask |= 1U << ((mmNIC1_QM1_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 6755 mask |= 1U << ((mmNIC1_QM1_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 6756 mask |= 1U << ((mmNIC1_QM1_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 6757 mask |= 1U << ((mmNIC1_QM1_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 6758 mask |= 1U << ((mmNIC1_QM1_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 6759 mask |= 1U << ((mmNIC1_QM1_GLBL_AXCACHE & 0x7F) >> 2); 6760 mask |= 1U << ((mmNIC1_QM1_IND_GW_APB_CFG & 0x7F) >> 2); 6761 mask |= 1U << ((mmNIC1_QM1_IND_GW_APB_WDATA & 0x7F) >> 2); 6762 mask |= 1U << ((mmNIC1_QM1_IND_GW_APB_RDATA & 0x7F) >> 2); 6763 mask |= 1U << ((mmNIC1_QM1_IND_GW_APB_STATUS & 0x7F) >> 2); 6764 mask |= 1U << ((mmNIC1_QM1_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 6765 mask |= 1U << ((mmNIC1_QM1_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 6766 mask |= 1U << ((mmNIC1_QM1_GLBL_ERR_WDATA & 0x7F) >> 2); 6767 6768 WREG32(pb_addr + word_offset, ~mask); 6769 6770 pb_addr = (mmNIC1_QM1_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 6771 word_offset = ((mmNIC1_QM1_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) 6772 >> 7) << 2; 6773 mask = 1U << ((mmNIC1_QM1_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 6774 6775 WREG32(pb_addr + word_offset, ~mask); 6776 6777 WREG32(mmNIC2_QM0_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 6778 WREG32(mmNIC2_QM1_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 6779 6780 pb_addr = (mmNIC2_QM0_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 6781 word_offset = ((mmNIC2_QM0_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 6782 mask = 1U << ((mmNIC2_QM0_GLBL_CFG0 & 0x7F) >> 2); 6783 mask |= 1U << ((mmNIC2_QM0_GLBL_CFG1 & 0x7F) >> 2); 6784 mask |= 1U << ((mmNIC2_QM0_GLBL_PROT & 0x7F) >> 2); 6785 mask |= 1U << ((mmNIC2_QM0_GLBL_ERR_CFG & 0x7F) >> 2); 6786 mask |= 1U << ((mmNIC2_QM0_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 6787 mask |= 1U << ((mmNIC2_QM0_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 6788 mask |= 1U << ((mmNIC2_QM0_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 6789 mask |= 1U << ((mmNIC2_QM0_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 6790 mask |= 1U << ((mmNIC2_QM0_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 6791 mask |= 1U << ((mmNIC2_QM0_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 6792 mask |= 1U << ((mmNIC2_QM0_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 6793 mask |= 1U << ((mmNIC2_QM0_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 6794 mask |= 1U << ((mmNIC2_QM0_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 6795 mask |= 1U << ((mmNIC2_QM0_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 6796 mask |= 1U << ((mmNIC2_QM0_GLBL_STS0 & 0x7F) >> 2); 6797 mask |= 1U << ((mmNIC2_QM0_GLBL_STS1_0 & 0x7F) >> 2); 6798 mask |= 1U << ((mmNIC2_QM0_GLBL_STS1_1 & 0x7F) >> 2); 6799 mask |= 1U << ((mmNIC2_QM0_GLBL_STS1_2 & 0x7F) >> 2); 6800 mask |= 1U << ((mmNIC2_QM0_GLBL_STS1_3 & 0x7F) >> 2); 6801 mask |= 1U << ((mmNIC2_QM0_GLBL_STS1_4 & 0x7F) >> 2); 6802 mask |= 1U << ((mmNIC2_QM0_GLBL_MSG_EN_0 & 0x7F) >> 2); 6803 mask |= 1U << ((mmNIC2_QM0_GLBL_MSG_EN_1 & 0x7F) >> 2); 6804 mask |= 1U << ((mmNIC2_QM0_GLBL_MSG_EN_2 & 0x7F) >> 2); 6805 mask |= 1U << ((mmNIC2_QM0_GLBL_MSG_EN_3 & 0x7F) >> 2); 6806 mask |= 1U << ((mmNIC2_QM0_GLBL_MSG_EN_4 & 0x7F) >> 2); 6807 mask |= 1U << ((mmNIC2_QM0_PQ_BASE_LO_0 & 0x7F) >> 2); 6808 mask |= 1U << ((mmNIC2_QM0_PQ_BASE_LO_1 & 0x7F) >> 2); 6809 mask |= 1U << ((mmNIC2_QM0_PQ_BASE_LO_2 & 0x7F) >> 2); 6810 mask |= 1U << ((mmNIC2_QM0_PQ_BASE_LO_3 & 0x7F) >> 2); 6811 6812 WREG32(pb_addr + word_offset, ~mask); 6813 6814 pb_addr = (mmNIC2_QM0_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 6815 word_offset = ((mmNIC2_QM0_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 6816 mask = 1U << ((mmNIC2_QM0_PQ_BASE_HI_0 & 0x7F) >> 2); 6817 mask |= 1U << ((mmNIC2_QM0_PQ_BASE_HI_1 & 0x7F) >> 2); 6818 mask |= 1U << ((mmNIC2_QM0_PQ_BASE_HI_2 & 0x7F) >> 2); 6819 mask |= 1U << ((mmNIC2_QM0_PQ_BASE_HI_3 & 0x7F) >> 2); 6820 mask |= 1U << ((mmNIC2_QM0_PQ_SIZE_0 & 0x7F) >> 2); 6821 mask |= 1U << ((mmNIC2_QM0_PQ_SIZE_1 & 0x7F) >> 2); 6822 mask |= 1U << ((mmNIC2_QM0_PQ_SIZE_2 & 0x7F) >> 2); 6823 mask |= 1U << ((mmNIC2_QM0_PQ_SIZE_3 & 0x7F) >> 2); 6824 mask |= 1U << ((mmNIC2_QM0_PQ_PI_0 & 0x7F) >> 2); 6825 mask |= 1U << ((mmNIC2_QM0_PQ_PI_1 & 0x7F) >> 2); 6826 mask |= 1U << ((mmNIC2_QM0_PQ_PI_2 & 0x7F) >> 2); 6827 mask |= 1U << ((mmNIC2_QM0_PQ_PI_3 & 0x7F) >> 2); 6828 mask |= 1U << ((mmNIC2_QM0_PQ_CI_0 & 0x7F) >> 2); 6829 mask |= 1U << ((mmNIC2_QM0_PQ_CI_1 & 0x7F) >> 2); 6830 mask |= 1U << ((mmNIC2_QM0_PQ_CI_2 & 0x7F) >> 2); 6831 mask |= 1U << ((mmNIC2_QM0_PQ_CI_3 & 0x7F) >> 2); 6832 mask |= 1U << ((mmNIC2_QM0_PQ_CFG0_0 & 0x7F) >> 2); 6833 mask |= 1U << ((mmNIC2_QM0_PQ_CFG0_1 & 0x7F) >> 2); 6834 mask |= 1U << ((mmNIC2_QM0_PQ_CFG0_2 & 0x7F) >> 2); 6835 mask |= 1U << ((mmNIC2_QM0_PQ_CFG0_3 & 0x7F) >> 2); 6836 mask |= 1U << ((mmNIC2_QM0_PQ_CFG1_0 & 0x7F) >> 2); 6837 mask |= 1U << ((mmNIC2_QM0_PQ_CFG1_1 & 0x7F) >> 2); 6838 mask |= 1U << ((mmNIC2_QM0_PQ_CFG1_2 & 0x7F) >> 2); 6839 mask |= 1U << ((mmNIC2_QM0_PQ_CFG1_3 & 0x7F) >> 2); 6840 mask |= 1U << ((mmNIC2_QM0_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 6841 mask |= 1U << ((mmNIC2_QM0_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 6842 mask |= 1U << ((mmNIC2_QM0_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 6843 mask |= 1U << ((mmNIC2_QM0_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 6844 mask |= 1U << ((mmNIC2_QM0_PQ_STS0_0 & 0x7F) >> 2); 6845 mask |= 1U << ((mmNIC2_QM0_PQ_STS0_1 & 0x7F) >> 2); 6846 mask |= 1U << ((mmNIC2_QM0_PQ_STS0_2 & 0x7F) >> 2); 6847 mask |= 1U << ((mmNIC2_QM0_PQ_STS0_3 & 0x7F) >> 2); 6848 6849 WREG32(pb_addr + word_offset, ~mask); 6850 6851 pb_addr = (mmNIC2_QM0_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 6852 word_offset = ((mmNIC2_QM0_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 6853 mask = 1U << ((mmNIC2_QM0_PQ_STS1_0 & 0x7F) >> 2); 6854 mask |= 1U << ((mmNIC2_QM0_PQ_STS1_1 & 0x7F) >> 2); 6855 mask |= 1U << ((mmNIC2_QM0_PQ_STS1_2 & 0x7F) >> 2); 6856 mask |= 1U << ((mmNIC2_QM0_PQ_STS1_3 & 0x7F) >> 2); 6857 mask |= 1U << ((mmNIC2_QM0_CQ_STS0_0 & 0x7F) >> 2); 6858 mask |= 1U << ((mmNIC2_QM0_CQ_STS0_1 & 0x7F) >> 2); 6859 mask |= 1U << ((mmNIC2_QM0_CQ_STS0_2 & 0x7F) >> 2); 6860 mask |= 1U << ((mmNIC2_QM0_CQ_STS0_3 & 0x7F) >> 2); 6861 mask |= 1U << ((mmNIC2_QM0_CQ_STS1_0 & 0x7F) >> 2); 6862 mask |= 1U << ((mmNIC2_QM0_CQ_STS1_1 & 0x7F) >> 2); 6863 mask |= 1U << ((mmNIC2_QM0_CQ_STS1_2 & 0x7F) >> 2); 6864 mask |= 1U << ((mmNIC2_QM0_CQ_STS1_3 & 0x7F) >> 2); 6865 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_0 & 0x7F) >> 2); 6866 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_0 & 0x7F) >> 2); 6867 mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_0 & 0x7F) >> 2); 6868 6869 WREG32(pb_addr + word_offset, ~mask); 6870 6871 pb_addr = (mmNIC2_QM0_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 6872 word_offset = ((mmNIC2_QM0_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 6873 mask = 1U << ((mmNIC2_QM0_CQ_CTL_0 & 0x7F) >> 2); 6874 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_1 & 0x7F) >> 2); 6875 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_1 & 0x7F) >> 2); 6876 mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_1 & 0x7F) >> 2); 6877 mask |= 1U << ((mmNIC2_QM0_CQ_CTL_1 & 0x7F) >> 2); 6878 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_2 & 0x7F) >> 2); 6879 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_2 & 0x7F) >> 2); 6880 mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_2 & 0x7F) >> 2); 6881 mask |= 1U << ((mmNIC2_QM0_CQ_CTL_2 & 0x7F) >> 2); 6882 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_3 & 0x7F) >> 2); 6883 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_3 & 0x7F) >> 2); 6884 mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_3 & 0x7F) >> 2); 6885 mask |= 1U << ((mmNIC2_QM0_CQ_CTL_3 & 0x7F) >> 2); 6886 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 6887 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 6888 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 6889 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 6890 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 6891 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 6892 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 6893 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 6894 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 6895 mask |= 1U << ((mmNIC2_QM0_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 6896 mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_STS_0 & 0x7F) >> 2); 6897 mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_STS_1 & 0x7F) >> 2); 6898 mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_STS_2 & 0x7F) >> 2); 6899 mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_STS_3 & 0x7F) >> 2); 6900 mask |= 1U << ((mmNIC2_QM0_CQ_TSIZE_STS_4 & 0x7F) >> 2); 6901 6902 WREG32(pb_addr + word_offset, ~mask); 6903 6904 pb_addr = (mmNIC2_QM0_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 6905 word_offset = ((mmNIC2_QM0_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 6906 mask = 1U << ((mmNIC2_QM0_CQ_CTL_STS_0 & 0x7F) >> 2); 6907 mask |= 1U << ((mmNIC2_QM0_CQ_CTL_STS_1 & 0x7F) >> 2); 6908 mask |= 1U << ((mmNIC2_QM0_CQ_CTL_STS_2 & 0x7F) >> 2); 6909 mask |= 1U << ((mmNIC2_QM0_CQ_CTL_STS_3 & 0x7F) >> 2); 6910 mask |= 1U << ((mmNIC2_QM0_CQ_CTL_STS_4 & 0x7F) >> 2); 6911 mask |= 1U << ((mmNIC2_QM0_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 6912 mask |= 1U << ((mmNIC2_QM0_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 6913 mask |= 1U << ((mmNIC2_QM0_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 6914 mask |= 1U << ((mmNIC2_QM0_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 6915 mask |= 1U << ((mmNIC2_QM0_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 6916 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 6917 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 6918 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 6919 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 6920 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 6921 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 6922 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 6923 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 6924 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 6925 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 6926 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 6927 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 6928 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 6929 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 6930 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 6931 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 6932 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 6933 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 6934 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 6935 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 6936 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 6937 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 6938 6939 WREG32(pb_addr + word_offset, ~mask); 6940 6941 pb_addr = (mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + 6942 PROT_BITS_OFFS; 6943 word_offset = ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) 6944 >> 7) << 2; 6945 mask = 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 6946 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 6947 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 6948 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 6949 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 6950 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 6951 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 6952 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 6953 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 6954 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 6955 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 6956 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 6957 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 6958 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 6959 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 6960 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 6961 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 6962 mask |= 1U << ((mmNIC2_QM0_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 6963 mask |= 1U << ((mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 6964 mask |= 1U << ((mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 6965 mask |= 1U << ((mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 6966 mask |= 1U << ((mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 6967 mask |= 1U << ((mmNIC2_QM0_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 6968 mask |= 1U << ((mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 6969 mask |= 1U << ((mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 6970 mask |= 1U << ((mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 6971 mask |= 1U << ((mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 6972 mask |= 1U << ((mmNIC2_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 6973 mask |= 1U << ((mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 6974 mask |= 1U << ((mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 6975 mask |= 1U << ((mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 6976 6977 WREG32(pb_addr + word_offset, ~mask); 6978 6979 pb_addr = (mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 6980 PROT_BITS_OFFS; 6981 word_offset = ((mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & 6982 PROT_BITS_OFFS) >> 7) << 2; 6983 mask = 1U << ((mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 6984 mask |= 1U << ((mmNIC2_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 6985 6986 WREG32(pb_addr + word_offset, ~mask); 6987 6988 pb_addr = (mmNIC2_QM0_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 6989 word_offset = ((mmNIC2_QM0_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 6990 mask = 1U << ((mmNIC2_QM0_CP_STS_0 & 0x7F) >> 2); 6991 mask |= 1U << ((mmNIC2_QM0_CP_STS_1 & 0x7F) >> 2); 6992 mask |= 1U << ((mmNIC2_QM0_CP_STS_2 & 0x7F) >> 2); 6993 mask |= 1U << ((mmNIC2_QM0_CP_STS_3 & 0x7F) >> 2); 6994 mask |= 1U << ((mmNIC2_QM0_CP_STS_4 & 0x7F) >> 2); 6995 mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 6996 mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 6997 mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 6998 mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 6999 mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 7000 mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 7001 mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 7002 mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 7003 mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 7004 mask |= 1U << ((mmNIC2_QM0_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 7005 mask |= 1U << ((mmNIC2_QM0_CP_BARRIER_CFG_0 & 0x7F) >> 2); 7006 mask |= 1U << ((mmNIC2_QM0_CP_BARRIER_CFG_1 & 0x7F) >> 2); 7007 mask |= 1U << ((mmNIC2_QM0_CP_BARRIER_CFG_2 & 0x7F) >> 2); 7008 7009 WREG32(pb_addr + word_offset, ~mask); 7010 7011 pb_addr = (mmNIC2_QM0_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 7012 word_offset = ((mmNIC2_QM0_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) 7013 >> 7) << 2; 7014 mask = 1U << ((mmNIC2_QM0_CP_BARRIER_CFG_3 & 0x7F) >> 2); 7015 mask |= 1U << ((mmNIC2_QM0_CP_BARRIER_CFG_4 & 0x7F) >> 2); 7016 mask |= 1U << ((mmNIC2_QM0_CP_DBG_0_0 & 0x7F) >> 2); 7017 mask |= 1U << ((mmNIC2_QM0_CP_DBG_0_1 & 0x7F) >> 2); 7018 7019 WREG32(pb_addr + word_offset, ~mask); 7020 7021 pb_addr = (mmNIC2_QM0_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 7022 word_offset = ((mmNIC2_QM0_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 7023 mask = 1U << ((mmNIC2_QM0_CP_DBG_0_2 & 0x7F) >> 2); 7024 mask |= 1U << ((mmNIC2_QM0_CP_DBG_0_3 & 0x7F) >> 2); 7025 mask |= 1U << ((mmNIC2_QM0_CP_DBG_0_4 & 0x7F) >> 2); 7026 mask |= 1U << ((mmNIC2_QM0_CP_ARUSER_31_11_0 & 0x7F) >> 2); 7027 mask |= 1U << ((mmNIC2_QM0_CP_ARUSER_31_11_1 & 0x7F) >> 2); 7028 mask |= 1U << ((mmNIC2_QM0_CP_ARUSER_31_11_2 & 0x7F) >> 2); 7029 mask |= 1U << ((mmNIC2_QM0_CP_ARUSER_31_11_3 & 0x7F) >> 2); 7030 mask |= 1U << ((mmNIC2_QM0_CP_ARUSER_31_11_4 & 0x7F) >> 2); 7031 mask |= 1U << ((mmNIC2_QM0_CP_AWUSER_31_11_0 & 0x7F) >> 2); 7032 mask |= 1U << ((mmNIC2_QM0_CP_AWUSER_31_11_1 & 0x7F) >> 2); 7033 mask |= 1U << ((mmNIC2_QM0_CP_AWUSER_31_11_2 & 0x7F) >> 2); 7034 mask |= 1U << ((mmNIC2_QM0_CP_AWUSER_31_11_3 & 0x7F) >> 2); 7035 mask |= 1U << ((mmNIC2_QM0_CP_AWUSER_31_11_4 & 0x7F) >> 2); 7036 7037 WREG32(pb_addr + word_offset, ~mask); 7038 7039 pb_addr = (mmNIC2_QM0_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 7040 word_offset = ((mmNIC2_QM0_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 7041 mask = 1U << ((mmNIC2_QM0_ARB_CFG_1 & 0x7F) >> 2); 7042 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 7043 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 7044 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 7045 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 7046 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 7047 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 7048 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 7049 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 7050 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 7051 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 7052 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 7053 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 7054 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 7055 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 7056 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 7057 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 7058 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 7059 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 7060 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 7061 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 7062 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 7063 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 7064 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 7065 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 7066 7067 WREG32(pb_addr + word_offset, ~mask); 7068 7069 pb_addr = (mmNIC2_QM0_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 7070 word_offset = ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_24 & 7071 PROT_BITS_OFFS) >> 7) << 2; 7072 mask = 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 7073 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 7074 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 7075 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 7076 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 7077 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 7078 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 7079 mask |= 1U << ((mmNIC2_QM0_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 7080 7081 WREG32(pb_addr + word_offset, ~mask); 7082 7083 pb_addr = (mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 7084 PROT_BITS_OFFS; 7085 word_offset = ((mmNIC2_QM0_ARB_MST_CHOISE_PUSH_OFST_23 & 7086 PROT_BITS_OFFS) >> 7) << 2; 7087 mask = 1U << ((mmNIC2_QM0_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 7088 mask |= 1U << ((mmNIC2_QM0_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 7089 mask |= 1U << ((mmNIC2_QM0_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 7090 mask |= 1U << ((mmNIC2_QM0_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 7091 mask |= 1U << ((mmNIC2_QM0_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 7092 7093 WREG32(pb_addr + word_offset, ~mask); 7094 7095 pb_addr = (mmNIC2_QM0_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 7096 word_offset = ((mmNIC2_QM0_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 7097 mask = 1U << ((mmNIC2_QM0_ARB_STATE_STS & 0x7F) >> 2); 7098 mask |= 1U << ((mmNIC2_QM0_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 7099 mask |= 1U << ((mmNIC2_QM0_ARB_MSG_STS & 0x7F) >> 2); 7100 mask |= 1U << ((mmNIC2_QM0_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 7101 mask |= 1U << ((mmNIC2_QM0_ARB_ERR_CAUSE & 0x7F) >> 2); 7102 mask |= 1U << ((mmNIC2_QM0_ARB_ERR_MSG_EN & 0x7F) >> 2); 7103 mask |= 1U << ((mmNIC2_QM0_ARB_ERR_STS_DRP & 0x7F) >> 2); 7104 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 7105 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 7106 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 7107 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 7108 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 7109 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 7110 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 7111 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 7112 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 7113 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 7114 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 7115 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 7116 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 7117 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 7118 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 7119 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 7120 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 7121 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 7122 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 7123 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 7124 7125 WREG32(pb_addr + word_offset, ~mask); 7126 7127 pb_addr = (mmNIC2_QM0_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 7128 word_offset = ((mmNIC2_QM0_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) 7129 >> 7) << 2; 7130 mask = 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 7131 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 7132 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 7133 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 7134 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 7135 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 7136 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 7137 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 7138 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 7139 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 7140 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 7141 mask |= 1U << ((mmNIC2_QM0_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 7142 mask |= 1U << ((mmNIC2_QM0_CGM_CFG & 0x7F) >> 2); 7143 mask |= 1U << ((mmNIC2_QM0_CGM_STS & 0x7F) >> 2); 7144 mask |= 1U << ((mmNIC2_QM0_CGM_CFG1 & 0x7F) >> 2); 7145 7146 WREG32(pb_addr + word_offset, ~mask); 7147 7148 pb_addr = (mmNIC2_QM0_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 7149 word_offset = ((mmNIC2_QM0_LOCAL_RANGE_BASE & PROT_BITS_OFFS) 7150 >> 7) << 2; 7151 mask = 1U << ((mmNIC2_QM0_LOCAL_RANGE_BASE & 0x7F) >> 2); 7152 mask |= 1U << ((mmNIC2_QM0_LOCAL_RANGE_SIZE & 0x7F) >> 2); 7153 mask |= 1U << ((mmNIC2_QM0_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 7154 mask |= 1U << ((mmNIC2_QM0_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 7155 mask |= 1U << ((mmNIC2_QM0_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 7156 mask |= 1U << ((mmNIC2_QM0_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 7157 mask |= 1U << ((mmNIC2_QM0_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 7158 mask |= 1U << ((mmNIC2_QM0_GLBL_AXCACHE & 0x7F) >> 2); 7159 mask |= 1U << ((mmNIC2_QM0_IND_GW_APB_CFG & 0x7F) >> 2); 7160 mask |= 1U << ((mmNIC2_QM0_IND_GW_APB_WDATA & 0x7F) >> 2); 7161 mask |= 1U << ((mmNIC2_QM0_IND_GW_APB_RDATA & 0x7F) >> 2); 7162 mask |= 1U << ((mmNIC2_QM0_IND_GW_APB_STATUS & 0x7F) >> 2); 7163 mask |= 1U << ((mmNIC2_QM0_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 7164 mask |= 1U << ((mmNIC2_QM0_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 7165 mask |= 1U << ((mmNIC2_QM0_GLBL_ERR_WDATA & 0x7F) >> 2); 7166 7167 WREG32(pb_addr + word_offset, ~mask); 7168 7169 pb_addr = (mmNIC2_QM0_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 7170 word_offset = ((mmNIC2_QM0_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) 7171 >> 7) << 2; 7172 mask = 1U << ((mmNIC2_QM0_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 7173 7174 WREG32(pb_addr + word_offset, ~mask); 7175 7176 pb_addr = (mmNIC2_QM1_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 7177 word_offset = ((mmNIC2_QM1_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 7178 mask = 1U << ((mmNIC2_QM1_GLBL_CFG0 & 0x7F) >> 2); 7179 mask |= 1U << ((mmNIC2_QM1_GLBL_CFG1 & 0x7F) >> 2); 7180 mask |= 1U << ((mmNIC2_QM1_GLBL_PROT & 0x7F) >> 2); 7181 mask |= 1U << ((mmNIC2_QM1_GLBL_ERR_CFG & 0x7F) >> 2); 7182 mask |= 1U << ((mmNIC2_QM1_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 7183 mask |= 1U << ((mmNIC2_QM1_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 7184 mask |= 1U << ((mmNIC2_QM1_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 7185 mask |= 1U << ((mmNIC2_QM1_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 7186 mask |= 1U << ((mmNIC2_QM1_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 7187 mask |= 1U << ((mmNIC2_QM1_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 7188 mask |= 1U << ((mmNIC2_QM1_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 7189 mask |= 1U << ((mmNIC2_QM1_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 7190 mask |= 1U << ((mmNIC2_QM1_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 7191 mask |= 1U << ((mmNIC2_QM1_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 7192 mask |= 1U << ((mmNIC2_QM1_GLBL_STS0 & 0x7F) >> 2); 7193 mask |= 1U << ((mmNIC2_QM1_GLBL_STS1_0 & 0x7F) >> 2); 7194 mask |= 1U << ((mmNIC2_QM1_GLBL_STS1_1 & 0x7F) >> 2); 7195 mask |= 1U << ((mmNIC2_QM1_GLBL_STS1_2 & 0x7F) >> 2); 7196 mask |= 1U << ((mmNIC2_QM1_GLBL_STS1_3 & 0x7F) >> 2); 7197 mask |= 1U << ((mmNIC2_QM1_GLBL_STS1_4 & 0x7F) >> 2); 7198 mask |= 1U << ((mmNIC2_QM1_GLBL_MSG_EN_0 & 0x7F) >> 2); 7199 mask |= 1U << ((mmNIC2_QM1_GLBL_MSG_EN_1 & 0x7F) >> 2); 7200 mask |= 1U << ((mmNIC2_QM1_GLBL_MSG_EN_2 & 0x7F) >> 2); 7201 mask |= 1U << ((mmNIC2_QM1_GLBL_MSG_EN_3 & 0x7F) >> 2); 7202 mask |= 1U << ((mmNIC2_QM1_GLBL_MSG_EN_4 & 0x7F) >> 2); 7203 mask |= 1U << ((mmNIC2_QM1_PQ_BASE_LO_0 & 0x7F) >> 2); 7204 mask |= 1U << ((mmNIC2_QM1_PQ_BASE_LO_1 & 0x7F) >> 2); 7205 mask |= 1U << ((mmNIC2_QM1_PQ_BASE_LO_2 & 0x7F) >> 2); 7206 mask |= 1U << ((mmNIC2_QM1_PQ_BASE_LO_3 & 0x7F) >> 2); 7207 7208 WREG32(pb_addr + word_offset, ~mask); 7209 7210 pb_addr = (mmNIC2_QM1_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 7211 word_offset = ((mmNIC2_QM1_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 7212 mask = 1U << ((mmNIC2_QM1_PQ_BASE_HI_0 & 0x7F) >> 2); 7213 mask |= 1U << ((mmNIC2_QM1_PQ_BASE_HI_1 & 0x7F) >> 2); 7214 mask |= 1U << ((mmNIC2_QM1_PQ_BASE_HI_2 & 0x7F) >> 2); 7215 mask |= 1U << ((mmNIC2_QM1_PQ_BASE_HI_3 & 0x7F) >> 2); 7216 mask |= 1U << ((mmNIC2_QM1_PQ_SIZE_0 & 0x7F) >> 2); 7217 mask |= 1U << ((mmNIC2_QM1_PQ_SIZE_1 & 0x7F) >> 2); 7218 mask |= 1U << ((mmNIC2_QM1_PQ_SIZE_2 & 0x7F) >> 2); 7219 mask |= 1U << ((mmNIC2_QM1_PQ_SIZE_3 & 0x7F) >> 2); 7220 mask |= 1U << ((mmNIC2_QM1_PQ_PI_0 & 0x7F) >> 2); 7221 mask |= 1U << ((mmNIC2_QM1_PQ_PI_1 & 0x7F) >> 2); 7222 mask |= 1U << ((mmNIC2_QM1_PQ_PI_2 & 0x7F) >> 2); 7223 mask |= 1U << ((mmNIC2_QM1_PQ_PI_3 & 0x7F) >> 2); 7224 mask |= 1U << ((mmNIC2_QM1_PQ_CI_0 & 0x7F) >> 2); 7225 mask |= 1U << ((mmNIC2_QM1_PQ_CI_1 & 0x7F) >> 2); 7226 mask |= 1U << ((mmNIC2_QM1_PQ_CI_2 & 0x7F) >> 2); 7227 mask |= 1U << ((mmNIC2_QM1_PQ_CI_3 & 0x7F) >> 2); 7228 mask |= 1U << ((mmNIC2_QM1_PQ_CFG0_0 & 0x7F) >> 2); 7229 mask |= 1U << ((mmNIC2_QM1_PQ_CFG0_1 & 0x7F) >> 2); 7230 mask |= 1U << ((mmNIC2_QM1_PQ_CFG0_2 & 0x7F) >> 2); 7231 mask |= 1U << ((mmNIC2_QM1_PQ_CFG0_3 & 0x7F) >> 2); 7232 mask |= 1U << ((mmNIC2_QM1_PQ_CFG1_0 & 0x7F) >> 2); 7233 mask |= 1U << ((mmNIC2_QM1_PQ_CFG1_1 & 0x7F) >> 2); 7234 mask |= 1U << ((mmNIC2_QM1_PQ_CFG1_2 & 0x7F) >> 2); 7235 mask |= 1U << ((mmNIC2_QM1_PQ_CFG1_3 & 0x7F) >> 2); 7236 mask |= 1U << ((mmNIC2_QM1_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 7237 mask |= 1U << ((mmNIC2_QM1_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 7238 mask |= 1U << ((mmNIC2_QM1_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 7239 mask |= 1U << ((mmNIC2_QM1_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 7240 mask |= 1U << ((mmNIC2_QM1_PQ_STS0_0 & 0x7F) >> 2); 7241 mask |= 1U << ((mmNIC2_QM1_PQ_STS0_1 & 0x7F) >> 2); 7242 mask |= 1U << ((mmNIC2_QM1_PQ_STS0_2 & 0x7F) >> 2); 7243 mask |= 1U << ((mmNIC2_QM1_PQ_STS0_3 & 0x7F) >> 2); 7244 7245 WREG32(pb_addr + word_offset, ~mask); 7246 7247 pb_addr = (mmNIC2_QM1_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 7248 word_offset = ((mmNIC2_QM1_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 7249 mask = 1U << ((mmNIC2_QM1_PQ_STS1_0 & 0x7F) >> 2); 7250 mask |= 1U << ((mmNIC2_QM1_PQ_STS1_1 & 0x7F) >> 2); 7251 mask |= 1U << ((mmNIC2_QM1_PQ_STS1_2 & 0x7F) >> 2); 7252 mask |= 1U << ((mmNIC2_QM1_PQ_STS1_3 & 0x7F) >> 2); 7253 mask |= 1U << ((mmNIC2_QM1_CQ_STS0_0 & 0x7F) >> 2); 7254 mask |= 1U << ((mmNIC2_QM1_CQ_STS0_1 & 0x7F) >> 2); 7255 mask |= 1U << ((mmNIC2_QM1_CQ_STS0_2 & 0x7F) >> 2); 7256 mask |= 1U << ((mmNIC2_QM1_CQ_STS0_3 & 0x7F) >> 2); 7257 mask |= 1U << ((mmNIC2_QM1_CQ_STS1_0 & 0x7F) >> 2); 7258 mask |= 1U << ((mmNIC2_QM1_CQ_STS1_1 & 0x7F) >> 2); 7259 mask |= 1U << ((mmNIC2_QM1_CQ_STS1_2 & 0x7F) >> 2); 7260 mask |= 1U << ((mmNIC2_QM1_CQ_STS1_3 & 0x7F) >> 2); 7261 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_0 & 0x7F) >> 2); 7262 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_0 & 0x7F) >> 2); 7263 mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_0 & 0x7F) >> 2); 7264 7265 WREG32(pb_addr + word_offset, ~mask); 7266 7267 pb_addr = (mmNIC2_QM1_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 7268 word_offset = ((mmNIC2_QM1_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 7269 mask = 1U << ((mmNIC2_QM1_CQ_CTL_0 & 0x7F) >> 2); 7270 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_1 & 0x7F) >> 2); 7271 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_1 & 0x7F) >> 2); 7272 mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_1 & 0x7F) >> 2); 7273 mask |= 1U << ((mmNIC2_QM1_CQ_CTL_1 & 0x7F) >> 2); 7274 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_2 & 0x7F) >> 2); 7275 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_2 & 0x7F) >> 2); 7276 mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_2 & 0x7F) >> 2); 7277 mask |= 1U << ((mmNIC2_QM1_CQ_CTL_2 & 0x7F) >> 2); 7278 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_3 & 0x7F) >> 2); 7279 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_3 & 0x7F) >> 2); 7280 mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_3 & 0x7F) >> 2); 7281 mask |= 1U << ((mmNIC2_QM1_CQ_CTL_3 & 0x7F) >> 2); 7282 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 7283 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 7284 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 7285 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 7286 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 7287 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 7288 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 7289 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 7290 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 7291 mask |= 1U << ((mmNIC2_QM1_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 7292 mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_STS_0 & 0x7F) >> 2); 7293 mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_STS_1 & 0x7F) >> 2); 7294 mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_STS_2 & 0x7F) >> 2); 7295 mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_STS_3 & 0x7F) >> 2); 7296 mask |= 1U << ((mmNIC2_QM1_CQ_TSIZE_STS_4 & 0x7F) >> 2); 7297 7298 WREG32(pb_addr + word_offset, ~mask); 7299 7300 pb_addr = (mmNIC2_QM1_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 7301 word_offset = ((mmNIC2_QM1_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 7302 mask = 1U << ((mmNIC2_QM1_CQ_CTL_STS_0 & 0x7F) >> 2); 7303 mask |= 1U << ((mmNIC2_QM1_CQ_CTL_STS_1 & 0x7F) >> 2); 7304 mask |= 1U << ((mmNIC2_QM1_CQ_CTL_STS_2 & 0x7F) >> 2); 7305 mask |= 1U << ((mmNIC2_QM1_CQ_CTL_STS_3 & 0x7F) >> 2); 7306 mask |= 1U << ((mmNIC2_QM1_CQ_CTL_STS_4 & 0x7F) >> 2); 7307 mask |= 1U << ((mmNIC2_QM1_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 7308 mask |= 1U << ((mmNIC2_QM1_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 7309 mask |= 1U << ((mmNIC2_QM1_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 7310 mask |= 1U << ((mmNIC2_QM1_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 7311 mask |= 1U << ((mmNIC2_QM1_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 7312 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 7313 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 7314 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 7315 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 7316 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 7317 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 7318 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 7319 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 7320 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 7321 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 7322 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 7323 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 7324 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 7325 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 7326 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 7327 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 7328 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 7329 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 7330 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 7331 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 7332 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 7333 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 7334 7335 WREG32(pb_addr + word_offset, ~mask); 7336 7337 pb_addr = (mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 7338 word_offset = ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_2 & 7339 PROT_BITS_OFFS) >> 7) << 2; 7340 mask = 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 7341 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 7342 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 7343 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 7344 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 7345 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 7346 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 7347 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 7348 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 7349 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 7350 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 7351 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 7352 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 7353 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 7354 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 7355 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 7356 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 7357 mask |= 1U << ((mmNIC2_QM1_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 7358 mask |= 1U << ((mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 7359 mask |= 1U << ((mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 7360 mask |= 1U << ((mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 7361 mask |= 1U << ((mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 7362 mask |= 1U << ((mmNIC2_QM1_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 7363 mask |= 1U << ((mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 7364 mask |= 1U << ((mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 7365 mask |= 1U << ((mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 7366 mask |= 1U << ((mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 7367 mask |= 1U << ((mmNIC2_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 7368 mask |= 1U << ((mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 7369 mask |= 1U << ((mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 7370 mask |= 1U << ((mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 7371 7372 WREG32(pb_addr + word_offset, ~mask); 7373 7374 pb_addr = (mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 7375 PROT_BITS_OFFS; 7376 word_offset = ((mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & 7377 PROT_BITS_OFFS) >> 7) << 2; 7378 mask = 1U << ((mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 7379 mask |= 1U << ((mmNIC2_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 7380 7381 WREG32(pb_addr + word_offset, ~mask); 7382 7383 pb_addr = (mmNIC2_QM1_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 7384 word_offset = ((mmNIC2_QM1_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 7385 mask = 1U << ((mmNIC2_QM1_CP_STS_0 & 0x7F) >> 2); 7386 mask |= 1U << ((mmNIC2_QM1_CP_STS_1 & 0x7F) >> 2); 7387 mask |= 1U << ((mmNIC2_QM1_CP_STS_2 & 0x7F) >> 2); 7388 mask |= 1U << ((mmNIC2_QM1_CP_STS_3 & 0x7F) >> 2); 7389 mask |= 1U << ((mmNIC2_QM1_CP_STS_4 & 0x7F) >> 2); 7390 mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 7391 mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 7392 mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 7393 mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 7394 mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 7395 mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 7396 mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 7397 mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 7398 mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 7399 mask |= 1U << ((mmNIC2_QM1_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 7400 mask |= 1U << ((mmNIC2_QM1_CP_BARRIER_CFG_0 & 0x7F) >> 2); 7401 mask |= 1U << ((mmNIC2_QM1_CP_BARRIER_CFG_1 & 0x7F) >> 2); 7402 mask |= 1U << ((mmNIC2_QM1_CP_BARRIER_CFG_2 & 0x7F) >> 2); 7403 7404 WREG32(pb_addr + word_offset, ~mask); 7405 7406 pb_addr = (mmNIC2_QM1_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 7407 word_offset = ((mmNIC2_QM1_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) 7408 >> 7) << 2; 7409 mask = 1U << ((mmNIC2_QM1_CP_BARRIER_CFG_3 & 0x7F) >> 2); 7410 mask |= 1U << ((mmNIC2_QM1_CP_BARRIER_CFG_4 & 0x7F) >> 2); 7411 mask |= 1U << ((mmNIC2_QM1_CP_DBG_0_0 & 0x7F) >> 2); 7412 mask |= 1U << ((mmNIC2_QM1_CP_DBG_0_1 & 0x7F) >> 2); 7413 7414 WREG32(pb_addr + word_offset, ~mask); 7415 7416 pb_addr = (mmNIC2_QM1_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 7417 word_offset = ((mmNIC2_QM1_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 7418 mask = 1U << ((mmNIC2_QM1_CP_DBG_0_2 & 0x7F) >> 2); 7419 mask |= 1U << ((mmNIC2_QM1_CP_DBG_0_3 & 0x7F) >> 2); 7420 mask |= 1U << ((mmNIC2_QM1_CP_DBG_0_4 & 0x7F) >> 2); 7421 mask |= 1U << ((mmNIC2_QM1_CP_ARUSER_31_11_0 & 0x7F) >> 2); 7422 mask |= 1U << ((mmNIC2_QM1_CP_ARUSER_31_11_1 & 0x7F) >> 2); 7423 mask |= 1U << ((mmNIC2_QM1_CP_ARUSER_31_11_2 & 0x7F) >> 2); 7424 mask |= 1U << ((mmNIC2_QM1_CP_ARUSER_31_11_3 & 0x7F) >> 2); 7425 mask |= 1U << ((mmNIC2_QM1_CP_ARUSER_31_11_4 & 0x7F) >> 2); 7426 mask |= 1U << ((mmNIC2_QM1_CP_AWUSER_31_11_0 & 0x7F) >> 2); 7427 mask |= 1U << ((mmNIC2_QM1_CP_AWUSER_31_11_1 & 0x7F) >> 2); 7428 mask |= 1U << ((mmNIC2_QM1_CP_AWUSER_31_11_2 & 0x7F) >> 2); 7429 mask |= 1U << ((mmNIC2_QM1_CP_AWUSER_31_11_3 & 0x7F) >> 2); 7430 mask |= 1U << ((mmNIC2_QM1_CP_AWUSER_31_11_4 & 0x7F) >> 2); 7431 7432 WREG32(pb_addr + word_offset, ~mask); 7433 7434 pb_addr = (mmNIC2_QM1_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 7435 word_offset = ((mmNIC2_QM1_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 7436 mask = 1U << ((mmNIC2_QM1_ARB_CFG_1 & 0x7F) >> 2); 7437 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 7438 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 7439 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 7440 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 7441 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 7442 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 7443 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 7444 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 7445 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 7446 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 7447 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 7448 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 7449 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 7450 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 7451 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 7452 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 7453 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 7454 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 7455 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 7456 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 7457 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 7458 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 7459 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 7460 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 7461 7462 WREG32(pb_addr + word_offset, ~mask); 7463 7464 pb_addr = (mmNIC2_QM1_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 7465 word_offset = ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_24 & 7466 PROT_BITS_OFFS) >> 7) << 2; 7467 mask = 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 7468 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 7469 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 7470 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 7471 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 7472 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 7473 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 7474 mask |= 1U << ((mmNIC2_QM1_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 7475 7476 WREG32(pb_addr + word_offset, ~mask); 7477 7478 pb_addr = (mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 7479 PROT_BITS_OFFS; 7480 word_offset = ((mmNIC2_QM1_ARB_MST_CHOISE_PUSH_OFST_23 & 7481 PROT_BITS_OFFS) >> 7) << 2; 7482 mask = 1U << ((mmNIC2_QM1_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 7483 mask |= 1U << ((mmNIC2_QM1_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 7484 mask |= 1U << ((mmNIC2_QM1_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 7485 mask |= 1U << ((mmNIC2_QM1_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 7486 mask |= 1U << ((mmNIC2_QM1_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 7487 7488 WREG32(pb_addr + word_offset, ~mask); 7489 7490 pb_addr = (mmNIC2_QM1_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 7491 word_offset = ((mmNIC2_QM1_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 7492 mask = 1U << ((mmNIC2_QM1_ARB_STATE_STS & 0x7F) >> 2); 7493 mask |= 1U << ((mmNIC2_QM1_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 7494 mask |= 1U << ((mmNIC2_QM1_ARB_MSG_STS & 0x7F) >> 2); 7495 mask |= 1U << ((mmNIC2_QM1_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 7496 mask |= 1U << ((mmNIC2_QM1_ARB_ERR_CAUSE & 0x7F) >> 2); 7497 mask |= 1U << ((mmNIC2_QM1_ARB_ERR_MSG_EN & 0x7F) >> 2); 7498 mask |= 1U << ((mmNIC2_QM1_ARB_ERR_STS_DRP & 0x7F) >> 2); 7499 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 7500 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 7501 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 7502 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 7503 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 7504 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 7505 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 7506 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 7507 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 7508 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 7509 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 7510 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 7511 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 7512 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 7513 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 7514 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 7515 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 7516 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 7517 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 7518 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 7519 7520 WREG32(pb_addr + word_offset, ~mask); 7521 7522 pb_addr = (mmNIC2_QM1_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 7523 word_offset = ((mmNIC2_QM1_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) 7524 >> 7) << 2; 7525 mask = 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 7526 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 7527 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 7528 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 7529 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 7530 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 7531 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 7532 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 7533 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 7534 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 7535 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 7536 mask |= 1U << ((mmNIC2_QM1_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 7537 mask |= 1U << ((mmNIC2_QM1_CGM_CFG & 0x7F) >> 2); 7538 mask |= 1U << ((mmNIC2_QM1_CGM_STS & 0x7F) >> 2); 7539 mask |= 1U << ((mmNIC2_QM1_CGM_CFG1 & 0x7F) >> 2); 7540 7541 WREG32(pb_addr + word_offset, ~mask); 7542 7543 pb_addr = (mmNIC2_QM1_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 7544 word_offset = ((mmNIC2_QM1_LOCAL_RANGE_BASE & PROT_BITS_OFFS) 7545 >> 7) << 2; 7546 mask = 1U << ((mmNIC2_QM1_LOCAL_RANGE_BASE & 0x7F) >> 2); 7547 mask |= 1U << ((mmNIC2_QM1_LOCAL_RANGE_SIZE & 0x7F) >> 2); 7548 mask |= 1U << ((mmNIC2_QM1_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 7549 mask |= 1U << ((mmNIC2_QM1_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 7550 mask |= 1U << ((mmNIC2_QM1_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 7551 mask |= 1U << ((mmNIC2_QM1_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 7552 mask |= 1U << ((mmNIC2_QM1_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 7553 mask |= 1U << ((mmNIC2_QM1_GLBL_AXCACHE & 0x7F) >> 2); 7554 mask |= 1U << ((mmNIC2_QM1_IND_GW_APB_CFG & 0x7F) >> 2); 7555 mask |= 1U << ((mmNIC2_QM1_IND_GW_APB_WDATA & 0x7F) >> 2); 7556 mask |= 1U << ((mmNIC2_QM1_IND_GW_APB_RDATA & 0x7F) >> 2); 7557 mask |= 1U << ((mmNIC2_QM1_IND_GW_APB_STATUS & 0x7F) >> 2); 7558 mask |= 1U << ((mmNIC2_QM1_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 7559 mask |= 1U << ((mmNIC2_QM1_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 7560 mask |= 1U << ((mmNIC2_QM1_GLBL_ERR_WDATA & 0x7F) >> 2); 7561 7562 WREG32(pb_addr + word_offset, ~mask); 7563 7564 pb_addr = (mmNIC2_QM1_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 7565 word_offset = ((mmNIC2_QM1_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) 7566 >> 7) << 2; 7567 mask = 1U << ((mmNIC2_QM1_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 7568 7569 WREG32(pb_addr + word_offset, ~mask); 7570 7571 WREG32(mmNIC3_QM0_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 7572 WREG32(mmNIC3_QM1_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 7573 7574 pb_addr = (mmNIC3_QM0_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 7575 word_offset = ((mmNIC3_QM0_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 7576 mask = 1U << ((mmNIC3_QM0_GLBL_CFG0 & 0x7F) >> 2); 7577 mask |= 1U << ((mmNIC3_QM0_GLBL_CFG1 & 0x7F) >> 2); 7578 mask |= 1U << ((mmNIC3_QM0_GLBL_PROT & 0x7F) >> 2); 7579 mask |= 1U << ((mmNIC3_QM0_GLBL_ERR_CFG & 0x7F) >> 2); 7580 mask |= 1U << ((mmNIC3_QM0_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 7581 mask |= 1U << ((mmNIC3_QM0_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 7582 mask |= 1U << ((mmNIC3_QM0_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 7583 mask |= 1U << ((mmNIC3_QM0_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 7584 mask |= 1U << ((mmNIC3_QM0_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 7585 mask |= 1U << ((mmNIC3_QM0_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 7586 mask |= 1U << ((mmNIC3_QM0_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 7587 mask |= 1U << ((mmNIC3_QM0_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 7588 mask |= 1U << ((mmNIC3_QM0_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 7589 mask |= 1U << ((mmNIC3_QM0_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 7590 mask |= 1U << ((mmNIC3_QM0_GLBL_STS0 & 0x7F) >> 2); 7591 mask |= 1U << ((mmNIC3_QM0_GLBL_STS1_0 & 0x7F) >> 2); 7592 mask |= 1U << ((mmNIC3_QM0_GLBL_STS1_1 & 0x7F) >> 2); 7593 mask |= 1U << ((mmNIC3_QM0_GLBL_STS1_2 & 0x7F) >> 2); 7594 mask |= 1U << ((mmNIC3_QM0_GLBL_STS1_3 & 0x7F) >> 2); 7595 mask |= 1U << ((mmNIC3_QM0_GLBL_STS1_4 & 0x7F) >> 2); 7596 mask |= 1U << ((mmNIC3_QM0_GLBL_MSG_EN_0 & 0x7F) >> 2); 7597 mask |= 1U << ((mmNIC3_QM0_GLBL_MSG_EN_1 & 0x7F) >> 2); 7598 mask |= 1U << ((mmNIC3_QM0_GLBL_MSG_EN_2 & 0x7F) >> 2); 7599 mask |= 1U << ((mmNIC3_QM0_GLBL_MSG_EN_3 & 0x7F) >> 2); 7600 mask |= 1U << ((mmNIC3_QM0_GLBL_MSG_EN_4 & 0x7F) >> 2); 7601 mask |= 1U << ((mmNIC3_QM0_PQ_BASE_LO_0 & 0x7F) >> 2); 7602 mask |= 1U << ((mmNIC3_QM0_PQ_BASE_LO_1 & 0x7F) >> 2); 7603 mask |= 1U << ((mmNIC3_QM0_PQ_BASE_LO_2 & 0x7F) >> 2); 7604 mask |= 1U << ((mmNIC3_QM0_PQ_BASE_LO_3 & 0x7F) >> 2); 7605 7606 WREG32(pb_addr + word_offset, ~mask); 7607 7608 pb_addr = (mmNIC3_QM0_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 7609 word_offset = ((mmNIC3_QM0_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 7610 mask = 1U << ((mmNIC3_QM0_PQ_BASE_HI_0 & 0x7F) >> 2); 7611 mask |= 1U << ((mmNIC3_QM0_PQ_BASE_HI_1 & 0x7F) >> 2); 7612 mask |= 1U << ((mmNIC3_QM0_PQ_BASE_HI_2 & 0x7F) >> 2); 7613 mask |= 1U << ((mmNIC3_QM0_PQ_BASE_HI_3 & 0x7F) >> 2); 7614 mask |= 1U << ((mmNIC3_QM0_PQ_SIZE_0 & 0x7F) >> 2); 7615 mask |= 1U << ((mmNIC3_QM0_PQ_SIZE_1 & 0x7F) >> 2); 7616 mask |= 1U << ((mmNIC3_QM0_PQ_SIZE_2 & 0x7F) >> 2); 7617 mask |= 1U << ((mmNIC3_QM0_PQ_SIZE_3 & 0x7F) >> 2); 7618 mask |= 1U << ((mmNIC3_QM0_PQ_PI_0 & 0x7F) >> 2); 7619 mask |= 1U << ((mmNIC3_QM0_PQ_PI_1 & 0x7F) >> 2); 7620 mask |= 1U << ((mmNIC3_QM0_PQ_PI_2 & 0x7F) >> 2); 7621 mask |= 1U << ((mmNIC3_QM0_PQ_PI_3 & 0x7F) >> 2); 7622 mask |= 1U << ((mmNIC3_QM0_PQ_CI_0 & 0x7F) >> 2); 7623 mask |= 1U << ((mmNIC3_QM0_PQ_CI_1 & 0x7F) >> 2); 7624 mask |= 1U << ((mmNIC3_QM0_PQ_CI_2 & 0x7F) >> 2); 7625 mask |= 1U << ((mmNIC3_QM0_PQ_CI_3 & 0x7F) >> 2); 7626 mask |= 1U << ((mmNIC3_QM0_PQ_CFG0_0 & 0x7F) >> 2); 7627 mask |= 1U << ((mmNIC3_QM0_PQ_CFG0_1 & 0x7F) >> 2); 7628 mask |= 1U << ((mmNIC3_QM0_PQ_CFG0_2 & 0x7F) >> 2); 7629 mask |= 1U << ((mmNIC3_QM0_PQ_CFG0_3 & 0x7F) >> 2); 7630 mask |= 1U << ((mmNIC3_QM0_PQ_CFG1_0 & 0x7F) >> 2); 7631 mask |= 1U << ((mmNIC3_QM0_PQ_CFG1_1 & 0x7F) >> 2); 7632 mask |= 1U << ((mmNIC3_QM0_PQ_CFG1_2 & 0x7F) >> 2); 7633 mask |= 1U << ((mmNIC3_QM0_PQ_CFG1_3 & 0x7F) >> 2); 7634 mask |= 1U << ((mmNIC3_QM0_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 7635 mask |= 1U << ((mmNIC3_QM0_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 7636 mask |= 1U << ((mmNIC3_QM0_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 7637 mask |= 1U << ((mmNIC3_QM0_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 7638 mask |= 1U << ((mmNIC3_QM0_PQ_STS0_0 & 0x7F) >> 2); 7639 mask |= 1U << ((mmNIC3_QM0_PQ_STS0_1 & 0x7F) >> 2); 7640 mask |= 1U << ((mmNIC3_QM0_PQ_STS0_2 & 0x7F) >> 2); 7641 mask |= 1U << ((mmNIC3_QM0_PQ_STS0_3 & 0x7F) >> 2); 7642 7643 WREG32(pb_addr + word_offset, ~mask); 7644 7645 pb_addr = (mmNIC3_QM0_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 7646 word_offset = ((mmNIC3_QM0_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 7647 mask = 1U << ((mmNIC3_QM0_PQ_STS1_0 & 0x7F) >> 2); 7648 mask |= 1U << ((mmNIC3_QM0_PQ_STS1_1 & 0x7F) >> 2); 7649 mask |= 1U << ((mmNIC3_QM0_PQ_STS1_2 & 0x7F) >> 2); 7650 mask |= 1U << ((mmNIC3_QM0_PQ_STS1_3 & 0x7F) >> 2); 7651 mask |= 1U << ((mmNIC3_QM0_CQ_STS0_0 & 0x7F) >> 2); 7652 mask |= 1U << ((mmNIC3_QM0_CQ_STS0_1 & 0x7F) >> 2); 7653 mask |= 1U << ((mmNIC3_QM0_CQ_STS0_2 & 0x7F) >> 2); 7654 mask |= 1U << ((mmNIC3_QM0_CQ_STS0_3 & 0x7F) >> 2); 7655 mask |= 1U << ((mmNIC3_QM0_CQ_STS1_0 & 0x7F) >> 2); 7656 mask |= 1U << ((mmNIC3_QM0_CQ_STS1_1 & 0x7F) >> 2); 7657 mask |= 1U << ((mmNIC3_QM0_CQ_STS1_2 & 0x7F) >> 2); 7658 mask |= 1U << ((mmNIC3_QM0_CQ_STS1_3 & 0x7F) >> 2); 7659 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_0 & 0x7F) >> 2); 7660 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_0 & 0x7F) >> 2); 7661 mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_0 & 0x7F) >> 2); 7662 7663 WREG32(pb_addr + word_offset, ~mask); 7664 7665 pb_addr = (mmNIC3_QM0_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 7666 word_offset = ((mmNIC3_QM0_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 7667 mask = 1U << ((mmNIC3_QM0_CQ_CTL_0 & 0x7F) >> 2); 7668 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_1 & 0x7F) >> 2); 7669 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_1 & 0x7F) >> 2); 7670 mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_1 & 0x7F) >> 2); 7671 mask |= 1U << ((mmNIC3_QM0_CQ_CTL_1 & 0x7F) >> 2); 7672 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_2 & 0x7F) >> 2); 7673 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_2 & 0x7F) >> 2); 7674 mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_2 & 0x7F) >> 2); 7675 mask |= 1U << ((mmNIC3_QM0_CQ_CTL_2 & 0x7F) >> 2); 7676 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_3 & 0x7F) >> 2); 7677 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_3 & 0x7F) >> 2); 7678 mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_3 & 0x7F) >> 2); 7679 mask |= 1U << ((mmNIC3_QM0_CQ_CTL_3 & 0x7F) >> 2); 7680 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 7681 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 7682 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 7683 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 7684 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 7685 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 7686 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 7687 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 7688 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 7689 mask |= 1U << ((mmNIC3_QM0_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 7690 mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_STS_0 & 0x7F) >> 2); 7691 mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_STS_1 & 0x7F) >> 2); 7692 mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_STS_2 & 0x7F) >> 2); 7693 mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_STS_3 & 0x7F) >> 2); 7694 mask |= 1U << ((mmNIC3_QM0_CQ_TSIZE_STS_4 & 0x7F) >> 2); 7695 7696 WREG32(pb_addr + word_offset, ~mask); 7697 7698 pb_addr = (mmNIC3_QM0_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 7699 word_offset = ((mmNIC3_QM0_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 7700 mask = 1U << ((mmNIC3_QM0_CQ_CTL_STS_0 & 0x7F) >> 2); 7701 mask |= 1U << ((mmNIC3_QM0_CQ_CTL_STS_1 & 0x7F) >> 2); 7702 mask |= 1U << ((mmNIC3_QM0_CQ_CTL_STS_2 & 0x7F) >> 2); 7703 mask |= 1U << ((mmNIC3_QM0_CQ_CTL_STS_3 & 0x7F) >> 2); 7704 mask |= 1U << ((mmNIC3_QM0_CQ_CTL_STS_4 & 0x7F) >> 2); 7705 mask |= 1U << ((mmNIC3_QM0_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 7706 mask |= 1U << ((mmNIC3_QM0_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 7707 mask |= 1U << ((mmNIC3_QM0_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 7708 mask |= 1U << ((mmNIC3_QM0_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 7709 mask |= 1U << ((mmNIC3_QM0_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 7710 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 7711 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 7712 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 7713 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 7714 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 7715 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 7716 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 7717 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 7718 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 7719 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 7720 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 7721 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 7722 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 7723 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 7724 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 7725 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 7726 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 7727 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 7728 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 7729 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 7730 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 7731 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 7732 7733 WREG32(pb_addr + word_offset, ~mask); 7734 7735 pb_addr = (mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 7736 word_offset = ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_2 & 7737 PROT_BITS_OFFS) >> 7) << 2; 7738 mask = 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 7739 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 7740 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 7741 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 7742 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 7743 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 7744 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 7745 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 7746 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 7747 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 7748 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 7749 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 7750 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 7751 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 7752 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 7753 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 7754 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 7755 mask |= 1U << ((mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 7756 mask |= 1U << ((mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 7757 mask |= 1U << ((mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 7758 mask |= 1U << ((mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 7759 mask |= 1U << ((mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 7760 mask |= 1U << ((mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 7761 mask |= 1U << ((mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 7762 mask |= 1U << ((mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 7763 mask |= 1U << ((mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 7764 mask |= 1U << ((mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 7765 mask |= 1U << ((mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 7766 mask |= 1U << ((mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 7767 mask |= 1U << ((mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 7768 mask |= 1U << ((mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 7769 7770 WREG32(pb_addr + word_offset, ~mask); 7771 7772 pb_addr = (mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 7773 PROT_BITS_OFFS; 7774 word_offset = ((mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & 7775 PROT_BITS_OFFS) >> 7) << 2; 7776 mask = 1U << ((mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 7777 mask |= 1U << ((mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 7778 7779 WREG32(pb_addr + word_offset, ~mask); 7780 7781 pb_addr = (mmNIC3_QM0_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 7782 word_offset = ((mmNIC3_QM0_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 7783 mask = 1U << ((mmNIC3_QM0_CP_STS_0 & 0x7F) >> 2); 7784 mask |= 1U << ((mmNIC3_QM0_CP_STS_1 & 0x7F) >> 2); 7785 mask |= 1U << ((mmNIC3_QM0_CP_STS_2 & 0x7F) >> 2); 7786 mask |= 1U << ((mmNIC3_QM0_CP_STS_3 & 0x7F) >> 2); 7787 mask |= 1U << ((mmNIC3_QM0_CP_STS_4 & 0x7F) >> 2); 7788 mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 7789 mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 7790 mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 7791 mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 7792 mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 7793 mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 7794 mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 7795 mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 7796 mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 7797 mask |= 1U << ((mmNIC3_QM0_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 7798 mask |= 1U << ((mmNIC3_QM0_CP_BARRIER_CFG_0 & 0x7F) >> 2); 7799 mask |= 1U << ((mmNIC3_QM0_CP_BARRIER_CFG_1 & 0x7F) >> 2); 7800 mask |= 1U << ((mmNIC3_QM0_CP_BARRIER_CFG_2 & 0x7F) >> 2); 7801 7802 WREG32(pb_addr + word_offset, ~mask); 7803 7804 pb_addr = (mmNIC3_QM0_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 7805 word_offset = ((mmNIC3_QM0_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) 7806 >> 7) << 2; 7807 mask = 1U << ((mmNIC3_QM0_CP_BARRIER_CFG_3 & 0x7F) >> 2); 7808 mask |= 1U << ((mmNIC3_QM0_CP_BARRIER_CFG_4 & 0x7F) >> 2); 7809 mask |= 1U << ((mmNIC3_QM0_CP_DBG_0_0 & 0x7F) >> 2); 7810 mask |= 1U << ((mmNIC3_QM0_CP_DBG_0_1 & 0x7F) >> 2); 7811 7812 WREG32(pb_addr + word_offset, ~mask); 7813 7814 pb_addr = (mmNIC3_QM0_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 7815 word_offset = ((mmNIC3_QM0_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 7816 mask = 1U << ((mmNIC3_QM0_CP_DBG_0_2 & 0x7F) >> 2); 7817 mask |= 1U << ((mmNIC3_QM0_CP_DBG_0_3 & 0x7F) >> 2); 7818 mask |= 1U << ((mmNIC3_QM0_CP_DBG_0_4 & 0x7F) >> 2); 7819 mask |= 1U << ((mmNIC3_QM0_CP_ARUSER_31_11_0 & 0x7F) >> 2); 7820 mask |= 1U << ((mmNIC3_QM0_CP_ARUSER_31_11_1 & 0x7F) >> 2); 7821 mask |= 1U << ((mmNIC3_QM0_CP_ARUSER_31_11_2 & 0x7F) >> 2); 7822 mask |= 1U << ((mmNIC3_QM0_CP_ARUSER_31_11_3 & 0x7F) >> 2); 7823 mask |= 1U << ((mmNIC3_QM0_CP_ARUSER_31_11_4 & 0x7F) >> 2); 7824 mask |= 1U << ((mmNIC3_QM0_CP_AWUSER_31_11_0 & 0x7F) >> 2); 7825 mask |= 1U << ((mmNIC3_QM0_CP_AWUSER_31_11_1 & 0x7F) >> 2); 7826 mask |= 1U << ((mmNIC3_QM0_CP_AWUSER_31_11_2 & 0x7F) >> 2); 7827 mask |= 1U << ((mmNIC3_QM0_CP_AWUSER_31_11_3 & 0x7F) >> 2); 7828 mask |= 1U << ((mmNIC3_QM0_CP_AWUSER_31_11_4 & 0x7F) >> 2); 7829 7830 WREG32(pb_addr + word_offset, ~mask); 7831 7832 pb_addr = (mmNIC3_QM0_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 7833 word_offset = ((mmNIC3_QM0_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 7834 mask = 1U << ((mmNIC3_QM0_ARB_CFG_1 & 0x7F) >> 2); 7835 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 7836 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 7837 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 7838 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 7839 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 7840 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 7841 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 7842 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 7843 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 7844 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 7845 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 7846 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 7847 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 7848 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 7849 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 7850 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 7851 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 7852 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 7853 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 7854 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 7855 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 7856 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 7857 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 7858 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 7859 7860 WREG32(pb_addr + word_offset, ~mask); 7861 7862 pb_addr = (mmNIC3_QM0_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 7863 word_offset = ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_24 & 7864 PROT_BITS_OFFS) >> 7) << 2; 7865 mask = 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 7866 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 7867 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 7868 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 7869 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 7870 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 7871 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 7872 mask |= 1U << ((mmNIC3_QM0_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 7873 7874 WREG32(pb_addr + word_offset, ~mask); 7875 7876 pb_addr = (mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 7877 PROT_BITS_OFFS; 7878 word_offset = ((mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_23 & 7879 PROT_BITS_OFFS) >> 7) << 2; 7880 mask = 1U << ((mmNIC3_QM0_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 7881 mask |= 1U << ((mmNIC3_QM0_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 7882 mask |= 1U << ((mmNIC3_QM0_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 7883 mask |= 1U << ((mmNIC3_QM0_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 7884 mask |= 1U << ((mmNIC3_QM0_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 7885 7886 WREG32(pb_addr + word_offset, ~mask); 7887 7888 pb_addr = (mmNIC3_QM0_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 7889 word_offset = ((mmNIC3_QM0_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 7890 mask = 1U << ((mmNIC3_QM0_ARB_STATE_STS & 0x7F) >> 2); 7891 mask |= 1U << ((mmNIC3_QM0_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 7892 mask |= 1U << ((mmNIC3_QM0_ARB_MSG_STS & 0x7F) >> 2); 7893 mask |= 1U << ((mmNIC3_QM0_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 7894 mask |= 1U << ((mmNIC3_QM0_ARB_ERR_CAUSE & 0x7F) >> 2); 7895 mask |= 1U << ((mmNIC3_QM0_ARB_ERR_MSG_EN & 0x7F) >> 2); 7896 mask |= 1U << ((mmNIC3_QM0_ARB_ERR_STS_DRP & 0x7F) >> 2); 7897 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 7898 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 7899 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 7900 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 7901 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 7902 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 7903 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 7904 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 7905 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 7906 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 7907 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 7908 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 7909 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 7910 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 7911 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 7912 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 7913 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 7914 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 7915 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 7916 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 7917 7918 WREG32(pb_addr + word_offset, ~mask); 7919 7920 pb_addr = (mmNIC3_QM0_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 7921 word_offset = ((mmNIC3_QM0_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) 7922 >> 7) << 2; 7923 mask = 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 7924 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 7925 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 7926 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 7927 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 7928 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 7929 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 7930 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 7931 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 7932 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 7933 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 7934 mask |= 1U << ((mmNIC3_QM0_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 7935 mask |= 1U << ((mmNIC3_QM0_CGM_CFG & 0x7F) >> 2); 7936 mask |= 1U << ((mmNIC3_QM0_CGM_STS & 0x7F) >> 2); 7937 mask |= 1U << ((mmNIC3_QM0_CGM_CFG1 & 0x7F) >> 2); 7938 7939 WREG32(pb_addr + word_offset, ~mask); 7940 7941 pb_addr = (mmNIC3_QM0_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 7942 word_offset = ((mmNIC3_QM0_LOCAL_RANGE_BASE & PROT_BITS_OFFS) 7943 >> 7) << 2; 7944 mask = 1U << ((mmNIC3_QM0_LOCAL_RANGE_BASE & 0x7F) >> 2); 7945 mask |= 1U << ((mmNIC3_QM0_LOCAL_RANGE_SIZE & 0x7F) >> 2); 7946 mask |= 1U << ((mmNIC3_QM0_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 7947 mask |= 1U << ((mmNIC3_QM0_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 7948 mask |= 1U << ((mmNIC3_QM0_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 7949 mask |= 1U << ((mmNIC3_QM0_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 7950 mask |= 1U << ((mmNIC3_QM0_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 7951 mask |= 1U << ((mmNIC3_QM0_GLBL_AXCACHE & 0x7F) >> 2); 7952 mask |= 1U << ((mmNIC3_QM0_IND_GW_APB_CFG & 0x7F) >> 2); 7953 mask |= 1U << ((mmNIC3_QM0_IND_GW_APB_WDATA & 0x7F) >> 2); 7954 mask |= 1U << ((mmNIC3_QM0_IND_GW_APB_RDATA & 0x7F) >> 2); 7955 mask |= 1U << ((mmNIC3_QM0_IND_GW_APB_STATUS & 0x7F) >> 2); 7956 mask |= 1U << ((mmNIC3_QM0_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 7957 mask |= 1U << ((mmNIC3_QM0_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 7958 mask |= 1U << ((mmNIC3_QM0_GLBL_ERR_WDATA & 0x7F) >> 2); 7959 7960 WREG32(pb_addr + word_offset, ~mask); 7961 7962 pb_addr = (mmNIC3_QM0_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 7963 word_offset = ((mmNIC3_QM0_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) 7964 >> 7) << 2; 7965 mask = 1U << ((mmNIC3_QM0_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 7966 7967 WREG32(pb_addr + word_offset, ~mask); 7968 7969 pb_addr = (mmNIC3_QM1_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 7970 word_offset = ((mmNIC3_QM1_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 7971 mask = 1U << ((mmNIC3_QM1_GLBL_CFG0 & 0x7F) >> 2); 7972 mask |= 1U << ((mmNIC3_QM1_GLBL_CFG1 & 0x7F) >> 2); 7973 mask |= 1U << ((mmNIC3_QM1_GLBL_PROT & 0x7F) >> 2); 7974 mask |= 1U << ((mmNIC3_QM1_GLBL_ERR_CFG & 0x7F) >> 2); 7975 mask |= 1U << ((mmNIC3_QM1_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 7976 mask |= 1U << ((mmNIC3_QM1_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 7977 mask |= 1U << ((mmNIC3_QM1_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 7978 mask |= 1U << ((mmNIC3_QM1_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 7979 mask |= 1U << ((mmNIC3_QM1_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 7980 mask |= 1U << ((mmNIC3_QM1_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 7981 mask |= 1U << ((mmNIC3_QM1_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 7982 mask |= 1U << ((mmNIC3_QM1_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 7983 mask |= 1U << ((mmNIC3_QM1_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 7984 mask |= 1U << ((mmNIC3_QM1_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 7985 mask |= 1U << ((mmNIC3_QM1_GLBL_STS0 & 0x7F) >> 2); 7986 mask |= 1U << ((mmNIC3_QM1_GLBL_STS1_0 & 0x7F) >> 2); 7987 mask |= 1U << ((mmNIC3_QM1_GLBL_STS1_1 & 0x7F) >> 2); 7988 mask |= 1U << ((mmNIC3_QM1_GLBL_STS1_2 & 0x7F) >> 2); 7989 mask |= 1U << ((mmNIC3_QM1_GLBL_STS1_3 & 0x7F) >> 2); 7990 mask |= 1U << ((mmNIC3_QM1_GLBL_STS1_4 & 0x7F) >> 2); 7991 mask |= 1U << ((mmNIC3_QM1_GLBL_MSG_EN_0 & 0x7F) >> 2); 7992 mask |= 1U << ((mmNIC3_QM1_GLBL_MSG_EN_1 & 0x7F) >> 2); 7993 mask |= 1U << ((mmNIC3_QM1_GLBL_MSG_EN_2 & 0x7F) >> 2); 7994 mask |= 1U << ((mmNIC3_QM1_GLBL_MSG_EN_3 & 0x7F) >> 2); 7995 mask |= 1U << ((mmNIC3_QM1_GLBL_MSG_EN_4 & 0x7F) >> 2); 7996 mask |= 1U << ((mmNIC3_QM1_PQ_BASE_LO_0 & 0x7F) >> 2); 7997 mask |= 1U << ((mmNIC3_QM1_PQ_BASE_LO_1 & 0x7F) >> 2); 7998 mask |= 1U << ((mmNIC3_QM1_PQ_BASE_LO_2 & 0x7F) >> 2); 7999 mask |= 1U << ((mmNIC3_QM1_PQ_BASE_LO_3 & 0x7F) >> 2); 8000 8001 WREG32(pb_addr + word_offset, ~mask); 8002 8003 pb_addr = (mmNIC3_QM1_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 8004 word_offset = ((mmNIC3_QM1_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 8005 mask = 1U << ((mmNIC3_QM1_PQ_BASE_HI_0 & 0x7F) >> 2); 8006 mask |= 1U << ((mmNIC3_QM1_PQ_BASE_HI_1 & 0x7F) >> 2); 8007 mask |= 1U << ((mmNIC3_QM1_PQ_BASE_HI_2 & 0x7F) >> 2); 8008 mask |= 1U << ((mmNIC3_QM1_PQ_BASE_HI_3 & 0x7F) >> 2); 8009 mask |= 1U << ((mmNIC3_QM1_PQ_SIZE_0 & 0x7F) >> 2); 8010 mask |= 1U << ((mmNIC3_QM1_PQ_SIZE_1 & 0x7F) >> 2); 8011 mask |= 1U << ((mmNIC3_QM1_PQ_SIZE_2 & 0x7F) >> 2); 8012 mask |= 1U << ((mmNIC3_QM1_PQ_SIZE_3 & 0x7F) >> 2); 8013 mask |= 1U << ((mmNIC3_QM1_PQ_PI_0 & 0x7F) >> 2); 8014 mask |= 1U << ((mmNIC3_QM1_PQ_PI_1 & 0x7F) >> 2); 8015 mask |= 1U << ((mmNIC3_QM1_PQ_PI_2 & 0x7F) >> 2); 8016 mask |= 1U << ((mmNIC3_QM1_PQ_PI_3 & 0x7F) >> 2); 8017 mask |= 1U << ((mmNIC3_QM1_PQ_CI_0 & 0x7F) >> 2); 8018 mask |= 1U << ((mmNIC3_QM1_PQ_CI_1 & 0x7F) >> 2); 8019 mask |= 1U << ((mmNIC3_QM1_PQ_CI_2 & 0x7F) >> 2); 8020 mask |= 1U << ((mmNIC3_QM1_PQ_CI_3 & 0x7F) >> 2); 8021 mask |= 1U << ((mmNIC3_QM1_PQ_CFG0_0 & 0x7F) >> 2); 8022 mask |= 1U << ((mmNIC3_QM1_PQ_CFG0_1 & 0x7F) >> 2); 8023 mask |= 1U << ((mmNIC3_QM1_PQ_CFG0_2 & 0x7F) >> 2); 8024 mask |= 1U << ((mmNIC3_QM1_PQ_CFG0_3 & 0x7F) >> 2); 8025 mask |= 1U << ((mmNIC3_QM1_PQ_CFG1_0 & 0x7F) >> 2); 8026 mask |= 1U << ((mmNIC3_QM1_PQ_CFG1_1 & 0x7F) >> 2); 8027 mask |= 1U << ((mmNIC3_QM1_PQ_CFG1_2 & 0x7F) >> 2); 8028 mask |= 1U << ((mmNIC3_QM1_PQ_CFG1_3 & 0x7F) >> 2); 8029 mask |= 1U << ((mmNIC3_QM1_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 8030 mask |= 1U << ((mmNIC3_QM1_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 8031 mask |= 1U << ((mmNIC3_QM1_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 8032 mask |= 1U << ((mmNIC3_QM1_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 8033 mask |= 1U << ((mmNIC3_QM1_PQ_STS0_0 & 0x7F) >> 2); 8034 mask |= 1U << ((mmNIC3_QM1_PQ_STS0_1 & 0x7F) >> 2); 8035 mask |= 1U << ((mmNIC3_QM1_PQ_STS0_2 & 0x7F) >> 2); 8036 mask |= 1U << ((mmNIC3_QM1_PQ_STS0_3 & 0x7F) >> 2); 8037 8038 WREG32(pb_addr + word_offset, ~mask); 8039 8040 pb_addr = (mmNIC3_QM1_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 8041 word_offset = ((mmNIC3_QM1_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 8042 mask = 1U << ((mmNIC3_QM1_PQ_STS1_0 & 0x7F) >> 2); 8043 mask |= 1U << ((mmNIC3_QM1_PQ_STS1_1 & 0x7F) >> 2); 8044 mask |= 1U << ((mmNIC3_QM1_PQ_STS1_2 & 0x7F) >> 2); 8045 mask |= 1U << ((mmNIC3_QM1_PQ_STS1_3 & 0x7F) >> 2); 8046 mask |= 1U << ((mmNIC3_QM1_CQ_STS0_0 & 0x7F) >> 2); 8047 mask |= 1U << ((mmNIC3_QM1_CQ_STS0_1 & 0x7F) >> 2); 8048 mask |= 1U << ((mmNIC3_QM1_CQ_STS0_2 & 0x7F) >> 2); 8049 mask |= 1U << ((mmNIC3_QM1_CQ_STS0_3 & 0x7F) >> 2); 8050 mask |= 1U << ((mmNIC3_QM1_CQ_STS1_0 & 0x7F) >> 2); 8051 mask |= 1U << ((mmNIC3_QM1_CQ_STS1_1 & 0x7F) >> 2); 8052 mask |= 1U << ((mmNIC3_QM1_CQ_STS1_2 & 0x7F) >> 2); 8053 mask |= 1U << ((mmNIC3_QM1_CQ_STS1_3 & 0x7F) >> 2); 8054 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_0 & 0x7F) >> 2); 8055 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_0 & 0x7F) >> 2); 8056 mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_0 & 0x7F) >> 2); 8057 8058 WREG32(pb_addr + word_offset, ~mask); 8059 8060 pb_addr = (mmNIC3_QM1_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 8061 word_offset = ((mmNIC3_QM1_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 8062 mask = 1U << ((mmNIC3_QM1_CQ_CTL_0 & 0x7F) >> 2); 8063 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_1 & 0x7F) >> 2); 8064 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_1 & 0x7F) >> 2); 8065 mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_1 & 0x7F) >> 2); 8066 mask |= 1U << ((mmNIC3_QM1_CQ_CTL_1 & 0x7F) >> 2); 8067 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_2 & 0x7F) >> 2); 8068 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_2 & 0x7F) >> 2); 8069 mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_2 & 0x7F) >> 2); 8070 mask |= 1U << ((mmNIC3_QM1_CQ_CTL_2 & 0x7F) >> 2); 8071 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_3 & 0x7F) >> 2); 8072 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_3 & 0x7F) >> 2); 8073 mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_3 & 0x7F) >> 2); 8074 mask |= 1U << ((mmNIC3_QM1_CQ_CTL_3 & 0x7F) >> 2); 8075 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 8076 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 8077 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 8078 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 8079 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 8080 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 8081 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 8082 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 8083 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 8084 mask |= 1U << ((mmNIC3_QM1_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 8085 mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_STS_0 & 0x7F) >> 2); 8086 mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_STS_1 & 0x7F) >> 2); 8087 mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_STS_2 & 0x7F) >> 2); 8088 mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_STS_3 & 0x7F) >> 2); 8089 mask |= 1U << ((mmNIC3_QM1_CQ_TSIZE_STS_4 & 0x7F) >> 2); 8090 8091 WREG32(pb_addr + word_offset, ~mask); 8092 8093 pb_addr = (mmNIC3_QM1_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 8094 word_offset = ((mmNIC3_QM1_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 8095 mask = 1U << ((mmNIC3_QM1_CQ_CTL_STS_0 & 0x7F) >> 2); 8096 mask |= 1U << ((mmNIC3_QM1_CQ_CTL_STS_1 & 0x7F) >> 2); 8097 mask |= 1U << ((mmNIC3_QM1_CQ_CTL_STS_2 & 0x7F) >> 2); 8098 mask |= 1U << ((mmNIC3_QM1_CQ_CTL_STS_3 & 0x7F) >> 2); 8099 mask |= 1U << ((mmNIC3_QM1_CQ_CTL_STS_4 & 0x7F) >> 2); 8100 mask |= 1U << ((mmNIC3_QM1_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 8101 mask |= 1U << ((mmNIC3_QM1_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 8102 mask |= 1U << ((mmNIC3_QM1_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 8103 mask |= 1U << ((mmNIC3_QM1_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 8104 mask |= 1U << ((mmNIC3_QM1_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 8105 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 8106 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 8107 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 8108 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 8109 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 8110 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 8111 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 8112 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 8113 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 8114 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 8115 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 8116 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 8117 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 8118 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 8119 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 8120 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 8121 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 8122 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 8123 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 8124 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 8125 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 8126 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 8127 8128 WREG32(pb_addr + word_offset, ~mask); 8129 8130 pb_addr = (mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 8131 word_offset = ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_2 & 8132 PROT_BITS_OFFS) >> 7) << 2; 8133 mask = 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 8134 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 8135 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 8136 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 8137 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 8138 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 8139 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 8140 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 8141 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 8142 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 8143 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 8144 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 8145 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 8146 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 8147 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 8148 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 8149 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 8150 mask |= 1U << ((mmNIC3_QM1_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 8151 mask |= 1U << ((mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 8152 mask |= 1U << ((mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 8153 mask |= 1U << ((mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 8154 mask |= 1U << ((mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 8155 mask |= 1U << ((mmNIC3_QM1_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 8156 mask |= 1U << ((mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 8157 mask |= 1U << ((mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 8158 mask |= 1U << ((mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 8159 mask |= 1U << ((mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 8160 mask |= 1U << ((mmNIC3_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 8161 mask |= 1U << ((mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 8162 mask |= 1U << ((mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 8163 mask |= 1U << ((mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 8164 8165 WREG32(pb_addr + word_offset, ~mask); 8166 8167 pb_addr = (mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 8168 PROT_BITS_OFFS; 8169 word_offset = ((mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & 8170 PROT_BITS_OFFS) >> 7) << 2; 8171 mask = 1U << ((mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 8172 mask |= 1U << ((mmNIC3_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 8173 8174 WREG32(pb_addr + word_offset, ~mask); 8175 8176 pb_addr = (mmNIC3_QM1_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 8177 word_offset = ((mmNIC3_QM1_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 8178 mask = 1U << ((mmNIC3_QM1_CP_STS_0 & 0x7F) >> 2); 8179 mask |= 1U << ((mmNIC3_QM1_CP_STS_1 & 0x7F) >> 2); 8180 mask |= 1U << ((mmNIC3_QM1_CP_STS_2 & 0x7F) >> 2); 8181 mask |= 1U << ((mmNIC3_QM1_CP_STS_3 & 0x7F) >> 2); 8182 mask |= 1U << ((mmNIC3_QM1_CP_STS_4 & 0x7F) >> 2); 8183 mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 8184 mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 8185 mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 8186 mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 8187 mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 8188 mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 8189 mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 8190 mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 8191 mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 8192 mask |= 1U << ((mmNIC3_QM1_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 8193 mask |= 1U << ((mmNIC3_QM1_CP_BARRIER_CFG_0 & 0x7F) >> 2); 8194 mask |= 1U << ((mmNIC3_QM1_CP_BARRIER_CFG_1 & 0x7F) >> 2); 8195 mask |= 1U << ((mmNIC3_QM1_CP_BARRIER_CFG_2 & 0x7F) >> 2); 8196 8197 WREG32(pb_addr + word_offset, ~mask); 8198 8199 pb_addr = (mmNIC3_QM1_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 8200 word_offset = ((mmNIC3_QM1_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) 8201 >> 7) << 2; 8202 mask = 1U << ((mmNIC3_QM1_CP_BARRIER_CFG_3 & 0x7F) >> 2); 8203 mask |= 1U << ((mmNIC3_QM1_CP_BARRIER_CFG_4 & 0x7F) >> 2); 8204 mask |= 1U << ((mmNIC3_QM1_CP_DBG_0_0 & 0x7F) >> 2); 8205 mask |= 1U << ((mmNIC3_QM1_CP_DBG_0_1 & 0x7F) >> 2); 8206 8207 WREG32(pb_addr + word_offset, ~mask); 8208 8209 pb_addr = (mmNIC3_QM1_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 8210 word_offset = ((mmNIC3_QM1_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 8211 mask = 1U << ((mmNIC3_QM1_CP_DBG_0_2 & 0x7F) >> 2); 8212 mask |= 1U << ((mmNIC3_QM1_CP_DBG_0_3 & 0x7F) >> 2); 8213 mask |= 1U << ((mmNIC3_QM1_CP_DBG_0_4 & 0x7F) >> 2); 8214 mask |= 1U << ((mmNIC3_QM1_CP_ARUSER_31_11_0 & 0x7F) >> 2); 8215 mask |= 1U << ((mmNIC3_QM1_CP_ARUSER_31_11_1 & 0x7F) >> 2); 8216 mask |= 1U << ((mmNIC3_QM1_CP_ARUSER_31_11_2 & 0x7F) >> 2); 8217 mask |= 1U << ((mmNIC3_QM1_CP_ARUSER_31_11_3 & 0x7F) >> 2); 8218 mask |= 1U << ((mmNIC3_QM1_CP_ARUSER_31_11_4 & 0x7F) >> 2); 8219 mask |= 1U << ((mmNIC3_QM1_CP_AWUSER_31_11_0 & 0x7F) >> 2); 8220 mask |= 1U << ((mmNIC3_QM1_CP_AWUSER_31_11_1 & 0x7F) >> 2); 8221 mask |= 1U << ((mmNIC3_QM1_CP_AWUSER_31_11_2 & 0x7F) >> 2); 8222 mask |= 1U << ((mmNIC3_QM1_CP_AWUSER_31_11_3 & 0x7F) >> 2); 8223 mask |= 1U << ((mmNIC3_QM1_CP_AWUSER_31_11_4 & 0x7F) >> 2); 8224 8225 WREG32(pb_addr + word_offset, ~mask); 8226 8227 pb_addr = (mmNIC3_QM1_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 8228 word_offset = ((mmNIC3_QM1_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 8229 mask = 1U << ((mmNIC3_QM1_ARB_CFG_1 & 0x7F) >> 2); 8230 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 8231 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 8232 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 8233 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 8234 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 8235 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 8236 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 8237 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 8238 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 8239 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 8240 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 8241 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 8242 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 8243 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 8244 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 8245 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 8246 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 8247 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 8248 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 8249 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 8250 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 8251 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 8252 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 8253 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 8254 8255 WREG32(pb_addr + word_offset, ~mask); 8256 8257 pb_addr = (mmNIC3_QM1_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 8258 word_offset = ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_24 & 8259 PROT_BITS_OFFS) >> 7) << 2; 8260 mask = 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 8261 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 8262 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 8263 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 8264 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 8265 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 8266 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 8267 mask |= 1U << ((mmNIC3_QM1_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 8268 8269 WREG32(pb_addr + word_offset, ~mask); 8270 8271 pb_addr = (mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 8272 PROT_BITS_OFFS; 8273 word_offset = ((mmNIC3_QM1_ARB_MST_CHOISE_PUSH_OFST_23 & 8274 PROT_BITS_OFFS) >> 7) << 2; 8275 mask = 1U << ((mmNIC3_QM1_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 8276 mask |= 1U << ((mmNIC3_QM1_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 8277 mask |= 1U << ((mmNIC3_QM1_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 8278 mask |= 1U << ((mmNIC3_QM1_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 8279 mask |= 1U << ((mmNIC3_QM1_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 8280 8281 WREG32(pb_addr + word_offset, ~mask); 8282 8283 pb_addr = (mmNIC3_QM1_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 8284 word_offset = ((mmNIC3_QM1_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 8285 mask = 1U << ((mmNIC3_QM1_ARB_STATE_STS & 0x7F) >> 2); 8286 mask |= 1U << ((mmNIC3_QM1_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 8287 mask |= 1U << ((mmNIC3_QM1_ARB_MSG_STS & 0x7F) >> 2); 8288 mask |= 1U << ((mmNIC3_QM1_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 8289 mask |= 1U << ((mmNIC3_QM1_ARB_ERR_CAUSE & 0x7F) >> 2); 8290 mask |= 1U << ((mmNIC3_QM1_ARB_ERR_MSG_EN & 0x7F) >> 2); 8291 mask |= 1U << ((mmNIC3_QM1_ARB_ERR_STS_DRP & 0x7F) >> 2); 8292 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 8293 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 8294 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 8295 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 8296 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 8297 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 8298 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 8299 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 8300 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 8301 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 8302 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 8303 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 8304 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 8305 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 8306 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 8307 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 8308 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 8309 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 8310 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 8311 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 8312 8313 WREG32(pb_addr + word_offset, ~mask); 8314 8315 pb_addr = (mmNIC3_QM1_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 8316 word_offset = ((mmNIC3_QM1_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) 8317 >> 7) << 2; 8318 mask = 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 8319 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 8320 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 8321 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 8322 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 8323 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 8324 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 8325 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 8326 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 8327 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 8328 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 8329 mask |= 1U << ((mmNIC3_QM1_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 8330 mask |= 1U << ((mmNIC3_QM1_CGM_CFG & 0x7F) >> 2); 8331 mask |= 1U << ((mmNIC3_QM1_CGM_STS & 0x7F) >> 2); 8332 mask |= 1U << ((mmNIC3_QM1_CGM_CFG1 & 0x7F) >> 2); 8333 8334 WREG32(pb_addr + word_offset, ~mask); 8335 8336 pb_addr = (mmNIC3_QM1_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 8337 word_offset = ((mmNIC3_QM1_LOCAL_RANGE_BASE & PROT_BITS_OFFS) 8338 >> 7) << 2; 8339 mask = 1U << ((mmNIC3_QM1_LOCAL_RANGE_BASE & 0x7F) >> 2); 8340 mask |= 1U << ((mmNIC3_QM1_LOCAL_RANGE_SIZE & 0x7F) >> 2); 8341 mask |= 1U << ((mmNIC3_QM1_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 8342 mask |= 1U << ((mmNIC3_QM1_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 8343 mask |= 1U << ((mmNIC3_QM1_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 8344 mask |= 1U << ((mmNIC3_QM1_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 8345 mask |= 1U << ((mmNIC3_QM1_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 8346 mask |= 1U << ((mmNIC3_QM1_GLBL_AXCACHE & 0x7F) >> 2); 8347 mask |= 1U << ((mmNIC3_QM1_IND_GW_APB_CFG & 0x7F) >> 2); 8348 mask |= 1U << ((mmNIC3_QM1_IND_GW_APB_WDATA & 0x7F) >> 2); 8349 mask |= 1U << ((mmNIC3_QM1_IND_GW_APB_RDATA & 0x7F) >> 2); 8350 mask |= 1U << ((mmNIC3_QM1_IND_GW_APB_STATUS & 0x7F) >> 2); 8351 mask |= 1U << ((mmNIC3_QM1_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 8352 mask |= 1U << ((mmNIC3_QM1_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 8353 mask |= 1U << ((mmNIC3_QM1_GLBL_ERR_WDATA & 0x7F) >> 2); 8354 8355 WREG32(pb_addr + word_offset, ~mask); 8356 8357 pb_addr = (mmNIC3_QM1_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 8358 word_offset = ((mmNIC3_QM1_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) 8359 >> 7) << 2; 8360 mask = 1U << ((mmNIC3_QM1_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 8361 8362 WREG32(pb_addr + word_offset, ~mask); 8363 8364 WREG32(mmNIC4_QM0_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 8365 WREG32(mmNIC4_QM1_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 8366 8367 pb_addr = (mmNIC4_QM0_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 8368 word_offset = ((mmNIC4_QM0_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 8369 mask = 1U << ((mmNIC4_QM0_GLBL_CFG0 & 0x7F) >> 2); 8370 mask |= 1U << ((mmNIC4_QM0_GLBL_CFG1 & 0x7F) >> 2); 8371 mask |= 1U << ((mmNIC4_QM0_GLBL_PROT & 0x7F) >> 2); 8372 mask |= 1U << ((mmNIC4_QM0_GLBL_ERR_CFG & 0x7F) >> 2); 8373 mask |= 1U << ((mmNIC4_QM0_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 8374 mask |= 1U << ((mmNIC4_QM0_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 8375 mask |= 1U << ((mmNIC4_QM0_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 8376 mask |= 1U << ((mmNIC4_QM0_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 8377 mask |= 1U << ((mmNIC4_QM0_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 8378 mask |= 1U << ((mmNIC4_QM0_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 8379 mask |= 1U << ((mmNIC4_QM0_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 8380 mask |= 1U << ((mmNIC4_QM0_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 8381 mask |= 1U << ((mmNIC4_QM0_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 8382 mask |= 1U << ((mmNIC4_QM0_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 8383 mask |= 1U << ((mmNIC4_QM0_GLBL_STS0 & 0x7F) >> 2); 8384 mask |= 1U << ((mmNIC4_QM0_GLBL_STS1_0 & 0x7F) >> 2); 8385 mask |= 1U << ((mmNIC4_QM0_GLBL_STS1_1 & 0x7F) >> 2); 8386 mask |= 1U << ((mmNIC4_QM0_GLBL_STS1_2 & 0x7F) >> 2); 8387 mask |= 1U << ((mmNIC4_QM0_GLBL_STS1_3 & 0x7F) >> 2); 8388 mask |= 1U << ((mmNIC4_QM0_GLBL_STS1_4 & 0x7F) >> 2); 8389 mask |= 1U << ((mmNIC4_QM0_GLBL_MSG_EN_0 & 0x7F) >> 2); 8390 mask |= 1U << ((mmNIC4_QM0_GLBL_MSG_EN_1 & 0x7F) >> 2); 8391 mask |= 1U << ((mmNIC4_QM0_GLBL_MSG_EN_2 & 0x7F) >> 2); 8392 mask |= 1U << ((mmNIC4_QM0_GLBL_MSG_EN_3 & 0x7F) >> 2); 8393 mask |= 1U << ((mmNIC4_QM0_GLBL_MSG_EN_4 & 0x7F) >> 2); 8394 mask |= 1U << ((mmNIC4_QM0_PQ_BASE_LO_0 & 0x7F) >> 2); 8395 mask |= 1U << ((mmNIC4_QM0_PQ_BASE_LO_1 & 0x7F) >> 2); 8396 mask |= 1U << ((mmNIC4_QM0_PQ_BASE_LO_2 & 0x7F) >> 2); 8397 mask |= 1U << ((mmNIC4_QM0_PQ_BASE_LO_3 & 0x7F) >> 2); 8398 8399 WREG32(pb_addr + word_offset, ~mask); 8400 8401 pb_addr = (mmNIC4_QM0_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 8402 word_offset = ((mmNIC4_QM0_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 8403 mask = 1U << ((mmNIC4_QM0_PQ_BASE_HI_0 & 0x7F) >> 2); 8404 mask |= 1U << ((mmNIC4_QM0_PQ_BASE_HI_1 & 0x7F) >> 2); 8405 mask |= 1U << ((mmNIC4_QM0_PQ_BASE_HI_2 & 0x7F) >> 2); 8406 mask |= 1U << ((mmNIC4_QM0_PQ_BASE_HI_3 & 0x7F) >> 2); 8407 mask |= 1U << ((mmNIC4_QM0_PQ_SIZE_0 & 0x7F) >> 2); 8408 mask |= 1U << ((mmNIC4_QM0_PQ_SIZE_1 & 0x7F) >> 2); 8409 mask |= 1U << ((mmNIC4_QM0_PQ_SIZE_2 & 0x7F) >> 2); 8410 mask |= 1U << ((mmNIC4_QM0_PQ_SIZE_3 & 0x7F) >> 2); 8411 mask |= 1U << ((mmNIC4_QM0_PQ_PI_0 & 0x7F) >> 2); 8412 mask |= 1U << ((mmNIC4_QM0_PQ_PI_1 & 0x7F) >> 2); 8413 mask |= 1U << ((mmNIC4_QM0_PQ_PI_2 & 0x7F) >> 2); 8414 mask |= 1U << ((mmNIC4_QM0_PQ_PI_3 & 0x7F) >> 2); 8415 mask |= 1U << ((mmNIC4_QM0_PQ_CI_0 & 0x7F) >> 2); 8416 mask |= 1U << ((mmNIC4_QM0_PQ_CI_1 & 0x7F) >> 2); 8417 mask |= 1U << ((mmNIC4_QM0_PQ_CI_2 & 0x7F) >> 2); 8418 mask |= 1U << ((mmNIC4_QM0_PQ_CI_3 & 0x7F) >> 2); 8419 mask |= 1U << ((mmNIC4_QM0_PQ_CFG0_0 & 0x7F) >> 2); 8420 mask |= 1U << ((mmNIC4_QM0_PQ_CFG0_1 & 0x7F) >> 2); 8421 mask |= 1U << ((mmNIC4_QM0_PQ_CFG0_2 & 0x7F) >> 2); 8422 mask |= 1U << ((mmNIC4_QM0_PQ_CFG0_3 & 0x7F) >> 2); 8423 mask |= 1U << ((mmNIC4_QM0_PQ_CFG1_0 & 0x7F) >> 2); 8424 mask |= 1U << ((mmNIC4_QM0_PQ_CFG1_1 & 0x7F) >> 2); 8425 mask |= 1U << ((mmNIC4_QM0_PQ_CFG1_2 & 0x7F) >> 2); 8426 mask |= 1U << ((mmNIC4_QM0_PQ_CFG1_3 & 0x7F) >> 2); 8427 mask |= 1U << ((mmNIC4_QM0_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 8428 mask |= 1U << ((mmNIC4_QM0_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 8429 mask |= 1U << ((mmNIC4_QM0_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 8430 mask |= 1U << ((mmNIC4_QM0_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 8431 mask |= 1U << ((mmNIC4_QM0_PQ_STS0_0 & 0x7F) >> 2); 8432 mask |= 1U << ((mmNIC4_QM0_PQ_STS0_1 & 0x7F) >> 2); 8433 mask |= 1U << ((mmNIC4_QM0_PQ_STS0_2 & 0x7F) >> 2); 8434 mask |= 1U << ((mmNIC4_QM0_PQ_STS0_3 & 0x7F) >> 2); 8435 8436 WREG32(pb_addr + word_offset, ~mask); 8437 8438 pb_addr = (mmNIC4_QM0_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 8439 word_offset = ((mmNIC4_QM0_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 8440 mask = 1U << ((mmNIC4_QM0_PQ_STS1_0 & 0x7F) >> 2); 8441 mask |= 1U << ((mmNIC4_QM0_PQ_STS1_1 & 0x7F) >> 2); 8442 mask |= 1U << ((mmNIC4_QM0_PQ_STS1_2 & 0x7F) >> 2); 8443 mask |= 1U << ((mmNIC4_QM0_PQ_STS1_3 & 0x7F) >> 2); 8444 mask |= 1U << ((mmNIC4_QM0_CQ_STS0_0 & 0x7F) >> 2); 8445 mask |= 1U << ((mmNIC4_QM0_CQ_STS0_1 & 0x7F) >> 2); 8446 mask |= 1U << ((mmNIC4_QM0_CQ_STS0_2 & 0x7F) >> 2); 8447 mask |= 1U << ((mmNIC4_QM0_CQ_STS0_3 & 0x7F) >> 2); 8448 mask |= 1U << ((mmNIC4_QM0_CQ_STS1_0 & 0x7F) >> 2); 8449 mask |= 1U << ((mmNIC4_QM0_CQ_STS1_1 & 0x7F) >> 2); 8450 mask |= 1U << ((mmNIC4_QM0_CQ_STS1_2 & 0x7F) >> 2); 8451 mask |= 1U << ((mmNIC4_QM0_CQ_STS1_3 & 0x7F) >> 2); 8452 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_0 & 0x7F) >> 2); 8453 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_0 & 0x7F) >> 2); 8454 mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_0 & 0x7F) >> 2); 8455 8456 WREG32(pb_addr + word_offset, ~mask); 8457 8458 pb_addr = (mmNIC4_QM0_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 8459 word_offset = ((mmNIC4_QM0_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 8460 mask = 1U << ((mmNIC4_QM0_CQ_CTL_0 & 0x7F) >> 2); 8461 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_1 & 0x7F) >> 2); 8462 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_1 & 0x7F) >> 2); 8463 mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_1 & 0x7F) >> 2); 8464 mask |= 1U << ((mmNIC4_QM0_CQ_CTL_1 & 0x7F) >> 2); 8465 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_2 & 0x7F) >> 2); 8466 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_2 & 0x7F) >> 2); 8467 mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_2 & 0x7F) >> 2); 8468 mask |= 1U << ((mmNIC4_QM0_CQ_CTL_2 & 0x7F) >> 2); 8469 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_3 & 0x7F) >> 2); 8470 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_3 & 0x7F) >> 2); 8471 mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_3 & 0x7F) >> 2); 8472 mask |= 1U << ((mmNIC4_QM0_CQ_CTL_3 & 0x7F) >> 2); 8473 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 8474 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 8475 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 8476 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 8477 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 8478 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 8479 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 8480 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 8481 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 8482 mask |= 1U << ((mmNIC4_QM0_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 8483 mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_STS_0 & 0x7F) >> 2); 8484 mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_STS_1 & 0x7F) >> 2); 8485 mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_STS_2 & 0x7F) >> 2); 8486 mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_STS_3 & 0x7F) >> 2); 8487 mask |= 1U << ((mmNIC4_QM0_CQ_TSIZE_STS_4 & 0x7F) >> 2); 8488 8489 WREG32(pb_addr + word_offset, ~mask); 8490 8491 pb_addr = (mmNIC4_QM0_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 8492 word_offset = ((mmNIC4_QM0_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 8493 mask = 1U << ((mmNIC4_QM0_CQ_CTL_STS_0 & 0x7F) >> 2); 8494 mask |= 1U << ((mmNIC4_QM0_CQ_CTL_STS_1 & 0x7F) >> 2); 8495 mask |= 1U << ((mmNIC4_QM0_CQ_CTL_STS_2 & 0x7F) >> 2); 8496 mask |= 1U << ((mmNIC4_QM0_CQ_CTL_STS_3 & 0x7F) >> 2); 8497 mask |= 1U << ((mmNIC4_QM0_CQ_CTL_STS_4 & 0x7F) >> 2); 8498 mask |= 1U << ((mmNIC4_QM0_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 8499 mask |= 1U << ((mmNIC4_QM0_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 8500 mask |= 1U << ((mmNIC4_QM0_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 8501 mask |= 1U << ((mmNIC4_QM0_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 8502 mask |= 1U << ((mmNIC4_QM0_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 8503 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 8504 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 8505 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 8506 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 8507 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 8508 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 8509 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 8510 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 8511 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 8512 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 8513 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 8514 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 8515 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 8516 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 8517 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 8518 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 8519 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 8520 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 8521 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 8522 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 8523 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 8524 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 8525 8526 WREG32(pb_addr + word_offset, ~mask); 8527 8528 pb_addr = (mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 8529 word_offset = ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_2 & 8530 PROT_BITS_OFFS) >> 7) << 2; 8531 mask = 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 8532 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 8533 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 8534 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 8535 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 8536 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 8537 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 8538 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 8539 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 8540 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 8541 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 8542 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 8543 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 8544 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 8545 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 8546 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 8547 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 8548 mask |= 1U << ((mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 8549 mask |= 1U << ((mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 8550 mask |= 1U << ((mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 8551 mask |= 1U << ((mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 8552 mask |= 1U << ((mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 8553 mask |= 1U << ((mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 8554 mask |= 1U << ((mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 8555 mask |= 1U << ((mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 8556 mask |= 1U << ((mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 8557 mask |= 1U << ((mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 8558 mask |= 1U << ((mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 8559 mask |= 1U << ((mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 8560 mask |= 1U << ((mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 8561 mask |= 1U << ((mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 8562 8563 WREG32(pb_addr + word_offset, ~mask); 8564 8565 pb_addr = (mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 8566 PROT_BITS_OFFS; 8567 word_offset = ((mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & 8568 PROT_BITS_OFFS) >> 7) << 2; 8569 mask = 1U << ((mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 8570 mask |= 1U << ((mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 8571 8572 WREG32(pb_addr + word_offset, ~mask); 8573 8574 pb_addr = (mmNIC4_QM0_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 8575 word_offset = ((mmNIC4_QM0_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 8576 mask = 1U << ((mmNIC4_QM0_CP_STS_0 & 0x7F) >> 2); 8577 mask |= 1U << ((mmNIC4_QM0_CP_STS_1 & 0x7F) >> 2); 8578 mask |= 1U << ((mmNIC4_QM0_CP_STS_2 & 0x7F) >> 2); 8579 mask |= 1U << ((mmNIC4_QM0_CP_STS_3 & 0x7F) >> 2); 8580 mask |= 1U << ((mmNIC4_QM0_CP_STS_4 & 0x7F) >> 2); 8581 mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 8582 mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 8583 mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 8584 mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 8585 mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 8586 mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 8587 mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 8588 mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 8589 mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 8590 mask |= 1U << ((mmNIC4_QM0_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 8591 mask |= 1U << ((mmNIC4_QM0_CP_BARRIER_CFG_0 & 0x7F) >> 2); 8592 mask |= 1U << ((mmNIC4_QM0_CP_BARRIER_CFG_1 & 0x7F) >> 2); 8593 mask |= 1U << ((mmNIC4_QM0_CP_BARRIER_CFG_2 & 0x7F) >> 2); 8594 8595 WREG32(pb_addr + word_offset, ~mask); 8596 8597 pb_addr = (mmNIC4_QM0_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 8598 word_offset = ((mmNIC4_QM0_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) 8599 >> 7) << 2; 8600 mask = 1U << ((mmNIC4_QM0_CP_BARRIER_CFG_3 & 0x7F) >> 2); 8601 mask |= 1U << ((mmNIC4_QM0_CP_BARRIER_CFG_4 & 0x7F) >> 2); 8602 mask |= 1U << ((mmNIC4_QM0_CP_DBG_0_0 & 0x7F) >> 2); 8603 mask |= 1U << ((mmNIC4_QM0_CP_DBG_0_1 & 0x7F) >> 2); 8604 8605 WREG32(pb_addr + word_offset, ~mask); 8606 8607 pb_addr = (mmNIC4_QM0_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 8608 word_offset = ((mmNIC4_QM0_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 8609 mask = 1U << ((mmNIC4_QM0_CP_DBG_0_2 & 0x7F) >> 2); 8610 mask |= 1U << ((mmNIC4_QM0_CP_DBG_0_3 & 0x7F) >> 2); 8611 mask |= 1U << ((mmNIC4_QM0_CP_DBG_0_4 & 0x7F) >> 2); 8612 mask |= 1U << ((mmNIC4_QM0_CP_ARUSER_31_11_0 & 0x7F) >> 2); 8613 mask |= 1U << ((mmNIC4_QM0_CP_ARUSER_31_11_1 & 0x7F) >> 2); 8614 mask |= 1U << ((mmNIC4_QM0_CP_ARUSER_31_11_2 & 0x7F) >> 2); 8615 mask |= 1U << ((mmNIC4_QM0_CP_ARUSER_31_11_3 & 0x7F) >> 2); 8616 mask |= 1U << ((mmNIC4_QM0_CP_ARUSER_31_11_4 & 0x7F) >> 2); 8617 mask |= 1U << ((mmNIC4_QM0_CP_AWUSER_31_11_0 & 0x7F) >> 2); 8618 mask |= 1U << ((mmNIC4_QM0_CP_AWUSER_31_11_1 & 0x7F) >> 2); 8619 mask |= 1U << ((mmNIC4_QM0_CP_AWUSER_31_11_2 & 0x7F) >> 2); 8620 mask |= 1U << ((mmNIC4_QM0_CP_AWUSER_31_11_3 & 0x7F) >> 2); 8621 mask |= 1U << ((mmNIC4_QM0_CP_AWUSER_31_11_4 & 0x7F) >> 2); 8622 8623 WREG32(pb_addr + word_offset, ~mask); 8624 8625 pb_addr = (mmNIC4_QM0_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 8626 word_offset = ((mmNIC4_QM0_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 8627 mask = 1U << ((mmNIC4_QM0_ARB_CFG_1 & 0x7F) >> 2); 8628 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 8629 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 8630 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 8631 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 8632 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 8633 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 8634 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 8635 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 8636 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 8637 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 8638 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 8639 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 8640 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 8641 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 8642 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 8643 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 8644 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 8645 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 8646 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 8647 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 8648 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 8649 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 8650 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 8651 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 8652 8653 WREG32(pb_addr + word_offset, ~mask); 8654 8655 pb_addr = (mmNIC4_QM0_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 8656 word_offset = ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_24 & 8657 PROT_BITS_OFFS) >> 7) << 2; 8658 mask = 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 8659 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 8660 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 8661 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 8662 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 8663 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 8664 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 8665 mask |= 1U << ((mmNIC4_QM0_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 8666 8667 WREG32(pb_addr + word_offset, ~mask); 8668 8669 pb_addr = (mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 8670 PROT_BITS_OFFS; 8671 word_offset = ((mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_23 & 8672 PROT_BITS_OFFS) >> 7) << 2; 8673 mask = 1U << ((mmNIC4_QM0_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 8674 mask |= 1U << ((mmNIC4_QM0_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 8675 mask |= 1U << ((mmNIC4_QM0_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 8676 mask |= 1U << ((mmNIC4_QM0_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 8677 mask |= 1U << ((mmNIC4_QM0_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 8678 8679 WREG32(pb_addr + word_offset, ~mask); 8680 8681 pb_addr = (mmNIC4_QM0_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 8682 word_offset = ((mmNIC4_QM0_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 8683 mask = 1U << ((mmNIC4_QM0_ARB_STATE_STS & 0x7F) >> 2); 8684 mask |= 1U << ((mmNIC4_QM0_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 8685 mask |= 1U << ((mmNIC4_QM0_ARB_MSG_STS & 0x7F) >> 2); 8686 mask |= 1U << ((mmNIC4_QM0_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 8687 mask |= 1U << ((mmNIC4_QM0_ARB_ERR_CAUSE & 0x7F) >> 2); 8688 mask |= 1U << ((mmNIC4_QM0_ARB_ERR_MSG_EN & 0x7F) >> 2); 8689 mask |= 1U << ((mmNIC4_QM0_ARB_ERR_STS_DRP & 0x7F) >> 2); 8690 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 8691 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 8692 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 8693 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 8694 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 8695 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 8696 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 8697 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 8698 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 8699 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 8700 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 8701 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 8702 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 8703 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 8704 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 8705 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 8706 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 8707 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 8708 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 8709 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 8710 8711 WREG32(pb_addr + word_offset, ~mask); 8712 8713 pb_addr = (mmNIC4_QM0_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 8714 word_offset = ((mmNIC4_QM0_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) 8715 >> 7) << 2; 8716 mask = 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 8717 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 8718 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 8719 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 8720 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 8721 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 8722 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 8723 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 8724 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 8725 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 8726 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 8727 mask |= 1U << ((mmNIC4_QM0_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 8728 mask |= 1U << ((mmNIC4_QM0_CGM_CFG & 0x7F) >> 2); 8729 mask |= 1U << ((mmNIC4_QM0_CGM_STS & 0x7F) >> 2); 8730 mask |= 1U << ((mmNIC4_QM0_CGM_CFG1 & 0x7F) >> 2); 8731 8732 WREG32(pb_addr + word_offset, ~mask); 8733 8734 pb_addr = (mmNIC4_QM0_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 8735 word_offset = ((mmNIC4_QM0_LOCAL_RANGE_BASE & PROT_BITS_OFFS) 8736 >> 7) << 2; 8737 mask = 1U << ((mmNIC4_QM0_LOCAL_RANGE_BASE & 0x7F) >> 2); 8738 mask |= 1U << ((mmNIC4_QM0_LOCAL_RANGE_SIZE & 0x7F) >> 2); 8739 mask |= 1U << ((mmNIC4_QM0_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 8740 mask |= 1U << ((mmNIC4_QM0_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 8741 mask |= 1U << ((mmNIC4_QM0_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 8742 mask |= 1U << ((mmNIC4_QM0_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 8743 mask |= 1U << ((mmNIC4_QM0_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 8744 mask |= 1U << ((mmNIC4_QM0_GLBL_AXCACHE & 0x7F) >> 2); 8745 mask |= 1U << ((mmNIC4_QM0_IND_GW_APB_CFG & 0x7F) >> 2); 8746 mask |= 1U << ((mmNIC4_QM0_IND_GW_APB_WDATA & 0x7F) >> 2); 8747 mask |= 1U << ((mmNIC4_QM0_IND_GW_APB_RDATA & 0x7F) >> 2); 8748 mask |= 1U << ((mmNIC4_QM0_IND_GW_APB_STATUS & 0x7F) >> 2); 8749 mask |= 1U << ((mmNIC4_QM0_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 8750 mask |= 1U << ((mmNIC4_QM0_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 8751 mask |= 1U << ((mmNIC4_QM0_GLBL_ERR_WDATA & 0x7F) >> 2); 8752 8753 WREG32(pb_addr + word_offset, ~mask); 8754 8755 pb_addr = (mmNIC4_QM0_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 8756 word_offset = ((mmNIC4_QM0_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) 8757 >> 7) << 2; 8758 mask = 1U << ((mmNIC4_QM0_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 8759 8760 WREG32(pb_addr + word_offset, ~mask); 8761 8762 pb_addr = (mmNIC4_QM1_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 8763 word_offset = ((mmNIC4_QM1_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 8764 mask = 1U << ((mmNIC4_QM1_GLBL_CFG0 & 0x7F) >> 2); 8765 mask |= 1U << ((mmNIC4_QM1_GLBL_CFG1 & 0x7F) >> 2); 8766 mask |= 1U << ((mmNIC4_QM1_GLBL_PROT & 0x7F) >> 2); 8767 mask |= 1U << ((mmNIC4_QM1_GLBL_ERR_CFG & 0x7F) >> 2); 8768 mask |= 1U << ((mmNIC4_QM1_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 8769 mask |= 1U << ((mmNIC4_QM1_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 8770 mask |= 1U << ((mmNIC4_QM1_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 8771 mask |= 1U << ((mmNIC4_QM1_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 8772 mask |= 1U << ((mmNIC4_QM1_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 8773 mask |= 1U << ((mmNIC4_QM1_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 8774 mask |= 1U << ((mmNIC4_QM1_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 8775 mask |= 1U << ((mmNIC4_QM1_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 8776 mask |= 1U << ((mmNIC4_QM1_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 8777 mask |= 1U << ((mmNIC4_QM1_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 8778 mask |= 1U << ((mmNIC4_QM1_GLBL_STS0 & 0x7F) >> 2); 8779 mask |= 1U << ((mmNIC4_QM1_GLBL_STS1_0 & 0x7F) >> 2); 8780 mask |= 1U << ((mmNIC4_QM1_GLBL_STS1_1 & 0x7F) >> 2); 8781 mask |= 1U << ((mmNIC4_QM1_GLBL_STS1_2 & 0x7F) >> 2); 8782 mask |= 1U << ((mmNIC4_QM1_GLBL_STS1_3 & 0x7F) >> 2); 8783 mask |= 1U << ((mmNIC4_QM1_GLBL_STS1_4 & 0x7F) >> 2); 8784 mask |= 1U << ((mmNIC4_QM1_GLBL_MSG_EN_0 & 0x7F) >> 2); 8785 mask |= 1U << ((mmNIC4_QM1_GLBL_MSG_EN_1 & 0x7F) >> 2); 8786 mask |= 1U << ((mmNIC4_QM1_GLBL_MSG_EN_2 & 0x7F) >> 2); 8787 mask |= 1U << ((mmNIC4_QM1_GLBL_MSG_EN_3 & 0x7F) >> 2); 8788 mask |= 1U << ((mmNIC4_QM1_GLBL_MSG_EN_4 & 0x7F) >> 2); 8789 mask |= 1U << ((mmNIC4_QM1_PQ_BASE_LO_0 & 0x7F) >> 2); 8790 mask |= 1U << ((mmNIC4_QM1_PQ_BASE_LO_1 & 0x7F) >> 2); 8791 mask |= 1U << ((mmNIC4_QM1_PQ_BASE_LO_2 & 0x7F) >> 2); 8792 mask |= 1U << ((mmNIC4_QM1_PQ_BASE_LO_3 & 0x7F) >> 2); 8793 8794 WREG32(pb_addr + word_offset, ~mask); 8795 8796 pb_addr = (mmNIC4_QM1_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 8797 word_offset = ((mmNIC4_QM1_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 8798 mask = 1U << ((mmNIC4_QM1_PQ_BASE_HI_0 & 0x7F) >> 2); 8799 mask |= 1U << ((mmNIC4_QM1_PQ_BASE_HI_1 & 0x7F) >> 2); 8800 mask |= 1U << ((mmNIC4_QM1_PQ_BASE_HI_2 & 0x7F) >> 2); 8801 mask |= 1U << ((mmNIC4_QM1_PQ_BASE_HI_3 & 0x7F) >> 2); 8802 mask |= 1U << ((mmNIC4_QM1_PQ_SIZE_0 & 0x7F) >> 2); 8803 mask |= 1U << ((mmNIC4_QM1_PQ_SIZE_1 & 0x7F) >> 2); 8804 mask |= 1U << ((mmNIC4_QM1_PQ_SIZE_2 & 0x7F) >> 2); 8805 mask |= 1U << ((mmNIC4_QM1_PQ_SIZE_3 & 0x7F) >> 2); 8806 mask |= 1U << ((mmNIC4_QM1_PQ_PI_0 & 0x7F) >> 2); 8807 mask |= 1U << ((mmNIC4_QM1_PQ_PI_1 & 0x7F) >> 2); 8808 mask |= 1U << ((mmNIC4_QM1_PQ_PI_2 & 0x7F) >> 2); 8809 mask |= 1U << ((mmNIC4_QM1_PQ_PI_3 & 0x7F) >> 2); 8810 mask |= 1U << ((mmNIC4_QM1_PQ_CI_0 & 0x7F) >> 2); 8811 mask |= 1U << ((mmNIC4_QM1_PQ_CI_1 & 0x7F) >> 2); 8812 mask |= 1U << ((mmNIC4_QM1_PQ_CI_2 & 0x7F) >> 2); 8813 mask |= 1U << ((mmNIC4_QM1_PQ_CI_3 & 0x7F) >> 2); 8814 mask |= 1U << ((mmNIC4_QM1_PQ_CFG0_0 & 0x7F) >> 2); 8815 mask |= 1U << ((mmNIC4_QM1_PQ_CFG0_1 & 0x7F) >> 2); 8816 mask |= 1U << ((mmNIC4_QM1_PQ_CFG0_2 & 0x7F) >> 2); 8817 mask |= 1U << ((mmNIC4_QM1_PQ_CFG0_3 & 0x7F) >> 2); 8818 mask |= 1U << ((mmNIC4_QM1_PQ_CFG1_0 & 0x7F) >> 2); 8819 mask |= 1U << ((mmNIC4_QM1_PQ_CFG1_1 & 0x7F) >> 2); 8820 mask |= 1U << ((mmNIC4_QM1_PQ_CFG1_2 & 0x7F) >> 2); 8821 mask |= 1U << ((mmNIC4_QM1_PQ_CFG1_3 & 0x7F) >> 2); 8822 mask |= 1U << ((mmNIC4_QM1_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 8823 mask |= 1U << ((mmNIC4_QM1_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 8824 mask |= 1U << ((mmNIC4_QM1_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 8825 mask |= 1U << ((mmNIC4_QM1_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 8826 mask |= 1U << ((mmNIC4_QM1_PQ_STS0_0 & 0x7F) >> 2); 8827 mask |= 1U << ((mmNIC4_QM1_PQ_STS0_1 & 0x7F) >> 2); 8828 mask |= 1U << ((mmNIC4_QM1_PQ_STS0_2 & 0x7F) >> 2); 8829 mask |= 1U << ((mmNIC4_QM1_PQ_STS0_3 & 0x7F) >> 2); 8830 8831 WREG32(pb_addr + word_offset, ~mask); 8832 8833 pb_addr = (mmNIC4_QM1_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 8834 word_offset = ((mmNIC4_QM1_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 8835 mask = 1U << ((mmNIC4_QM1_PQ_STS1_0 & 0x7F) >> 2); 8836 mask |= 1U << ((mmNIC4_QM1_PQ_STS1_1 & 0x7F) >> 2); 8837 mask |= 1U << ((mmNIC4_QM1_PQ_STS1_2 & 0x7F) >> 2); 8838 mask |= 1U << ((mmNIC4_QM1_PQ_STS1_3 & 0x7F) >> 2); 8839 mask |= 1U << ((mmNIC4_QM1_CQ_STS0_0 & 0x7F) >> 2); 8840 mask |= 1U << ((mmNIC4_QM1_CQ_STS0_1 & 0x7F) >> 2); 8841 mask |= 1U << ((mmNIC4_QM1_CQ_STS0_2 & 0x7F) >> 2); 8842 mask |= 1U << ((mmNIC4_QM1_CQ_STS0_3 & 0x7F) >> 2); 8843 mask |= 1U << ((mmNIC4_QM1_CQ_STS1_0 & 0x7F) >> 2); 8844 mask |= 1U << ((mmNIC4_QM1_CQ_STS1_1 & 0x7F) >> 2); 8845 mask |= 1U << ((mmNIC4_QM1_CQ_STS1_2 & 0x7F) >> 2); 8846 mask |= 1U << ((mmNIC4_QM1_CQ_STS1_3 & 0x7F) >> 2); 8847 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_0 & 0x7F) >> 2); 8848 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_0 & 0x7F) >> 2); 8849 mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_0 & 0x7F) >> 2); 8850 8851 WREG32(pb_addr + word_offset, ~mask); 8852 8853 pb_addr = (mmNIC4_QM1_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 8854 word_offset = ((mmNIC4_QM1_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 8855 mask = 1U << ((mmNIC4_QM1_CQ_CTL_0 & 0x7F) >> 2); 8856 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_1 & 0x7F) >> 2); 8857 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_1 & 0x7F) >> 2); 8858 mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_1 & 0x7F) >> 2); 8859 mask |= 1U << ((mmNIC4_QM1_CQ_CTL_1 & 0x7F) >> 2); 8860 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_2 & 0x7F) >> 2); 8861 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_2 & 0x7F) >> 2); 8862 mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_2 & 0x7F) >> 2); 8863 mask |= 1U << ((mmNIC4_QM1_CQ_CTL_2 & 0x7F) >> 2); 8864 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_3 & 0x7F) >> 2); 8865 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_3 & 0x7F) >> 2); 8866 mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_3 & 0x7F) >> 2); 8867 mask |= 1U << ((mmNIC4_QM1_CQ_CTL_3 & 0x7F) >> 2); 8868 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 8869 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 8870 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 8871 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 8872 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 8873 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 8874 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 8875 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 8876 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 8877 mask |= 1U << ((mmNIC4_QM1_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 8878 mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_STS_0 & 0x7F) >> 2); 8879 mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_STS_1 & 0x7F) >> 2); 8880 mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_STS_2 & 0x7F) >> 2); 8881 mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_STS_3 & 0x7F) >> 2); 8882 mask |= 1U << ((mmNIC4_QM1_CQ_TSIZE_STS_4 & 0x7F) >> 2); 8883 8884 WREG32(pb_addr + word_offset, ~mask); 8885 8886 pb_addr = (mmNIC4_QM1_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 8887 word_offset = ((mmNIC4_QM1_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 8888 mask = 1U << ((mmNIC4_QM1_CQ_CTL_STS_0 & 0x7F) >> 2); 8889 mask |= 1U << ((mmNIC4_QM1_CQ_CTL_STS_1 & 0x7F) >> 2); 8890 mask |= 1U << ((mmNIC4_QM1_CQ_CTL_STS_2 & 0x7F) >> 2); 8891 mask |= 1U << ((mmNIC4_QM1_CQ_CTL_STS_3 & 0x7F) >> 2); 8892 mask |= 1U << ((mmNIC4_QM1_CQ_CTL_STS_4 & 0x7F) >> 2); 8893 mask |= 1U << ((mmNIC4_QM1_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 8894 mask |= 1U << ((mmNIC4_QM1_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 8895 mask |= 1U << ((mmNIC4_QM1_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 8896 mask |= 1U << ((mmNIC4_QM1_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 8897 mask |= 1U << ((mmNIC4_QM1_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 8898 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 8899 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 8900 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 8901 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 8902 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 8903 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 8904 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 8905 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 8906 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 8907 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 8908 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 8909 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 8910 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 8911 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 8912 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 8913 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 8914 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 8915 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 8916 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 8917 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 8918 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 8919 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 8920 8921 WREG32(pb_addr + word_offset, ~mask); 8922 8923 pb_addr = (mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 8924 word_offset = ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_2 & 8925 PROT_BITS_OFFS) >> 7) << 2; 8926 mask = 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 8927 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 8928 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 8929 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 8930 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 8931 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 8932 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 8933 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 8934 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 8935 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 8936 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 8937 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 8938 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 8939 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 8940 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 8941 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 8942 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 8943 mask |= 1U << ((mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 8944 mask |= 1U << ((mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 8945 mask |= 1U << ((mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 8946 mask |= 1U << ((mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 8947 mask |= 1U << ((mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 8948 mask |= 1U << ((mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 8949 mask |= 1U << ((mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 8950 mask |= 1U << ((mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 8951 mask |= 1U << ((mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 8952 mask |= 1U << ((mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 8953 mask |= 1U << ((mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 8954 mask |= 1U << ((mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 8955 mask |= 1U << ((mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 8956 mask |= 1U << ((mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 8957 8958 WREG32(pb_addr + word_offset, ~mask); 8959 8960 pb_addr = (mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 8961 PROT_BITS_OFFS; 8962 word_offset = ((mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & 8963 PROT_BITS_OFFS) >> 7) << 2; 8964 mask = 1U << ((mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 8965 mask |= 1U << ((mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 8966 8967 WREG32(pb_addr + word_offset, ~mask); 8968 8969 pb_addr = (mmNIC4_QM1_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 8970 word_offset = ((mmNIC4_QM1_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 8971 mask = 1U << ((mmNIC4_QM1_CP_STS_0 & 0x7F) >> 2); 8972 mask |= 1U << ((mmNIC4_QM1_CP_STS_1 & 0x7F) >> 2); 8973 mask |= 1U << ((mmNIC4_QM1_CP_STS_2 & 0x7F) >> 2); 8974 mask |= 1U << ((mmNIC4_QM1_CP_STS_3 & 0x7F) >> 2); 8975 mask |= 1U << ((mmNIC4_QM1_CP_STS_4 & 0x7F) >> 2); 8976 mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 8977 mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 8978 mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 8979 mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 8980 mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 8981 mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 8982 mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 8983 mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 8984 mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 8985 mask |= 1U << ((mmNIC4_QM1_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 8986 mask |= 1U << ((mmNIC4_QM1_CP_BARRIER_CFG_0 & 0x7F) >> 2); 8987 mask |= 1U << ((mmNIC4_QM1_CP_BARRIER_CFG_1 & 0x7F) >> 2); 8988 mask |= 1U << ((mmNIC4_QM1_CP_BARRIER_CFG_2 & 0x7F) >> 2); 8989 8990 WREG32(pb_addr + word_offset, ~mask); 8991 8992 pb_addr = (mmNIC4_QM1_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 8993 word_offset = ((mmNIC4_QM1_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) 8994 >> 7) << 2; 8995 mask = 1U << ((mmNIC4_QM1_CP_BARRIER_CFG_3 & 0x7F) >> 2); 8996 mask |= 1U << ((mmNIC4_QM1_CP_BARRIER_CFG_4 & 0x7F) >> 2); 8997 mask |= 1U << ((mmNIC4_QM1_CP_DBG_0_0 & 0x7F) >> 2); 8998 mask |= 1U << ((mmNIC4_QM1_CP_DBG_0_1 & 0x7F) >> 2); 8999 9000 WREG32(pb_addr + word_offset, ~mask); 9001 9002 pb_addr = (mmNIC4_QM1_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 9003 word_offset = ((mmNIC4_QM1_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 9004 mask = 1U << ((mmNIC4_QM1_CP_DBG_0_2 & 0x7F) >> 2); 9005 mask |= 1U << ((mmNIC4_QM1_CP_DBG_0_3 & 0x7F) >> 2); 9006 mask |= 1U << ((mmNIC4_QM1_CP_DBG_0_4 & 0x7F) >> 2); 9007 mask |= 1U << ((mmNIC4_QM1_CP_ARUSER_31_11_0 & 0x7F) >> 2); 9008 mask |= 1U << ((mmNIC4_QM1_CP_ARUSER_31_11_1 & 0x7F) >> 2); 9009 mask |= 1U << ((mmNIC4_QM1_CP_ARUSER_31_11_2 & 0x7F) >> 2); 9010 mask |= 1U << ((mmNIC4_QM1_CP_ARUSER_31_11_3 & 0x7F) >> 2); 9011 mask |= 1U << ((mmNIC4_QM1_CP_ARUSER_31_11_4 & 0x7F) >> 2); 9012 mask |= 1U << ((mmNIC4_QM1_CP_AWUSER_31_11_0 & 0x7F) >> 2); 9013 mask |= 1U << ((mmNIC4_QM1_CP_AWUSER_31_11_1 & 0x7F) >> 2); 9014 mask |= 1U << ((mmNIC4_QM1_CP_AWUSER_31_11_2 & 0x7F) >> 2); 9015 mask |= 1U << ((mmNIC4_QM1_CP_AWUSER_31_11_3 & 0x7F) >> 2); 9016 mask |= 1U << ((mmNIC4_QM1_CP_AWUSER_31_11_4 & 0x7F) >> 2); 9017 9018 WREG32(pb_addr + word_offset, ~mask); 9019 9020 pb_addr = (mmNIC4_QM1_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 9021 word_offset = ((mmNIC4_QM1_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 9022 mask = 1U << ((mmNIC4_QM1_ARB_CFG_1 & 0x7F) >> 2); 9023 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 9024 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 9025 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 9026 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 9027 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 9028 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 9029 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 9030 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 9031 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 9032 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 9033 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 9034 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 9035 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 9036 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 9037 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 9038 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 9039 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 9040 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 9041 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 9042 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 9043 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 9044 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 9045 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 9046 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 9047 9048 WREG32(pb_addr + word_offset, ~mask); 9049 9050 pb_addr = (mmNIC4_QM1_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 9051 word_offset = ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_24 & 9052 PROT_BITS_OFFS) >> 7) << 2; 9053 mask = 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 9054 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 9055 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 9056 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 9057 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 9058 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 9059 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 9060 mask |= 1U << ((mmNIC4_QM1_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 9061 9062 WREG32(pb_addr + word_offset, ~mask); 9063 9064 pb_addr = (mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 9065 PROT_BITS_OFFS; 9066 word_offset = ((mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_23 & 9067 PROT_BITS_OFFS) >> 7) << 2; 9068 mask = 1U << ((mmNIC4_QM1_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 9069 mask |= 1U << ((mmNIC4_QM1_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 9070 mask |= 1U << ((mmNIC4_QM1_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 9071 mask |= 1U << ((mmNIC4_QM1_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 9072 mask |= 1U << ((mmNIC4_QM1_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 9073 9074 WREG32(pb_addr + word_offset, ~mask); 9075 9076 pb_addr = (mmNIC4_QM1_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 9077 word_offset = ((mmNIC4_QM1_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 9078 mask = 1U << ((mmNIC4_QM1_ARB_STATE_STS & 0x7F) >> 2); 9079 mask |= 1U << ((mmNIC4_QM1_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 9080 mask |= 1U << ((mmNIC4_QM1_ARB_MSG_STS & 0x7F) >> 2); 9081 mask |= 1U << ((mmNIC4_QM1_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 9082 mask |= 1U << ((mmNIC4_QM1_ARB_ERR_CAUSE & 0x7F) >> 2); 9083 mask |= 1U << ((mmNIC4_QM1_ARB_ERR_MSG_EN & 0x7F) >> 2); 9084 mask |= 1U << ((mmNIC4_QM1_ARB_ERR_STS_DRP & 0x7F) >> 2); 9085 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 9086 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 9087 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 9088 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 9089 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 9090 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 9091 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 9092 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 9093 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 9094 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 9095 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 9096 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 9097 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 9098 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 9099 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 9100 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 9101 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 9102 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 9103 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 9104 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 9105 9106 WREG32(pb_addr + word_offset, ~mask); 9107 9108 pb_addr = (mmNIC4_QM1_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 9109 word_offset = ((mmNIC4_QM1_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) 9110 >> 7) << 2; 9111 mask = 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 9112 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 9113 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 9114 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 9115 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 9116 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 9117 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 9118 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 9119 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 9120 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 9121 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 9122 mask |= 1U << ((mmNIC4_QM1_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 9123 mask |= 1U << ((mmNIC4_QM1_CGM_CFG & 0x7F) >> 2); 9124 mask |= 1U << ((mmNIC4_QM1_CGM_STS & 0x7F) >> 2); 9125 mask |= 1U << ((mmNIC4_QM1_CGM_CFG1 & 0x7F) >> 2); 9126 9127 WREG32(pb_addr + word_offset, ~mask); 9128 9129 pb_addr = (mmNIC4_QM1_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 9130 word_offset = ((mmNIC4_QM1_LOCAL_RANGE_BASE & PROT_BITS_OFFS) 9131 >> 7) << 2; 9132 mask = 1U << ((mmNIC4_QM1_LOCAL_RANGE_BASE & 0x7F) >> 2); 9133 mask |= 1U << ((mmNIC4_QM1_LOCAL_RANGE_SIZE & 0x7F) >> 2); 9134 mask |= 1U << ((mmNIC4_QM1_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 9135 mask |= 1U << ((mmNIC4_QM1_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 9136 mask |= 1U << ((mmNIC4_QM1_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 9137 mask |= 1U << ((mmNIC4_QM1_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 9138 mask |= 1U << ((mmNIC4_QM1_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 9139 mask |= 1U << ((mmNIC4_QM1_GLBL_AXCACHE & 0x7F) >> 2); 9140 mask |= 1U << ((mmNIC4_QM1_IND_GW_APB_CFG & 0x7F) >> 2); 9141 mask |= 1U << ((mmNIC4_QM1_IND_GW_APB_WDATA & 0x7F) >> 2); 9142 mask |= 1U << ((mmNIC4_QM1_IND_GW_APB_RDATA & 0x7F) >> 2); 9143 mask |= 1U << ((mmNIC4_QM1_IND_GW_APB_STATUS & 0x7F) >> 2); 9144 mask |= 1U << ((mmNIC4_QM1_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 9145 mask |= 1U << ((mmNIC4_QM1_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 9146 mask |= 1U << ((mmNIC4_QM1_GLBL_ERR_WDATA & 0x7F) >> 2); 9147 9148 WREG32(pb_addr + word_offset, ~mask); 9149 9150 pb_addr = (mmNIC4_QM1_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 9151 word_offset = ((mmNIC4_QM1_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) 9152 >> 7) << 2; 9153 mask = 1U << ((mmNIC4_QM1_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 9154 9155 WREG32(pb_addr + word_offset, ~mask); 9156} 9157 9158static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) 9159{ 9160 u32 pb_addr, mask; 9161 u8 word_offset; 9162 9163 if (!hdev->asic_prop.fw_security_enabled) { 9164 gaudi_pb_set_block(hdev, mmTPC0_E2E_CRED_BASE); 9165 gaudi_pb_set_block(hdev, mmTPC1_E2E_CRED_BASE); 9166 gaudi_pb_set_block(hdev, mmTPC2_E2E_CRED_BASE); 9167 gaudi_pb_set_block(hdev, mmTPC3_E2E_CRED_BASE); 9168 gaudi_pb_set_block(hdev, mmTPC4_E2E_CRED_BASE); 9169 gaudi_pb_set_block(hdev, mmTPC5_E2E_CRED_BASE); 9170 gaudi_pb_set_block(hdev, mmTPC6_E2E_CRED_BASE); 9171 gaudi_pb_set_block(hdev, mmTPC7_E2E_CRED_BASE); 9172 } 9173 9174 WREG32(mmTPC0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 9175 WREG32(mmTPC0_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 9176 9177 pb_addr = (mmTPC0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 9178 word_offset = ((mmTPC0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 9179 mask = 1U << ((mmTPC0_QM_GLBL_CFG0 & 0x7F) >> 2); 9180 mask |= 1U << ((mmTPC0_QM_GLBL_CFG1 & 0x7F) >> 2); 9181 mask |= 1U << ((mmTPC0_QM_GLBL_PROT & 0x7F) >> 2); 9182 mask |= 1U << ((mmTPC0_QM_GLBL_ERR_CFG & 0x7F) >> 2); 9183 mask |= 1U << ((mmTPC0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 9184 mask |= 1U << ((mmTPC0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 9185 mask |= 1U << ((mmTPC0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 9186 mask |= 1U << ((mmTPC0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 9187 mask |= 1U << ((mmTPC0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 9188 mask |= 1U << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 9189 mask |= 1U << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 9190 mask |= 1U << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 9191 mask |= 1U << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 9192 mask |= 1U << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 9193 mask |= 1U << ((mmTPC0_QM_GLBL_STS0 & 0x7F) >> 2); 9194 mask |= 1U << ((mmTPC0_QM_GLBL_STS1_0 & 0x7F) >> 2); 9195 mask |= 1U << ((mmTPC0_QM_GLBL_STS1_1 & 0x7F) >> 2); 9196 mask |= 1U << ((mmTPC0_QM_GLBL_STS1_2 & 0x7F) >> 2); 9197 mask |= 1U << ((mmTPC0_QM_GLBL_STS1_3 & 0x7F) >> 2); 9198 mask |= 1U << ((mmTPC0_QM_GLBL_STS1_4 & 0x7F) >> 2); 9199 mask |= 1U << ((mmTPC0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 9200 mask |= 1U << ((mmTPC0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 9201 mask |= 1U << ((mmTPC0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 9202 mask |= 1U << ((mmTPC0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 9203 mask |= 1U << ((mmTPC0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 9204 mask |= 1U << ((mmTPC0_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 9205 mask |= 1U << ((mmTPC0_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 9206 mask |= 1U << ((mmTPC0_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 9207 mask |= 1U << ((mmTPC0_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 9208 9209 WREG32(pb_addr + word_offset, ~mask); 9210 9211 pb_addr = (mmTPC0_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 9212 word_offset = ((mmTPC0_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 9213 mask = 1U << ((mmTPC0_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 9214 mask |= 1U << ((mmTPC0_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 9215 mask |= 1U << ((mmTPC0_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 9216 mask |= 1U << ((mmTPC0_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 9217 mask |= 1U << ((mmTPC0_QM_PQ_SIZE_0 & 0x7F) >> 2); 9218 mask |= 1U << ((mmTPC0_QM_PQ_SIZE_1 & 0x7F) >> 2); 9219 mask |= 1U << ((mmTPC0_QM_PQ_SIZE_2 & 0x7F) >> 2); 9220 mask |= 1U << ((mmTPC0_QM_PQ_SIZE_3 & 0x7F) >> 2); 9221 mask |= 1U << ((mmTPC0_QM_PQ_PI_0 & 0x7F) >> 2); 9222 mask |= 1U << ((mmTPC0_QM_PQ_PI_1 & 0x7F) >> 2); 9223 mask |= 1U << ((mmTPC0_QM_PQ_PI_2 & 0x7F) >> 2); 9224 mask |= 1U << ((mmTPC0_QM_PQ_PI_3 & 0x7F) >> 2); 9225 mask |= 1U << ((mmTPC0_QM_PQ_CI_0 & 0x7F) >> 2); 9226 mask |= 1U << ((mmTPC0_QM_PQ_CI_1 & 0x7F) >> 2); 9227 mask |= 1U << ((mmTPC0_QM_PQ_CI_2 & 0x7F) >> 2); 9228 mask |= 1U << ((mmTPC0_QM_PQ_CI_3 & 0x7F) >> 2); 9229 mask |= 1U << ((mmTPC0_QM_PQ_CFG0_0 & 0x7F) >> 2); 9230 mask |= 1U << ((mmTPC0_QM_PQ_CFG0_1 & 0x7F) >> 2); 9231 mask |= 1U << ((mmTPC0_QM_PQ_CFG0_2 & 0x7F) >> 2); 9232 mask |= 1U << ((mmTPC0_QM_PQ_CFG0_3 & 0x7F) >> 2); 9233 mask |= 1U << ((mmTPC0_QM_PQ_CFG1_0 & 0x7F) >> 2); 9234 mask |= 1U << ((mmTPC0_QM_PQ_CFG1_1 & 0x7F) >> 2); 9235 mask |= 1U << ((mmTPC0_QM_PQ_CFG1_2 & 0x7F) >> 2); 9236 mask |= 1U << ((mmTPC0_QM_PQ_CFG1_3 & 0x7F) >> 2); 9237 mask |= 1U << ((mmTPC0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 9238 mask |= 1U << ((mmTPC0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 9239 mask |= 1U << ((mmTPC0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 9240 mask |= 1U << ((mmTPC0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 9241 mask |= 1U << ((mmTPC0_QM_PQ_STS0_0 & 0x7F) >> 2); 9242 mask |= 1U << ((mmTPC0_QM_PQ_STS0_1 & 0x7F) >> 2); 9243 mask |= 1U << ((mmTPC0_QM_PQ_STS0_2 & 0x7F) >> 2); 9244 mask |= 1U << ((mmTPC0_QM_PQ_STS0_3 & 0x7F) >> 2); 9245 9246 WREG32(pb_addr + word_offset, ~mask); 9247 9248 pb_addr = (mmTPC0_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 9249 word_offset = ((mmTPC0_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 9250 mask = 1U << ((mmTPC0_QM_PQ_STS1_0 & 0x7F) >> 2); 9251 mask |= 1U << ((mmTPC0_QM_PQ_STS1_1 & 0x7F) >> 2); 9252 mask |= 1U << ((mmTPC0_QM_PQ_STS1_2 & 0x7F) >> 2); 9253 mask |= 1U << ((mmTPC0_QM_PQ_STS1_3 & 0x7F) >> 2); 9254 mask |= 1U << ((mmTPC0_QM_CQ_STS0_0 & 0x7F) >> 2); 9255 mask |= 1U << ((mmTPC0_QM_CQ_STS0_1 & 0x7F) >> 2); 9256 mask |= 1U << ((mmTPC0_QM_CQ_STS0_2 & 0x7F) >> 2); 9257 mask |= 1U << ((mmTPC0_QM_CQ_STS0_3 & 0x7F) >> 2); 9258 mask |= 1U << ((mmTPC0_QM_CQ_STS1_0 & 0x7F) >> 2); 9259 mask |= 1U << ((mmTPC0_QM_CQ_STS1_1 & 0x7F) >> 2); 9260 mask |= 1U << ((mmTPC0_QM_CQ_STS1_2 & 0x7F) >> 2); 9261 mask |= 1U << ((mmTPC0_QM_CQ_STS1_3 & 0x7F) >> 2); 9262 mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 9263 mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 9264 mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_0 & 0x7F) >> 2); 9265 9266 WREG32(pb_addr + word_offset, ~mask); 9267 9268 pb_addr = (mmTPC0_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 9269 word_offset = ((mmTPC0_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 9270 mask = 1U << ((mmTPC0_QM_CQ_CTL_0 & 0x7F) >> 2); 9271 mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 9272 mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 9273 mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_1 & 0x7F) >> 2); 9274 mask |= 1U << ((mmTPC0_QM_CQ_CTL_1 & 0x7F) >> 2); 9275 mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 9276 mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 9277 mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_2 & 0x7F) >> 2); 9278 mask |= 1U << ((mmTPC0_QM_CQ_CTL_2 & 0x7F) >> 2); 9279 mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 9280 mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 9281 mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_3 & 0x7F) >> 2); 9282 mask |= 1U << ((mmTPC0_QM_CQ_CTL_3 & 0x7F) >> 2); 9283 mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 9284 mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 9285 mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 9286 mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 9287 mask |= 1U << ((mmTPC0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 9288 mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 9289 mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 9290 mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 9291 mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 9292 mask |= 1U << ((mmTPC0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 9293 mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 9294 mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 9295 mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 9296 mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 9297 mask |= 1U << ((mmTPC0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 9298 9299 WREG32(pb_addr + word_offset, ~mask); 9300 9301 pb_addr = (mmTPC0_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 9302 word_offset = ((mmTPC0_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 9303 mask = 1U << ((mmTPC0_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 9304 mask |= 1U << ((mmTPC0_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 9305 mask |= 1U << ((mmTPC0_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 9306 mask |= 1U << ((mmTPC0_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 9307 mask |= 1U << ((mmTPC0_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 9308 mask |= 1U << ((mmTPC0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 9309 mask |= 1U << ((mmTPC0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 9310 mask |= 1U << ((mmTPC0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 9311 mask |= 1U << ((mmTPC0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 9312 mask |= 1U << ((mmTPC0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 9313 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 9314 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 9315 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 9316 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 9317 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 9318 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 9319 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 9320 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 9321 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 9322 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 9323 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 9324 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 9325 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 9326 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 9327 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 9328 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 9329 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 9330 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 9331 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 9332 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 9333 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 9334 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 9335 9336 WREG32(pb_addr + word_offset, ~mask); 9337 9338 pb_addr = (mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 9339 word_offset = ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 9340 << 2; 9341 mask = 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 9342 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 9343 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 9344 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 9345 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 9346 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 9347 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 9348 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 9349 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 9350 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 9351 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 9352 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 9353 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 9354 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 9355 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 9356 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 9357 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 9358 mask |= 1U << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 9359 mask |= 1U << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 9360 mask |= 1U << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 9361 mask |= 1U << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 9362 mask |= 1U << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 9363 mask |= 1U << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 9364 mask |= 1U << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 9365 mask |= 1U << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 9366 mask |= 1U << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 9367 mask |= 1U << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 9368 mask |= 1U << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 9369 mask |= 1U << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 9370 mask |= 1U << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 9371 mask |= 1U << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 9372 9373 WREG32(pb_addr + word_offset, ~mask); 9374 9375 pb_addr = (mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 9376 PROT_BITS_OFFS; 9377 9378 word_offset = ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) 9379 >> 7) << 2; 9380 9381 mask = 1U << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 9382 mask |= 1U << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 9383 9384 WREG32(pb_addr + word_offset, ~mask); 9385 9386 pb_addr = (mmTPC0_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 9387 word_offset = ((mmTPC0_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 9388 mask = 1U << ((mmTPC0_QM_CP_STS_0 & 0x7F) >> 2); 9389 mask |= 1U << ((mmTPC0_QM_CP_STS_1 & 0x7F) >> 2); 9390 mask |= 1U << ((mmTPC0_QM_CP_STS_2 & 0x7F) >> 2); 9391 mask |= 1U << ((mmTPC0_QM_CP_STS_3 & 0x7F) >> 2); 9392 mask |= 1U << ((mmTPC0_QM_CP_STS_4 & 0x7F) >> 2); 9393 mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 9394 mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 9395 mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 9396 mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 9397 mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 9398 mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 9399 mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 9400 mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 9401 mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 9402 mask |= 1U << ((mmTPC0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 9403 mask |= 1U << ((mmTPC0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 9404 mask |= 1U << ((mmTPC0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 9405 mask |= 1U << ((mmTPC0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 9406 9407 WREG32(pb_addr + word_offset, ~mask); 9408 9409 pb_addr = (mmTPC0_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 9410 word_offset = ((mmTPC0_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 9411 mask = 1U << ((mmTPC0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 9412 mask |= 1U << ((mmTPC0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 9413 mask |= 1U << ((mmTPC0_QM_CP_DBG_0_0 & 0x7F) >> 2); 9414 mask |= 1U << ((mmTPC0_QM_CP_DBG_0_1 & 0x7F) >> 2); 9415 9416 WREG32(pb_addr + word_offset, ~mask); 9417 9418 pb_addr = (mmTPC0_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 9419 word_offset = ((mmTPC0_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 9420 mask = 1U << ((mmTPC0_QM_CP_DBG_0_2 & 0x7F) >> 2); 9421 mask |= 1U << ((mmTPC0_QM_CP_DBG_0_3 & 0x7F) >> 2); 9422 mask |= 1U << ((mmTPC0_QM_CP_DBG_0_4 & 0x7F) >> 2); 9423 mask |= 1U << ((mmTPC0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 9424 mask |= 1U << ((mmTPC0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 9425 mask |= 1U << ((mmTPC0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 9426 mask |= 1U << ((mmTPC0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 9427 mask |= 1U << ((mmTPC0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 9428 mask |= 1U << ((mmTPC0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 9429 mask |= 1U << ((mmTPC0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 9430 mask |= 1U << ((mmTPC0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 9431 mask |= 1U << ((mmTPC0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 9432 mask |= 1U << ((mmTPC0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 9433 9434 WREG32(pb_addr + word_offset, ~mask); 9435 9436 pb_addr = (mmTPC0_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 9437 word_offset = ((mmTPC0_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 9438 mask = 1U << ((mmTPC0_QM_ARB_CFG_1 & 0x7F) >> 2); 9439 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 9440 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 9441 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 9442 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 9443 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 9444 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 9445 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 9446 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 9447 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 9448 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 9449 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 9450 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 9451 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 9452 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 9453 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 9454 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 9455 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 9456 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 9457 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 9458 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 9459 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 9460 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 9461 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 9462 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 9463 9464 WREG32(pb_addr + word_offset, ~mask); 9465 9466 pb_addr = (mmTPC0_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 9467 word_offset = ((mmTPC0_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 9468 << 2; 9469 mask = 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 9470 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 9471 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 9472 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 9473 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 9474 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 9475 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 9476 mask |= 1U << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 9477 9478 WREG32(pb_addr + word_offset, ~mask); 9479 9480 pb_addr = (mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 9481 PROT_BITS_OFFS; 9482 9483 word_offset = ((mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) 9484 >> 7) << 2; 9485 mask = 1U << ((mmTPC0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 9486 mask |= 1U << ((mmTPC0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 9487 mask |= 1U << ((mmTPC0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 9488 mask |= 1U << ((mmTPC0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 9489 mask |= 1U << ((mmTPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 9490 9491 WREG32(pb_addr + word_offset, ~mask); 9492 9493 pb_addr = (mmTPC0_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 9494 word_offset = ((mmTPC0_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 9495 mask = 1U << ((mmTPC0_QM_ARB_STATE_STS & 0x7F) >> 2); 9496 mask |= 1U << ((mmTPC0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 9497 mask |= 1U << ((mmTPC0_QM_ARB_MSG_STS & 0x7F) >> 2); 9498 mask |= 1U << ((mmTPC0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 9499 mask |= 1U << ((mmTPC0_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 9500 mask |= 1U << ((mmTPC0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 9501 mask |= 1U << ((mmTPC0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 9502 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 9503 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 9504 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 9505 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 9506 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 9507 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 9508 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 9509 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 9510 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 9511 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 9512 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 9513 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 9514 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 9515 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 9516 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 9517 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 9518 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 9519 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 9520 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 9521 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 9522 9523 WREG32(pb_addr + word_offset, ~mask); 9524 9525 pb_addr = (mmTPC0_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 9526 word_offset = ((mmTPC0_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 9527 << 2; 9528 mask = 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 9529 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 9530 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 9531 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 9532 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 9533 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 9534 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 9535 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 9536 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 9537 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 9538 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 9539 mask |= 1U << ((mmTPC0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 9540 mask |= 1U << ((mmTPC0_QM_CGM_CFG & 0x7F) >> 2); 9541 mask |= 1U << ((mmTPC0_QM_CGM_STS & 0x7F) >> 2); 9542 mask |= 1U << ((mmTPC0_QM_CGM_CFG1 & 0x7F) >> 2); 9543 9544 WREG32(pb_addr + word_offset, ~mask); 9545 9546 pb_addr = (mmTPC0_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 9547 word_offset = ((mmTPC0_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 9548 mask = 1U << ((mmTPC0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 9549 mask |= 1U << ((mmTPC0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 9550 mask |= 1U << ((mmTPC0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 9551 mask |= 1U << ((mmTPC0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 9552 mask |= 1U << ((mmTPC0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 9553 mask |= 1U << ((mmTPC0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 9554 mask |= 1U << ((mmTPC0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 9555 mask |= 1U << ((mmTPC0_QM_GLBL_AXCACHE & 0x7F) >> 2); 9556 mask |= 1U << ((mmTPC0_QM_IND_GW_APB_CFG & 0x7F) >> 2); 9557 mask |= 1U << ((mmTPC0_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 9558 mask |= 1U << ((mmTPC0_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 9559 mask |= 1U << ((mmTPC0_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 9560 mask |= 1U << ((mmTPC0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 9561 mask |= 1U << ((mmTPC0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 9562 mask |= 1U << ((mmTPC0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 9563 9564 WREG32(pb_addr + word_offset, ~mask); 9565 9566 pb_addr = (mmTPC0_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 9567 word_offset = ((mmTPC0_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 9568 << 2; 9569 mask = 1U << ((mmTPC0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 9570 9571 WREG32(pb_addr + word_offset, ~mask); 9572 9573 pb_addr = (mmTPC0_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; 9574 word_offset = ((mmTPC0_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; 9575 mask = 1U << ((mmTPC0_CFG_ROUND_CSR & 0x7F) >> 2); 9576 9577 WREG32(pb_addr + word_offset, ~mask); 9578 9579 pb_addr = (mmTPC0_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; 9580 word_offset = ((mmTPC0_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; 9581 mask = 1U << ((mmTPC0_CFG_PROT & 0x7F) >> 2); 9582 mask |= 1U << ((mmTPC0_CFG_VFLAGS & 0x7F) >> 2); 9583 mask |= 1U << ((mmTPC0_CFG_SFLAGS & 0x7F) >> 2); 9584 mask |= 1U << ((mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); 9585 mask |= 1U << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); 9586 mask |= 1U << ((mmTPC0_CFG_TPC_STALL & 0x7F) >> 2); 9587 mask |= 1U << ((mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH & 0x7F) >> 2); 9588 mask |= 1U << ((mmTPC0_CFG_RD_RATE_LIMIT & 0x7F) >> 2); 9589 mask |= 1U << ((mmTPC0_CFG_WR_RATE_LIMIT & 0x7F) >> 2); 9590 mask |= 1U << ((mmTPC0_CFG_MSS_CONFIG & 0x7F) >> 2); 9591 mask |= 1U << ((mmTPC0_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); 9592 mask |= 1U << ((mmTPC0_CFG_TPC_INTR_MASK & 0x7F) >> 2); 9593 mask |= 1U << ((mmTPC0_CFG_WQ_CREDITS & 0x7F) >> 2); 9594 mask |= 1U << ((mmTPC0_CFG_ARUSER_LO & 0x7F) >> 2); 9595 mask |= 1U << ((mmTPC0_CFG_ARUSER_HI & 0x7F) >> 2); 9596 mask |= 1U << ((mmTPC0_CFG_AWUSER_LO & 0x7F) >> 2); 9597 mask |= 1U << ((mmTPC0_CFG_AWUSER_HI & 0x7F) >> 2); 9598 mask |= 1U << ((mmTPC0_CFG_OPCODE_EXEC & 0x7F) >> 2); 9599 9600 WREG32(pb_addr + word_offset, ~mask); 9601 9602 pb_addr = (mmTPC0_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; 9603 word_offset = ((mmTPC0_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) 9604 << 2; 9605 mask = 1U << ((mmTPC0_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); 9606 mask |= 1U << ((mmTPC0_CFG_DBGMEM_ADD & 0x7F) >> 2); 9607 mask |= 1U << ((mmTPC0_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); 9608 mask |= 1U << ((mmTPC0_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); 9609 mask |= 1U << ((mmTPC0_CFG_DBGMEM_CTRL & 0x7F) >> 2); 9610 mask |= 1U << ((mmTPC0_CFG_DBGMEM_RC & 0x7F) >> 2); 9611 mask |= 1U << ((mmTPC0_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); 9612 mask |= 1U << ((mmTPC0_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); 9613 mask |= 1U << ((mmTPC0_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); 9614 mask |= 1U << ((mmTPC0_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); 9615 mask |= 1U << ((mmTPC0_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); 9616 mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); 9617 mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); 9618 mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); 9619 mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); 9620 mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); 9621 mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); 9622 mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); 9623 mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); 9624 mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); 9625 mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); 9626 mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); 9627 mask |= 1U << ((mmTPC0_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); 9628 9629 WREG32(pb_addr + word_offset, ~mask); 9630 9631 WREG32(mmTPC1_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 9632 WREG32(mmTPC1_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 9633 9634 pb_addr = (mmTPC1_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 9635 word_offset = ((mmTPC1_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 9636 mask = 1U << ((mmTPC1_QM_GLBL_CFG0 & 0x7F) >> 2); 9637 mask |= 1U << ((mmTPC1_QM_GLBL_CFG1 & 0x7F) >> 2); 9638 mask |= 1U << ((mmTPC1_QM_GLBL_PROT & 0x7F) >> 2); 9639 mask |= 1U << ((mmTPC1_QM_GLBL_ERR_CFG & 0x7F) >> 2); 9640 mask |= 1U << ((mmTPC1_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 9641 mask |= 1U << ((mmTPC1_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 9642 mask |= 1U << ((mmTPC1_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 9643 mask |= 1U << ((mmTPC1_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 9644 mask |= 1U << ((mmTPC1_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 9645 mask |= 1U << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 9646 mask |= 1U << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 9647 mask |= 1U << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 9648 mask |= 1U << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 9649 mask |= 1U << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 9650 mask |= 1U << ((mmTPC1_QM_GLBL_STS0 & 0x7F) >> 2); 9651 mask |= 1U << ((mmTPC1_QM_GLBL_STS1_0 & 0x7F) >> 2); 9652 mask |= 1U << ((mmTPC1_QM_GLBL_STS1_1 & 0x7F) >> 2); 9653 mask |= 1U << ((mmTPC1_QM_GLBL_STS1_2 & 0x7F) >> 2); 9654 mask |= 1U << ((mmTPC1_QM_GLBL_STS1_3 & 0x7F) >> 2); 9655 mask |= 1U << ((mmTPC1_QM_GLBL_STS1_4 & 0x7F) >> 2); 9656 mask |= 1U << ((mmTPC1_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 9657 mask |= 1U << ((mmTPC1_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 9658 mask |= 1U << ((mmTPC1_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 9659 mask |= 1U << ((mmTPC1_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 9660 mask |= 1U << ((mmTPC1_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 9661 mask |= 1U << ((mmTPC1_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 9662 mask |= 1U << ((mmTPC1_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 9663 mask |= 1U << ((mmTPC1_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 9664 mask |= 1U << ((mmTPC1_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 9665 9666 WREG32(pb_addr + word_offset, ~mask); 9667 9668 pb_addr = (mmTPC1_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 9669 word_offset = ((mmTPC1_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 9670 mask = 1U << ((mmTPC1_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 9671 mask |= 1U << ((mmTPC1_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 9672 mask |= 1U << ((mmTPC1_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 9673 mask |= 1U << ((mmTPC1_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 9674 mask |= 1U << ((mmTPC1_QM_PQ_SIZE_0 & 0x7F) >> 2); 9675 mask |= 1U << ((mmTPC1_QM_PQ_SIZE_1 & 0x7F) >> 2); 9676 mask |= 1U << ((mmTPC1_QM_PQ_SIZE_2 & 0x7F) >> 2); 9677 mask |= 1U << ((mmTPC1_QM_PQ_SIZE_3 & 0x7F) >> 2); 9678 mask |= 1U << ((mmTPC1_QM_PQ_PI_0 & 0x7F) >> 2); 9679 mask |= 1U << ((mmTPC1_QM_PQ_PI_1 & 0x7F) >> 2); 9680 mask |= 1U << ((mmTPC1_QM_PQ_PI_2 & 0x7F) >> 2); 9681 mask |= 1U << ((mmTPC1_QM_PQ_PI_3 & 0x7F) >> 2); 9682 mask |= 1U << ((mmTPC1_QM_PQ_CI_0 & 0x7F) >> 2); 9683 mask |= 1U << ((mmTPC1_QM_PQ_CI_1 & 0x7F) >> 2); 9684 mask |= 1U << ((mmTPC1_QM_PQ_CI_2 & 0x7F) >> 2); 9685 mask |= 1U << ((mmTPC1_QM_PQ_CI_3 & 0x7F) >> 2); 9686 mask |= 1U << ((mmTPC1_QM_PQ_CFG0_0 & 0x7F) >> 2); 9687 mask |= 1U << ((mmTPC1_QM_PQ_CFG0_1 & 0x7F) >> 2); 9688 mask |= 1U << ((mmTPC1_QM_PQ_CFG0_2 & 0x7F) >> 2); 9689 mask |= 1U << ((mmTPC1_QM_PQ_CFG0_3 & 0x7F) >> 2); 9690 mask |= 1U << ((mmTPC1_QM_PQ_CFG1_0 & 0x7F) >> 2); 9691 mask |= 1U << ((mmTPC1_QM_PQ_CFG1_1 & 0x7F) >> 2); 9692 mask |= 1U << ((mmTPC1_QM_PQ_CFG1_2 & 0x7F) >> 2); 9693 mask |= 1U << ((mmTPC1_QM_PQ_CFG1_3 & 0x7F) >> 2); 9694 mask |= 1U << ((mmTPC1_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 9695 mask |= 1U << ((mmTPC1_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 9696 mask |= 1U << ((mmTPC1_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 9697 mask |= 1U << ((mmTPC1_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 9698 mask |= 1U << ((mmTPC1_QM_PQ_STS0_0 & 0x7F) >> 2); 9699 mask |= 1U << ((mmTPC1_QM_PQ_STS0_1 & 0x7F) >> 2); 9700 mask |= 1U << ((mmTPC1_QM_PQ_STS0_2 & 0x7F) >> 2); 9701 mask |= 1U << ((mmTPC1_QM_PQ_STS0_3 & 0x7F) >> 2); 9702 9703 WREG32(pb_addr + word_offset, ~mask); 9704 9705 pb_addr = (mmTPC1_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 9706 word_offset = ((mmTPC1_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 9707 mask = 1U << ((mmTPC1_QM_PQ_STS1_0 & 0x7F) >> 2); 9708 mask |= 1U << ((mmTPC1_QM_PQ_STS1_1 & 0x7F) >> 2); 9709 mask |= 1U << ((mmTPC1_QM_PQ_STS1_2 & 0x7F) >> 2); 9710 mask |= 1U << ((mmTPC1_QM_PQ_STS1_3 & 0x7F) >> 2); 9711 mask |= 1U << ((mmTPC1_QM_CQ_STS0_0 & 0x7F) >> 2); 9712 mask |= 1U << ((mmTPC1_QM_CQ_STS0_1 & 0x7F) >> 2); 9713 mask |= 1U << ((mmTPC1_QM_CQ_STS0_2 & 0x7F) >> 2); 9714 mask |= 1U << ((mmTPC1_QM_CQ_STS0_3 & 0x7F) >> 2); 9715 mask |= 1U << ((mmTPC1_QM_CQ_STS1_0 & 0x7F) >> 2); 9716 mask |= 1U << ((mmTPC1_QM_CQ_STS1_1 & 0x7F) >> 2); 9717 mask |= 1U << ((mmTPC1_QM_CQ_STS1_2 & 0x7F) >> 2); 9718 mask |= 1U << ((mmTPC1_QM_CQ_STS1_3 & 0x7F) >> 2); 9719 mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 9720 mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 9721 mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_0 & 0x7F) >> 2); 9722 9723 WREG32(pb_addr + word_offset, ~mask); 9724 9725 pb_addr = (mmTPC1_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 9726 word_offset = ((mmTPC1_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 9727 mask = 1U << ((mmTPC1_QM_CQ_CTL_0 & 0x7F) >> 2); 9728 mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 9729 mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 9730 mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_1 & 0x7F) >> 2); 9731 mask |= 1U << ((mmTPC1_QM_CQ_CTL_1 & 0x7F) >> 2); 9732 mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 9733 mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 9734 mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_2 & 0x7F) >> 2); 9735 mask |= 1U << ((mmTPC1_QM_CQ_CTL_2 & 0x7F) >> 2); 9736 mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 9737 mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 9738 mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_3 & 0x7F) >> 2); 9739 mask |= 1U << ((mmTPC1_QM_CQ_CTL_3 & 0x7F) >> 2); 9740 mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 9741 mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 9742 mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 9743 mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 9744 mask |= 1U << ((mmTPC1_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 9745 mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 9746 mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 9747 mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 9748 mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 9749 mask |= 1U << ((mmTPC1_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 9750 mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 9751 mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 9752 mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 9753 mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 9754 mask |= 1U << ((mmTPC1_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 9755 9756 WREG32(pb_addr + word_offset, ~mask); 9757 9758 pb_addr = (mmTPC1_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 9759 word_offset = ((mmTPC1_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 9760 mask = 1U << ((mmTPC1_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 9761 mask |= 1U << ((mmTPC1_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 9762 mask |= 1U << ((mmTPC1_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 9763 mask |= 1U << ((mmTPC1_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 9764 mask |= 1U << ((mmTPC1_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 9765 mask |= 1U << ((mmTPC1_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 9766 mask |= 1U << ((mmTPC1_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 9767 mask |= 1U << ((mmTPC1_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 9768 mask |= 1U << ((mmTPC1_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 9769 mask |= 1U << ((mmTPC1_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 9770 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 9771 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 9772 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 9773 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 9774 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 9775 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 9776 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 9777 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 9778 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 9779 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 9780 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 9781 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 9782 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 9783 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 9784 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 9785 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 9786 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 9787 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 9788 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 9789 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 9790 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 9791 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 9792 9793 WREG32(pb_addr + word_offset, ~mask); 9794 9795 pb_addr = (mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 9796 word_offset = ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 9797 << 2; 9798 mask = 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 9799 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 9800 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 9801 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 9802 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 9803 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 9804 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 9805 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 9806 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 9807 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 9808 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 9809 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 9810 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 9811 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 9812 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 9813 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 9814 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 9815 mask |= 1U << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 9816 mask |= 1U << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 9817 mask |= 1U << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 9818 mask |= 1U << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 9819 mask |= 1U << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 9820 mask |= 1U << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 9821 mask |= 1U << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 9822 mask |= 1U << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 9823 mask |= 1U << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 9824 mask |= 1U << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 9825 mask |= 1U << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 9826 mask |= 1U << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 9827 mask |= 1U << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 9828 mask |= 1U << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 9829 9830 WREG32(pb_addr + word_offset, ~mask); 9831 9832 pb_addr = (mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 9833 PROT_BITS_OFFS; 9834 word_offset = ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) 9835 >> 7) << 2; 9836 mask = 1U << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 9837 mask |= 1U << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 9838 9839 WREG32(pb_addr + word_offset, ~mask); 9840 9841 pb_addr = (mmTPC1_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 9842 word_offset = ((mmTPC1_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 9843 mask = 1U << ((mmTPC1_QM_CP_STS_0 & 0x7F) >> 2); 9844 mask |= 1U << ((mmTPC1_QM_CP_STS_1 & 0x7F) >> 2); 9845 mask |= 1U << ((mmTPC1_QM_CP_STS_2 & 0x7F) >> 2); 9846 mask |= 1U << ((mmTPC1_QM_CP_STS_3 & 0x7F) >> 2); 9847 mask |= 1U << ((mmTPC1_QM_CP_STS_4 & 0x7F) >> 2); 9848 mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 9849 mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 9850 mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 9851 mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 9852 mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 9853 mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 9854 mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 9855 mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 9856 mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 9857 mask |= 1U << ((mmTPC1_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 9858 mask |= 1U << ((mmTPC1_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 9859 mask |= 1U << ((mmTPC1_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 9860 mask |= 1U << ((mmTPC1_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 9861 9862 WREG32(pb_addr + word_offset, ~mask); 9863 9864 pb_addr = (mmTPC1_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 9865 word_offset = ((mmTPC1_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 9866 mask = 1U << ((mmTPC1_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 9867 mask |= 1U << ((mmTPC1_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 9868 mask |= 1U << ((mmTPC1_QM_CP_DBG_0_0 & 0x7F) >> 2); 9869 mask |= 1U << ((mmTPC1_QM_CP_DBG_0_1 & 0x7F) >> 2); 9870 9871 WREG32(pb_addr + word_offset, ~mask); 9872 9873 pb_addr = (mmTPC1_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 9874 word_offset = ((mmTPC1_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 9875 mask = 1U << ((mmTPC1_QM_CP_DBG_0_2 & 0x7F) >> 2); 9876 mask |= 1U << ((mmTPC1_QM_CP_DBG_0_3 & 0x7F) >> 2); 9877 mask |= 1U << ((mmTPC1_QM_CP_DBG_0_4 & 0x7F) >> 2); 9878 mask |= 1U << ((mmTPC1_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 9879 mask |= 1U << ((mmTPC1_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 9880 mask |= 1U << ((mmTPC1_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 9881 mask |= 1U << ((mmTPC1_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 9882 mask |= 1U << ((mmTPC1_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 9883 mask |= 1U << ((mmTPC1_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 9884 mask |= 1U << ((mmTPC1_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 9885 mask |= 1U << ((mmTPC1_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 9886 mask |= 1U << ((mmTPC1_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 9887 mask |= 1U << ((mmTPC1_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 9888 9889 WREG32(pb_addr + word_offset, ~mask); 9890 9891 pb_addr = (mmTPC1_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 9892 word_offset = ((mmTPC1_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 9893 mask = 1U << ((mmTPC1_QM_ARB_CFG_1 & 0x7F) >> 2); 9894 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 9895 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 9896 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 9897 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 9898 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 9899 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 9900 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 9901 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 9902 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 9903 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 9904 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 9905 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 9906 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 9907 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 9908 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 9909 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 9910 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 9911 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 9912 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 9913 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 9914 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 9915 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 9916 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 9917 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 9918 9919 WREG32(pb_addr + word_offset, ~mask); 9920 9921 pb_addr = (mmTPC1_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 9922 word_offset = ((mmTPC1_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 9923 << 2; 9924 mask = 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 9925 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 9926 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 9927 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 9928 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 9929 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 9930 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 9931 mask |= 1U << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 9932 9933 WREG32(pb_addr + word_offset, ~mask); 9934 9935 pb_addr = (mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 9936 PROT_BITS_OFFS; 9937 9938 word_offset = ((mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) 9939 >> 7) << 2; 9940 mask = 1U << ((mmTPC1_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 9941 mask |= 1U << ((mmTPC1_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 9942 mask |= 1U << ((mmTPC1_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 9943 mask |= 1U << ((mmTPC1_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 9944 mask |= 1U << ((mmTPC1_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 9945 9946 WREG32(pb_addr + word_offset, ~mask); 9947 9948 pb_addr = (mmTPC1_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 9949 word_offset = ((mmTPC1_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 9950 mask = 1U << ((mmTPC1_QM_ARB_STATE_STS & 0x7F) >> 2); 9951 mask |= 1U << ((mmTPC1_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 9952 mask |= 1U << ((mmTPC1_QM_ARB_MSG_STS & 0x7F) >> 2); 9953 mask |= 1U << ((mmTPC1_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 9954 mask |= 1U << ((mmTPC1_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 9955 mask |= 1U << ((mmTPC1_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 9956 mask |= 1U << ((mmTPC1_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 9957 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 9958 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 9959 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 9960 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 9961 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 9962 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 9963 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 9964 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 9965 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 9966 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 9967 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 9968 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 9969 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 9970 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 9971 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 9972 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 9973 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 9974 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 9975 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 9976 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 9977 9978 WREG32(pb_addr + word_offset, ~mask); 9979 9980 pb_addr = (mmTPC1_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 9981 word_offset = ((mmTPC1_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 9982 << 2; 9983 mask = 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 9984 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 9985 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 9986 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 9987 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 9988 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 9989 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 9990 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 9991 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 9992 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 9993 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 9994 mask |= 1U << ((mmTPC1_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 9995 mask |= 1U << ((mmTPC1_QM_CGM_CFG & 0x7F) >> 2); 9996 mask |= 1U << ((mmTPC1_QM_CGM_STS & 0x7F) >> 2); 9997 mask |= 1U << ((mmTPC1_QM_CGM_CFG1 & 0x7F) >> 2); 9998 9999 WREG32(pb_addr + word_offset, ~mask); 10000 10001 pb_addr = (mmTPC1_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 10002 word_offset = ((mmTPC1_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 10003 mask = 1U << ((mmTPC1_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 10004 mask |= 1U << ((mmTPC1_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 10005 mask |= 1U << ((mmTPC1_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 10006 mask |= 1U << ((mmTPC1_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 10007 mask |= 1U << ((mmTPC1_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 10008 mask |= 1U << ((mmTPC1_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 10009 mask |= 1U << ((mmTPC1_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 10010 mask |= 1U << ((mmTPC1_QM_GLBL_AXCACHE & 0x7F) >> 2); 10011 mask |= 1U << ((mmTPC1_QM_IND_GW_APB_CFG & 0x7F) >> 2); 10012 mask |= 1U << ((mmTPC1_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 10013 mask |= 1U << ((mmTPC1_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 10014 mask |= 1U << ((mmTPC1_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 10015 mask |= 1U << ((mmTPC1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 10016 mask |= 1U << ((mmTPC1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 10017 mask |= 1U << ((mmTPC1_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 10018 10019 WREG32(pb_addr + word_offset, ~mask); 10020 10021 pb_addr = (mmTPC1_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 10022 word_offset = ((mmTPC1_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 10023 << 2; 10024 mask = 1U << ((mmTPC1_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 10025 10026 WREG32(pb_addr + word_offset, ~mask); 10027 10028 pb_addr = (mmTPC1_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; 10029 word_offset = ((mmTPC1_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; 10030 mask = 1U << ((mmTPC1_CFG_ROUND_CSR & 0x7F) >> 2); 10031 10032 WREG32(pb_addr + word_offset, ~mask); 10033 10034 pb_addr = (mmTPC1_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; 10035 word_offset = ((mmTPC1_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; 10036 mask = 1U << ((mmTPC1_CFG_PROT & 0x7F) >> 2); 10037 mask |= 1U << ((mmTPC1_CFG_VFLAGS & 0x7F) >> 2); 10038 mask |= 1U << ((mmTPC1_CFG_SFLAGS & 0x7F) >> 2); 10039 mask |= 1U << ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); 10040 mask |= 1U << ((mmTPC1_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); 10041 mask |= 1U << ((mmTPC1_CFG_TPC_STALL & 0x7F) >> 2); 10042 mask |= 1U << ((mmTPC1_CFG_ICACHE_BASE_ADDERESS_HIGH & 0x7F) >> 2); 10043 mask |= 1U << ((mmTPC1_CFG_RD_RATE_LIMIT & 0x7F) >> 2); 10044 mask |= 1U << ((mmTPC1_CFG_WR_RATE_LIMIT & 0x7F) >> 2); 10045 mask |= 1U << ((mmTPC1_CFG_MSS_CONFIG & 0x7F) >> 2); 10046 mask |= 1U << ((mmTPC1_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); 10047 mask |= 1U << ((mmTPC1_CFG_TPC_INTR_MASK & 0x7F) >> 2); 10048 mask |= 1U << ((mmTPC1_CFG_WQ_CREDITS & 0x7F) >> 2); 10049 mask |= 1U << ((mmTPC1_CFG_ARUSER_LO & 0x7F) >> 2); 10050 mask |= 1U << ((mmTPC1_CFG_ARUSER_HI & 0x7F) >> 2); 10051 mask |= 1U << ((mmTPC1_CFG_AWUSER_LO & 0x7F) >> 2); 10052 mask |= 1U << ((mmTPC1_CFG_AWUSER_HI & 0x7F) >> 2); 10053 mask |= 1U << ((mmTPC1_CFG_OPCODE_EXEC & 0x7F) >> 2); 10054 10055 WREG32(pb_addr + word_offset, ~mask); 10056 10057 pb_addr = (mmTPC1_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; 10058 word_offset = ((mmTPC1_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) 10059 << 2; 10060 mask = 1U << ((mmTPC1_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); 10061 mask |= 1U << ((mmTPC1_CFG_DBGMEM_ADD & 0x7F) >> 2); 10062 mask |= 1U << ((mmTPC1_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); 10063 mask |= 1U << ((mmTPC1_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); 10064 mask |= 1U << ((mmTPC1_CFG_DBGMEM_CTRL & 0x7F) >> 2); 10065 mask |= 1U << ((mmTPC1_CFG_DBGMEM_RC & 0x7F) >> 2); 10066 mask |= 1U << ((mmTPC1_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); 10067 mask |= 1U << ((mmTPC1_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); 10068 mask |= 1U << ((mmTPC1_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); 10069 mask |= 1U << ((mmTPC1_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); 10070 mask |= 1U << ((mmTPC1_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); 10071 mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); 10072 mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); 10073 mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); 10074 mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); 10075 mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); 10076 mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); 10077 mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); 10078 mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); 10079 mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); 10080 mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); 10081 mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); 10082 mask |= 1U << ((mmTPC1_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); 10083 10084 WREG32(pb_addr + word_offset, ~mask); 10085 10086 WREG32(mmTPC2_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 10087 WREG32(mmTPC2_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 10088 10089 pb_addr = (mmTPC2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 10090 word_offset = ((mmTPC2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 10091 mask = 1U << ((mmTPC2_QM_GLBL_CFG0 & 0x7F) >> 2); 10092 mask |= 1U << ((mmTPC2_QM_GLBL_CFG1 & 0x7F) >> 2); 10093 mask |= 1U << ((mmTPC2_QM_GLBL_PROT & 0x7F) >> 2); 10094 mask |= 1U << ((mmTPC2_QM_GLBL_ERR_CFG & 0x7F) >> 2); 10095 mask |= 1U << ((mmTPC2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 10096 mask |= 1U << ((mmTPC2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 10097 mask |= 1U << ((mmTPC2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 10098 mask |= 1U << ((mmTPC2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 10099 mask |= 1U << ((mmTPC2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 10100 mask |= 1U << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 10101 mask |= 1U << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 10102 mask |= 1U << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 10103 mask |= 1U << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 10104 mask |= 1U << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 10105 mask |= 1U << ((mmTPC2_QM_GLBL_STS0 & 0x7F) >> 2); 10106 mask |= 1U << ((mmTPC2_QM_GLBL_STS1_0 & 0x7F) >> 2); 10107 mask |= 1U << ((mmTPC2_QM_GLBL_STS1_1 & 0x7F) >> 2); 10108 mask |= 1U << ((mmTPC2_QM_GLBL_STS1_2 & 0x7F) >> 2); 10109 mask |= 1U << ((mmTPC2_QM_GLBL_STS1_3 & 0x7F) >> 2); 10110 mask |= 1U << ((mmTPC2_QM_GLBL_STS1_4 & 0x7F) >> 2); 10111 mask |= 1U << ((mmTPC2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 10112 mask |= 1U << ((mmTPC2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 10113 mask |= 1U << ((mmTPC2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 10114 mask |= 1U << ((mmTPC2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 10115 mask |= 1U << ((mmTPC2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 10116 mask |= 1U << ((mmTPC2_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 10117 mask |= 1U << ((mmTPC2_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 10118 mask |= 1U << ((mmTPC2_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 10119 mask |= 1U << ((mmTPC2_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 10120 10121 WREG32(pb_addr + word_offset, ~mask); 10122 10123 pb_addr = (mmTPC2_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 10124 word_offset = ((mmTPC2_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 10125 mask = 1U << ((mmTPC2_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 10126 mask |= 1U << ((mmTPC2_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 10127 mask |= 1U << ((mmTPC2_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 10128 mask |= 1U << ((mmTPC2_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 10129 mask |= 1U << ((mmTPC2_QM_PQ_SIZE_0 & 0x7F) >> 2); 10130 mask |= 1U << ((mmTPC2_QM_PQ_SIZE_1 & 0x7F) >> 2); 10131 mask |= 1U << ((mmTPC2_QM_PQ_SIZE_2 & 0x7F) >> 2); 10132 mask |= 1U << ((mmTPC2_QM_PQ_SIZE_3 & 0x7F) >> 2); 10133 mask |= 1U << ((mmTPC2_QM_PQ_PI_0 & 0x7F) >> 2); 10134 mask |= 1U << ((mmTPC2_QM_PQ_PI_1 & 0x7F) >> 2); 10135 mask |= 1U << ((mmTPC2_QM_PQ_PI_2 & 0x7F) >> 2); 10136 mask |= 1U << ((mmTPC2_QM_PQ_PI_3 & 0x7F) >> 2); 10137 mask |= 1U << ((mmTPC2_QM_PQ_CI_0 & 0x7F) >> 2); 10138 mask |= 1U << ((mmTPC2_QM_PQ_CI_1 & 0x7F) >> 2); 10139 mask |= 1U << ((mmTPC2_QM_PQ_CI_2 & 0x7F) >> 2); 10140 mask |= 1U << ((mmTPC2_QM_PQ_CI_3 & 0x7F) >> 2); 10141 mask |= 1U << ((mmTPC2_QM_PQ_CFG0_0 & 0x7F) >> 2); 10142 mask |= 1U << ((mmTPC2_QM_PQ_CFG0_1 & 0x7F) >> 2); 10143 mask |= 1U << ((mmTPC2_QM_PQ_CFG0_2 & 0x7F) >> 2); 10144 mask |= 1U << ((mmTPC2_QM_PQ_CFG0_3 & 0x7F) >> 2); 10145 mask |= 1U << ((mmTPC2_QM_PQ_CFG1_0 & 0x7F) >> 2); 10146 mask |= 1U << ((mmTPC2_QM_PQ_CFG1_1 & 0x7F) >> 2); 10147 mask |= 1U << ((mmTPC2_QM_PQ_CFG1_2 & 0x7F) >> 2); 10148 mask |= 1U << ((mmTPC2_QM_PQ_CFG1_3 & 0x7F) >> 2); 10149 mask |= 1U << ((mmTPC2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 10150 mask |= 1U << ((mmTPC2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 10151 mask |= 1U << ((mmTPC2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 10152 mask |= 1U << ((mmTPC2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 10153 mask |= 1U << ((mmTPC2_QM_PQ_STS0_0 & 0x7F) >> 2); 10154 mask |= 1U << ((mmTPC2_QM_PQ_STS0_1 & 0x7F) >> 2); 10155 mask |= 1U << ((mmTPC2_QM_PQ_STS0_2 & 0x7F) >> 2); 10156 mask |= 1U << ((mmTPC2_QM_PQ_STS0_3 & 0x7F) >> 2); 10157 10158 WREG32(pb_addr + word_offset, ~mask); 10159 10160 pb_addr = (mmTPC2_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 10161 word_offset = ((mmTPC2_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 10162 mask = 1U << ((mmTPC2_QM_PQ_STS1_0 & 0x7F) >> 2); 10163 mask |= 1U << ((mmTPC2_QM_PQ_STS1_1 & 0x7F) >> 2); 10164 mask |= 1U << ((mmTPC2_QM_PQ_STS1_2 & 0x7F) >> 2); 10165 mask |= 1U << ((mmTPC2_QM_PQ_STS1_3 & 0x7F) >> 2); 10166 mask |= 1U << ((mmTPC2_QM_CQ_STS0_0 & 0x7F) >> 2); 10167 mask |= 1U << ((mmTPC2_QM_CQ_STS0_1 & 0x7F) >> 2); 10168 mask |= 1U << ((mmTPC2_QM_CQ_STS0_2 & 0x7F) >> 2); 10169 mask |= 1U << ((mmTPC2_QM_CQ_STS0_3 & 0x7F) >> 2); 10170 mask |= 1U << ((mmTPC2_QM_CQ_STS1_0 & 0x7F) >> 2); 10171 mask |= 1U << ((mmTPC2_QM_CQ_STS1_1 & 0x7F) >> 2); 10172 mask |= 1U << ((mmTPC2_QM_CQ_STS1_2 & 0x7F) >> 2); 10173 mask |= 1U << ((mmTPC2_QM_CQ_STS1_3 & 0x7F) >> 2); 10174 mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 10175 mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 10176 mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_0 & 0x7F) >> 2); 10177 10178 WREG32(pb_addr + word_offset, ~mask); 10179 10180 pb_addr = (mmTPC2_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 10181 word_offset = ((mmTPC2_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 10182 mask = 1U << ((mmTPC2_QM_CQ_CTL_0 & 0x7F) >> 2); 10183 mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 10184 mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 10185 mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_1 & 0x7F) >> 2); 10186 mask |= 1U << ((mmTPC2_QM_CQ_CTL_1 & 0x7F) >> 2); 10187 mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 10188 mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 10189 mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_2 & 0x7F) >> 2); 10190 mask |= 1U << ((mmTPC2_QM_CQ_CTL_2 & 0x7F) >> 2); 10191 mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 10192 mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 10193 mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_3 & 0x7F) >> 2); 10194 mask |= 1U << ((mmTPC2_QM_CQ_CTL_3 & 0x7F) >> 2); 10195 mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 10196 mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 10197 mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 10198 mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 10199 mask |= 1U << ((mmTPC2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 10200 mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 10201 mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 10202 mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 10203 mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 10204 mask |= 1U << ((mmTPC2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 10205 mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 10206 mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 10207 mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 10208 mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 10209 mask |= 1U << ((mmTPC2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 10210 10211 WREG32(pb_addr + word_offset, ~mask); 10212 10213 pb_addr = (mmTPC2_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 10214 word_offset = ((mmTPC2_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 10215 mask = 1U << ((mmTPC2_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 10216 mask |= 1U << ((mmTPC2_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 10217 mask |= 1U << ((mmTPC2_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 10218 mask |= 1U << ((mmTPC2_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 10219 mask |= 1U << ((mmTPC2_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 10220 mask |= 1U << ((mmTPC2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 10221 mask |= 1U << ((mmTPC2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 10222 mask |= 1U << ((mmTPC2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 10223 mask |= 1U << ((mmTPC2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 10224 mask |= 1U << ((mmTPC2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 10225 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 10226 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 10227 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 10228 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 10229 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 10230 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 10231 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 10232 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 10233 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 10234 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 10235 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 10236 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 10237 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 10238 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 10239 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 10240 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 10241 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 10242 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 10243 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 10244 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 10245 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 10246 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 10247 10248 WREG32(pb_addr + word_offset, ~mask); 10249 10250 pb_addr = (mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 10251 word_offset = ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 10252 << 2; 10253 mask = 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 10254 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 10255 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 10256 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 10257 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 10258 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 10259 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 10260 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 10261 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 10262 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 10263 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 10264 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 10265 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 10266 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 10267 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 10268 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 10269 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 10270 mask |= 1U << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 10271 mask |= 1U << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 10272 mask |= 1U << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 10273 mask |= 1U << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 10274 mask |= 1U << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 10275 mask |= 1U << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 10276 mask |= 1U << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 10277 mask |= 1U << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 10278 mask |= 1U << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 10279 mask |= 1U << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 10280 mask |= 1U << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 10281 mask |= 1U << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 10282 mask |= 1U << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 10283 mask |= 1U << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 10284 10285 WREG32(pb_addr + word_offset, ~mask); 10286 10287 pb_addr = (mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 10288 PROT_BITS_OFFS; 10289 word_offset = ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) 10290 >> 7) << 2; 10291 mask = 1U << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 10292 mask |= 1U << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 10293 10294 WREG32(pb_addr + word_offset, ~mask); 10295 10296 pb_addr = (mmTPC2_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 10297 word_offset = ((mmTPC2_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 10298 mask = 1U << ((mmTPC2_QM_CP_STS_0 & 0x7F) >> 2); 10299 mask |= 1U << ((mmTPC2_QM_CP_STS_1 & 0x7F) >> 2); 10300 mask |= 1U << ((mmTPC2_QM_CP_STS_2 & 0x7F) >> 2); 10301 mask |= 1U << ((mmTPC2_QM_CP_STS_3 & 0x7F) >> 2); 10302 mask |= 1U << ((mmTPC2_QM_CP_STS_4 & 0x7F) >> 2); 10303 mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 10304 mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 10305 mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 10306 mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 10307 mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 10308 mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 10309 mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 10310 mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 10311 mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 10312 mask |= 1U << ((mmTPC2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 10313 mask |= 1U << ((mmTPC2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 10314 mask |= 1U << ((mmTPC2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 10315 mask |= 1U << ((mmTPC2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 10316 10317 WREG32(pb_addr + word_offset, ~mask); 10318 10319 pb_addr = (mmTPC2_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 10320 word_offset = ((mmTPC2_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 10321 mask = 1U << ((mmTPC2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 10322 mask |= 1U << ((mmTPC2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 10323 mask |= 1U << ((mmTPC2_QM_CP_DBG_0_0 & 0x7F) >> 2); 10324 mask |= 1U << ((mmTPC2_QM_CP_DBG_0_1 & 0x7F) >> 2); 10325 10326 WREG32(pb_addr + word_offset, ~mask); 10327 10328 pb_addr = (mmTPC2_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 10329 word_offset = ((mmTPC2_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 10330 mask = 1U << ((mmTPC2_QM_CP_DBG_0_2 & 0x7F) >> 2); 10331 mask |= 1U << ((mmTPC2_QM_CP_DBG_0_3 & 0x7F) >> 2); 10332 mask |= 1U << ((mmTPC2_QM_CP_DBG_0_4 & 0x7F) >> 2); 10333 mask |= 1U << ((mmTPC2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 10334 mask |= 1U << ((mmTPC2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 10335 mask |= 1U << ((mmTPC2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 10336 mask |= 1U << ((mmTPC2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 10337 mask |= 1U << ((mmTPC2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 10338 mask |= 1U << ((mmTPC2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 10339 mask |= 1U << ((mmTPC2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 10340 mask |= 1U << ((mmTPC2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 10341 mask |= 1U << ((mmTPC2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 10342 mask |= 1U << ((mmTPC2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 10343 10344 WREG32(pb_addr + word_offset, ~mask); 10345 10346 pb_addr = (mmTPC2_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 10347 word_offset = ((mmTPC2_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 10348 mask = 1U << ((mmTPC2_QM_ARB_CFG_1 & 0x7F) >> 2); 10349 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 10350 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 10351 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 10352 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 10353 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 10354 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 10355 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 10356 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 10357 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 10358 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 10359 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 10360 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 10361 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 10362 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 10363 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 10364 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 10365 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 10366 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 10367 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 10368 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 10369 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 10370 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 10371 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 10372 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 10373 10374 WREG32(pb_addr + word_offset, ~mask); 10375 10376 pb_addr = (mmTPC2_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 10377 word_offset = ((mmTPC2_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 10378 << 2; 10379 mask = 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 10380 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 10381 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 10382 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 10383 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 10384 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 10385 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 10386 mask |= 1U << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 10387 10388 WREG32(pb_addr + word_offset, ~mask); 10389 10390 pb_addr = (mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 10391 PROT_BITS_OFFS; 10392 word_offset = ((mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) 10393 >> 7) << 2; 10394 mask = 1U << ((mmTPC2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 10395 mask |= 1U << ((mmTPC2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 10396 mask |= 1U << ((mmTPC2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 10397 mask |= 1U << ((mmTPC2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 10398 mask |= 1U << ((mmTPC2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 10399 10400 WREG32(pb_addr + word_offset, ~mask); 10401 10402 pb_addr = (mmTPC2_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 10403 word_offset = ((mmTPC2_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 10404 mask = 1U << ((mmTPC2_QM_ARB_STATE_STS & 0x7F) >> 2); 10405 mask |= 1U << ((mmTPC2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 10406 mask |= 1U << ((mmTPC2_QM_ARB_MSG_STS & 0x7F) >> 2); 10407 mask |= 1U << ((mmTPC2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 10408 mask |= 1U << ((mmTPC2_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 10409 mask |= 1U << ((mmTPC2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 10410 mask |= 1U << ((mmTPC2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 10411 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 10412 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 10413 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 10414 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 10415 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 10416 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 10417 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 10418 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 10419 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 10420 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 10421 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 10422 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 10423 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 10424 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 10425 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 10426 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 10427 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 10428 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 10429 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 10430 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 10431 10432 WREG32(pb_addr + word_offset, ~mask); 10433 10434 pb_addr = (mmTPC2_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 10435 word_offset = ((mmTPC2_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 10436 << 2; 10437 mask = 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 10438 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 10439 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 10440 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 10441 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 10442 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 10443 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 10444 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 10445 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 10446 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 10447 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 10448 mask |= 1U << ((mmTPC2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 10449 mask |= 1U << ((mmTPC2_QM_CGM_CFG & 0x7F) >> 2); 10450 mask |= 1U << ((mmTPC2_QM_CGM_STS & 0x7F) >> 2); 10451 mask |= 1U << ((mmTPC2_QM_CGM_CFG1 & 0x7F) >> 2); 10452 10453 WREG32(pb_addr + word_offset, ~mask); 10454 10455 pb_addr = (mmTPC2_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 10456 word_offset = ((mmTPC2_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 10457 mask = 1U << ((mmTPC2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 10458 mask |= 1U << ((mmTPC2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 10459 mask |= 1U << ((mmTPC2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 10460 mask |= 1U << ((mmTPC2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 10461 mask |= 1U << ((mmTPC2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 10462 mask |= 1U << ((mmTPC2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 10463 mask |= 1U << ((mmTPC2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 10464 mask |= 1U << ((mmTPC2_QM_GLBL_AXCACHE & 0x7F) >> 2); 10465 mask |= 1U << ((mmTPC2_QM_IND_GW_APB_CFG & 0x7F) >> 2); 10466 mask |= 1U << ((mmTPC2_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 10467 mask |= 1U << ((mmTPC2_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 10468 mask |= 1U << ((mmTPC2_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 10469 mask |= 1U << ((mmTPC2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 10470 mask |= 1U << ((mmTPC2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 10471 mask |= 1U << ((mmTPC2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 10472 10473 WREG32(pb_addr + word_offset, ~mask); 10474 10475 pb_addr = (mmTPC2_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 10476 word_offset = ((mmTPC2_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 10477 << 2; 10478 mask = 1U << ((mmTPC2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 10479 10480 WREG32(pb_addr + word_offset, ~mask); 10481 10482 pb_addr = (mmTPC2_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; 10483 word_offset = ((mmTPC2_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; 10484 mask = 1U << ((mmTPC2_CFG_ROUND_CSR & 0x7F) >> 2); 10485 10486 WREG32(pb_addr + word_offset, ~mask); 10487 10488 pb_addr = (mmTPC2_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; 10489 word_offset = ((mmTPC2_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; 10490 mask = 1U << ((mmTPC2_CFG_PROT & 0x7F) >> 2); 10491 mask |= 1U << ((mmTPC2_CFG_VFLAGS & 0x7F) >> 2); 10492 mask |= 1U << ((mmTPC2_CFG_SFLAGS & 0x7F) >> 2); 10493 mask |= 1U << ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); 10494 mask |= 1U << ((mmTPC2_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); 10495 mask |= 1U << ((mmTPC2_CFG_TPC_STALL & 0x7F) >> 2); 10496 mask |= 1U << ((mmTPC2_CFG_ICACHE_BASE_ADDERESS_HIGH & 0x7F) >> 2); 10497 mask |= 1U << ((mmTPC2_CFG_RD_RATE_LIMIT & 0x7F) >> 2); 10498 mask |= 1U << ((mmTPC2_CFG_WR_RATE_LIMIT & 0x7F) >> 2); 10499 mask |= 1U << ((mmTPC2_CFG_MSS_CONFIG & 0x7F) >> 2); 10500 mask |= 1U << ((mmTPC2_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); 10501 mask |= 1U << ((mmTPC2_CFG_TPC_INTR_MASK & 0x7F) >> 2); 10502 mask |= 1U << ((mmTPC2_CFG_WQ_CREDITS & 0x7F) >> 2); 10503 mask |= 1U << ((mmTPC2_CFG_ARUSER_LO & 0x7F) >> 2); 10504 mask |= 1U << ((mmTPC2_CFG_ARUSER_HI & 0x7F) >> 2); 10505 mask |= 1U << ((mmTPC2_CFG_AWUSER_LO & 0x7F) >> 2); 10506 mask |= 1U << ((mmTPC2_CFG_AWUSER_HI & 0x7F) >> 2); 10507 mask |= 1U << ((mmTPC2_CFG_OPCODE_EXEC & 0x7F) >> 2); 10508 10509 WREG32(pb_addr + word_offset, ~mask); 10510 10511 pb_addr = (mmTPC2_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; 10512 word_offset = ((mmTPC2_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) 10513 << 2; 10514 mask = 1U << ((mmTPC2_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); 10515 mask |= 1U << ((mmTPC2_CFG_DBGMEM_ADD & 0x7F) >> 2); 10516 mask |= 1U << ((mmTPC2_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); 10517 mask |= 1U << ((mmTPC2_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); 10518 mask |= 1U << ((mmTPC2_CFG_DBGMEM_CTRL & 0x7F) >> 2); 10519 mask |= 1U << ((mmTPC2_CFG_DBGMEM_RC & 0x7F) >> 2); 10520 mask |= 1U << ((mmTPC2_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); 10521 mask |= 1U << ((mmTPC2_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); 10522 mask |= 1U << ((mmTPC2_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); 10523 mask |= 1U << ((mmTPC2_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); 10524 mask |= 1U << ((mmTPC2_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); 10525 mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); 10526 mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); 10527 mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); 10528 mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); 10529 mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); 10530 mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); 10531 mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); 10532 mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); 10533 mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); 10534 mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); 10535 mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); 10536 mask |= 1U << ((mmTPC2_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); 10537 10538 WREG32(pb_addr + word_offset, ~mask); 10539 10540 WREG32(mmTPC3_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 10541 WREG32(mmTPC3_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 10542 10543 pb_addr = (mmTPC3_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 10544 word_offset = ((mmTPC3_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 10545 mask = 1U << ((mmTPC3_QM_GLBL_CFG0 & 0x7F) >> 2); 10546 mask |= 1U << ((mmTPC3_QM_GLBL_CFG1 & 0x7F) >> 2); 10547 mask |= 1U << ((mmTPC3_QM_GLBL_PROT & 0x7F) >> 2); 10548 mask |= 1U << ((mmTPC3_QM_GLBL_ERR_CFG & 0x7F) >> 2); 10549 mask |= 1U << ((mmTPC3_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 10550 mask |= 1U << ((mmTPC3_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 10551 mask |= 1U << ((mmTPC3_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 10552 mask |= 1U << ((mmTPC3_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 10553 mask |= 1U << ((mmTPC3_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 10554 mask |= 1U << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 10555 mask |= 1U << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 10556 mask |= 1U << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 10557 mask |= 1U << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 10558 mask |= 1U << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 10559 mask |= 1U << ((mmTPC3_QM_GLBL_STS0 & 0x7F) >> 2); 10560 mask |= 1U << ((mmTPC3_QM_GLBL_STS1_0 & 0x7F) >> 2); 10561 mask |= 1U << ((mmTPC3_QM_GLBL_STS1_1 & 0x7F) >> 2); 10562 mask |= 1U << ((mmTPC3_QM_GLBL_STS1_2 & 0x7F) >> 2); 10563 mask |= 1U << ((mmTPC3_QM_GLBL_STS1_3 & 0x7F) >> 2); 10564 mask |= 1U << ((mmTPC3_QM_GLBL_STS1_4 & 0x7F) >> 2); 10565 mask |= 1U << ((mmTPC3_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 10566 mask |= 1U << ((mmTPC3_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 10567 mask |= 1U << ((mmTPC3_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 10568 mask |= 1U << ((mmTPC3_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 10569 mask |= 1U << ((mmTPC3_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 10570 mask |= 1U << ((mmTPC3_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 10571 mask |= 1U << ((mmTPC3_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 10572 mask |= 1U << ((mmTPC3_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 10573 mask |= 1U << ((mmTPC3_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 10574 10575 WREG32(pb_addr + word_offset, ~mask); 10576 10577 pb_addr = (mmTPC3_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 10578 word_offset = ((mmTPC3_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 10579 mask = 1U << ((mmTPC3_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 10580 mask |= 1U << ((mmTPC3_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 10581 mask |= 1U << ((mmTPC3_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 10582 mask |= 1U << ((mmTPC3_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 10583 mask |= 1U << ((mmTPC3_QM_PQ_SIZE_0 & 0x7F) >> 2); 10584 mask |= 1U << ((mmTPC3_QM_PQ_SIZE_1 & 0x7F) >> 2); 10585 mask |= 1U << ((mmTPC3_QM_PQ_SIZE_2 & 0x7F) >> 2); 10586 mask |= 1U << ((mmTPC3_QM_PQ_SIZE_3 & 0x7F) >> 2); 10587 mask |= 1U << ((mmTPC3_QM_PQ_PI_0 & 0x7F) >> 2); 10588 mask |= 1U << ((mmTPC3_QM_PQ_PI_1 & 0x7F) >> 2); 10589 mask |= 1U << ((mmTPC3_QM_PQ_PI_2 & 0x7F) >> 2); 10590 mask |= 1U << ((mmTPC3_QM_PQ_PI_3 & 0x7F) >> 2); 10591 mask |= 1U << ((mmTPC3_QM_PQ_CI_0 & 0x7F) >> 2); 10592 mask |= 1U << ((mmTPC3_QM_PQ_CI_1 & 0x7F) >> 2); 10593 mask |= 1U << ((mmTPC3_QM_PQ_CI_2 & 0x7F) >> 2); 10594 mask |= 1U << ((mmTPC3_QM_PQ_CI_3 & 0x7F) >> 2); 10595 mask |= 1U << ((mmTPC3_QM_PQ_CFG0_0 & 0x7F) >> 2); 10596 mask |= 1U << ((mmTPC3_QM_PQ_CFG0_1 & 0x7F) >> 2); 10597 mask |= 1U << ((mmTPC3_QM_PQ_CFG0_2 & 0x7F) >> 2); 10598 mask |= 1U << ((mmTPC3_QM_PQ_CFG0_3 & 0x7F) >> 2); 10599 mask |= 1U << ((mmTPC3_QM_PQ_CFG1_0 & 0x7F) >> 2); 10600 mask |= 1U << ((mmTPC3_QM_PQ_CFG1_1 & 0x7F) >> 2); 10601 mask |= 1U << ((mmTPC3_QM_PQ_CFG1_2 & 0x7F) >> 2); 10602 mask |= 1U << ((mmTPC3_QM_PQ_CFG1_3 & 0x7F) >> 2); 10603 mask |= 1U << ((mmTPC3_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 10604 mask |= 1U << ((mmTPC3_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 10605 mask |= 1U << ((mmTPC3_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 10606 mask |= 1U << ((mmTPC3_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 10607 mask |= 1U << ((mmTPC3_QM_PQ_STS0_0 & 0x7F) >> 2); 10608 mask |= 1U << ((mmTPC3_QM_PQ_STS0_1 & 0x7F) >> 2); 10609 mask |= 1U << ((mmTPC3_QM_PQ_STS0_2 & 0x7F) >> 2); 10610 mask |= 1U << ((mmTPC3_QM_PQ_STS0_3 & 0x7F) >> 2); 10611 10612 WREG32(pb_addr + word_offset, ~mask); 10613 10614 pb_addr = (mmTPC3_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 10615 word_offset = ((mmTPC3_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 10616 mask = 1U << ((mmTPC3_QM_PQ_STS1_0 & 0x7F) >> 2); 10617 mask |= 1U << ((mmTPC3_QM_PQ_STS1_1 & 0x7F) >> 2); 10618 mask |= 1U << ((mmTPC3_QM_PQ_STS1_2 & 0x7F) >> 2); 10619 mask |= 1U << ((mmTPC3_QM_PQ_STS1_3 & 0x7F) >> 2); 10620 mask |= 1U << ((mmTPC3_QM_CQ_STS0_0 & 0x7F) >> 2); 10621 mask |= 1U << ((mmTPC3_QM_CQ_STS0_1 & 0x7F) >> 2); 10622 mask |= 1U << ((mmTPC3_QM_CQ_STS0_2 & 0x7F) >> 2); 10623 mask |= 1U << ((mmTPC3_QM_CQ_STS0_3 & 0x7F) >> 2); 10624 mask |= 1U << ((mmTPC3_QM_CQ_STS1_0 & 0x7F) >> 2); 10625 mask |= 1U << ((mmTPC3_QM_CQ_STS1_1 & 0x7F) >> 2); 10626 mask |= 1U << ((mmTPC3_QM_CQ_STS1_2 & 0x7F) >> 2); 10627 mask |= 1U << ((mmTPC3_QM_CQ_STS1_3 & 0x7F) >> 2); 10628 mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 10629 mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 10630 mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_0 & 0x7F) >> 2); 10631 10632 WREG32(pb_addr + word_offset, ~mask); 10633 10634 pb_addr = (mmTPC3_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 10635 word_offset = ((mmTPC3_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 10636 mask = 1U << ((mmTPC3_QM_CQ_CTL_0 & 0x7F) >> 2); 10637 mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 10638 mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 10639 mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_1 & 0x7F) >> 2); 10640 mask |= 1U << ((mmTPC3_QM_CQ_CTL_1 & 0x7F) >> 2); 10641 mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 10642 mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 10643 mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_2 & 0x7F) >> 2); 10644 mask |= 1U << ((mmTPC3_QM_CQ_CTL_2 & 0x7F) >> 2); 10645 mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 10646 mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 10647 mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_3 & 0x7F) >> 2); 10648 mask |= 1U << ((mmTPC3_QM_CQ_CTL_3 & 0x7F) >> 2); 10649 mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 10650 mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 10651 mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 10652 mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 10653 mask |= 1U << ((mmTPC3_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 10654 mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 10655 mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 10656 mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 10657 mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 10658 mask |= 1U << ((mmTPC3_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 10659 mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 10660 mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 10661 mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 10662 mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 10663 mask |= 1U << ((mmTPC3_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 10664 10665 WREG32(pb_addr + word_offset, ~mask); 10666 10667 pb_addr = (mmTPC3_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 10668 word_offset = ((mmTPC3_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 10669 mask = 1U << ((mmTPC3_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 10670 mask |= 1U << ((mmTPC3_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 10671 mask |= 1U << ((mmTPC3_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 10672 mask |= 1U << ((mmTPC3_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 10673 mask |= 1U << ((mmTPC3_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 10674 mask |= 1U << ((mmTPC3_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 10675 mask |= 1U << ((mmTPC3_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 10676 mask |= 1U << ((mmTPC3_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 10677 mask |= 1U << ((mmTPC3_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 10678 mask |= 1U << ((mmTPC3_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 10679 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 10680 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 10681 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 10682 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 10683 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 10684 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 10685 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 10686 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 10687 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 10688 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 10689 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 10690 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 10691 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 10692 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 10693 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 10694 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 10695 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 10696 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 10697 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 10698 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 10699 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 10700 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 10701 10702 WREG32(pb_addr + word_offset, ~mask); 10703 10704 pb_addr = (mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 10705 word_offset = ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 10706 << 2; 10707 mask = 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 10708 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 10709 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 10710 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 10711 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 10712 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 10713 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 10714 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 10715 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 10716 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 10717 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 10718 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 10719 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 10720 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 10721 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 10722 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 10723 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 10724 mask |= 1U << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 10725 mask |= 1U << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 10726 mask |= 1U << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 10727 mask |= 1U << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 10728 mask |= 1U << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 10729 mask |= 1U << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 10730 mask |= 1U << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 10731 mask |= 1U << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 10732 mask |= 1U << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 10733 mask |= 1U << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 10734 mask |= 1U << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 10735 mask |= 1U << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 10736 mask |= 1U << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 10737 mask |= 1U << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 10738 10739 WREG32(pb_addr + word_offset, ~mask); 10740 10741 pb_addr = (mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 10742 PROT_BITS_OFFS; 10743 word_offset = ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) 10744 >> 7) << 2; 10745 mask = 1U << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 10746 mask |= 1U << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 10747 10748 WREG32(pb_addr + word_offset, ~mask); 10749 10750 pb_addr = (mmTPC3_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 10751 word_offset = ((mmTPC3_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 10752 mask = 1U << ((mmTPC3_QM_CP_STS_0 & 0x7F) >> 2); 10753 mask |= 1U << ((mmTPC3_QM_CP_STS_1 & 0x7F) >> 2); 10754 mask |= 1U << ((mmTPC3_QM_CP_STS_2 & 0x7F) >> 2); 10755 mask |= 1U << ((mmTPC3_QM_CP_STS_3 & 0x7F) >> 2); 10756 mask |= 1U << ((mmTPC3_QM_CP_STS_4 & 0x7F) >> 2); 10757 mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 10758 mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 10759 mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 10760 mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 10761 mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 10762 mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 10763 mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 10764 mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 10765 mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 10766 mask |= 1U << ((mmTPC3_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 10767 mask |= 1U << ((mmTPC3_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 10768 mask |= 1U << ((mmTPC3_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 10769 mask |= 1U << ((mmTPC3_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 10770 10771 WREG32(pb_addr + word_offset, ~mask); 10772 10773 pb_addr = (mmTPC3_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 10774 word_offset = ((mmTPC3_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 10775 mask = 1U << ((mmTPC3_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 10776 mask |= 1U << ((mmTPC3_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 10777 mask |= 1U << ((mmTPC3_QM_CP_DBG_0_0 & 0x7F) >> 2); 10778 mask |= 1U << ((mmTPC3_QM_CP_DBG_0_1 & 0x7F) >> 2); 10779 10780 WREG32(pb_addr + word_offset, ~mask); 10781 10782 pb_addr = (mmTPC3_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 10783 word_offset = ((mmTPC3_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 10784 mask = 1U << ((mmTPC3_QM_CP_DBG_0_2 & 0x7F) >> 2); 10785 mask |= 1U << ((mmTPC3_QM_CP_DBG_0_3 & 0x7F) >> 2); 10786 mask |= 1U << ((mmTPC3_QM_CP_DBG_0_4 & 0x7F) >> 2); 10787 mask |= 1U << ((mmTPC3_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 10788 mask |= 1U << ((mmTPC3_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 10789 mask |= 1U << ((mmTPC3_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 10790 mask |= 1U << ((mmTPC3_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 10791 mask |= 1U << ((mmTPC3_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 10792 mask |= 1U << ((mmTPC3_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 10793 mask |= 1U << ((mmTPC3_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 10794 mask |= 1U << ((mmTPC3_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 10795 mask |= 1U << ((mmTPC3_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 10796 mask |= 1U << ((mmTPC3_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 10797 10798 WREG32(pb_addr + word_offset, ~mask); 10799 10800 pb_addr = (mmTPC3_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 10801 word_offset = ((mmTPC3_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 10802 mask = 1U << ((mmTPC3_QM_ARB_CFG_1 & 0x7F) >> 2); 10803 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 10804 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 10805 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 10806 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 10807 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 10808 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 10809 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 10810 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 10811 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 10812 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 10813 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 10814 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 10815 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 10816 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 10817 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 10818 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 10819 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 10820 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 10821 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 10822 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 10823 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 10824 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 10825 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 10826 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 10827 10828 WREG32(pb_addr + word_offset, ~mask); 10829 10830 pb_addr = (mmTPC3_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 10831 word_offset = ((mmTPC3_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 10832 << 2; 10833 mask = 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 10834 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 10835 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 10836 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 10837 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 10838 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 10839 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 10840 mask |= 1U << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 10841 10842 WREG32(pb_addr + word_offset, ~mask); 10843 10844 pb_addr = (mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 10845 PROT_BITS_OFFS; 10846 word_offset = ((mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) 10847 >> 7) << 2; 10848 mask = 1U << ((mmTPC3_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 10849 mask |= 1U << ((mmTPC3_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 10850 mask |= 1U << ((mmTPC3_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 10851 mask |= 1U << ((mmTPC3_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 10852 mask |= 1U << ((mmTPC3_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 10853 10854 WREG32(pb_addr + word_offset, ~mask); 10855 10856 pb_addr = (mmTPC3_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 10857 word_offset = ((mmTPC3_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 10858 mask = 1U << ((mmTPC3_QM_ARB_STATE_STS & 0x7F) >> 2); 10859 mask |= 1U << ((mmTPC3_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 10860 mask |= 1U << ((mmTPC3_QM_ARB_MSG_STS & 0x7F) >> 2); 10861 mask |= 1U << ((mmTPC3_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 10862 mask |= 1U << ((mmTPC3_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 10863 mask |= 1U << ((mmTPC3_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 10864 mask |= 1U << ((mmTPC3_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 10865 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 10866 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 10867 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 10868 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 10869 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 10870 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 10871 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 10872 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 10873 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 10874 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 10875 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 10876 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 10877 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 10878 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 10879 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 10880 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 10881 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 10882 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 10883 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 10884 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 10885 10886 WREG32(pb_addr + word_offset, ~mask); 10887 10888 pb_addr = (mmTPC3_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 10889 word_offset = ((mmTPC3_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 10890 << 2; 10891 mask = 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 10892 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 10893 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 10894 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 10895 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 10896 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 10897 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 10898 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 10899 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 10900 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 10901 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 10902 mask |= 1U << ((mmTPC3_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 10903 mask |= 1U << ((mmTPC3_QM_CGM_CFG & 0x7F) >> 2); 10904 mask |= 1U << ((mmTPC3_QM_CGM_STS & 0x7F) >> 2); 10905 mask |= 1U << ((mmTPC3_QM_CGM_CFG1 & 0x7F) >> 2); 10906 10907 WREG32(pb_addr + word_offset, ~mask); 10908 10909 pb_addr = (mmTPC3_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 10910 word_offset = ((mmTPC3_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 10911 mask = 1U << ((mmTPC3_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 10912 mask |= 1U << ((mmTPC3_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 10913 mask |= 1U << ((mmTPC3_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 10914 mask |= 1U << ((mmTPC3_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 10915 mask |= 1U << ((mmTPC3_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 10916 mask |= 1U << ((mmTPC3_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 10917 mask |= 1U << ((mmTPC3_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 10918 mask |= 1U << ((mmTPC3_QM_GLBL_AXCACHE & 0x7F) >> 2); 10919 mask |= 1U << ((mmTPC3_QM_IND_GW_APB_CFG & 0x7F) >> 2); 10920 mask |= 1U << ((mmTPC3_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 10921 mask |= 1U << ((mmTPC3_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 10922 mask |= 1U << ((mmTPC3_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 10923 mask |= 1U << ((mmTPC3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 10924 mask |= 1U << ((mmTPC3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 10925 mask |= 1U << ((mmTPC3_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 10926 10927 WREG32(pb_addr + word_offset, ~mask); 10928 10929 pb_addr = (mmTPC3_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 10930 word_offset = ((mmTPC3_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 10931 << 2; 10932 mask = 1U << ((mmTPC3_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 10933 10934 WREG32(pb_addr + word_offset, ~mask); 10935 10936 pb_addr = (mmTPC3_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; 10937 word_offset = ((mmTPC3_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; 10938 mask = 1U << ((mmTPC3_CFG_ROUND_CSR & 0x7F) >> 2); 10939 10940 WREG32(pb_addr + word_offset, ~mask); 10941 10942 pb_addr = (mmTPC3_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; 10943 word_offset = ((mmTPC3_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; 10944 mask = 1U << ((mmTPC3_CFG_PROT & 0x7F) >> 2); 10945 mask |= 1U << ((mmTPC3_CFG_VFLAGS & 0x7F) >> 2); 10946 mask |= 1U << ((mmTPC3_CFG_SFLAGS & 0x7F) >> 2); 10947 mask |= 1U << ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); 10948 mask |= 1U << ((mmTPC3_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); 10949 mask |= 1U << ((mmTPC3_CFG_TPC_STALL & 0x7F) >> 2); 10950 mask |= 1U << ((mmTPC3_CFG_ICACHE_BASE_ADDERESS_HIGH & 0x7F) >> 2); 10951 mask |= 1U << ((mmTPC3_CFG_RD_RATE_LIMIT & 0x7F) >> 2); 10952 mask |= 1U << ((mmTPC3_CFG_WR_RATE_LIMIT & 0x7F) >> 2); 10953 mask |= 1U << ((mmTPC3_CFG_MSS_CONFIG & 0x7F) >> 2); 10954 mask |= 1U << ((mmTPC3_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); 10955 mask |= 1U << ((mmTPC3_CFG_TPC_INTR_MASK & 0x7F) >> 2); 10956 mask |= 1U << ((mmTPC3_CFG_WQ_CREDITS & 0x7F) >> 2); 10957 mask |= 1U << ((mmTPC3_CFG_ARUSER_LO & 0x7F) >> 2); 10958 mask |= 1U << ((mmTPC3_CFG_ARUSER_HI & 0x7F) >> 2); 10959 mask |= 1U << ((mmTPC3_CFG_AWUSER_LO & 0x7F) >> 2); 10960 mask |= 1U << ((mmTPC3_CFG_AWUSER_HI & 0x7F) >> 2); 10961 mask |= 1U << ((mmTPC3_CFG_OPCODE_EXEC & 0x7F) >> 2); 10962 10963 WREG32(pb_addr + word_offset, ~mask); 10964 10965 pb_addr = (mmTPC3_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; 10966 word_offset = ((mmTPC3_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) 10967 << 2; 10968 mask = 1U << ((mmTPC3_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); 10969 mask |= 1U << ((mmTPC3_CFG_DBGMEM_ADD & 0x7F) >> 2); 10970 mask |= 1U << ((mmTPC3_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); 10971 mask |= 1U << ((mmTPC3_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); 10972 mask |= 1U << ((mmTPC3_CFG_DBGMEM_CTRL & 0x7F) >> 2); 10973 mask |= 1U << ((mmTPC3_CFG_DBGMEM_RC & 0x7F) >> 2); 10974 mask |= 1U << ((mmTPC3_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); 10975 mask |= 1U << ((mmTPC3_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); 10976 mask |= 1U << ((mmTPC3_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); 10977 mask |= 1U << ((mmTPC3_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); 10978 mask |= 1U << ((mmTPC3_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); 10979 mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); 10980 mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); 10981 mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); 10982 mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); 10983 mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); 10984 mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); 10985 mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); 10986 mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); 10987 mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); 10988 mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); 10989 mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); 10990 mask |= 1U << ((mmTPC3_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); 10991 10992 WREG32(pb_addr + word_offset, ~mask); 10993 10994 WREG32(mmTPC4_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 10995 WREG32(mmTPC4_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 10996 10997 pb_addr = (mmTPC4_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 10998 word_offset = ((mmTPC4_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 10999 mask = 1U << ((mmTPC4_QM_GLBL_CFG0 & 0x7F) >> 2); 11000 mask |= 1U << ((mmTPC4_QM_GLBL_CFG1 & 0x7F) >> 2); 11001 mask |= 1U << ((mmTPC4_QM_GLBL_PROT & 0x7F) >> 2); 11002 mask |= 1U << ((mmTPC4_QM_GLBL_ERR_CFG & 0x7F) >> 2); 11003 mask |= 1U << ((mmTPC4_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 11004 mask |= 1U << ((mmTPC4_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 11005 mask |= 1U << ((mmTPC4_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 11006 mask |= 1U << ((mmTPC4_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 11007 mask |= 1U << ((mmTPC4_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 11008 mask |= 1U << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 11009 mask |= 1U << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 11010 mask |= 1U << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 11011 mask |= 1U << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 11012 mask |= 1U << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 11013 mask |= 1U << ((mmTPC4_QM_GLBL_STS0 & 0x7F) >> 2); 11014 mask |= 1U << ((mmTPC4_QM_GLBL_STS1_0 & 0x7F) >> 2); 11015 mask |= 1U << ((mmTPC4_QM_GLBL_STS1_1 & 0x7F) >> 2); 11016 mask |= 1U << ((mmTPC4_QM_GLBL_STS1_2 & 0x7F) >> 2); 11017 mask |= 1U << ((mmTPC4_QM_GLBL_STS1_3 & 0x7F) >> 2); 11018 mask |= 1U << ((mmTPC4_QM_GLBL_STS1_4 & 0x7F) >> 2); 11019 mask |= 1U << ((mmTPC4_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 11020 mask |= 1U << ((mmTPC4_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 11021 mask |= 1U << ((mmTPC4_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 11022 mask |= 1U << ((mmTPC4_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 11023 mask |= 1U << ((mmTPC4_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 11024 mask |= 1U << ((mmTPC4_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 11025 mask |= 1U << ((mmTPC4_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 11026 mask |= 1U << ((mmTPC4_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 11027 mask |= 1U << ((mmTPC4_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 11028 11029 WREG32(pb_addr + word_offset, ~mask); 11030 11031 pb_addr = (mmTPC4_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 11032 word_offset = ((mmTPC4_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 11033 mask = 1U << ((mmTPC4_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 11034 mask |= 1U << ((mmTPC4_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 11035 mask |= 1U << ((mmTPC4_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 11036 mask |= 1U << ((mmTPC4_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 11037 mask |= 1U << ((mmTPC4_QM_PQ_SIZE_0 & 0x7F) >> 2); 11038 mask |= 1U << ((mmTPC4_QM_PQ_SIZE_1 & 0x7F) >> 2); 11039 mask |= 1U << ((mmTPC4_QM_PQ_SIZE_2 & 0x7F) >> 2); 11040 mask |= 1U << ((mmTPC4_QM_PQ_SIZE_3 & 0x7F) >> 2); 11041 mask |= 1U << ((mmTPC4_QM_PQ_PI_0 & 0x7F) >> 2); 11042 mask |= 1U << ((mmTPC4_QM_PQ_PI_1 & 0x7F) >> 2); 11043 mask |= 1U << ((mmTPC4_QM_PQ_PI_2 & 0x7F) >> 2); 11044 mask |= 1U << ((mmTPC4_QM_PQ_PI_3 & 0x7F) >> 2); 11045 mask |= 1U << ((mmTPC4_QM_PQ_CI_0 & 0x7F) >> 2); 11046 mask |= 1U << ((mmTPC4_QM_PQ_CI_1 & 0x7F) >> 2); 11047 mask |= 1U << ((mmTPC4_QM_PQ_CI_2 & 0x7F) >> 2); 11048 mask |= 1U << ((mmTPC4_QM_PQ_CI_3 & 0x7F) >> 2); 11049 mask |= 1U << ((mmTPC4_QM_PQ_CFG0_0 & 0x7F) >> 2); 11050 mask |= 1U << ((mmTPC4_QM_PQ_CFG0_1 & 0x7F) >> 2); 11051 mask |= 1U << ((mmTPC4_QM_PQ_CFG0_2 & 0x7F) >> 2); 11052 mask |= 1U << ((mmTPC4_QM_PQ_CFG0_3 & 0x7F) >> 2); 11053 mask |= 1U << ((mmTPC4_QM_PQ_CFG1_0 & 0x7F) >> 2); 11054 mask |= 1U << ((mmTPC4_QM_PQ_CFG1_1 & 0x7F) >> 2); 11055 mask |= 1U << ((mmTPC4_QM_PQ_CFG1_2 & 0x7F) >> 2); 11056 mask |= 1U << ((mmTPC4_QM_PQ_CFG1_3 & 0x7F) >> 2); 11057 mask |= 1U << ((mmTPC4_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 11058 mask |= 1U << ((mmTPC4_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 11059 mask |= 1U << ((mmTPC4_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 11060 mask |= 1U << ((mmTPC4_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 11061 mask |= 1U << ((mmTPC4_QM_PQ_STS0_0 & 0x7F) >> 2); 11062 mask |= 1U << ((mmTPC4_QM_PQ_STS0_1 & 0x7F) >> 2); 11063 mask |= 1U << ((mmTPC4_QM_PQ_STS0_2 & 0x7F) >> 2); 11064 mask |= 1U << ((mmTPC4_QM_PQ_STS0_3 & 0x7F) >> 2); 11065 11066 WREG32(pb_addr + word_offset, ~mask); 11067 11068 pb_addr = (mmTPC4_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 11069 word_offset = ((mmTPC4_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 11070 mask = 1U << ((mmTPC4_QM_PQ_STS1_0 & 0x7F) >> 2); 11071 mask |= 1U << ((mmTPC4_QM_PQ_STS1_1 & 0x7F) >> 2); 11072 mask |= 1U << ((mmTPC4_QM_PQ_STS1_2 & 0x7F) >> 2); 11073 mask |= 1U << ((mmTPC4_QM_PQ_STS1_3 & 0x7F) >> 2); 11074 mask |= 1U << ((mmTPC4_QM_CQ_STS0_0 & 0x7F) >> 2); 11075 mask |= 1U << ((mmTPC4_QM_CQ_STS0_1 & 0x7F) >> 2); 11076 mask |= 1U << ((mmTPC4_QM_CQ_STS0_2 & 0x7F) >> 2); 11077 mask |= 1U << ((mmTPC4_QM_CQ_STS0_3 & 0x7F) >> 2); 11078 mask |= 1U << ((mmTPC4_QM_CQ_STS1_0 & 0x7F) >> 2); 11079 mask |= 1U << ((mmTPC4_QM_CQ_STS1_1 & 0x7F) >> 2); 11080 mask |= 1U << ((mmTPC4_QM_CQ_STS1_2 & 0x7F) >> 2); 11081 mask |= 1U << ((mmTPC4_QM_CQ_STS1_3 & 0x7F) >> 2); 11082 mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 11083 mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 11084 mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_0 & 0x7F) >> 2); 11085 11086 WREG32(pb_addr + word_offset, ~mask); 11087 11088 pb_addr = (mmTPC4_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 11089 word_offset = ((mmTPC4_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 11090 mask = 1U << ((mmTPC4_QM_CQ_CTL_0 & 0x7F) >> 2); 11091 mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 11092 mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 11093 mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_1 & 0x7F) >> 2); 11094 mask |= 1U << ((mmTPC4_QM_CQ_CTL_1 & 0x7F) >> 2); 11095 mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 11096 mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 11097 mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_2 & 0x7F) >> 2); 11098 mask |= 1U << ((mmTPC4_QM_CQ_CTL_2 & 0x7F) >> 2); 11099 mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 11100 mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 11101 mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_3 & 0x7F) >> 2); 11102 mask |= 1U << ((mmTPC4_QM_CQ_CTL_3 & 0x7F) >> 2); 11103 mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 11104 mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 11105 mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 11106 mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 11107 mask |= 1U << ((mmTPC4_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 11108 mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 11109 mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 11110 mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 11111 mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 11112 mask |= 1U << ((mmTPC4_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 11113 mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 11114 mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 11115 mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 11116 mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 11117 mask |= 1U << ((mmTPC4_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 11118 11119 WREG32(pb_addr + word_offset, ~mask); 11120 11121 pb_addr = (mmTPC4_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 11122 word_offset = ((mmTPC4_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 11123 mask = 1U << ((mmTPC4_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 11124 mask |= 1U << ((mmTPC4_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 11125 mask |= 1U << ((mmTPC4_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 11126 mask |= 1U << ((mmTPC4_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 11127 mask |= 1U << ((mmTPC4_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 11128 mask |= 1U << ((mmTPC4_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 11129 mask |= 1U << ((mmTPC4_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 11130 mask |= 1U << ((mmTPC4_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 11131 mask |= 1U << ((mmTPC4_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 11132 mask |= 1U << ((mmTPC4_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 11133 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 11134 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 11135 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 11136 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 11137 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 11138 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 11139 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 11140 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 11141 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 11142 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 11143 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 11144 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 11145 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 11146 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 11147 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 11148 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 11149 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 11150 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 11151 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 11152 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 11153 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 11154 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 11155 11156 WREG32(pb_addr + word_offset, ~mask); 11157 11158 pb_addr = (mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 11159 word_offset = ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 11160 << 2; 11161 mask = 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 11162 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 11163 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 11164 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 11165 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 11166 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 11167 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 11168 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 11169 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 11170 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 11171 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 11172 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 11173 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 11174 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 11175 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 11176 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 11177 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 11178 mask |= 1U << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 11179 mask |= 1U << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 11180 mask |= 1U << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 11181 mask |= 1U << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 11182 mask |= 1U << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 11183 mask |= 1U << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 11184 mask |= 1U << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 11185 mask |= 1U << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 11186 mask |= 1U << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 11187 mask |= 1U << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 11188 mask |= 1U << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 11189 mask |= 1U << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 11190 mask |= 1U << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 11191 mask |= 1U << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 11192 11193 WREG32(pb_addr + word_offset, ~mask); 11194 11195 pb_addr = (mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 11196 PROT_BITS_OFFS; 11197 word_offset = ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) 11198 >> 7) << 2; 11199 mask = 1U << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 11200 mask |= 1U << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 11201 11202 WREG32(pb_addr + word_offset, ~mask); 11203 11204 pb_addr = (mmTPC4_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 11205 word_offset = ((mmTPC4_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 11206 mask = 1U << ((mmTPC4_QM_CP_STS_0 & 0x7F) >> 2); 11207 mask |= 1U << ((mmTPC4_QM_CP_STS_1 & 0x7F) >> 2); 11208 mask |= 1U << ((mmTPC4_QM_CP_STS_2 & 0x7F) >> 2); 11209 mask |= 1U << ((mmTPC4_QM_CP_STS_3 & 0x7F) >> 2); 11210 mask |= 1U << ((mmTPC4_QM_CP_STS_4 & 0x7F) >> 2); 11211 mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 11212 mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 11213 mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 11214 mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 11215 mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 11216 mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 11217 mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 11218 mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 11219 mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 11220 mask |= 1U << ((mmTPC4_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 11221 mask |= 1U << ((mmTPC4_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 11222 mask |= 1U << ((mmTPC4_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 11223 mask |= 1U << ((mmTPC4_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 11224 11225 WREG32(pb_addr + word_offset, ~mask); 11226 11227 pb_addr = (mmTPC4_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 11228 word_offset = ((mmTPC4_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 11229 mask = 1U << ((mmTPC4_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 11230 mask |= 1U << ((mmTPC4_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 11231 mask |= 1U << ((mmTPC4_QM_CP_DBG_0_0 & 0x7F) >> 2); 11232 mask |= 1U << ((mmTPC4_QM_CP_DBG_0_1 & 0x7F) >> 2); 11233 11234 WREG32(pb_addr + word_offset, ~mask); 11235 11236 pb_addr = (mmTPC4_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 11237 word_offset = ((mmTPC4_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 11238 mask = 1U << ((mmTPC4_QM_CP_DBG_0_2 & 0x7F) >> 2); 11239 mask |= 1U << ((mmTPC4_QM_CP_DBG_0_3 & 0x7F) >> 2); 11240 mask |= 1U << ((mmTPC4_QM_CP_DBG_0_4 & 0x7F) >> 2); 11241 mask |= 1U << ((mmTPC4_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 11242 mask |= 1U << ((mmTPC4_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 11243 mask |= 1U << ((mmTPC4_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 11244 mask |= 1U << ((mmTPC4_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 11245 mask |= 1U << ((mmTPC4_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 11246 mask |= 1U << ((mmTPC4_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 11247 mask |= 1U << ((mmTPC4_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 11248 mask |= 1U << ((mmTPC4_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 11249 mask |= 1U << ((mmTPC4_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 11250 mask |= 1U << ((mmTPC4_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 11251 11252 WREG32(pb_addr + word_offset, ~mask); 11253 11254 pb_addr = (mmTPC4_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 11255 word_offset = ((mmTPC4_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 11256 mask = 1U << ((mmTPC4_QM_ARB_CFG_1 & 0x7F) >> 2); 11257 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 11258 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 11259 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 11260 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 11261 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 11262 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 11263 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 11264 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 11265 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 11266 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 11267 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 11268 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 11269 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 11270 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 11271 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 11272 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 11273 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 11274 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 11275 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 11276 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 11277 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 11278 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 11279 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 11280 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 11281 11282 WREG32(pb_addr + word_offset, ~mask); 11283 11284 pb_addr = (mmTPC4_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 11285 word_offset = ((mmTPC4_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 11286 << 2; 11287 mask = 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 11288 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 11289 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 11290 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 11291 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 11292 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 11293 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 11294 mask |= 1U << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 11295 11296 WREG32(pb_addr + word_offset, ~mask); 11297 11298 pb_addr = (mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 11299 PROT_BITS_OFFS; 11300 word_offset = ((mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) 11301 >> 7) << 2; 11302 mask = 1U << ((mmTPC4_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 11303 mask |= 1U << ((mmTPC4_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 11304 mask |= 1U << ((mmTPC4_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 11305 mask |= 1U << ((mmTPC4_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 11306 mask |= 1U << ((mmTPC4_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 11307 11308 WREG32(pb_addr + word_offset, ~mask); 11309 11310 pb_addr = (mmTPC4_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 11311 word_offset = ((mmTPC4_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 11312 mask = 1U << ((mmTPC4_QM_ARB_STATE_STS & 0x7F) >> 2); 11313 mask |= 1U << ((mmTPC4_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 11314 mask |= 1U << ((mmTPC4_QM_ARB_MSG_STS & 0x7F) >> 2); 11315 mask |= 1U << ((mmTPC4_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 11316 mask |= 1U << ((mmTPC4_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 11317 mask |= 1U << ((mmTPC4_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 11318 mask |= 1U << ((mmTPC4_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 11319 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 11320 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 11321 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 11322 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 11323 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 11324 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 11325 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 11326 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 11327 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 11328 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 11329 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 11330 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 11331 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 11332 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 11333 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 11334 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 11335 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 11336 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 11337 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 11338 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 11339 11340 WREG32(pb_addr + word_offset, ~mask); 11341 11342 pb_addr = (mmTPC4_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 11343 word_offset = ((mmTPC4_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 11344 << 2; 11345 mask = 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 11346 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 11347 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 11348 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 11349 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 11350 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 11351 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 11352 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 11353 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 11354 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 11355 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 11356 mask |= 1U << ((mmTPC4_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 11357 mask |= 1U << ((mmTPC4_QM_CGM_CFG & 0x7F) >> 2); 11358 mask |= 1U << ((mmTPC4_QM_CGM_STS & 0x7F) >> 2); 11359 mask |= 1U << ((mmTPC4_QM_CGM_CFG1 & 0x7F) >> 2); 11360 11361 WREG32(pb_addr + word_offset, ~mask); 11362 11363 pb_addr = (mmTPC4_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 11364 word_offset = ((mmTPC4_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 11365 mask = 1U << ((mmTPC4_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 11366 mask |= 1U << ((mmTPC4_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 11367 mask |= 1U << ((mmTPC4_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 11368 mask |= 1U << ((mmTPC4_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 11369 mask |= 1U << ((mmTPC4_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 11370 mask |= 1U << ((mmTPC4_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 11371 mask |= 1U << ((mmTPC4_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 11372 mask |= 1U << ((mmTPC4_QM_GLBL_AXCACHE & 0x7F) >> 2); 11373 mask |= 1U << ((mmTPC4_QM_IND_GW_APB_CFG & 0x7F) >> 2); 11374 mask |= 1U << ((mmTPC4_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 11375 mask |= 1U << ((mmTPC4_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 11376 mask |= 1U << ((mmTPC4_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 11377 mask |= 1U << ((mmTPC4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 11378 mask |= 1U << ((mmTPC4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 11379 mask |= 1U << ((mmTPC4_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 11380 11381 WREG32(pb_addr + word_offset, ~mask); 11382 11383 pb_addr = (mmTPC4_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 11384 word_offset = ((mmTPC4_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 11385 << 2; 11386 mask = 1U << ((mmTPC4_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 11387 11388 WREG32(pb_addr + word_offset, ~mask); 11389 11390 pb_addr = (mmTPC4_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; 11391 word_offset = ((mmTPC4_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; 11392 mask = 1U << ((mmTPC4_CFG_ROUND_CSR & 0x7F) >> 2); 11393 11394 WREG32(pb_addr + word_offset, ~mask); 11395 11396 pb_addr = (mmTPC4_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; 11397 word_offset = ((mmTPC4_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; 11398 mask = 1U << ((mmTPC4_CFG_PROT & 0x7F) >> 2); 11399 mask |= 1U << ((mmTPC4_CFG_VFLAGS & 0x7F) >> 2); 11400 mask |= 1U << ((mmTPC4_CFG_SFLAGS & 0x7F) >> 2); 11401 mask |= 1U << ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); 11402 mask |= 1U << ((mmTPC4_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); 11403 mask |= 1U << ((mmTPC4_CFG_TPC_STALL & 0x7F) >> 2); 11404 mask |= 1U << ((mmTPC4_CFG_ICACHE_BASE_ADDERESS_HIGH & 0x7F) >> 2); 11405 mask |= 1U << ((mmTPC4_CFG_RD_RATE_LIMIT & 0x7F) >> 2); 11406 mask |= 1U << ((mmTPC4_CFG_WR_RATE_LIMIT & 0x7F) >> 2); 11407 mask |= 1U << ((mmTPC4_CFG_MSS_CONFIG & 0x7F) >> 2); 11408 mask |= 1U << ((mmTPC4_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); 11409 mask |= 1U << ((mmTPC4_CFG_TPC_INTR_MASK & 0x7F) >> 2); 11410 mask |= 1U << ((mmTPC4_CFG_WQ_CREDITS & 0x7F) >> 2); 11411 mask |= 1U << ((mmTPC4_CFG_ARUSER_LO & 0x7F) >> 2); 11412 mask |= 1U << ((mmTPC4_CFG_ARUSER_HI & 0x7F) >> 2); 11413 mask |= 1U << ((mmTPC4_CFG_AWUSER_LO & 0x7F) >> 2); 11414 mask |= 1U << ((mmTPC4_CFG_AWUSER_HI & 0x7F) >> 2); 11415 mask |= 1U << ((mmTPC4_CFG_OPCODE_EXEC & 0x7F) >> 2); 11416 11417 WREG32(pb_addr + word_offset, ~mask); 11418 11419 pb_addr = (mmTPC4_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; 11420 word_offset = ((mmTPC4_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) 11421 << 2; 11422 mask = 1U << ((mmTPC4_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); 11423 mask |= 1U << ((mmTPC4_CFG_DBGMEM_ADD & 0x7F) >> 2); 11424 mask |= 1U << ((mmTPC4_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); 11425 mask |= 1U << ((mmTPC4_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); 11426 mask |= 1U << ((mmTPC4_CFG_DBGMEM_CTRL & 0x7F) >> 2); 11427 mask |= 1U << ((mmTPC4_CFG_DBGMEM_RC & 0x7F) >> 2); 11428 mask |= 1U << ((mmTPC4_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); 11429 mask |= 1U << ((mmTPC4_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); 11430 mask |= 1U << ((mmTPC4_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); 11431 mask |= 1U << ((mmTPC4_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); 11432 mask |= 1U << ((mmTPC4_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); 11433 mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); 11434 mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); 11435 mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); 11436 mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); 11437 mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); 11438 mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); 11439 mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); 11440 mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); 11441 mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); 11442 mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); 11443 mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); 11444 mask |= 1U << ((mmTPC4_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); 11445 11446 WREG32(pb_addr + word_offset, ~mask); 11447 11448 WREG32(mmTPC5_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 11449 WREG32(mmTPC5_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 11450 11451 pb_addr = (mmTPC5_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 11452 word_offset = ((mmTPC5_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 11453 mask = 1U << ((mmTPC5_QM_GLBL_CFG0 & 0x7F) >> 2); 11454 mask |= 1U << ((mmTPC5_QM_GLBL_CFG1 & 0x7F) >> 2); 11455 mask |= 1U << ((mmTPC5_QM_GLBL_PROT & 0x7F) >> 2); 11456 mask |= 1U << ((mmTPC5_QM_GLBL_ERR_CFG & 0x7F) >> 2); 11457 mask |= 1U << ((mmTPC5_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 11458 mask |= 1U << ((mmTPC5_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 11459 mask |= 1U << ((mmTPC5_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 11460 mask |= 1U << ((mmTPC5_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 11461 mask |= 1U << ((mmTPC5_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 11462 mask |= 1U << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 11463 mask |= 1U << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 11464 mask |= 1U << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 11465 mask |= 1U << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 11466 mask |= 1U << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 11467 mask |= 1U << ((mmTPC5_QM_GLBL_STS0 & 0x7F) >> 2); 11468 mask |= 1U << ((mmTPC5_QM_GLBL_STS1_0 & 0x7F) >> 2); 11469 mask |= 1U << ((mmTPC5_QM_GLBL_STS1_1 & 0x7F) >> 2); 11470 mask |= 1U << ((mmTPC5_QM_GLBL_STS1_2 & 0x7F) >> 2); 11471 mask |= 1U << ((mmTPC5_QM_GLBL_STS1_3 & 0x7F) >> 2); 11472 mask |= 1U << ((mmTPC5_QM_GLBL_STS1_4 & 0x7F) >> 2); 11473 mask |= 1U << ((mmTPC5_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 11474 mask |= 1U << ((mmTPC5_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 11475 mask |= 1U << ((mmTPC5_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 11476 mask |= 1U << ((mmTPC5_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 11477 mask |= 1U << ((mmTPC5_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 11478 mask |= 1U << ((mmTPC5_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 11479 mask |= 1U << ((mmTPC5_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 11480 mask |= 1U << ((mmTPC5_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 11481 mask |= 1U << ((mmTPC5_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 11482 11483 WREG32(pb_addr + word_offset, ~mask); 11484 11485 pb_addr = (mmTPC5_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 11486 word_offset = ((mmTPC5_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 11487 mask = 1U << ((mmTPC5_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 11488 mask |= 1U << ((mmTPC5_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 11489 mask |= 1U << ((mmTPC5_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 11490 mask |= 1U << ((mmTPC5_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 11491 mask |= 1U << ((mmTPC5_QM_PQ_SIZE_0 & 0x7F) >> 2); 11492 mask |= 1U << ((mmTPC5_QM_PQ_SIZE_1 & 0x7F) >> 2); 11493 mask |= 1U << ((mmTPC5_QM_PQ_SIZE_2 & 0x7F) >> 2); 11494 mask |= 1U << ((mmTPC5_QM_PQ_SIZE_3 & 0x7F) >> 2); 11495 mask |= 1U << ((mmTPC5_QM_PQ_PI_0 & 0x7F) >> 2); 11496 mask |= 1U << ((mmTPC5_QM_PQ_PI_1 & 0x7F) >> 2); 11497 mask |= 1U << ((mmTPC5_QM_PQ_PI_2 & 0x7F) >> 2); 11498 mask |= 1U << ((mmTPC5_QM_PQ_PI_3 & 0x7F) >> 2); 11499 mask |= 1U << ((mmTPC5_QM_PQ_CI_0 & 0x7F) >> 2); 11500 mask |= 1U << ((mmTPC5_QM_PQ_CI_1 & 0x7F) >> 2); 11501 mask |= 1U << ((mmTPC5_QM_PQ_CI_2 & 0x7F) >> 2); 11502 mask |= 1U << ((mmTPC5_QM_PQ_CI_3 & 0x7F) >> 2); 11503 mask |= 1U << ((mmTPC5_QM_PQ_CFG0_0 & 0x7F) >> 2); 11504 mask |= 1U << ((mmTPC5_QM_PQ_CFG0_1 & 0x7F) >> 2); 11505 mask |= 1U << ((mmTPC5_QM_PQ_CFG0_2 & 0x7F) >> 2); 11506 mask |= 1U << ((mmTPC5_QM_PQ_CFG0_3 & 0x7F) >> 2); 11507 mask |= 1U << ((mmTPC5_QM_PQ_CFG1_0 & 0x7F) >> 2); 11508 mask |= 1U << ((mmTPC5_QM_PQ_CFG1_1 & 0x7F) >> 2); 11509 mask |= 1U << ((mmTPC5_QM_PQ_CFG1_2 & 0x7F) >> 2); 11510 mask |= 1U << ((mmTPC5_QM_PQ_CFG1_3 & 0x7F) >> 2); 11511 mask |= 1U << ((mmTPC5_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 11512 mask |= 1U << ((mmTPC5_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 11513 mask |= 1U << ((mmTPC5_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 11514 mask |= 1U << ((mmTPC5_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 11515 mask |= 1U << ((mmTPC5_QM_PQ_STS0_0 & 0x7F) >> 2); 11516 mask |= 1U << ((mmTPC5_QM_PQ_STS0_1 & 0x7F) >> 2); 11517 mask |= 1U << ((mmTPC5_QM_PQ_STS0_2 & 0x7F) >> 2); 11518 mask |= 1U << ((mmTPC5_QM_PQ_STS0_3 & 0x7F) >> 2); 11519 11520 WREG32(pb_addr + word_offset, ~mask); 11521 11522 pb_addr = (mmTPC5_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 11523 word_offset = ((mmTPC5_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 11524 mask = 1U << ((mmTPC5_QM_PQ_STS1_0 & 0x7F) >> 2); 11525 mask |= 1U << ((mmTPC5_QM_PQ_STS1_1 & 0x7F) >> 2); 11526 mask |= 1U << ((mmTPC5_QM_PQ_STS1_2 & 0x7F) >> 2); 11527 mask |= 1U << ((mmTPC5_QM_PQ_STS1_3 & 0x7F) >> 2); 11528 mask |= 1U << ((mmTPC5_QM_CQ_STS0_0 & 0x7F) >> 2); 11529 mask |= 1U << ((mmTPC5_QM_CQ_STS0_1 & 0x7F) >> 2); 11530 mask |= 1U << ((mmTPC5_QM_CQ_STS0_2 & 0x7F) >> 2); 11531 mask |= 1U << ((mmTPC5_QM_CQ_STS0_3 & 0x7F) >> 2); 11532 mask |= 1U << ((mmTPC5_QM_CQ_STS1_0 & 0x7F) >> 2); 11533 mask |= 1U << ((mmTPC5_QM_CQ_STS1_1 & 0x7F) >> 2); 11534 mask |= 1U << ((mmTPC5_QM_CQ_STS1_2 & 0x7F) >> 2); 11535 mask |= 1U << ((mmTPC5_QM_CQ_STS1_3 & 0x7F) >> 2); 11536 mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 11537 mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 11538 mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_0 & 0x7F) >> 2); 11539 11540 WREG32(pb_addr + word_offset, ~mask); 11541 11542 pb_addr = (mmTPC5_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 11543 word_offset = ((mmTPC5_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 11544 mask = 1U << ((mmTPC5_QM_CQ_CTL_0 & 0x7F) >> 2); 11545 mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 11546 mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 11547 mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_1 & 0x7F) >> 2); 11548 mask |= 1U << ((mmTPC5_QM_CQ_CTL_1 & 0x7F) >> 2); 11549 mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 11550 mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 11551 mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_2 & 0x7F) >> 2); 11552 mask |= 1U << ((mmTPC5_QM_CQ_CTL_2 & 0x7F) >> 2); 11553 mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 11554 mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 11555 mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_3 & 0x7F) >> 2); 11556 mask |= 1U << ((mmTPC5_QM_CQ_CTL_3 & 0x7F) >> 2); 11557 mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 11558 mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 11559 mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 11560 mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 11561 mask |= 1U << ((mmTPC5_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 11562 mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 11563 mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 11564 mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 11565 mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 11566 mask |= 1U << ((mmTPC5_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 11567 mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 11568 mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 11569 mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 11570 mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 11571 mask |= 1U << ((mmTPC5_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 11572 11573 WREG32(pb_addr + word_offset, ~mask); 11574 11575 pb_addr = (mmTPC5_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 11576 word_offset = ((mmTPC5_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 11577 mask = 1U << ((mmTPC5_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 11578 mask |= 1U << ((mmTPC5_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 11579 mask |= 1U << ((mmTPC5_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 11580 mask |= 1U << ((mmTPC5_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 11581 mask |= 1U << ((mmTPC5_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 11582 mask |= 1U << ((mmTPC5_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 11583 mask |= 1U << ((mmTPC5_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 11584 mask |= 1U << ((mmTPC5_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 11585 mask |= 1U << ((mmTPC5_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 11586 mask |= 1U << ((mmTPC5_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 11587 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 11588 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 11589 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 11590 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 11591 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 11592 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 11593 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 11594 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 11595 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 11596 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 11597 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 11598 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 11599 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 11600 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 11601 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 11602 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 11603 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 11604 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 11605 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 11606 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 11607 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 11608 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 11609 11610 WREG32(pb_addr + word_offset, ~mask); 11611 11612 pb_addr = (mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 11613 word_offset = ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 11614 << 2; 11615 mask = 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 11616 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 11617 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 11618 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 11619 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 11620 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 11621 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 11622 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 11623 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 11624 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 11625 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 11626 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 11627 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 11628 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 11629 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 11630 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 11631 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 11632 mask |= 1U << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 11633 mask |= 1U << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 11634 mask |= 1U << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 11635 mask |= 1U << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 11636 mask |= 1U << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 11637 mask |= 1U << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 11638 mask |= 1U << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 11639 mask |= 1U << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 11640 mask |= 1U << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 11641 mask |= 1U << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 11642 mask |= 1U << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 11643 mask |= 1U << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 11644 mask |= 1U << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 11645 mask |= 1U << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 11646 11647 WREG32(pb_addr + word_offset, ~mask); 11648 11649 pb_addr = (mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 11650 PROT_BITS_OFFS; 11651 word_offset = ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) 11652 >> 7) << 2; 11653 mask = 1U << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 11654 mask |= 1U << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 11655 11656 WREG32(pb_addr + word_offset, ~mask); 11657 11658 pb_addr = (mmTPC5_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 11659 word_offset = ((mmTPC5_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 11660 mask = 1U << ((mmTPC5_QM_CP_STS_0 & 0x7F) >> 2); 11661 mask |= 1U << ((mmTPC5_QM_CP_STS_1 & 0x7F) >> 2); 11662 mask |= 1U << ((mmTPC5_QM_CP_STS_2 & 0x7F) >> 2); 11663 mask |= 1U << ((mmTPC5_QM_CP_STS_3 & 0x7F) >> 2); 11664 mask |= 1U << ((mmTPC5_QM_CP_STS_4 & 0x7F) >> 2); 11665 mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 11666 mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 11667 mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 11668 mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 11669 mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 11670 mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 11671 mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 11672 mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 11673 mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 11674 mask |= 1U << ((mmTPC5_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 11675 mask |= 1U << ((mmTPC5_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 11676 mask |= 1U << ((mmTPC5_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 11677 mask |= 1U << ((mmTPC5_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 11678 11679 WREG32(pb_addr + word_offset, ~mask); 11680 11681 pb_addr = (mmTPC5_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 11682 word_offset = ((mmTPC5_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 11683 mask = 1U << ((mmTPC5_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 11684 mask |= 1U << ((mmTPC5_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 11685 mask |= 1U << ((mmTPC5_QM_CP_DBG_0_0 & 0x7F) >> 2); 11686 mask |= 1U << ((mmTPC5_QM_CP_DBG_0_1 & 0x7F) >> 2); 11687 11688 WREG32(pb_addr + word_offset, ~mask); 11689 11690 pb_addr = (mmTPC5_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 11691 word_offset = ((mmTPC5_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 11692 mask = 1U << ((mmTPC5_QM_CP_DBG_0_2 & 0x7F) >> 2); 11693 mask |= 1U << ((mmTPC5_QM_CP_DBG_0_3 & 0x7F) >> 2); 11694 mask |= 1U << ((mmTPC5_QM_CP_DBG_0_4 & 0x7F) >> 2); 11695 mask |= 1U << ((mmTPC5_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 11696 mask |= 1U << ((mmTPC5_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 11697 mask |= 1U << ((mmTPC5_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 11698 mask |= 1U << ((mmTPC5_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 11699 mask |= 1U << ((mmTPC5_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 11700 mask |= 1U << ((mmTPC5_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 11701 mask |= 1U << ((mmTPC5_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 11702 mask |= 1U << ((mmTPC5_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 11703 mask |= 1U << ((mmTPC5_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 11704 mask |= 1U << ((mmTPC5_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 11705 11706 WREG32(pb_addr + word_offset, ~mask); 11707 11708 pb_addr = (mmTPC5_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 11709 word_offset = ((mmTPC5_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 11710 mask = 1U << ((mmTPC5_QM_ARB_CFG_1 & 0x7F) >> 2); 11711 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 11712 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 11713 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 11714 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 11715 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 11716 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 11717 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 11718 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 11719 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 11720 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 11721 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 11722 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 11723 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 11724 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 11725 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 11726 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 11727 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 11728 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 11729 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 11730 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 11731 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 11732 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 11733 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 11734 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 11735 11736 WREG32(pb_addr + word_offset, ~mask); 11737 11738 pb_addr = (mmTPC5_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 11739 word_offset = ((mmTPC5_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 11740 << 2; 11741 mask = 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 11742 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 11743 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 11744 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 11745 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 11746 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 11747 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 11748 mask |= 1U << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 11749 11750 WREG32(pb_addr + word_offset, ~mask); 11751 11752 pb_addr = (mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 11753 PROT_BITS_OFFS; 11754 word_offset = ((mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) 11755 >> 7) << 2; 11756 mask = 1U << ((mmTPC5_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 11757 mask |= 1U << ((mmTPC5_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 11758 mask |= 1U << ((mmTPC5_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 11759 mask |= 1U << ((mmTPC5_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 11760 mask |= 1U << ((mmTPC5_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 11761 11762 WREG32(pb_addr + word_offset, ~mask); 11763 11764 pb_addr = (mmTPC5_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 11765 word_offset = ((mmTPC5_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 11766 mask = 1U << ((mmTPC5_QM_ARB_STATE_STS & 0x7F) >> 2); 11767 mask |= 1U << ((mmTPC5_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 11768 mask |= 1U << ((mmTPC5_QM_ARB_MSG_STS & 0x7F) >> 2); 11769 mask |= 1U << ((mmTPC5_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 11770 mask |= 1U << ((mmTPC5_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 11771 mask |= 1U << ((mmTPC5_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 11772 mask |= 1U << ((mmTPC5_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 11773 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 11774 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 11775 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 11776 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 11777 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 11778 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 11779 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 11780 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 11781 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 11782 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 11783 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 11784 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 11785 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 11786 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 11787 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 11788 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 11789 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 11790 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 11791 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 11792 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 11793 11794 WREG32(pb_addr + word_offset, ~mask); 11795 11796 pb_addr = (mmTPC5_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 11797 word_offset = ((mmTPC5_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 11798 << 2; 11799 mask = 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 11800 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 11801 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 11802 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 11803 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 11804 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 11805 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 11806 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 11807 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 11808 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 11809 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 11810 mask |= 1U << ((mmTPC5_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 11811 mask |= 1U << ((mmTPC5_QM_CGM_CFG & 0x7F) >> 2); 11812 mask |= 1U << ((mmTPC5_QM_CGM_STS & 0x7F) >> 2); 11813 mask |= 1U << ((mmTPC5_QM_CGM_CFG1 & 0x7F) >> 2); 11814 11815 WREG32(pb_addr + word_offset, ~mask); 11816 11817 pb_addr = (mmTPC5_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 11818 word_offset = ((mmTPC5_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 11819 mask = 1U << ((mmTPC5_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 11820 mask |= 1U << ((mmTPC5_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 11821 mask |= 1U << ((mmTPC5_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 11822 mask |= 1U << ((mmTPC5_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 11823 mask |= 1U << ((mmTPC5_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 11824 mask |= 1U << ((mmTPC5_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 11825 mask |= 1U << ((mmTPC5_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 11826 mask |= 1U << ((mmTPC5_QM_GLBL_AXCACHE & 0x7F) >> 2); 11827 mask |= 1U << ((mmTPC5_QM_IND_GW_APB_CFG & 0x7F) >> 2); 11828 mask |= 1U << ((mmTPC5_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 11829 mask |= 1U << ((mmTPC5_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 11830 mask |= 1U << ((mmTPC5_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 11831 mask |= 1U << ((mmTPC5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 11832 mask |= 1U << ((mmTPC5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 11833 mask |= 1U << ((mmTPC5_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 11834 11835 WREG32(pb_addr + word_offset, ~mask); 11836 11837 pb_addr = (mmTPC5_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 11838 word_offset = ((mmTPC5_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 11839 << 2; 11840 mask = 1U << ((mmTPC5_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 11841 11842 WREG32(pb_addr + word_offset, ~mask); 11843 11844 pb_addr = (mmTPC5_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; 11845 word_offset = ((mmTPC5_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; 11846 mask = 1U << ((mmTPC5_CFG_ROUND_CSR & 0x7F) >> 2); 11847 11848 WREG32(pb_addr + word_offset, ~mask); 11849 11850 pb_addr = (mmTPC5_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; 11851 word_offset = ((mmTPC5_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; 11852 mask = 1U << ((mmTPC5_CFG_PROT & 0x7F) >> 2); 11853 mask |= 1U << ((mmTPC5_CFG_VFLAGS & 0x7F) >> 2); 11854 mask |= 1U << ((mmTPC5_CFG_SFLAGS & 0x7F) >> 2); 11855 mask |= 1U << ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); 11856 mask |= 1U << ((mmTPC5_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); 11857 mask |= 1U << ((mmTPC5_CFG_TPC_STALL & 0x7F) >> 2); 11858 mask |= 1U << ((mmTPC5_CFG_ICACHE_BASE_ADDERESS_HIGH & 0x7F) >> 2); 11859 mask |= 1U << ((mmTPC5_CFG_RD_RATE_LIMIT & 0x7F) >> 2); 11860 mask |= 1U << ((mmTPC5_CFG_WR_RATE_LIMIT & 0x7F) >> 2); 11861 mask |= 1U << ((mmTPC5_CFG_MSS_CONFIG & 0x7F) >> 2); 11862 mask |= 1U << ((mmTPC5_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); 11863 mask |= 1U << ((mmTPC5_CFG_TPC_INTR_MASK & 0x7F) >> 2); 11864 mask |= 1U << ((mmTPC5_CFG_WQ_CREDITS & 0x7F) >> 2); 11865 mask |= 1U << ((mmTPC5_CFG_ARUSER_LO & 0x7F) >> 2); 11866 mask |= 1U << ((mmTPC5_CFG_ARUSER_HI & 0x7F) >> 2); 11867 mask |= 1U << ((mmTPC5_CFG_AWUSER_LO & 0x7F) >> 2); 11868 mask |= 1U << ((mmTPC5_CFG_AWUSER_HI & 0x7F) >> 2); 11869 mask |= 1U << ((mmTPC5_CFG_OPCODE_EXEC & 0x7F) >> 2); 11870 11871 WREG32(pb_addr + word_offset, ~mask); 11872 11873 pb_addr = (mmTPC5_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; 11874 word_offset = ((mmTPC5_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) 11875 << 2; 11876 mask = 1U << ((mmTPC5_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); 11877 mask |= 1U << ((mmTPC5_CFG_DBGMEM_ADD & 0x7F) >> 2); 11878 mask |= 1U << ((mmTPC5_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); 11879 mask |= 1U << ((mmTPC5_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); 11880 mask |= 1U << ((mmTPC5_CFG_DBGMEM_CTRL & 0x7F) >> 2); 11881 mask |= 1U << ((mmTPC5_CFG_DBGMEM_RC & 0x7F) >> 2); 11882 mask |= 1U << ((mmTPC5_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); 11883 mask |= 1U << ((mmTPC5_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); 11884 mask |= 1U << ((mmTPC5_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); 11885 mask |= 1U << ((mmTPC5_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); 11886 mask |= 1U << ((mmTPC5_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); 11887 mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); 11888 mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); 11889 mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); 11890 mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); 11891 mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); 11892 mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); 11893 mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); 11894 mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); 11895 mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); 11896 mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); 11897 mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); 11898 mask |= 1U << ((mmTPC5_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); 11899 11900 WREG32(pb_addr + word_offset, ~mask); 11901 11902 WREG32(mmTPC6_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 11903 WREG32(mmTPC6_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 11904 11905 pb_addr = (mmTPC6_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 11906 word_offset = ((mmTPC6_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 11907 mask = 1U << ((mmTPC6_QM_GLBL_CFG0 & 0x7F) >> 2); 11908 mask |= 1U << ((mmTPC6_QM_GLBL_CFG1 & 0x7F) >> 2); 11909 mask |= 1U << ((mmTPC6_QM_GLBL_PROT & 0x7F) >> 2); 11910 mask |= 1U << ((mmTPC6_QM_GLBL_ERR_CFG & 0x7F) >> 2); 11911 mask |= 1U << ((mmTPC6_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 11912 mask |= 1U << ((mmTPC6_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 11913 mask |= 1U << ((mmTPC6_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 11914 mask |= 1U << ((mmTPC6_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 11915 mask |= 1U << ((mmTPC6_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 11916 mask |= 1U << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 11917 mask |= 1U << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 11918 mask |= 1U << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 11919 mask |= 1U << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 11920 mask |= 1U << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 11921 mask |= 1U << ((mmTPC6_QM_GLBL_STS0 & 0x7F) >> 2); 11922 mask |= 1U << ((mmTPC6_QM_GLBL_STS1_0 & 0x7F) >> 2); 11923 mask |= 1U << ((mmTPC6_QM_GLBL_STS1_1 & 0x7F) >> 2); 11924 mask |= 1U << ((mmTPC6_QM_GLBL_STS1_2 & 0x7F) >> 2); 11925 mask |= 1U << ((mmTPC6_QM_GLBL_STS1_3 & 0x7F) >> 2); 11926 mask |= 1U << ((mmTPC6_QM_GLBL_STS1_4 & 0x7F) >> 2); 11927 mask |= 1U << ((mmTPC6_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 11928 mask |= 1U << ((mmTPC6_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 11929 mask |= 1U << ((mmTPC6_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 11930 mask |= 1U << ((mmTPC6_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 11931 mask |= 1U << ((mmTPC6_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 11932 mask |= 1U << ((mmTPC6_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 11933 mask |= 1U << ((mmTPC6_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 11934 mask |= 1U << ((mmTPC6_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 11935 mask |= 1U << ((mmTPC6_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 11936 11937 WREG32(pb_addr + word_offset, ~mask); 11938 11939 pb_addr = (mmTPC6_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 11940 word_offset = ((mmTPC6_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 11941 mask = 1U << ((mmTPC6_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 11942 mask |= 1U << ((mmTPC6_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 11943 mask |= 1U << ((mmTPC6_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 11944 mask |= 1U << ((mmTPC6_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 11945 mask |= 1U << ((mmTPC6_QM_PQ_SIZE_0 & 0x7F) >> 2); 11946 mask |= 1U << ((mmTPC6_QM_PQ_SIZE_1 & 0x7F) >> 2); 11947 mask |= 1U << ((mmTPC6_QM_PQ_SIZE_2 & 0x7F) >> 2); 11948 mask |= 1U << ((mmTPC6_QM_PQ_SIZE_3 & 0x7F) >> 2); 11949 mask |= 1U << ((mmTPC6_QM_PQ_PI_0 & 0x7F) >> 2); 11950 mask |= 1U << ((mmTPC6_QM_PQ_PI_1 & 0x7F) >> 2); 11951 mask |= 1U << ((mmTPC6_QM_PQ_PI_2 & 0x7F) >> 2); 11952 mask |= 1U << ((mmTPC6_QM_PQ_PI_3 & 0x7F) >> 2); 11953 mask |= 1U << ((mmTPC6_QM_PQ_CI_0 & 0x7F) >> 2); 11954 mask |= 1U << ((mmTPC6_QM_PQ_CI_1 & 0x7F) >> 2); 11955 mask |= 1U << ((mmTPC6_QM_PQ_CI_2 & 0x7F) >> 2); 11956 mask |= 1U << ((mmTPC6_QM_PQ_CI_3 & 0x7F) >> 2); 11957 mask |= 1U << ((mmTPC6_QM_PQ_CFG0_0 & 0x7F) >> 2); 11958 mask |= 1U << ((mmTPC6_QM_PQ_CFG0_1 & 0x7F) >> 2); 11959 mask |= 1U << ((mmTPC6_QM_PQ_CFG0_2 & 0x7F) >> 2); 11960 mask |= 1U << ((mmTPC6_QM_PQ_CFG0_3 & 0x7F) >> 2); 11961 mask |= 1U << ((mmTPC6_QM_PQ_CFG1_0 & 0x7F) >> 2); 11962 mask |= 1U << ((mmTPC6_QM_PQ_CFG1_1 & 0x7F) >> 2); 11963 mask |= 1U << ((mmTPC6_QM_PQ_CFG1_2 & 0x7F) >> 2); 11964 mask |= 1U << ((mmTPC6_QM_PQ_CFG1_3 & 0x7F) >> 2); 11965 mask |= 1U << ((mmTPC6_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 11966 mask |= 1U << ((mmTPC6_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 11967 mask |= 1U << ((mmTPC6_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 11968 mask |= 1U << ((mmTPC6_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 11969 mask |= 1U << ((mmTPC6_QM_PQ_STS0_0 & 0x7F) >> 2); 11970 mask |= 1U << ((mmTPC6_QM_PQ_STS0_1 & 0x7F) >> 2); 11971 mask |= 1U << ((mmTPC6_QM_PQ_STS0_2 & 0x7F) >> 2); 11972 mask |= 1U << ((mmTPC6_QM_PQ_STS0_3 & 0x7F) >> 2); 11973 11974 WREG32(pb_addr + word_offset, ~mask); 11975 11976 pb_addr = (mmTPC6_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 11977 word_offset = ((mmTPC6_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 11978 mask = 1U << ((mmTPC6_QM_PQ_STS1_0 & 0x7F) >> 2); 11979 mask |= 1U << ((mmTPC6_QM_PQ_STS1_1 & 0x7F) >> 2); 11980 mask |= 1U << ((mmTPC6_QM_PQ_STS1_2 & 0x7F) >> 2); 11981 mask |= 1U << ((mmTPC6_QM_PQ_STS1_3 & 0x7F) >> 2); 11982 mask |= 1U << ((mmTPC6_QM_CQ_STS0_0 & 0x7F) >> 2); 11983 mask |= 1U << ((mmTPC6_QM_CQ_STS0_1 & 0x7F) >> 2); 11984 mask |= 1U << ((mmTPC6_QM_CQ_STS0_2 & 0x7F) >> 2); 11985 mask |= 1U << ((mmTPC6_QM_CQ_STS0_3 & 0x7F) >> 2); 11986 mask |= 1U << ((mmTPC6_QM_CQ_STS1_0 & 0x7F) >> 2); 11987 mask |= 1U << ((mmTPC6_QM_CQ_STS1_1 & 0x7F) >> 2); 11988 mask |= 1U << ((mmTPC6_QM_CQ_STS1_2 & 0x7F) >> 2); 11989 mask |= 1U << ((mmTPC6_QM_CQ_STS1_3 & 0x7F) >> 2); 11990 mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 11991 mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 11992 mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_0 & 0x7F) >> 2); 11993 11994 WREG32(pb_addr + word_offset, ~mask); 11995 11996 pb_addr = (mmTPC6_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 11997 word_offset = ((mmTPC6_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 11998 mask = 1U << ((mmTPC6_QM_CQ_CTL_0 & 0x7F) >> 2); 11999 mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 12000 mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 12001 mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_1 & 0x7F) >> 2); 12002 mask |= 1U << ((mmTPC6_QM_CQ_CTL_1 & 0x7F) >> 2); 12003 mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 12004 mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 12005 mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_2 & 0x7F) >> 2); 12006 mask |= 1U << ((mmTPC6_QM_CQ_CTL_2 & 0x7F) >> 2); 12007 mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 12008 mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 12009 mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_3 & 0x7F) >> 2); 12010 mask |= 1U << ((mmTPC6_QM_CQ_CTL_3 & 0x7F) >> 2); 12011 mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 12012 mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 12013 mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 12014 mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 12015 mask |= 1U << ((mmTPC6_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 12016 mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 12017 mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 12018 mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 12019 mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 12020 mask |= 1U << ((mmTPC6_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 12021 mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 12022 mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 12023 mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 12024 mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 12025 mask |= 1U << ((mmTPC6_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 12026 12027 WREG32(pb_addr + word_offset, ~mask); 12028 12029 pb_addr = (mmTPC6_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 12030 word_offset = ((mmTPC6_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 12031 mask = 1U << ((mmTPC6_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 12032 mask |= 1U << ((mmTPC6_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 12033 mask |= 1U << ((mmTPC6_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 12034 mask |= 1U << ((mmTPC6_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 12035 mask |= 1U << ((mmTPC6_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 12036 mask |= 1U << ((mmTPC6_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 12037 mask |= 1U << ((mmTPC6_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 12038 mask |= 1U << ((mmTPC6_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 12039 mask |= 1U << ((mmTPC6_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 12040 mask |= 1U << ((mmTPC6_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 12041 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 12042 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 12043 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 12044 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 12045 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 12046 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 12047 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 12048 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 12049 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 12050 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 12051 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 12052 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 12053 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 12054 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 12055 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 12056 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 12057 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 12058 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 12059 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 12060 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 12061 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 12062 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 12063 12064 WREG32(pb_addr + word_offset, ~mask); 12065 12066 pb_addr = (mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 12067 word_offset = ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 12068 << 2; 12069 mask = 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 12070 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 12071 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 12072 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 12073 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 12074 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 12075 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 12076 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 12077 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 12078 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 12079 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 12080 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 12081 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 12082 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 12083 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 12084 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 12085 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 12086 mask |= 1U << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 12087 mask |= 1U << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 12088 mask |= 1U << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 12089 mask |= 1U << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 12090 mask |= 1U << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 12091 mask |= 1U << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 12092 mask |= 1U << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 12093 mask |= 1U << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 12094 mask |= 1U << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 12095 mask |= 1U << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 12096 mask |= 1U << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 12097 mask |= 1U << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 12098 mask |= 1U << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 12099 mask |= 1U << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 12100 12101 WREG32(pb_addr + word_offset, ~mask); 12102 12103 pb_addr = (mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 12104 PROT_BITS_OFFS; 12105 word_offset = ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) 12106 >> 7) << 2; 12107 mask = 1U << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 12108 mask |= 1U << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 12109 12110 WREG32(pb_addr + word_offset, ~mask); 12111 12112 pb_addr = (mmTPC6_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 12113 word_offset = ((mmTPC6_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 12114 mask = 1U << ((mmTPC6_QM_CP_STS_0 & 0x7F) >> 2); 12115 mask |= 1U << ((mmTPC6_QM_CP_STS_1 & 0x7F) >> 2); 12116 mask |= 1U << ((mmTPC6_QM_CP_STS_2 & 0x7F) >> 2); 12117 mask |= 1U << ((mmTPC6_QM_CP_STS_3 & 0x7F) >> 2); 12118 mask |= 1U << ((mmTPC6_QM_CP_STS_4 & 0x7F) >> 2); 12119 mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 12120 mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 12121 mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 12122 mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 12123 mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 12124 mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 12125 mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 12126 mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 12127 mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 12128 mask |= 1U << ((mmTPC6_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 12129 mask |= 1U << ((mmTPC6_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 12130 mask |= 1U << ((mmTPC6_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 12131 mask |= 1U << ((mmTPC6_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 12132 12133 WREG32(pb_addr + word_offset, ~mask); 12134 12135 pb_addr = (mmTPC6_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 12136 word_offset = ((mmTPC6_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 12137 mask = 1U << ((mmTPC6_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 12138 mask |= 1U << ((mmTPC6_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 12139 mask |= 1U << ((mmTPC6_QM_CP_DBG_0_0 & 0x7F) >> 2); 12140 mask |= 1U << ((mmTPC6_QM_CP_DBG_0_1 & 0x7F) >> 2); 12141 12142 WREG32(pb_addr + word_offset, ~mask); 12143 12144 pb_addr = (mmTPC6_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 12145 word_offset = ((mmTPC6_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 12146 mask = 1U << ((mmTPC6_QM_CP_DBG_0_2 & 0x7F) >> 2); 12147 mask |= 1U << ((mmTPC6_QM_CP_DBG_0_3 & 0x7F) >> 2); 12148 mask |= 1U << ((mmTPC6_QM_CP_DBG_0_4 & 0x7F) >> 2); 12149 mask |= 1U << ((mmTPC6_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 12150 mask |= 1U << ((mmTPC6_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 12151 mask |= 1U << ((mmTPC6_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 12152 mask |= 1U << ((mmTPC6_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 12153 mask |= 1U << ((mmTPC6_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 12154 mask |= 1U << ((mmTPC6_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 12155 mask |= 1U << ((mmTPC6_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 12156 mask |= 1U << ((mmTPC6_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 12157 mask |= 1U << ((mmTPC6_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 12158 mask |= 1U << ((mmTPC6_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 12159 12160 WREG32(pb_addr + word_offset, ~mask); 12161 12162 pb_addr = (mmTPC6_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 12163 word_offset = ((mmTPC6_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 12164 mask = 1U << ((mmTPC6_QM_ARB_CFG_1 & 0x7F) >> 2); 12165 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 12166 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 12167 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 12168 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 12169 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 12170 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 12171 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 12172 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 12173 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 12174 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 12175 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 12176 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 12177 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 12178 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 12179 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 12180 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 12181 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 12182 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 12183 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 12184 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 12185 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 12186 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 12187 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 12188 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 12189 12190 WREG32(pb_addr + word_offset, ~mask); 12191 12192 pb_addr = (mmTPC6_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 12193 word_offset = ((mmTPC6_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 12194 << 2; 12195 mask = 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 12196 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 12197 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 12198 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 12199 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 12200 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 12201 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 12202 mask |= 1U << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 12203 12204 WREG32(pb_addr + word_offset, ~mask); 12205 12206 pb_addr = (mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 12207 PROT_BITS_OFFS; 12208 12209 word_offset = ((mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) 12210 >> 7) << 2; 12211 mask = 1U << ((mmTPC6_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 12212 mask |= 1U << ((mmTPC6_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 12213 mask |= 1U << ((mmTPC6_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 12214 mask |= 1U << ((mmTPC6_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 12215 mask |= 1U << ((mmTPC6_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 12216 12217 WREG32(pb_addr + word_offset, ~mask); 12218 12219 pb_addr = (mmTPC6_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 12220 word_offset = ((mmTPC6_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 12221 mask = 1U << ((mmTPC6_QM_ARB_STATE_STS & 0x7F) >> 2); 12222 mask |= 1U << ((mmTPC6_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 12223 mask |= 1U << ((mmTPC6_QM_ARB_MSG_STS & 0x7F) >> 2); 12224 mask |= 1U << ((mmTPC6_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 12225 mask |= 1U << ((mmTPC6_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 12226 mask |= 1U << ((mmTPC6_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 12227 mask |= 1U << ((mmTPC6_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 12228 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 12229 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 12230 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 12231 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 12232 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 12233 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 12234 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 12235 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 12236 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 12237 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 12238 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 12239 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 12240 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 12241 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 12242 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 12243 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 12244 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 12245 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 12246 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 12247 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 12248 12249 WREG32(pb_addr + word_offset, ~mask); 12250 12251 pb_addr = (mmTPC6_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 12252 word_offset = ((mmTPC6_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 12253 << 2; 12254 mask = 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 12255 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 12256 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 12257 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 12258 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 12259 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 12260 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 12261 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 12262 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 12263 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 12264 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 12265 mask |= 1U << ((mmTPC6_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 12266 mask |= 1U << ((mmTPC6_QM_CGM_CFG & 0x7F) >> 2); 12267 mask |= 1U << ((mmTPC6_QM_CGM_STS & 0x7F) >> 2); 12268 mask |= 1U << ((mmTPC6_QM_CGM_CFG1 & 0x7F) >> 2); 12269 12270 WREG32(pb_addr + word_offset, ~mask); 12271 12272 pb_addr = (mmTPC6_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 12273 word_offset = ((mmTPC6_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 12274 mask = 1U << ((mmTPC6_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 12275 mask |= 1U << ((mmTPC6_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 12276 mask |= 1U << ((mmTPC6_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 12277 mask |= 1U << ((mmTPC6_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 12278 mask |= 1U << ((mmTPC6_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 12279 mask |= 1U << ((mmTPC6_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 12280 mask |= 1U << ((mmTPC6_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 12281 mask |= 1U << ((mmTPC6_QM_GLBL_AXCACHE & 0x7F) >> 2); 12282 mask |= 1U << ((mmTPC6_QM_IND_GW_APB_CFG & 0x7F) >> 2); 12283 mask |= 1U << ((mmTPC6_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 12284 mask |= 1U << ((mmTPC6_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 12285 mask |= 1U << ((mmTPC6_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 12286 mask |= 1U << ((mmTPC6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 12287 mask |= 1U << ((mmTPC6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 12288 mask |= 1U << ((mmTPC6_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 12289 12290 WREG32(pb_addr + word_offset, ~mask); 12291 12292 pb_addr = (mmTPC6_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 12293 word_offset = ((mmTPC6_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 12294 << 2; 12295 12296 mask = 1U << ((mmTPC6_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 12297 12298 WREG32(pb_addr + word_offset, ~mask); 12299 12300 pb_addr = (mmTPC6_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; 12301 word_offset = ((mmTPC6_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; 12302 mask = 1U << ((mmTPC6_CFG_ROUND_CSR & 0x7F) >> 2); 12303 12304 WREG32(pb_addr + word_offset, ~mask); 12305 12306 pb_addr = (mmTPC6_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; 12307 word_offset = ((mmTPC6_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; 12308 mask = 1U << ((mmTPC6_CFG_PROT & 0x7F) >> 2); 12309 mask |= 1U << ((mmTPC6_CFG_VFLAGS & 0x7F) >> 2); 12310 mask |= 1U << ((mmTPC6_CFG_SFLAGS & 0x7F) >> 2); 12311 mask |= 1U << ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); 12312 mask |= 1U << ((mmTPC6_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); 12313 mask |= 1U << ((mmTPC6_CFG_TPC_STALL & 0x7F) >> 2); 12314 mask |= 1U << ((mmTPC6_CFG_ICACHE_BASE_ADDERESS_HIGH & 0x7F) >> 2); 12315 mask |= 1U << ((mmTPC6_CFG_RD_RATE_LIMIT & 0x7F) >> 2); 12316 mask |= 1U << ((mmTPC6_CFG_WR_RATE_LIMIT & 0x7F) >> 2); 12317 mask |= 1U << ((mmTPC6_CFG_MSS_CONFIG & 0x7F) >> 2); 12318 mask |= 1U << ((mmTPC6_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); 12319 mask |= 1U << ((mmTPC6_CFG_TPC_INTR_MASK & 0x7F) >> 2); 12320 mask |= 1U << ((mmTPC6_CFG_WQ_CREDITS & 0x7F) >> 2); 12321 mask |= 1U << ((mmTPC6_CFG_ARUSER_LO & 0x7F) >> 2); 12322 mask |= 1U << ((mmTPC6_CFG_ARUSER_HI & 0x7F) >> 2); 12323 mask |= 1U << ((mmTPC6_CFG_AWUSER_LO & 0x7F) >> 2); 12324 mask |= 1U << ((mmTPC6_CFG_AWUSER_HI & 0x7F) >> 2); 12325 mask |= 1U << ((mmTPC6_CFG_OPCODE_EXEC & 0x7F) >> 2); 12326 12327 WREG32(pb_addr + word_offset, ~mask); 12328 12329 pb_addr = (mmTPC6_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; 12330 word_offset = ((mmTPC6_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) 12331 << 2; 12332 mask = 1U << ((mmTPC6_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); 12333 mask |= 1U << ((mmTPC6_CFG_DBGMEM_ADD & 0x7F) >> 2); 12334 mask |= 1U << ((mmTPC6_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); 12335 mask |= 1U << ((mmTPC6_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); 12336 mask |= 1U << ((mmTPC6_CFG_DBGMEM_CTRL & 0x7F) >> 2); 12337 mask |= 1U << ((mmTPC6_CFG_DBGMEM_RC & 0x7F) >> 2); 12338 mask |= 1U << ((mmTPC6_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); 12339 mask |= 1U << ((mmTPC6_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); 12340 mask |= 1U << ((mmTPC6_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); 12341 mask |= 1U << ((mmTPC6_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); 12342 mask |= 1U << ((mmTPC6_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); 12343 mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); 12344 mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); 12345 mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); 12346 mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); 12347 mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); 12348 mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); 12349 mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); 12350 mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); 12351 mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); 12352 mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); 12353 mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); 12354 mask |= 1U << ((mmTPC6_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); 12355 12356 WREG32(pb_addr + word_offset, ~mask); 12357 12358 WREG32(mmTPC7_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 12359 WREG32(mmTPC7_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); 12360 12361 pb_addr = (mmTPC7_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; 12362 word_offset = ((mmTPC7_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; 12363 mask = 1U << ((mmTPC7_QM_GLBL_CFG0 & 0x7F) >> 2); 12364 mask |= 1U << ((mmTPC7_QM_GLBL_CFG1 & 0x7F) >> 2); 12365 mask |= 1U << ((mmTPC7_QM_GLBL_PROT & 0x7F) >> 2); 12366 mask |= 1U << ((mmTPC7_QM_GLBL_ERR_CFG & 0x7F) >> 2); 12367 mask |= 1U << ((mmTPC7_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); 12368 mask |= 1U << ((mmTPC7_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); 12369 mask |= 1U << ((mmTPC7_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); 12370 mask |= 1U << ((mmTPC7_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); 12371 mask |= 1U << ((mmTPC7_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); 12372 mask |= 1U << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); 12373 mask |= 1U << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); 12374 mask |= 1U << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); 12375 mask |= 1U << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); 12376 mask |= 1U << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); 12377 mask |= 1U << ((mmTPC7_QM_GLBL_STS0 & 0x7F) >> 2); 12378 mask |= 1U << ((mmTPC7_QM_GLBL_STS1_0 & 0x7F) >> 2); 12379 mask |= 1U << ((mmTPC7_QM_GLBL_STS1_1 & 0x7F) >> 2); 12380 mask |= 1U << ((mmTPC7_QM_GLBL_STS1_2 & 0x7F) >> 2); 12381 mask |= 1U << ((mmTPC7_QM_GLBL_STS1_3 & 0x7F) >> 2); 12382 mask |= 1U << ((mmTPC7_QM_GLBL_STS1_4 & 0x7F) >> 2); 12383 mask |= 1U << ((mmTPC7_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); 12384 mask |= 1U << ((mmTPC7_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); 12385 mask |= 1U << ((mmTPC7_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); 12386 mask |= 1U << ((mmTPC7_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); 12387 mask |= 1U << ((mmTPC7_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); 12388 mask |= 1U << ((mmTPC7_QM_PQ_BASE_LO_0 & 0x7F) >> 2); 12389 mask |= 1U << ((mmTPC7_QM_PQ_BASE_LO_1 & 0x7F) >> 2); 12390 mask |= 1U << ((mmTPC7_QM_PQ_BASE_LO_2 & 0x7F) >> 2); 12391 mask |= 1U << ((mmTPC7_QM_PQ_BASE_LO_3 & 0x7F) >> 2); 12392 12393 WREG32(pb_addr + word_offset, ~mask); 12394 12395 pb_addr = (mmTPC7_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; 12396 word_offset = ((mmTPC7_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; 12397 mask = 1U << ((mmTPC7_QM_PQ_BASE_HI_0 & 0x7F) >> 2); 12398 mask |= 1U << ((mmTPC7_QM_PQ_BASE_HI_1 & 0x7F) >> 2); 12399 mask |= 1U << ((mmTPC7_QM_PQ_BASE_HI_2 & 0x7F) >> 2); 12400 mask |= 1U << ((mmTPC7_QM_PQ_BASE_HI_3 & 0x7F) >> 2); 12401 mask |= 1U << ((mmTPC7_QM_PQ_SIZE_0 & 0x7F) >> 2); 12402 mask |= 1U << ((mmTPC7_QM_PQ_SIZE_1 & 0x7F) >> 2); 12403 mask |= 1U << ((mmTPC7_QM_PQ_SIZE_2 & 0x7F) >> 2); 12404 mask |= 1U << ((mmTPC7_QM_PQ_SIZE_3 & 0x7F) >> 2); 12405 mask |= 1U << ((mmTPC7_QM_PQ_PI_0 & 0x7F) >> 2); 12406 mask |= 1U << ((mmTPC7_QM_PQ_PI_1 & 0x7F) >> 2); 12407 mask |= 1U << ((mmTPC7_QM_PQ_PI_2 & 0x7F) >> 2); 12408 mask |= 1U << ((mmTPC7_QM_PQ_PI_3 & 0x7F) >> 2); 12409 mask |= 1U << ((mmTPC7_QM_PQ_CI_0 & 0x7F) >> 2); 12410 mask |= 1U << ((mmTPC7_QM_PQ_CI_1 & 0x7F) >> 2); 12411 mask |= 1U << ((mmTPC7_QM_PQ_CI_2 & 0x7F) >> 2); 12412 mask |= 1U << ((mmTPC7_QM_PQ_CI_3 & 0x7F) >> 2); 12413 mask |= 1U << ((mmTPC7_QM_PQ_CFG0_0 & 0x7F) >> 2); 12414 mask |= 1U << ((mmTPC7_QM_PQ_CFG0_1 & 0x7F) >> 2); 12415 mask |= 1U << ((mmTPC7_QM_PQ_CFG0_2 & 0x7F) >> 2); 12416 mask |= 1U << ((mmTPC7_QM_PQ_CFG0_3 & 0x7F) >> 2); 12417 mask |= 1U << ((mmTPC7_QM_PQ_CFG1_0 & 0x7F) >> 2); 12418 mask |= 1U << ((mmTPC7_QM_PQ_CFG1_1 & 0x7F) >> 2); 12419 mask |= 1U << ((mmTPC7_QM_PQ_CFG1_2 & 0x7F) >> 2); 12420 mask |= 1U << ((mmTPC7_QM_PQ_CFG1_3 & 0x7F) >> 2); 12421 mask |= 1U << ((mmTPC7_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); 12422 mask |= 1U << ((mmTPC7_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); 12423 mask |= 1U << ((mmTPC7_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); 12424 mask |= 1U << ((mmTPC7_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); 12425 mask |= 1U << ((mmTPC7_QM_PQ_STS0_0 & 0x7F) >> 2); 12426 mask |= 1U << ((mmTPC7_QM_PQ_STS0_1 & 0x7F) >> 2); 12427 mask |= 1U << ((mmTPC7_QM_PQ_STS0_2 & 0x7F) >> 2); 12428 mask |= 1U << ((mmTPC7_QM_PQ_STS0_3 & 0x7F) >> 2); 12429 12430 WREG32(pb_addr + word_offset, ~mask); 12431 12432 pb_addr = (mmTPC7_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; 12433 word_offset = ((mmTPC7_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; 12434 mask = 1U << ((mmTPC7_QM_PQ_STS1_0 & 0x7F) >> 2); 12435 mask |= 1U << ((mmTPC7_QM_PQ_STS1_1 & 0x7F) >> 2); 12436 mask |= 1U << ((mmTPC7_QM_PQ_STS1_2 & 0x7F) >> 2); 12437 mask |= 1U << ((mmTPC7_QM_PQ_STS1_3 & 0x7F) >> 2); 12438 mask |= 1U << ((mmTPC7_QM_CQ_STS0_0 & 0x7F) >> 2); 12439 mask |= 1U << ((mmTPC7_QM_CQ_STS0_1 & 0x7F) >> 2); 12440 mask |= 1U << ((mmTPC7_QM_CQ_STS0_2 & 0x7F) >> 2); 12441 mask |= 1U << ((mmTPC7_QM_CQ_STS0_3 & 0x7F) >> 2); 12442 mask |= 1U << ((mmTPC7_QM_CQ_STS1_0 & 0x7F) >> 2); 12443 mask |= 1U << ((mmTPC7_QM_CQ_STS1_1 & 0x7F) >> 2); 12444 mask |= 1U << ((mmTPC7_QM_CQ_STS1_2 & 0x7F) >> 2); 12445 mask |= 1U << ((mmTPC7_QM_CQ_STS1_3 & 0x7F) >> 2); 12446 mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_0 & 0x7F) >> 2); 12447 mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_0 & 0x7F) >> 2); 12448 mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_0 & 0x7F) >> 2); 12449 12450 WREG32(pb_addr + word_offset, ~mask); 12451 12452 pb_addr = (mmTPC7_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; 12453 word_offset = ((mmTPC7_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; 12454 mask = 1U << ((mmTPC7_QM_CQ_CTL_0 & 0x7F) >> 2); 12455 mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_1 & 0x7F) >> 2); 12456 mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_1 & 0x7F) >> 2); 12457 mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_1 & 0x7F) >> 2); 12458 mask |= 1U << ((mmTPC7_QM_CQ_CTL_1 & 0x7F) >> 2); 12459 mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_2 & 0x7F) >> 2); 12460 mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_2 & 0x7F) >> 2); 12461 mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_2 & 0x7F) >> 2); 12462 mask |= 1U << ((mmTPC7_QM_CQ_CTL_2 & 0x7F) >> 2); 12463 mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_3 & 0x7F) >> 2); 12464 mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_3 & 0x7F) >> 2); 12465 mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_3 & 0x7F) >> 2); 12466 mask |= 1U << ((mmTPC7_QM_CQ_CTL_3 & 0x7F) >> 2); 12467 mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); 12468 mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); 12469 mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); 12470 mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); 12471 mask |= 1U << ((mmTPC7_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); 12472 mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); 12473 mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); 12474 mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); 12475 mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); 12476 mask |= 1U << ((mmTPC7_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); 12477 mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); 12478 mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); 12479 mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); 12480 mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); 12481 mask |= 1U << ((mmTPC7_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); 12482 12483 WREG32(pb_addr + word_offset, ~mask); 12484 12485 pb_addr = (mmTPC7_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 12486 word_offset = ((mmTPC7_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 12487 mask = 1U << ((mmTPC7_QM_CQ_CTL_STS_0 & 0x7F) >> 2); 12488 mask |= 1U << ((mmTPC7_QM_CQ_CTL_STS_1 & 0x7F) >> 2); 12489 mask |= 1U << ((mmTPC7_QM_CQ_CTL_STS_2 & 0x7F) >> 2); 12490 mask |= 1U << ((mmTPC7_QM_CQ_CTL_STS_3 & 0x7F) >> 2); 12491 mask |= 1U << ((mmTPC7_QM_CQ_CTL_STS_4 & 0x7F) >> 2); 12492 mask |= 1U << ((mmTPC7_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); 12493 mask |= 1U << ((mmTPC7_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); 12494 mask |= 1U << ((mmTPC7_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); 12495 mask |= 1U << ((mmTPC7_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); 12496 mask |= 1U << ((mmTPC7_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); 12497 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); 12498 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); 12499 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); 12500 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); 12501 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); 12502 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); 12503 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); 12504 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); 12505 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); 12506 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); 12507 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); 12508 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); 12509 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); 12510 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); 12511 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); 12512 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); 12513 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); 12514 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); 12515 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); 12516 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); 12517 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); 12518 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); 12519 12520 WREG32(pb_addr + word_offset, ~mask); 12521 12522 pb_addr = (mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; 12523 word_offset = ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) 12524 << 2; 12525 mask = 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); 12526 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); 12527 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); 12528 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); 12529 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); 12530 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); 12531 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); 12532 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); 12533 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); 12534 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); 12535 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); 12536 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); 12537 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); 12538 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); 12539 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); 12540 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); 12541 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); 12542 mask |= 1U << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); 12543 mask |= 1U << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); 12544 mask |= 1U << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); 12545 mask |= 1U << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); 12546 mask |= 1U << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); 12547 mask |= 1U << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); 12548 mask |= 1U << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); 12549 mask |= 1U << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); 12550 mask |= 1U << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); 12551 mask |= 1U << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); 12552 mask |= 1U << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); 12553 mask |= 1U << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); 12554 mask |= 1U << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); 12555 mask |= 1U << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); 12556 12557 WREG32(pb_addr + word_offset, ~mask); 12558 12559 pb_addr = (mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + 12560 PROT_BITS_OFFS; 12561 12562 word_offset = ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) 12563 >> 7) << 2; 12564 12565 mask = 1U << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); 12566 mask |= 1U << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); 12567 12568 WREG32(pb_addr + word_offset, ~mask); 12569 12570 pb_addr = (mmTPC7_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; 12571 word_offset = ((mmTPC7_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; 12572 mask = 1U << ((mmTPC7_QM_CP_STS_0 & 0x7F) >> 2); 12573 mask |= 1U << ((mmTPC7_QM_CP_STS_1 & 0x7F) >> 2); 12574 mask |= 1U << ((mmTPC7_QM_CP_STS_2 & 0x7F) >> 2); 12575 mask |= 1U << ((mmTPC7_QM_CP_STS_3 & 0x7F) >> 2); 12576 mask |= 1U << ((mmTPC7_QM_CP_STS_4 & 0x7F) >> 2); 12577 mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); 12578 mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); 12579 mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); 12580 mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); 12581 mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); 12582 mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); 12583 mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); 12584 mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); 12585 mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); 12586 mask |= 1U << ((mmTPC7_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); 12587 mask |= 1U << ((mmTPC7_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); 12588 mask |= 1U << ((mmTPC7_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); 12589 mask |= 1U << ((mmTPC7_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); 12590 12591 WREG32(pb_addr + word_offset, ~mask); 12592 12593 pb_addr = (mmTPC7_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; 12594 word_offset = ((mmTPC7_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; 12595 mask = 1U << ((mmTPC7_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); 12596 mask |= 1U << ((mmTPC7_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); 12597 mask |= 1U << ((mmTPC7_QM_CP_DBG_0_0 & 0x7F) >> 2); 12598 mask |= 1U << ((mmTPC7_QM_CP_DBG_0_1 & 0x7F) >> 2); 12599 12600 WREG32(pb_addr + word_offset, ~mask); 12601 12602 pb_addr = (mmTPC7_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; 12603 word_offset = ((mmTPC7_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; 12604 mask = 1U << ((mmTPC7_QM_CP_DBG_0_2 & 0x7F) >> 2); 12605 mask |= 1U << ((mmTPC7_QM_CP_DBG_0_3 & 0x7F) >> 2); 12606 mask |= 1U << ((mmTPC7_QM_CP_DBG_0_4 & 0x7F) >> 2); 12607 mask |= 1U << ((mmTPC7_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); 12608 mask |= 1U << ((mmTPC7_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); 12609 mask |= 1U << ((mmTPC7_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); 12610 mask |= 1U << ((mmTPC7_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); 12611 mask |= 1U << ((mmTPC7_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); 12612 mask |= 1U << ((mmTPC7_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); 12613 mask |= 1U << ((mmTPC7_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); 12614 mask |= 1U << ((mmTPC7_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); 12615 mask |= 1U << ((mmTPC7_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); 12616 mask |= 1U << ((mmTPC7_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); 12617 12618 WREG32(pb_addr + word_offset, ~mask); 12619 12620 pb_addr = (mmTPC7_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; 12621 word_offset = ((mmTPC7_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; 12622 mask = 1U << ((mmTPC7_QM_ARB_CFG_1 & 0x7F) >> 2); 12623 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); 12624 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); 12625 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); 12626 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); 12627 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); 12628 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); 12629 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); 12630 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); 12631 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); 12632 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); 12633 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); 12634 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); 12635 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); 12636 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); 12637 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); 12638 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); 12639 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); 12640 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); 12641 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); 12642 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); 12643 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); 12644 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); 12645 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); 12646 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); 12647 12648 WREG32(pb_addr + word_offset, ~mask); 12649 12650 pb_addr = (mmTPC7_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; 12651 word_offset = ((mmTPC7_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) 12652 << 2; 12653 mask = 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); 12654 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); 12655 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); 12656 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); 12657 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); 12658 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); 12659 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); 12660 mask |= 1U << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); 12661 12662 WREG32(pb_addr + word_offset, ~mask); 12663 12664 pb_addr = (mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + 12665 PROT_BITS_OFFS; 12666 word_offset = ((mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) 12667 >> 7) << 2; 12668 mask = 1U << ((mmTPC7_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); 12669 mask |= 1U << ((mmTPC7_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); 12670 mask |= 1U << ((mmTPC7_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); 12671 mask |= 1U << ((mmTPC7_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); 12672 mask |= 1U << ((mmTPC7_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); 12673 12674 WREG32(pb_addr + word_offset, ~mask); 12675 12676 pb_addr = (mmTPC7_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; 12677 word_offset = ((mmTPC7_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; 12678 mask = 1U << ((mmTPC7_QM_ARB_STATE_STS & 0x7F) >> 2); 12679 mask |= 1U << ((mmTPC7_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); 12680 mask |= 1U << ((mmTPC7_QM_ARB_MSG_STS & 0x7F) >> 2); 12681 mask |= 1U << ((mmTPC7_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); 12682 mask |= 1U << ((mmTPC7_QM_ARB_ERR_CAUSE & 0x7F) >> 2); 12683 mask |= 1U << ((mmTPC7_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); 12684 mask |= 1U << ((mmTPC7_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); 12685 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); 12686 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); 12687 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); 12688 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); 12689 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); 12690 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); 12691 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); 12692 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); 12693 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); 12694 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); 12695 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); 12696 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); 12697 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); 12698 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); 12699 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); 12700 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); 12701 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); 12702 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); 12703 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); 12704 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); 12705 12706 WREG32(pb_addr + word_offset, ~mask); 12707 12708 pb_addr = (mmTPC7_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; 12709 word_offset = ((mmTPC7_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) 12710 << 2; 12711 mask = 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); 12712 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); 12713 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); 12714 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); 12715 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); 12716 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); 12717 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); 12718 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); 12719 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); 12720 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); 12721 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); 12722 mask |= 1U << ((mmTPC7_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); 12723 mask |= 1U << ((mmTPC7_QM_CGM_CFG & 0x7F) >> 2); 12724 mask |= 1U << ((mmTPC7_QM_CGM_STS & 0x7F) >> 2); 12725 mask |= 1U << ((mmTPC7_QM_CGM_CFG1 & 0x7F) >> 2); 12726 12727 WREG32(pb_addr + word_offset, ~mask); 12728 12729 pb_addr = (mmTPC7_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; 12730 word_offset = ((mmTPC7_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; 12731 mask = 1U << ((mmTPC7_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); 12732 mask |= 1U << ((mmTPC7_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); 12733 mask |= 1U << ((mmTPC7_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); 12734 mask |= 1U << ((mmTPC7_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); 12735 mask |= 1U << ((mmTPC7_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); 12736 mask |= 1U << ((mmTPC7_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); 12737 mask |= 1U << ((mmTPC7_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); 12738 mask |= 1U << ((mmTPC7_QM_GLBL_AXCACHE & 0x7F) >> 2); 12739 mask |= 1U << ((mmTPC7_QM_IND_GW_APB_CFG & 0x7F) >> 2); 12740 mask |= 1U << ((mmTPC7_QM_IND_GW_APB_WDATA & 0x7F) >> 2); 12741 mask |= 1U << ((mmTPC7_QM_IND_GW_APB_RDATA & 0x7F) >> 2); 12742 mask |= 1U << ((mmTPC7_QM_IND_GW_APB_STATUS & 0x7F) >> 2); 12743 mask |= 1U << ((mmTPC7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); 12744 mask |= 1U << ((mmTPC7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); 12745 mask |= 1U << ((mmTPC7_QM_GLBL_ERR_WDATA & 0x7F) >> 2); 12746 12747 WREG32(pb_addr + word_offset, ~mask); 12748 12749 pb_addr = (mmTPC7_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; 12750 word_offset = ((mmTPC7_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) 12751 << 2; 12752 mask = 1U << ((mmTPC7_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); 12753 12754 WREG32(pb_addr + word_offset, ~mask); 12755 12756 pb_addr = (mmTPC7_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; 12757 word_offset = ((mmTPC7_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; 12758 mask = 1U << ((mmTPC7_CFG_ROUND_CSR & 0x7F) >> 2); 12759 12760 WREG32(pb_addr + word_offset, ~mask); 12761 12762 pb_addr = (mmTPC7_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; 12763 word_offset = ((mmTPC7_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; 12764 mask = 1U << ((mmTPC7_CFG_PROT & 0x7F) >> 2); 12765 mask |= 1U << ((mmTPC7_CFG_VFLAGS & 0x7F) >> 2); 12766 mask |= 1U << ((mmTPC7_CFG_SFLAGS & 0x7F) >> 2); 12767 mask |= 1U << ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); 12768 mask |= 1U << ((mmTPC7_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); 12769 mask |= 1U << ((mmTPC7_CFG_TPC_STALL & 0x7F) >> 2); 12770 mask |= 1U << ((mmTPC7_CFG_ICACHE_BASE_ADDERESS_HIGH & 0x7F) >> 2); 12771 mask |= 1U << ((mmTPC7_CFG_RD_RATE_LIMIT & 0x7F) >> 2); 12772 mask |= 1U << ((mmTPC7_CFG_WR_RATE_LIMIT & 0x7F) >> 2); 12773 mask |= 1U << ((mmTPC7_CFG_MSS_CONFIG & 0x7F) >> 2); 12774 mask |= 1U << ((mmTPC7_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); 12775 mask |= 1U << ((mmTPC7_CFG_TPC_INTR_MASK & 0x7F) >> 2); 12776 mask |= 1U << ((mmTPC7_CFG_WQ_CREDITS & 0x7F) >> 2); 12777 mask |= 1U << ((mmTPC7_CFG_ARUSER_LO & 0x7F) >> 2); 12778 mask |= 1U << ((mmTPC7_CFG_ARUSER_HI & 0x7F) >> 2); 12779 mask |= 1U << ((mmTPC7_CFG_AWUSER_LO & 0x7F) >> 2); 12780 mask |= 1U << ((mmTPC7_CFG_AWUSER_HI & 0x7F) >> 2); 12781 mask |= 1U << ((mmTPC7_CFG_OPCODE_EXEC & 0x7F) >> 2); 12782 12783 WREG32(pb_addr + word_offset, ~mask); 12784 12785 pb_addr = (mmTPC7_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; 12786 word_offset = ((mmTPC7_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) 12787 << 2; 12788 mask = 1U << ((mmTPC7_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); 12789 mask |= 1U << ((mmTPC7_CFG_DBGMEM_ADD & 0x7F) >> 2); 12790 mask |= 1U << ((mmTPC7_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); 12791 mask |= 1U << ((mmTPC7_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); 12792 mask |= 1U << ((mmTPC7_CFG_DBGMEM_CTRL & 0x7F) >> 2); 12793 mask |= 1U << ((mmTPC7_CFG_DBGMEM_RC & 0x7F) >> 2); 12794 mask |= 1U << ((mmTPC7_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); 12795 mask |= 1U << ((mmTPC7_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); 12796 mask |= 1U << ((mmTPC7_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); 12797 mask |= 1U << ((mmTPC7_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); 12798 mask |= 1U << ((mmTPC7_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); 12799 mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); 12800 mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); 12801 mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); 12802 mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); 12803 mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); 12804 mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); 12805 mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); 12806 mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); 12807 mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); 12808 mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); 12809 mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); 12810 mask |= 1U << ((mmTPC7_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); 12811 12812 WREG32(pb_addr + word_offset, ~mask); 12813} 12814 12815/** 12816 * gaudi_init_protection_bits - Initialize protection bits of specific registers 12817 * 12818 * @hdev: pointer to hl_device structure 12819 * 12820 * All protection bits are 1 by default, means not protected. Need to set to 0 12821 * each bit that belongs to a protected register. 12822 * 12823 */ 12824static void gaudi_init_protection_bits(struct hl_device *hdev) 12825{ 12826 /* 12827 * In each 4K block of registers, the last 128 bytes are protection 12828 * bits - total of 1024 bits, one for each register. Each bit is related 12829 * to a specific register, by the order of the registers. 12830 * So in order to calculate the bit that is related to a given register, 12831 * we need to calculate its word offset and then the exact bit inside 12832 * the word (which is 4 bytes). 12833 * 12834 * Register address: 12835 * 12836 * 31 12 11 7 6 2 1 0 12837 * ----------------------------------------------------------------- 12838 * | Don't | word | bit location | 0 | 12839 * | care | offset | inside word | | 12840 * ----------------------------------------------------------------- 12841 * 12842 * Bits 7-11 represents the word offset inside the 128 bytes. 12843 * Bits 2-6 represents the bit location inside the word. 12844 * 12845 * When a bit is cleared, it means the register it represents can only 12846 * be accessed by a secured entity. When the bit is set, any entity can 12847 * access the register. 12848 * 12849 * The last 4 bytes in the block of the PBs control the security of 12850 * the PBs themselves, so they always need to be configured to be 12851 * secured 12852 */ 12853 12854 if (!hdev->asic_prop.fw_security_enabled) { 12855 gaudi_pb_set_block(hdev, mmIF_E_PLL_BASE); 12856 gaudi_pb_set_block(hdev, mmMESH_W_PLL_BASE); 12857 gaudi_pb_set_block(hdev, mmSRAM_W_PLL_BASE); 12858 gaudi_pb_set_block(hdev, mmMESH_E_PLL_BASE); 12859 gaudi_pb_set_block(hdev, mmSRAM_E_PLL_BASE); 12860 } 12861 12862 gaudi_init_dma_protection_bits(hdev); 12863 12864 gaudi_init_mme_protection_bits(hdev); 12865 12866 gaudi_init_nic_protection_bits(hdev); 12867 12868 gaudi_init_tpc_protection_bits(hdev); 12869} 12870 12871static void gaudi_init_range_registers_lbw(struct hl_device *hdev) 12872{ 12873 u32 lbw_rng_start[GAUDI_NUMBER_OF_LBW_RANGES]; 12874 u32 lbw_rng_end[GAUDI_NUMBER_OF_LBW_RANGES]; 12875 int i, j; 12876 12877 lbw_rng_start[0] = (0xFC0E8000 & 0x3FFFFFF) - 1; /* 0x000E7FFF */ 12878 lbw_rng_end[0] = (0xFC11FFFF & 0x3FFFFFF) + 1; /* 0x00120000 */ 12879 12880 lbw_rng_start[1] = (0xFC1E8000 & 0x3FFFFFF) - 1; /* 0x001E7FFF */ 12881 lbw_rng_end[1] = (0xFC48FFFF & 0x3FFFFFF) + 1; /* 0x00490000 */ 12882 12883 lbw_rng_start[2] = (0xFC600000 & 0x3FFFFFF) - 1; /* 0x005FFFFF */ 12884 lbw_rng_end[2] = (0xFCC48FFF & 0x3FFFFFF) + 1; /* 0x00C49000 */ 12885 12886 lbw_rng_start[3] = (0xFCC4A000 & 0x3FFFFFF) - 1; /* 0x00C49FFF */ 12887 lbw_rng_end[3] = (0xFCCDFFFF & 0x3FFFFFF) + 1; /* 0x00CE0000 */ 12888 12889 lbw_rng_start[4] = (0xFCCE4000 & 0x3FFFFFF) - 1; /* 0x00CE3FFF */ 12890 lbw_rng_end[4] = (0xFCD1FFFF & 0x3FFFFFF) + 1; /* 0x00D20000 */ 12891 12892 lbw_rng_start[5] = (0xFCD24000 & 0x3FFFFFF) - 1; /* 0x00D23FFF */ 12893 lbw_rng_end[5] = (0xFCD5FFFF & 0x3FFFFFF) + 1; /* 0x00D60000 */ 12894 12895 lbw_rng_start[6] = (0xFCD64000 & 0x3FFFFFF) - 1; /* 0x00D63FFF */ 12896 lbw_rng_end[6] = (0xFCD9FFFF & 0x3FFFFFF) + 1; /* 0x00DA0000 */ 12897 12898 lbw_rng_start[7] = (0xFCDA4000 & 0x3FFFFFF) - 1; /* 0x00DA3FFF */ 12899 lbw_rng_end[7] = (0xFCDDFFFF & 0x3FFFFFF) + 1; /* 0x00DE0000 */ 12900 12901 lbw_rng_start[8] = (0xFCDE4000 & 0x3FFFFFF) - 1; /* 0x00DE3FFF */ 12902 lbw_rng_end[8] = (0xFCE05FFF & 0x3FFFFFF) + 1; /* 0x00E06000 */ 12903 12904 lbw_rng_start[9] = (0xFCFC9000 & 0x3FFFFFF) - 1; /* 0x00FC8FFF */ 12905 lbw_rng_end[9] = (0xFFFFFFFE & 0x3FFFFFF) + 1; /* 0x03FFFFFF */ 12906 12907 for (i = 0 ; i < GAUDI_NUMBER_OF_LBW_RR_REGS ; i++) { 12908 WREG32(gaudi_rr_lbw_hit_aw_regs[i], 12909 (1 << GAUDI_NUMBER_OF_LBW_RANGES) - 1); 12910 WREG32(gaudi_rr_lbw_hit_ar_regs[i], 12911 (1 << GAUDI_NUMBER_OF_LBW_RANGES) - 1); 12912 } 12913 12914 for (i = 0 ; i < GAUDI_NUMBER_OF_LBW_RR_REGS ; i++) 12915 for (j = 0 ; j < GAUDI_NUMBER_OF_LBW_RANGES ; j++) { 12916 WREG32(gaudi_rr_lbw_min_aw_regs[i] + (j << 2), 12917 lbw_rng_start[j]); 12918 12919 WREG32(gaudi_rr_lbw_min_ar_regs[i] + (j << 2), 12920 lbw_rng_start[j]); 12921 12922 WREG32(gaudi_rr_lbw_max_aw_regs[i] + (j << 2), 12923 lbw_rng_end[j]); 12924 12925 WREG32(gaudi_rr_lbw_max_ar_regs[i] + (j << 2), 12926 lbw_rng_end[j]); 12927 } 12928} 12929 12930static void gaudi_init_range_registers_hbw(struct hl_device *hdev) 12931{ 12932 struct gaudi_device *gaudi = hdev->asic_specific; 12933 12934 u32 dram_addr_lo = lower_32_bits(DRAM_PHYS_BASE); 12935 u32 dram_addr_hi = upper_32_bits(DRAM_PHYS_BASE); 12936 12937 u32 sram_addr_lo = lower_32_bits(SRAM_BASE_ADDR); 12938 u32 sram_addr_hi = upper_32_bits(SRAM_BASE_ADDR); 12939 12940 u32 scratch_addr_lo = lower_32_bits(PSOC_SCRATCHPAD_ADDR); 12941 u32 scratch_addr_hi = upper_32_bits(PSOC_SCRATCHPAD_ADDR); 12942 12943 u32 pcie_fw_addr_lo = lower_32_bits(PCIE_FW_SRAM_ADDR); 12944 u32 pcie_fw_addr_hi = upper_32_bits(PCIE_FW_SRAM_ADDR); 12945 12946 u32 spi_addr_lo = lower_32_bits(SPI_FLASH_BASE_ADDR); 12947 u32 spi_addr_hi = upper_32_bits(SPI_FLASH_BASE_ADDR); 12948 12949 int i; 12950 12951 /* Configure HBW RR: 12952 * 1st range is the DRAM (first 512MB) 12953 * 2nd range is the 1st 128 bytes in SRAM (for tensor DMA). This area 12954 * is defined as read-only for user 12955 * 3rd range is the PSOC scratch-pad 12956 * 4th range is the PCIe F/W SRAM area 12957 * 5th range is the SPI FLASH area 12958 * 6th range is the host 12959 */ 12960 12961 for (i = 0 ; i < GAUDI_NUMBER_OF_HBW_RR_REGS ; i++) { 12962 WREG32(gaudi_rr_hbw_hit_aw_regs[i], 0x1F); 12963 WREG32(gaudi_rr_hbw_hit_ar_regs[i], 0x1D); 12964 } 12965 12966 for (i = 0 ; i < GAUDI_NUMBER_OF_HBW_RR_REGS ; i++) { 12967 WREG32(gaudi_rr_hbw_base_low_aw_regs[i], dram_addr_lo); 12968 WREG32(gaudi_rr_hbw_base_low_ar_regs[i], dram_addr_lo); 12969 12970 WREG32(gaudi_rr_hbw_base_high_aw_regs[i], dram_addr_hi); 12971 WREG32(gaudi_rr_hbw_base_high_ar_regs[i], dram_addr_hi); 12972 12973 WREG32(gaudi_rr_hbw_mask_low_aw_regs[i], 0xE0000000); 12974 WREG32(gaudi_rr_hbw_mask_low_ar_regs[i], 0xE0000000); 12975 12976 WREG32(gaudi_rr_hbw_mask_high_aw_regs[i], 0x3FFFF); 12977 WREG32(gaudi_rr_hbw_mask_high_ar_regs[i], 0x3FFFF); 12978 12979 WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 4, sram_addr_lo); 12980 WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 4, sram_addr_hi); 12981 WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 4, 0xFFFFFF80); 12982 WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 4, 0x3FFFF); 12983 12984 WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 8, scratch_addr_lo); 12985 WREG32(gaudi_rr_hbw_base_low_ar_regs[i] + 8, scratch_addr_lo); 12986 12987 WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 8, scratch_addr_hi); 12988 WREG32(gaudi_rr_hbw_base_high_ar_regs[i] + 8, scratch_addr_hi); 12989 12990 WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 8, 0xFFFF0000); 12991 WREG32(gaudi_rr_hbw_mask_low_ar_regs[i] + 8, 0xFFFF0000); 12992 12993 WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 8, 0x3FFFF); 12994 WREG32(gaudi_rr_hbw_mask_high_ar_regs[i] + 8, 0x3FFFF); 12995 12996 WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 12, pcie_fw_addr_lo); 12997 WREG32(gaudi_rr_hbw_base_low_ar_regs[i] + 12, pcie_fw_addr_lo); 12998 12999 WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 12, pcie_fw_addr_hi); 13000 WREG32(gaudi_rr_hbw_base_high_ar_regs[i] + 12, pcie_fw_addr_hi); 13001 13002 WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 12, 0xFFFF8000); 13003 WREG32(gaudi_rr_hbw_mask_low_ar_regs[i] + 12, 0xFFFF8000); 13004 13005 WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 12, 0x3FFFF); 13006 WREG32(gaudi_rr_hbw_mask_high_ar_regs[i] + 12, 0x3FFFF); 13007 13008 WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 16, spi_addr_lo); 13009 WREG32(gaudi_rr_hbw_base_low_ar_regs[i] + 16, spi_addr_lo); 13010 13011 WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 16, spi_addr_hi); 13012 WREG32(gaudi_rr_hbw_base_high_ar_regs[i] + 16, spi_addr_hi); 13013 13014 WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 16, 0xFE000000); 13015 WREG32(gaudi_rr_hbw_mask_low_ar_regs[i] + 16, 0xFE000000); 13016 13017 WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 16, 0x3FFFF); 13018 WREG32(gaudi_rr_hbw_mask_high_ar_regs[i] + 16, 0x3FFFF); 13019 13020 if (gaudi->hw_cap_initialized & HW_CAP_MMU) 13021 continue; 13022 13023 /* Protect HOST */ 13024 WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 20, 0); 13025 WREG32(gaudi_rr_hbw_base_low_ar_regs[i] + 20, 0); 13026 13027 WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 20, 0); 13028 WREG32(gaudi_rr_hbw_base_high_ar_regs[i] + 20, 0); 13029 13030 WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 20, 0); 13031 WREG32(gaudi_rr_hbw_mask_low_ar_regs[i] + 20, 0); 13032 13033 WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 20, 0xFFF80); 13034 WREG32(gaudi_rr_hbw_mask_high_ar_regs[i] + 20, 0xFFF80); 13035 } 13036} 13037 13038/** 13039 * gaudi_init_security - Initialize security model 13040 * 13041 * @hdev: pointer to hl_device structure 13042 * 13043 * Initialize the security model of the device 13044 * That includes range registers and protection bit per register 13045 * 13046 */ 13047void gaudi_init_security(struct hl_device *hdev) 13048{ 13049 /* Due to H/W errata GAUDI0500, need to override default security 13050 * property configuration of MME SBAB and ACC to be non-privileged and 13051 * non-secured 13052 */ 13053 if (!hdev->asic_prop.fw_security_enabled) { 13054 WREG32(mmMME0_SBAB_PROT, 0x2); 13055 WREG32(mmMME0_ACC_PROT, 0x2); 13056 WREG32(mmMME1_SBAB_PROT, 0x2); 13057 WREG32(mmMME1_ACC_PROT, 0x2); 13058 WREG32(mmMME2_SBAB_PROT, 0x2); 13059 WREG32(mmMME2_ACC_PROT, 0x2); 13060 WREG32(mmMME3_SBAB_PROT, 0x2); 13061 WREG32(mmMME3_ACC_PROT, 0x2); 13062 13063 /* 13064 * On RAZWI, 0 will be returned from RR and 0xBABA0BAD from PB 13065 */ 13066 WREG32(0xC01B28, 0x1); 13067 } 13068 13069 gaudi_init_range_registers_lbw(hdev); 13070 13071 gaudi_init_range_registers_hbw(hdev); 13072 13073 gaudi_init_protection_bits(hdev); 13074} 13075 13076void gaudi_ack_protection_bits_errors(struct hl_device *hdev) 13077{ 13078 13079}
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