npu4_regs.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
  4 */
  5
  6#include <drm/amdxdna_accel.h>
  7#include <drm/drm_device.h>
  8#include <drm/gpu_scheduler.h>
  9#include <linux/sizes.h>
 10
 11#include "aie2_pci.h"
 12#include "amdxdna_mailbox.h"
 13#include "amdxdna_pci_drv.h"
 14
 15/* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */
 16#define MPNPU_PUB_SEC_INTR             0x3010060
 17#define MPNPU_PUB_PWRMGMT_INTR         0x3010064
 18#define MPNPU_PUB_SCRATCH0             0x301006C
 19#define MPNPU_PUB_SCRATCH1             0x3010070
 20#define MPNPU_PUB_SCRATCH2             0x3010074
 21#define MPNPU_PUB_SCRATCH3             0x3010078
 22#define MPNPU_PUB_SCRATCH4             0x301007C
 23#define MPNPU_PUB_SCRATCH5             0x3010080
 24#define MPNPU_PUB_SCRATCH6             0x3010084
 25#define MPNPU_PUB_SCRATCH7             0x3010088
 26#define MPNPU_PUB_SCRATCH8             0x301008C
 27#define MPNPU_PUB_SCRATCH9             0x3010090
 28#define MPNPU_PUB_SCRATCH10            0x3010094
 29#define MPNPU_PUB_SCRATCH11            0x3010098
 30#define MPNPU_PUB_SCRATCH12            0x301009C
 31#define MPNPU_PUB_SCRATCH13            0x30100A0
 32#define MPNPU_PUB_SCRATCH14            0x30100A4
 33#define MPNPU_PUB_SCRATCH15            0x30100A8
 34#define MP0_C2PMSG_73                  0x3810A24
 35#define MP0_C2PMSG_123                 0x3810AEC
 36
 37#define MP1_C2PMSG_0                   0x3B10900
 38#define MP1_C2PMSG_60                  0x3B109F0
 39#define MP1_C2PMSG_61                  0x3B109F4
 40
 41#define MPNPU_SRAM_X2I_MAILBOX_0       0x3600000
 42#define MPNPU_SRAM_X2I_MAILBOX_15      0x361E000
 43#define MPNPU_SRAM_X2I_MAILBOX_31      0x363E000
 44#define MPNPU_SRAM_I2X_MAILBOX_31      0x363F000
 45
 46#define MMNPU_APERTURE0_BASE           0x3000000
 47#define MMNPU_APERTURE1_BASE           0x3600000
 48#define MMNPU_APERTURE3_BASE           0x3810000
 49#define MMNPU_APERTURE4_BASE           0x3B10000
 50
 51/* PCIe BAR Index for NPU4 */
 52#define NPU4_REG_BAR_INDEX	0
 53#define NPU4_MBOX_BAR_INDEX	0
 54#define NPU4_PSP_BAR_INDEX	4
 55#define NPU4_SMU_BAR_INDEX	5
 56#define NPU4_SRAM_BAR_INDEX	2
 57/* Associated BARs and Apertures */
 58#define NPU4_REG_BAR_BASE	MMNPU_APERTURE0_BASE
 59#define NPU4_MBOX_BAR_BASE	MMNPU_APERTURE0_BASE
 60#define NPU4_PSP_BAR_BASE	MMNPU_APERTURE3_BASE
 61#define NPU4_SMU_BAR_BASE	MMNPU_APERTURE4_BASE
 62#define NPU4_SRAM_BAR_BASE	MMNPU_APERTURE1_BASE
 63
 64const struct rt_config npu4_default_rt_cfg[] = {
 65	{ 5, 1, AIE2_RT_CFG_INIT }, /* PDI APP LOAD MODE */
 66	{ 10, 1, AIE2_RT_CFG_INIT }, /* DEBUG BUF */
 67	{ 14, 0, AIE2_RT_CFG_INIT, BIT_U64(AIE2_PREEMPT) }, /* Frame boundary preemption */
 68	{ 1, 1, AIE2_RT_CFG_CLK_GATING }, /* Clock gating on */
 69	{ 2, 1, AIE2_RT_CFG_CLK_GATING }, /* Clock gating on */
 70	{ 3, 1, AIE2_RT_CFG_CLK_GATING }, /* Clock gating on */
 71	{ 4, 1, AIE2_RT_CFG_CLK_GATING }, /* Clock gating on */
 72	{ 13, 0, AIE2_RT_CFG_FORCE_PREEMPT },
 73	{ 14, 0, AIE2_RT_CFG_FRAME_BOUNDARY_PREEMPT },
 74	{ 0 },
 75};
 76
 77const struct dpm_clk_freq npu4_dpm_clk_table[] = {
 78	{396, 792},
 79	{600, 1056},
 80	{792, 1152},
 81	{975, 1267},
 82	{975, 1267},
 83	{1056, 1408},
 84	{1152, 1584},
 85	{1267, 1800},
 86	{ 0 }
 87};
 88
 89const struct aie2_fw_feature_tbl npu4_fw_feature_table[] = {
 90	{ .feature = AIE2_NPU_COMMAND, .min_minor = 15 },
 91	{ .feature = AIE2_PREEMPT, .min_minor = 12 },
 92	{ .feature = AIE2_TEMPORAL_ONLY, .min_minor = 12 },
 93	{ 0 }
 94};
 95
 96static const struct amdxdna_dev_priv npu4_dev_priv = {
 97	.fw_path        = "amdnpu/17f0_10/npu.sbin",
 98	.protocol_major = 0x6,
 99	.protocol_minor = 12,
100	.rt_config	= npu4_default_rt_cfg,
101	.dpm_clk_tbl	= npu4_dpm_clk_table,
102	.fw_feature_tbl = npu4_fw_feature_table,
103	.col_align	= COL_ALIGN_NATURE,
104	.mbox_dev_addr  = NPU4_MBOX_BAR_BASE,
105	.mbox_size      = 0, /* Use BAR size */
106	.sram_dev_addr  = NPU4_SRAM_BAR_BASE,
107	.hwctx_limit    = 16,
108	.sram_offs      = {
109		DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU4_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
110		DEFINE_BAR_OFFSET(FW_ALIVE_OFF,   NPU4_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),
111	},
112	.psp_regs_off   = {
113		DEFINE_BAR_OFFSET(PSP_CMD_REG,    NPU4_PSP, MP0_C2PMSG_123),
114		DEFINE_BAR_OFFSET(PSP_ARG0_REG,   NPU4_REG, MPNPU_PUB_SCRATCH3),
115		DEFINE_BAR_OFFSET(PSP_ARG1_REG,   NPU4_REG, MPNPU_PUB_SCRATCH4),
116		DEFINE_BAR_OFFSET(PSP_ARG2_REG,   NPU4_REG, MPNPU_PUB_SCRATCH9),
117		DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU4_PSP, MP0_C2PMSG_73),
118		DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU4_PSP, MP0_C2PMSG_123),
119		DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU4_REG, MPNPU_PUB_SCRATCH3),
120	},
121	.smu_regs_off   = {
122		DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU4_SMU, MP1_C2PMSG_0),
123		DEFINE_BAR_OFFSET(SMU_ARG_REG,  NPU4_SMU, MP1_C2PMSG_60),
124		DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU4_SMU, MMNPU_APERTURE4_BASE),
125		DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU4_SMU, MP1_C2PMSG_61),
126		DEFINE_BAR_OFFSET(SMU_OUT_REG,  NPU4_SMU, MP1_C2PMSG_60),
127	},
128	.hw_ops		= {
129		.set_dpm = npu4_set_dpm,
130	},
131};
132
133const struct amdxdna_dev_info dev_npu4_info = {
134	.reg_bar           = NPU4_REG_BAR_INDEX,
135	.mbox_bar          = NPU4_MBOX_BAR_INDEX,
136	.sram_bar          = NPU4_SRAM_BAR_INDEX,
137	.psp_bar           = NPU4_PSP_BAR_INDEX,
138	.smu_bar           = NPU4_SMU_BAR_INDEX,
139	.first_col         = 0,
140	.dev_mem_buf_shift = 15, /* 32 KiB aligned */
141	.dev_mem_base      = AIE2_DEVM_BASE,
142	.dev_mem_size      = AIE2_DEVM_SIZE,
143	.vbnv              = "RyzenAI-npu4",
144	.device_type       = AMDXDNA_DEV_TYPE_KMQ,
145	.dev_priv          = &npu4_dev_priv,
146	.ops               = &aie2_ops, /* NPU4 can share NPU1's callback */
147};