npu1_regs.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
  4 */
  5
  6#include <drm/amdxdna_accel.h>
  7#include <drm/drm_device.h>
  8#include <drm/gpu_scheduler.h>
  9#include <linux/sizes.h>
 10
 11#include "aie2_pci.h"
 12#include "amdxdna_mailbox.h"
 13#include "amdxdna_pci_drv.h"
 14
 15/* Address definition from NPU1 docs */
 16#define MPNPU_PUB_SEC_INTR		0x3010090
 17#define MPNPU_PUB_PWRMGMT_INTR		0x3010094
 18#define MPNPU_PUB_SCRATCH2		0x30100A0
 19#define MPNPU_PUB_SCRATCH3		0x30100A4
 20#define MPNPU_PUB_SCRATCH4		0x30100A8
 21#define MPNPU_PUB_SCRATCH5		0x30100AC
 22#define MPNPU_PUB_SCRATCH6		0x30100B0
 23#define MPNPU_PUB_SCRATCH7		0x30100B4
 24#define MPNPU_PUB_SCRATCH9		0x30100BC
 25
 26#define MPNPU_SRAM_X2I_MAILBOX_0	0x30A0000
 27#define MPNPU_SRAM_X2I_MAILBOX_1	0x30A2000
 28#define MPNPU_SRAM_I2X_MAILBOX_15	0x30BF000
 29
 30#define MPNPU_APERTURE0_BASE		0x3000000
 31#define MPNPU_APERTURE1_BASE		0x3080000
 32#define MPNPU_APERTURE2_BASE		0x30C0000
 33
 34/* PCIe BAR Index for NPU1 */
 35#define NPU1_REG_BAR_INDEX  0
 36#define NPU1_MBOX_BAR_INDEX 4
 37#define NPU1_PSP_BAR_INDEX  0
 38#define NPU1_SMU_BAR_INDEX  0
 39#define NPU1_SRAM_BAR_INDEX 2
 40/* Associated BARs and Apertures */
 41#define NPU1_REG_BAR_BASE  MPNPU_APERTURE0_BASE
 42#define NPU1_MBOX_BAR_BASE MPNPU_APERTURE2_BASE
 43#define NPU1_PSP_BAR_BASE  MPNPU_APERTURE0_BASE
 44#define NPU1_SMU_BAR_BASE  MPNPU_APERTURE0_BASE
 45#define NPU1_SRAM_BAR_BASE MPNPU_APERTURE1_BASE
 46
 47const struct rt_config npu1_default_rt_cfg[] = {
 48	{ 2, 1, AIE2_RT_CFG_INIT }, /* PDI APP LOAD MODE */
 49	{ 4, 1, AIE2_RT_CFG_INIT }, /* Debug BO */
 50	{ 1, 1, AIE2_RT_CFG_CLK_GATING }, /* Clock gating on */
 51	{ 0 },
 52};
 53
 54const struct dpm_clk_freq npu1_dpm_clk_table[] = {
 55	{400, 800},
 56	{600, 1024},
 57	{600, 1024},
 58	{600, 1024},
 59	{600, 1024},
 60	{720, 1309},
 61	{720, 1309},
 62	{847, 1600},
 63	{ 0 }
 64};
 65
 66static const struct aie2_fw_feature_tbl npu1_fw_feature_table[] = {
 67	{ .feature = AIE2_NPU_COMMAND, .min_minor = 8 },
 68	{ 0 }
 69};
 70
 71static const struct amdxdna_dev_priv npu1_dev_priv = {
 72	.fw_path        = "amdnpu/1502_00/npu.sbin",
 73	.protocol_major = 0x5,
 74	.protocol_minor = 0x7,
 75	.rt_config	= npu1_default_rt_cfg,
 76	.dpm_clk_tbl	= npu1_dpm_clk_table,
 77	.fw_feature_tbl = npu1_fw_feature_table,
 78	.col_align	= COL_ALIGN_NONE,
 79	.mbox_dev_addr  = NPU1_MBOX_BAR_BASE,
 80	.mbox_size      = 0, /* Use BAR size */
 81	.sram_dev_addr  = NPU1_SRAM_BAR_BASE,
 82	.hwctx_limit    = 6,
 83	.sram_offs      = {
 84		DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU1_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
 85		DEFINE_BAR_OFFSET(FW_ALIVE_OFF,   NPU1_SRAM, MPNPU_SRAM_I2X_MAILBOX_15),
 86	},
 87	.psp_regs_off   = {
 88		DEFINE_BAR_OFFSET(PSP_CMD_REG,    NPU1_PSP, MPNPU_PUB_SCRATCH2),
 89		DEFINE_BAR_OFFSET(PSP_ARG0_REG,   NPU1_PSP, MPNPU_PUB_SCRATCH3),
 90		DEFINE_BAR_OFFSET(PSP_ARG1_REG,   NPU1_PSP, MPNPU_PUB_SCRATCH4),
 91		DEFINE_BAR_OFFSET(PSP_ARG2_REG,   NPU1_PSP, MPNPU_PUB_SCRATCH9),
 92		DEFINE_BAR_OFFSET(PSP_INTR_REG,   NPU1_PSP, MPNPU_PUB_SEC_INTR),
 93		DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU1_PSP, MPNPU_PUB_SCRATCH2),
 94		DEFINE_BAR_OFFSET(PSP_RESP_REG,   NPU1_PSP, MPNPU_PUB_SCRATCH3),
 95	},
 96	.smu_regs_off   = {
 97		DEFINE_BAR_OFFSET(SMU_CMD_REG,  NPU1_SMU, MPNPU_PUB_SCRATCH5),
 98		DEFINE_BAR_OFFSET(SMU_ARG_REG,  NPU1_SMU, MPNPU_PUB_SCRATCH7),
 99		DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU1_SMU, MPNPU_PUB_PWRMGMT_INTR),
100		DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU1_SMU, MPNPU_PUB_SCRATCH6),
101		DEFINE_BAR_OFFSET(SMU_OUT_REG,  NPU1_SMU, MPNPU_PUB_SCRATCH7),
102	},
103	.hw_ops		= {
104		.set_dpm = npu1_set_dpm,
105	},
106};
107
108const struct amdxdna_dev_info dev_npu1_info = {
109	.reg_bar           = NPU1_REG_BAR_INDEX,
110	.mbox_bar          = NPU1_MBOX_BAR_INDEX,
111	.sram_bar          = NPU1_SRAM_BAR_INDEX,
112	.psp_bar           = NPU1_PSP_BAR_INDEX,
113	.smu_bar           = NPU1_SMU_BAR_INDEX,
114	.first_col         = 1,
115	.dev_mem_buf_shift = 15, /* 32 KiB aligned */
116	.dev_mem_base      = AIE2_DEVM_BASE,
117	.dev_mem_size      = AIE2_DEVM_SIZE,
118	.vbnv              = "RyzenAI-npu1",
119	.device_type       = AMDXDNA_DEV_TYPE_KMQ,
120	.dev_priv          = &npu1_dev_priv,
121	.ops               = &aie2_ops,
122};