tie.h

  1/*
  2 * This header file describes this specific Xtensa processor's TIE extensions
  3 * that extend basic Xtensa core functionality.  It is customized to this
  4 * Xtensa processor configuration.
  5 *
  6 * This file is subject to the terms and conditions of the GNU General Public
  7 * License.  See the file "COPYING" in the main directory of this archive
  8 * for more details.
  9 *
 10 * Copyright (C) 1999-2007 Tensilica Inc.
 11 */
 12
 13#ifndef _XTENSA_CORE_TIE_H
 14#define _XTENSA_CORE_TIE_H
 15
 16#define XCHAL_CP_NUM			1	/* number of coprocessors */
 17#define XCHAL_CP_MAX			8	/* max CP ID + 1 (0 if none) */
 18#define XCHAL_CP_MASK			0x80	/* bitmask of all CPs by ID */
 19#define XCHAL_CP_PORT_MASK		0x80	/* bitmask of only port CPs */
 20
 21/*  Basic parameters of each coprocessor:  */
 22#define XCHAL_CP7_NAME			"XTIOP"
 23#define XCHAL_CP7_IDENT			XTIOP
 24#define XCHAL_CP7_SA_SIZE		0	/* size of state save area */
 25#define XCHAL_CP7_SA_ALIGN		1	/* min alignment of save area */
 26#define XCHAL_CP_ID_XTIOP		7	/* coprocessor ID (0..7) */
 27
 28/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
 29#define XCHAL_CP0_SA_SIZE		0
 30#define XCHAL_CP0_SA_ALIGN		1
 31#define XCHAL_CP1_SA_SIZE		0
 32#define XCHAL_CP1_SA_ALIGN		1
 33#define XCHAL_CP2_SA_SIZE		0
 34#define XCHAL_CP2_SA_ALIGN		1
 35#define XCHAL_CP3_SA_SIZE		0
 36#define XCHAL_CP3_SA_ALIGN		1
 37#define XCHAL_CP4_SA_SIZE		0
 38#define XCHAL_CP4_SA_ALIGN		1
 39#define XCHAL_CP5_SA_SIZE		0
 40#define XCHAL_CP5_SA_ALIGN		1
 41#define XCHAL_CP6_SA_SIZE		0
 42#define XCHAL_CP6_SA_ALIGN		1
 43
 44/*  Save area for non-coprocessor optional and custom (TIE) state:  */
 45#define XCHAL_NCP_SA_SIZE		32
 46#define XCHAL_NCP_SA_ALIGN		4
 47
 48/*  Total save area for optional and custom state (NCP + CPn):  */
 49#define XCHAL_TOTAL_SA_SIZE		32	/* with 16-byte align padding */
 50#define XCHAL_TOTAL_SA_ALIGN		4	/* actual minimum alignment */
 51
 52/*
 53 * Detailed contents of save areas.
 54 * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
 55 * before expanding the XCHAL_xxx_SA_LIST() macros.
 56 *
 57 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
 58 *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
 59 *
 60 *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
 61 *	ccused = set if used by compiler without special options or code
 62 *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
 63 *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
 64 *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
 65 *	name = lowercase reg name (no quotes)
 66 *	galign = group byte alignment (power of 2) (galign >= align)
 67 *	align = register byte alignment (power of 2)
 68 *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
 69 *	  (not including any pad bytes required to galign this or next reg)
 70 *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
 71 *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
 72 *	regnum = reg index in regfile, or special/TIE-user reg number
 73 *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
 74 *	gapsz = intervening bits, if bitsz bits not stored contiguously
 75 *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
 76 *	reset = register reset value (or 0 if undefined at reset)
 77 *	x = reserved for future use (0 until then)
 78 *
 79 *  To filter out certain registers, e.g. to expand only the non-global
 80 *  registers used by the compiler, you can do something like this:
 81 *
 82 *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
 83 *  #define SELCC0(p...)
 84 *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
 85 *  #define SELAK0(p...)		REG(p)
 86 *  #define SELAK1(p...)		REG(p)
 87 *  #define SELAK2(p...)
 88 *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
 89 *		...what you want to expand...
 90 */
 91
 92#define XCHAL_NCP_SA_NUM	8
 93#define XCHAL_NCP_SA_LIST(s)	\
 94 XCHAL_SA_REG(s,1,0,0,1,          acclo, 4, 4, 4,0x0210,  sr,16 , 32,0,0,0) \
 95 XCHAL_SA_REG(s,1,0,0,1,          acchi, 4, 4, 4,0x0211,  sr,17 ,  8,0,0,0) \
 96 XCHAL_SA_REG(s,0,0,0,1,             m0, 4, 4, 4,0x0220,  sr,32 , 32,0,0,0) \
 97 XCHAL_SA_REG(s,0,0,0,1,             m1, 4, 4, 4,0x0221,  sr,33 , 32,0,0,0) \
 98 XCHAL_SA_REG(s,0,0,0,1,             m2, 4, 4, 4,0x0222,  sr,34 , 32,0,0,0) \
 99 XCHAL_SA_REG(s,0,0,0,1,             m3, 4, 4, 4,0x0223,  sr,35 , 32,0,0,0) \
100 XCHAL_SA_REG(s,0,0,0,1,      scompare1, 4, 4, 4,0x020C,  sr,12 , 32,0,0,0) \
101 XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0)
102
103#define XCHAL_CP0_SA_NUM	0
104#define XCHAL_CP0_SA_LIST(s)	/* empty */
105
106#define XCHAL_CP1_SA_NUM	0
107#define XCHAL_CP1_SA_LIST(s)	/* empty */
108
109#define XCHAL_CP2_SA_NUM	0
110#define XCHAL_CP2_SA_LIST(s)	/* empty */
111
112#define XCHAL_CP3_SA_NUM	0
113#define XCHAL_CP3_SA_LIST(s)	/* empty */
114
115#define XCHAL_CP4_SA_NUM	0
116#define XCHAL_CP4_SA_LIST(s)	/* empty */
117
118#define XCHAL_CP5_SA_NUM	0
119#define XCHAL_CP5_SA_LIST(s)	/* empty */
120
121#define XCHAL_CP6_SA_NUM	0
122#define XCHAL_CP6_SA_LIST(s)	/* empty */
123
124#define XCHAL_CP7_SA_NUM	0
125#define XCHAL_CP7_SA_LIST(s)	/* empty */
126
127/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
128#define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
129
130#endif /*_XTENSA_CORE_TIE_H*/
131