regs.h

  1/*
  2 * Copyright (c) 2006 Tensilica, Inc.  All Rights Reserved.
  3 *
  4 * This program is free software; you can redistribute it and/or modify
  5 * it under the terms of version 2.1 of the GNU Lesser General Public
  6 * License as published by the Free Software Foundation.
  7 *
  8 * This program is distributed in the hope that it would be useful, but
  9 * WITHOUT ANY WARRANTY; without even the implied warranty of
 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 11 *
 12 * Further, this software is distributed without any warranty that it is
 13 * free of the rightful claim of any third person regarding infringement
 14 * or the like.  Any license provided herein, whether implied or
 15 * otherwise, applies only to this software file.  Patent licenses, if
 16 * any, provided herein do not apply to combinations of this program with
 17 * other software, or any other product whatsoever.
 18 *
 19 * You should have received a copy of the GNU Lesser General Public
 20 * License along with this program; if not, write the Free Software
 21 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
 22 * USA.
 23 */
 24
 25#ifndef _XTENSA_REGS_H
 26#define _XTENSA_REGS_H
 27
 28/*  Special registers.  */
 29
 30#define SREG_MR			32
 31#define SREG_IBREAKENABLE	96
 32#define SREG_IBREAKA		128
 33#define SREG_DBREAKA		144
 34#define SREG_DBREAKC		160
 35#define SREG_EPC		176
 36#define SREG_EPS		192
 37#define SREG_EXCSAVE		208
 38#define SREG_CCOMPARE		240
 39#define SREG_MISC		244
 40
 41/*  EXCCAUSE register fields  */
 42
 43#define EXCCAUSE_EXCCAUSE_SHIFT	0
 44#define EXCCAUSE_EXCCAUSE_MASK	0x3F
 45
 46#define EXCCAUSE_ILLEGAL_INSTRUCTION		0
 47#define EXCCAUSE_SYSTEM_CALL			1
 48#define EXCCAUSE_INSTRUCTION_FETCH_ERROR	2
 49#define EXCCAUSE_LOAD_STORE_ERROR		3
 50#define EXCCAUSE_LEVEL1_INTERRUPT		4
 51#define EXCCAUSE_ALLOCA				5
 52#define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO		6
 53#define EXCCAUSE_SPECULATION			7
 54#define EXCCAUSE_PRIVILEGED			8
 55#define EXCCAUSE_UNALIGNED			9
 56#define EXCCAUSE_INSTR_DATA_ERROR		12
 57#define EXCCAUSE_LOAD_STORE_DATA_ERROR		13
 58#define EXCCAUSE_INSTR_ADDR_ERROR		14
 59#define EXCCAUSE_LOAD_STORE_ADDR_ERROR		15
 60#define EXCCAUSE_ITLB_MISS			16
 61#define EXCCAUSE_ITLB_MULTIHIT			17
 62#define EXCCAUSE_ITLB_PRIVILEGE			18
 63#define EXCCAUSE_ITLB_SIZE_RESTRICTION		19
 64#define EXCCAUSE_FETCH_CACHE_ATTRIBUTE		20
 65#define EXCCAUSE_DTLB_MISS			24
 66#define EXCCAUSE_DTLB_MULTIHIT			25
 67#define EXCCAUSE_DTLB_PRIVILEGE			26
 68#define EXCCAUSE_DTLB_SIZE_RESTRICTION		27
 69#define EXCCAUSE_LOAD_CACHE_ATTRIBUTE		28
 70#define EXCCAUSE_STORE_CACHE_ATTRIBUTE		29
 71#define EXCCAUSE_COPROCESSOR0_DISABLED		32
 72#define EXCCAUSE_COPROCESSOR1_DISABLED		33
 73#define EXCCAUSE_COPROCESSOR2_DISABLED		34
 74#define EXCCAUSE_COPROCESSOR3_DISABLED		35
 75#define EXCCAUSE_COPROCESSOR4_DISABLED		36
 76#define EXCCAUSE_COPROCESSOR5_DISABLED		37
 77#define EXCCAUSE_COPROCESSOR6_DISABLED		38
 78#define EXCCAUSE_COPROCESSOR7_DISABLED		39
 79#define EXCCAUSE_N				64
 80
 81/*  PS register fields.  */
 82
 83#define PS_WOE_BIT		18
 84#define PS_WOE_MASK		0x00040000
 85#define PS_CALLINC_SHIFT	16
 86#define PS_CALLINC_MASK		0x00030000
 87#define PS_OWB_SHIFT		8
 88#define PS_OWB_WIDTH		4
 89#define PS_OWB_MASK		0x00000F00
 90#define PS_RING_SHIFT		6
 91#define PS_RING_MASK		0x000000C0
 92#define PS_UM_BIT		5
 93#define PS_EXCM_BIT		4
 94#define PS_INTLEVEL_SHIFT	0
 95#define PS_INTLEVEL_WIDTH	4
 96#define PS_INTLEVEL_MASK	0x0000000F
 97
 98/*  DBREAKCn register fields.  */
 99
100#define DBREAKC_MASK_BIT		0
101#define DBREAKC_MASK_MASK		0x0000003F
102#define DBREAKC_LOAD_BIT		30
103#define DBREAKC_LOAD_MASK		0x40000000
104#define DBREAKC_STOR_BIT		31
105#define DBREAKC_STOR_MASK		0x80000000
106
107/*  DEBUGCAUSE register fields.  */
108
109#define DEBUGCAUSE_DBNUM_MASK		0xf00
110#define DEBUGCAUSE_DBNUM_SHIFT		8	/* First bit of DBNUM field */
111#define DEBUGCAUSE_DEBUGINT_BIT		5	/* External debug interrupt */
112#define DEBUGCAUSE_BREAKN_BIT		4	/* BREAK.N instruction */
113#define DEBUGCAUSE_BREAK_BIT		3	/* BREAK instruction */
114#define DEBUGCAUSE_DBREAK_BIT		2	/* DBREAK match */
115#define DEBUGCAUSE_IBREAK_BIT		1	/* IBREAK match */
116#define DEBUGCAUSE_ICOUNT_BIT		0	/* ICOUNT would incr. to zero */
117
118#endif /* _XTENSA_SPECREG_H */