enlighten_pv.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Core of Xen paravirt_ops implementation.
   4 *
   5 * This file contains the xen_paravirt_ops structure itself, and the
   6 * implementations for:
   7 * - privileged instructions
   8 * - interrupt flags
   9 * - segment operations
  10 * - booting and setup
  11 *
  12 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  13 */
  14
  15#include <linux/cpu.h>
  16#include <linux/kernel.h>
  17#include <linux/init.h>
  18#include <linux/smp.h>
  19#include <linux/preempt.h>
  20#include <linux/hardirq.h>
  21#include <linux/percpu.h>
  22#include <linux/delay.h>
  23#include <linux/start_kernel.h>
  24#include <linux/sched.h>
  25#include <linux/kprobes.h>
  26#include <linux/kstrtox.h>
  27#include <linux/memblock.h>
  28#include <linux/export.h>
  29#include <linux/mm.h>
  30#include <linux/page-flags.h>
  31#include <linux/pci.h>
  32#include <linux/gfp.h>
  33#include <linux/edd.h>
  34#include <linux/reboot.h>
  35#include <linux/virtio_anchor.h>
  36#include <linux/stackprotector.h>
  37
  38#include <xen/xen.h>
  39#include <xen/events.h>
  40#include <xen/interface/xen.h>
  41#include <xen/interface/version.h>
  42#include <xen/interface/physdev.h>
  43#include <xen/interface/vcpu.h>
  44#include <xen/interface/memory.h>
  45#include <xen/interface/nmi.h>
  46#include <xen/interface/xen-mca.h>
  47#include <xen/features.h>
  48#include <xen/page.h>
  49#include <xen/hvc-console.h>
  50#include <xen/acpi.h>
  51
  52#include <asm/cpuid/api.h>
  53#include <asm/paravirt.h>
  54#include <asm/apic.h>
  55#include <asm/page.h>
  56#include <asm/xen/pci.h>
  57#include <asm/xen/hypercall.h>
  58#include <asm/xen/hypervisor.h>
  59#include <asm/xen/cpuid.h>
  60#include <asm/fixmap.h>
  61#include <asm/processor.h>
  62#include <asm/proto.h>
  63#include <asm/msr-index.h>
  64#include <asm/msr.h>
  65#include <asm/traps.h>
  66#include <asm/setup.h>
  67#include <asm/desc.h>
  68#include <asm/pgalloc.h>
  69#include <asm/tlbflush.h>
  70#include <asm/reboot.h>
  71#include <asm/hypervisor.h>
  72#include <asm/mach_traps.h>
  73#include <asm/mtrr.h>
  74#include <asm/mwait.h>
  75#include <asm/pci_x86.h>
  76#include <asm/cpu.h>
  77#include <asm/irq_stack.h>
  78#ifdef CONFIG_X86_IOPL_IOPERM
  79#include <asm/io_bitmap.h>
  80#endif
  81
  82#ifdef CONFIG_ACPI
  83#include <linux/acpi.h>
  84#include <asm/acpi.h>
  85#include <acpi/proc_cap_intel.h>
  86#include <acpi/processor.h>
  87#include <xen/interface/platform.h>
  88#endif
  89
  90#include "xen-ops.h"
  91
  92#include "../kernel/cpu/cpu.h" /* get_cpu_cap() */
  93
  94void *xen_initial_gdt;
  95
  96static int xen_cpu_up_prepare_pv(unsigned int cpu);
  97static int xen_cpu_dead_pv(unsigned int cpu);
  98
  99#ifndef CONFIG_PREEMPTION
 100/*
 101 * Some hypercalls issued by the toolstack can take many 10s of
 102 * seconds. Allow tasks running hypercalls via the privcmd driver to
 103 * be voluntarily preempted even if full kernel preemption is
 104 * disabled.
 105 *
 106 * Such preemptible hypercalls are bracketed by
 107 * xen_preemptible_hcall_begin() and xen_preemptible_hcall_end()
 108 * calls.
 109 */
 110DEFINE_PER_CPU(bool, xen_in_preemptible_hcall);
 111EXPORT_PER_CPU_SYMBOL_GPL(xen_in_preemptible_hcall);
 112
 113/*
 114 * In case of scheduling the flag must be cleared and restored after
 115 * returning from schedule as the task might move to a different CPU.
 116 */
 117static __always_inline bool get_and_clear_inhcall(void)
 118{
 119	bool inhcall = __this_cpu_read(xen_in_preemptible_hcall);
 120
 121	__this_cpu_write(xen_in_preemptible_hcall, false);
 122	return inhcall;
 123}
 124
 125static __always_inline void restore_inhcall(bool inhcall)
 126{
 127	__this_cpu_write(xen_in_preemptible_hcall, inhcall);
 128}
 129
 130#else
 131
 132static __always_inline bool get_and_clear_inhcall(void) { return false; }
 133static __always_inline void restore_inhcall(bool inhcall) { }
 134
 135#endif
 136
 137struct tls_descs {
 138	struct desc_struct desc[3];
 139};
 140
 141DEFINE_PER_CPU(enum xen_lazy_mode, xen_lazy_mode) = XEN_LAZY_NONE;
 142
 143enum xen_lazy_mode xen_get_lazy_mode(void)
 144{
 145	if (in_interrupt())
 146		return XEN_LAZY_NONE;
 147
 148	return this_cpu_read(xen_lazy_mode);
 149}
 150
 151/*
 152 * Updating the 3 TLS descriptors in the GDT on every task switch is
 153 * surprisingly expensive so we avoid updating them if they haven't
 154 * changed.  Since Xen writes different descriptors than the one
 155 * passed in the update_descriptor hypercall we keep shadow copies to
 156 * compare against.
 157 */
 158static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc);
 159
 160static __read_mostly bool xen_msr_safe = IS_ENABLED(CONFIG_XEN_PV_MSR_SAFE);
 161
 162static int __init parse_xen_msr_safe(char *str)
 163{
 164	if (str)
 165		return kstrtobool(str, &xen_msr_safe);
 166	return -EINVAL;
 167}
 168early_param("xen_msr_safe", parse_xen_msr_safe);
 169
 170/* Get MTRR settings from Xen and put them into mtrr_state. */
 171static void __init xen_set_mtrr_data(void)
 172{
 173#ifdef CONFIG_MTRR
 174	struct xen_platform_op op = {
 175		.cmd = XENPF_read_memtype,
 176		.interface_version = XENPF_INTERFACE_VERSION,
 177	};
 178	unsigned int reg;
 179	unsigned long mask;
 180	uint32_t eax, width;
 181	static struct mtrr_var_range var[MTRR_MAX_VAR_RANGES] __initdata;
 182
 183	/* Get physical address width (only 64-bit cpus supported). */
 184	width = 36;
 185	eax = cpuid_eax(0x80000000);
 186	if ((eax >> 16) == 0x8000 && eax >= 0x80000008) {
 187		eax = cpuid_eax(0x80000008);
 188		width = eax & 0xff;
 189	}
 190
 191	for (reg = 0; reg < MTRR_MAX_VAR_RANGES; reg++) {
 192		op.u.read_memtype.reg = reg;
 193		if (HYPERVISOR_platform_op(&op))
 194			break;
 195
 196		/*
 197		 * Only called in dom0, which has all RAM PFNs mapped at
 198		 * RAM MFNs, and all PCI space etc. is identity mapped.
 199		 * This means we can treat MFN == PFN regarding MTRR settings.
 200		 */
 201		var[reg].base_lo = op.u.read_memtype.type;
 202		var[reg].base_lo |= op.u.read_memtype.mfn << PAGE_SHIFT;
 203		var[reg].base_hi = op.u.read_memtype.mfn >> (32 - PAGE_SHIFT);
 204		mask = ~((op.u.read_memtype.nr_mfns << PAGE_SHIFT) - 1);
 205		mask &= (1UL << width) - 1;
 206		if (mask)
 207			mask |= MTRR_PHYSMASK_V;
 208		var[reg].mask_lo = mask;
 209		var[reg].mask_hi = mask >> 32;
 210	}
 211
 212	/* Only overwrite MTRR state if any MTRR could be got from Xen. */
 213	if (reg)
 214		guest_force_mtrr_state(var, reg, MTRR_TYPE_UNCACHABLE);
 215#endif
 216}
 217
 218static void __init xen_pv_init_platform(void)
 219{
 220	/* PV guests can't operate virtio devices without grants. */
 221	if (IS_ENABLED(CONFIG_XEN_VIRTIO))
 222		virtio_set_mem_acc_cb(xen_virtio_restricted_mem_acc);
 223
 224	populate_extra_pte(fix_to_virt(FIX_PARAVIRT_BOOTMAP));
 225
 226	set_fixmap(FIX_PARAVIRT_BOOTMAP, xen_start_info->shared_info);
 227	HYPERVISOR_shared_info = (void *)fix_to_virt(FIX_PARAVIRT_BOOTMAP);
 228
 229	/* xen clock uses per-cpu vcpu_info, need to init it for boot cpu */
 230	xen_vcpu_info_reset(0);
 231
 232	/* pvclock is in shared info area */
 233	xen_init_time_ops();
 234
 235	if (xen_initial_domain())
 236		xen_set_mtrr_data();
 237	else
 238		guest_force_mtrr_state(NULL, 0, MTRR_TYPE_WRBACK);
 239
 240	/* Adjust nr_cpu_ids before "enumeration" happens */
 241	xen_smp_count_cpus();
 242}
 243
 244static void __init xen_pv_guest_late_init(void)
 245{
 246#ifndef CONFIG_SMP
 247	/* Setup shared vcpu info for non-smp configurations */
 248	xen_setup_vcpu_info_placement();
 249#endif
 250}
 251
 252static __read_mostly unsigned int cpuid_leaf5_ecx_val;
 253static __read_mostly unsigned int cpuid_leaf5_edx_val;
 254
 255static void xen_cpuid(unsigned int *ax, unsigned int *bx,
 256		      unsigned int *cx, unsigned int *dx)
 257{
 258	unsigned int maskebx = ~0;
 259	unsigned int or_ebx = 0;
 260
 261	/*
 262	 * Mask out inconvenient features, to try and disable as many
 263	 * unsupported kernel subsystems as possible.
 264	 */
 265	switch (*ax) {
 266	case 0x1:
 267		/* Replace initial APIC ID in bits 24-31 of EBX. */
 268		/* See xen_pv_smp_config() for related topology preparations. */
 269		maskebx = 0x00ffffff;
 270		or_ebx = smp_processor_id() << 24;
 271		break;
 272
 273	case CPUID_LEAF_MWAIT:
 274		/* Synthesize the values.. */
 275		*ax = 0;
 276		*bx = 0;
 277		*cx = cpuid_leaf5_ecx_val;
 278		*dx = cpuid_leaf5_edx_val;
 279		return;
 280
 281	case 0xb:
 282		/* Suppress extended topology stuff */
 283		maskebx = 0;
 284		break;
 285	}
 286
 287	asm(XEN_EMULATE_PREFIX "cpuid"
 288		: "=a" (*ax),
 289		  "=b" (*bx),
 290		  "=c" (*cx),
 291		  "=d" (*dx)
 292		: "0" (*ax), "2" (*cx));
 293
 294	*bx &= maskebx;
 295	*bx |= or_ebx;
 296}
 297
 298static bool __init xen_check_mwait(void)
 299{
 300#ifdef CONFIG_ACPI
 301	struct xen_platform_op op = {
 302		.cmd			= XENPF_set_processor_pminfo,
 303		.u.set_pminfo.id	= -1,
 304		.u.set_pminfo.type	= XEN_PM_PDC,
 305	};
 306	uint32_t buf[3];
 307	unsigned int ax, bx, cx, dx;
 308	unsigned int mwait_mask;
 309
 310	/* We need to determine whether it is OK to expose the MWAIT
 311	 * capability to the kernel to harvest deeper than C3 states from ACPI
 312	 * _CST using the processor_harvest_xen.c module. For this to work, we
 313	 * need to gather the MWAIT_LEAF values (which the cstate.c code
 314	 * checks against). The hypervisor won't expose the MWAIT flag because
 315	 * it would break backwards compatibility; so we will find out directly
 316	 * from the hardware and hypercall.
 317	 */
 318	if (!xen_initial_domain())
 319		return false;
 320
 321	/*
 322	 * When running under platform earlier than Xen4.2, do not expose
 323	 * mwait, to avoid the risk of loading native acpi pad driver
 324	 */
 325	if (!xen_running_on_version_or_later(4, 2))
 326		return false;
 327
 328	ax = 1;
 329	cx = 0;
 330
 331	native_cpuid(&ax, &bx, &cx, &dx);
 332
 333	mwait_mask = (1 << (X86_FEATURE_EST % 32)) |
 334		     (1 << (X86_FEATURE_MWAIT % 32));
 335
 336	if ((cx & mwait_mask) != mwait_mask)
 337		return false;
 338
 339	/* We need to emulate the MWAIT_LEAF and for that we need both
 340	 * ecx and edx. The hypercall provides only partial information.
 341	 */
 342
 343	ax = CPUID_LEAF_MWAIT;
 344	bx = 0;
 345	cx = 0;
 346	dx = 0;
 347
 348	native_cpuid(&ax, &bx, &cx, &dx);
 349
 350	/* Ask the Hypervisor whether to clear ACPI_PROC_CAP_C_C2C3_FFH. If so,
 351	 * don't expose MWAIT_LEAF and let ACPI pick the IOPORT version of C3.
 352	 */
 353	buf[0] = ACPI_PDC_REVISION_ID;
 354	buf[1] = 1;
 355	buf[2] = (ACPI_PROC_CAP_C_CAPABILITY_SMP | ACPI_PROC_CAP_EST_CAPABILITY_SWSMP);
 356
 357	set_xen_guest_handle(op.u.set_pminfo.pdc, buf);
 358
 359	if ((HYPERVISOR_platform_op(&op) == 0) &&
 360	    (buf[2] & (ACPI_PROC_CAP_C_C1_FFH | ACPI_PROC_CAP_C_C2C3_FFH))) {
 361		cpuid_leaf5_ecx_val = cx;
 362		cpuid_leaf5_edx_val = dx;
 363	}
 364	return true;
 365#else
 366	return false;
 367#endif
 368}
 369
 370static bool __init xen_check_xsave(void)
 371{
 372	unsigned int cx, xsave_mask;
 373
 374	cx = cpuid_ecx(1);
 375
 376	xsave_mask = (1 << (X86_FEATURE_XSAVE % 32)) |
 377		     (1 << (X86_FEATURE_OSXSAVE % 32));
 378
 379	/* Xen will set CR4.OSXSAVE if supported and not disabled by force */
 380	return (cx & xsave_mask) == xsave_mask;
 381}
 382
 383static void __init xen_init_capabilities(void)
 384{
 385	setup_clear_cpu_cap(X86_FEATURE_DCA);
 386	setup_clear_cpu_cap(X86_FEATURE_APERFMPERF);
 387	setup_clear_cpu_cap(X86_FEATURE_MTRR);
 388	setup_clear_cpu_cap(X86_FEATURE_ACC);
 389	setup_clear_cpu_cap(X86_FEATURE_X2APIC);
 390	setup_clear_cpu_cap(X86_FEATURE_SME);
 391	setup_clear_cpu_cap(X86_FEATURE_LKGS);
 392
 393	/*
 394	 * Xen PV would need some work to support PCID: CR3 handling as well
 395	 * as xen_flush_tlb_others() would need updating.
 396	 */
 397	setup_clear_cpu_cap(X86_FEATURE_PCID);
 398
 399	if (!xen_initial_domain())
 400		setup_clear_cpu_cap(X86_FEATURE_ACPI);
 401
 402	if (xen_check_mwait())
 403		setup_force_cpu_cap(X86_FEATURE_MWAIT);
 404	else
 405		setup_clear_cpu_cap(X86_FEATURE_MWAIT);
 406
 407	if (!xen_check_xsave()) {
 408		setup_clear_cpu_cap(X86_FEATURE_XSAVE);
 409		setup_clear_cpu_cap(X86_FEATURE_OSXSAVE);
 410	}
 411}
 412
 413static noinstr void xen_set_debugreg(int reg, unsigned long val)
 414{
 415	HYPERVISOR_set_debugreg(reg, val);
 416}
 417
 418static noinstr unsigned long xen_get_debugreg(int reg)
 419{
 420	return HYPERVISOR_get_debugreg(reg);
 421}
 422
 423static void xen_start_context_switch(struct task_struct *prev)
 424{
 425	BUG_ON(preemptible());
 426
 427	if (this_cpu_read(xen_lazy_mode) == XEN_LAZY_MMU) {
 428		arch_leave_lazy_mmu_mode();
 429		set_ti_thread_flag(task_thread_info(prev), TIF_LAZY_MMU_UPDATES);
 430	}
 431	enter_lazy(XEN_LAZY_CPU);
 432}
 433
 434static void xen_end_context_switch(struct task_struct *next)
 435{
 436	BUG_ON(preemptible());
 437
 438	xen_mc_flush();
 439	leave_lazy(XEN_LAZY_CPU);
 440	if (test_and_clear_ti_thread_flag(task_thread_info(next), TIF_LAZY_MMU_UPDATES))
 441		arch_enter_lazy_mmu_mode();
 442}
 443
 444static unsigned long xen_store_tr(void)
 445{
 446	return 0;
 447}
 448
 449/*
 450 * Set the page permissions for a particular virtual address.  If the
 451 * address is a vmalloc mapping (or other non-linear mapping), then
 452 * find the linear mapping of the page and also set its protections to
 453 * match.
 454 */
 455static void set_aliased_prot(void *v, pgprot_t prot)
 456{
 457	int level;
 458	pte_t *ptep;
 459	pte_t pte;
 460	unsigned long pfn;
 461	unsigned char dummy;
 462	void *va;
 463
 464	ptep = lookup_address((unsigned long)v, &level);
 465	BUG_ON(ptep == NULL);
 466
 467	pfn = pte_pfn(*ptep);
 468	pte = pfn_pte(pfn, prot);
 469
 470	/*
 471	 * Careful: update_va_mapping() will fail if the virtual address
 472	 * we're poking isn't populated in the page tables.  We don't
 473	 * need to worry about the direct map (that's always in the page
 474	 * tables), but we need to be careful about vmap space.  In
 475	 * particular, the top level page table can lazily propagate
 476	 * entries between processes, so if we've switched mms since we
 477	 * vmapped the target in the first place, we might not have the
 478	 * top-level page table entry populated.
 479	 *
 480	 * We disable preemption because we want the same mm active when
 481	 * we probe the target and when we issue the hypercall.  We'll
 482	 * have the same nominal mm, but if we're a kernel thread, lazy
 483	 * mm dropping could change our pgd.
 484	 *
 485	 * Out of an abundance of caution, this uses __get_user() to fault
 486	 * in the target address just in case there's some obscure case
 487	 * in which the target address isn't readable.
 488	 */
 489
 490	preempt_disable();
 491
 492	copy_from_kernel_nofault(&dummy, v, 1);
 493
 494	if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0))
 495		BUG();
 496
 497	va = __va(PFN_PHYS(pfn));
 498
 499	if (va != v && HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0))
 500		BUG();
 501
 502	preempt_enable();
 503}
 504
 505static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries)
 506{
 507	const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE;
 508	int i;
 509
 510	/*
 511	 * We need to mark the all aliases of the LDT pages RO.  We
 512	 * don't need to call vm_flush_aliases(), though, since that's
 513	 * only responsible for flushing aliases out the TLBs, not the
 514	 * page tables, and Xen will flush the TLB for us if needed.
 515	 *
 516	 * To avoid confusing future readers: none of this is necessary
 517	 * to load the LDT.  The hypervisor only checks this when the
 518	 * LDT is faulted in due to subsequent descriptor access.
 519	 */
 520
 521	for (i = 0; i < entries; i += entries_per_page)
 522		set_aliased_prot(ldt + i, PAGE_KERNEL_RO);
 523}
 524
 525static void xen_free_ldt(struct desc_struct *ldt, unsigned entries)
 526{
 527	const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE;
 528	int i;
 529
 530	for (i = 0; i < entries; i += entries_per_page)
 531		set_aliased_prot(ldt + i, PAGE_KERNEL);
 532}
 533
 534static void xen_set_ldt(const void *addr, unsigned entries)
 535{
 536	struct mmuext_op *op;
 537	struct multicall_space mcs = xen_mc_entry(sizeof(*op));
 538
 539	trace_xen_cpu_set_ldt(addr, entries);
 540
 541	op = mcs.args;
 542	op->cmd = MMUEXT_SET_LDT;
 543	op->arg1.linear_addr = (unsigned long)addr;
 544	op->arg2.nr_ents = entries;
 545
 546	MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF);
 547
 548	xen_mc_issue(XEN_LAZY_CPU);
 549}
 550
 551static void xen_load_gdt(const struct desc_ptr *dtr)
 552{
 553	unsigned long va = dtr->address;
 554	unsigned int size = dtr->size + 1;
 555	unsigned long pfn, mfn;
 556	int level;
 557	pte_t *ptep;
 558	void *virt;
 559
 560	/* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */
 561	BUG_ON(size > PAGE_SIZE);
 562	BUG_ON(va & ~PAGE_MASK);
 563
 564	/*
 565	 * The GDT is per-cpu and is in the percpu data area.
 566	 * That can be virtually mapped, so we need to do a
 567	 * page-walk to get the underlying MFN for the
 568	 * hypercall.  The page can also be in the kernel's
 569	 * linear range, so we need to RO that mapping too.
 570	 */
 571	ptep = lookup_address(va, &level);
 572	BUG_ON(ptep == NULL);
 573
 574	pfn = pte_pfn(*ptep);
 575	mfn = pfn_to_mfn(pfn);
 576	virt = __va(PFN_PHYS(pfn));
 577
 578	make_lowmem_page_readonly((void *)va);
 579	make_lowmem_page_readonly(virt);
 580
 581	if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct)))
 582		BUG();
 583}
 584
 585/*
 586 * load_gdt for early boot, when the gdt is only mapped once
 587 */
 588static void __init xen_load_gdt_boot(const struct desc_ptr *dtr)
 589{
 590	unsigned long va = dtr->address;
 591	unsigned int size = dtr->size + 1;
 592	unsigned long pfn, mfn;
 593	pte_t pte;
 594
 595	/* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */
 596	BUG_ON(size > PAGE_SIZE);
 597	BUG_ON(va & ~PAGE_MASK);
 598
 599	pfn = virt_to_pfn((void *)va);
 600	mfn = pfn_to_mfn(pfn);
 601
 602	pte = pfn_pte(pfn, PAGE_KERNEL_RO);
 603
 604	if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0))
 605		BUG();
 606
 607	if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct)))
 608		BUG();
 609}
 610
 611static inline bool desc_equal(const struct desc_struct *d1,
 612			      const struct desc_struct *d2)
 613{
 614	return !memcmp(d1, d2, sizeof(*d1));
 615}
 616
 617static void load_TLS_descriptor(struct thread_struct *t,
 618				unsigned int cpu, unsigned int i)
 619{
 620	struct desc_struct *shadow = &per_cpu(shadow_tls_desc, cpu).desc[i];
 621	struct desc_struct *gdt;
 622	xmaddr_t maddr;
 623	struct multicall_space mc;
 624
 625	if (desc_equal(shadow, &t->tls_array[i]))
 626		return;
 627
 628	*shadow = t->tls_array[i];
 629
 630	gdt = get_cpu_gdt_rw(cpu);
 631	maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]);
 632	mc = __xen_mc_entry(0);
 633
 634	MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]);
 635}
 636
 637static void xen_load_tls(struct thread_struct *t, unsigned int cpu)
 638{
 639	/*
 640	 * In lazy mode we need to zero %fs, otherwise we may get an
 641	 * exception between the new %fs descriptor being loaded and
 642	 * %fs being effectively cleared at __switch_to().
 643	 */
 644	if (xen_get_lazy_mode() == XEN_LAZY_CPU)
 645		loadsegment(fs, 0);
 646
 647	xen_mc_batch();
 648
 649	load_TLS_descriptor(t, cpu, 0);
 650	load_TLS_descriptor(t, cpu, 1);
 651	load_TLS_descriptor(t, cpu, 2);
 652
 653	xen_mc_issue(XEN_LAZY_CPU);
 654}
 655
 656static void xen_load_gs_index(unsigned int idx)
 657{
 658	if (HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, idx))
 659		BUG();
 660}
 661
 662static void xen_write_ldt_entry(struct desc_struct *dt, int entrynum,
 663				const void *ptr)
 664{
 665	xmaddr_t mach_lp = arbitrary_virt_to_machine(&dt[entrynum]);
 666	u64 entry = *(u64 *)ptr;
 667
 668	trace_xen_cpu_write_ldt_entry(dt, entrynum, entry);
 669
 670	preempt_disable();
 671
 672	xen_mc_flush();
 673	if (HYPERVISOR_update_descriptor(mach_lp.maddr, entry))
 674		BUG();
 675
 676	preempt_enable();
 677}
 678
 679void noist_exc_debug(struct pt_regs *regs);
 680
 681DEFINE_IDTENTRY_RAW(xenpv_exc_nmi)
 682{
 683	/* On Xen PV, NMI doesn't use IST.  The C part is the same as native. */
 684	exc_nmi(regs);
 685}
 686
 687DEFINE_IDTENTRY_RAW_ERRORCODE(xenpv_exc_double_fault)
 688{
 689	/* On Xen PV, DF doesn't use IST.  The C part is the same as native. */
 690	exc_double_fault(regs, error_code);
 691}
 692
 693DEFINE_IDTENTRY_RAW(xenpv_exc_debug)
 694{
 695	/*
 696	 * There's no IST on Xen PV, but we still need to dispatch
 697	 * to the correct handler.
 698	 */
 699	if (user_mode(regs))
 700		noist_exc_debug(regs);
 701	else
 702		exc_debug(regs);
 703}
 704
 705DEFINE_IDTENTRY_RAW(exc_xen_unknown_trap)
 706{
 707	/* This should never happen and there is no way to handle it. */
 708	instrumentation_begin();
 709	pr_err("Unknown trap in Xen PV mode.");
 710	BUG();
 711	instrumentation_end();
 712}
 713
 714#ifdef CONFIG_X86_MCE
 715DEFINE_IDTENTRY_RAW(xenpv_exc_machine_check)
 716{
 717	/*
 718	 * There's no IST on Xen PV, but we still need to dispatch
 719	 * to the correct handler.
 720	 */
 721	if (user_mode(regs))
 722		noist_exc_machine_check(regs);
 723	else
 724		exc_machine_check(regs);
 725}
 726#endif
 727
 728static void __xen_pv_evtchn_do_upcall(struct pt_regs *regs)
 729{
 730	struct pt_regs *old_regs = set_irq_regs(regs);
 731
 732	inc_irq_stat(irq_hv_callback_count);
 733
 734	xen_evtchn_do_upcall();
 735
 736	set_irq_regs(old_regs);
 737}
 738
 739__visible noinstr void xen_pv_evtchn_do_upcall(struct pt_regs *regs)
 740{
 741	irqentry_state_t state = irqentry_enter(regs);
 742	bool inhcall;
 743
 744	instrumentation_begin();
 745	run_sysvec_on_irqstack_cond(__xen_pv_evtchn_do_upcall, regs);
 746
 747	inhcall = get_and_clear_inhcall();
 748	if (inhcall && !WARN_ON_ONCE(state.exit_rcu)) {
 749		irqentry_exit_cond_resched();
 750		instrumentation_end();
 751		restore_inhcall(inhcall);
 752	} else {
 753		instrumentation_end();
 754		irqentry_exit(regs, state);
 755	}
 756}
 757
 758struct trap_array_entry {
 759	void (*orig)(void);
 760	void (*xen)(void);
 761	bool ist_okay;
 762};
 763
 764#define TRAP_ENTRY(func, ist_ok) {			\
 765	.orig		= asm_##func,			\
 766	.xen		= xen_asm_##func,		\
 767	.ist_okay	= ist_ok }
 768
 769#define TRAP_ENTRY_REDIR(func, ist_ok) {		\
 770	.orig		= asm_##func,			\
 771	.xen		= xen_asm_xenpv_##func,		\
 772	.ist_okay	= ist_ok }
 773
 774static struct trap_array_entry trap_array[] = {
 775	TRAP_ENTRY_REDIR(exc_debug,			true  ),
 776	TRAP_ENTRY_REDIR(exc_double_fault,		true  ),
 777#ifdef CONFIG_X86_MCE
 778	TRAP_ENTRY_REDIR(exc_machine_check,		true  ),
 779#endif
 780	TRAP_ENTRY_REDIR(exc_nmi,			true  ),
 781	TRAP_ENTRY(exc_int3,				false ),
 782	TRAP_ENTRY(exc_overflow,			false ),
 783#ifdef CONFIG_IA32_EMULATION
 784	TRAP_ENTRY(int80_emulation,			false ),
 785#endif
 786	TRAP_ENTRY(exc_page_fault,			false ),
 787	TRAP_ENTRY(exc_divide_error,			false ),
 788	TRAP_ENTRY(exc_bounds,				false ),
 789	TRAP_ENTRY(exc_invalid_op,			false ),
 790	TRAP_ENTRY(exc_device_not_available,		false ),
 791	TRAP_ENTRY(exc_coproc_segment_overrun,		false ),
 792	TRAP_ENTRY(exc_invalid_tss,			false ),
 793	TRAP_ENTRY(exc_segment_not_present,		false ),
 794	TRAP_ENTRY(exc_stack_segment,			false ),
 795	TRAP_ENTRY(exc_general_protection,		false ),
 796	TRAP_ENTRY(exc_spurious_interrupt_bug,		false ),
 797	TRAP_ENTRY(exc_coprocessor_error,		false ),
 798	TRAP_ENTRY(exc_alignment_check,			false ),
 799	TRAP_ENTRY(exc_simd_coprocessor_error,		false ),
 800#ifdef CONFIG_X86_CET
 801	TRAP_ENTRY(exc_control_protection,		false ),
 802#endif
 803};
 804
 805static bool __ref get_trap_addr(void **addr, unsigned int ist)
 806{
 807	unsigned int nr;
 808	bool ist_okay = false;
 809	bool found = false;
 810
 811	/*
 812	 * Replace trap handler addresses by Xen specific ones.
 813	 * Check for known traps using IST and whitelist them.
 814	 * The debugger ones are the only ones we care about.
 815	 * Xen will handle faults like double_fault, so we should never see
 816	 * them.  Warn if there's an unexpected IST-using fault handler.
 817	 */
 818	for (nr = 0; nr < ARRAY_SIZE(trap_array); nr++) {
 819		struct trap_array_entry *entry = trap_array + nr;
 820
 821		if (*addr == entry->orig) {
 822			*addr = entry->xen;
 823			ist_okay = entry->ist_okay;
 824			found = true;
 825			break;
 826		}
 827	}
 828
 829	if (nr == ARRAY_SIZE(trap_array) &&
 830	    *addr >= (void *)early_idt_handler_array[0] &&
 831	    *addr < (void *)early_idt_handler_array[NUM_EXCEPTION_VECTORS]) {
 832		nr = (*addr - (void *)early_idt_handler_array[0]) /
 833		     EARLY_IDT_HANDLER_SIZE;
 834		*addr = (void *)xen_early_idt_handler_array[nr];
 835		found = true;
 836	}
 837
 838	if (!found)
 839		*addr = (void *)xen_asm_exc_xen_unknown_trap;
 840
 841	if (WARN_ON(found && ist != 0 && !ist_okay))
 842		return false;
 843
 844	return true;
 845}
 846
 847static int cvt_gate_to_trap(int vector, const gate_desc *val,
 848			    struct trap_info *info)
 849{
 850	unsigned long addr;
 851
 852	if (val->bits.type != GATE_TRAP && val->bits.type != GATE_INTERRUPT)
 853		return 0;
 854
 855	info->vector = vector;
 856
 857	addr = gate_offset(val);
 858	if (!get_trap_addr((void **)&addr, val->bits.ist))
 859		return 0;
 860	info->address = addr;
 861
 862	info->cs = gate_segment(val);
 863	info->flags = val->bits.dpl;
 864	/* interrupt gates clear IF */
 865	if (val->bits.type == GATE_INTERRUPT)
 866		info->flags |= 1 << 2;
 867
 868	return 1;
 869}
 870
 871/* Locations of each CPU's IDT */
 872static DEFINE_PER_CPU(struct desc_ptr, idt_desc);
 873
 874/* Set an IDT entry.  If the entry is part of the current IDT, then
 875   also update Xen. */
 876static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g)
 877{
 878	unsigned long p = (unsigned long)&dt[entrynum];
 879	unsigned long start, end;
 880
 881	trace_xen_cpu_write_idt_entry(dt, entrynum, g);
 882
 883	preempt_disable();
 884
 885	start = __this_cpu_read(idt_desc.address);
 886	end = start + __this_cpu_read(idt_desc.size) + 1;
 887
 888	xen_mc_flush();
 889
 890	native_write_idt_entry(dt, entrynum, g);
 891
 892	if (p >= start && (p + 8) <= end) {
 893		struct trap_info info[2];
 894
 895		info[1].address = 0;
 896
 897		if (cvt_gate_to_trap(entrynum, g, &info[0]))
 898			if (HYPERVISOR_set_trap_table(info))
 899				BUG();
 900	}
 901
 902	preempt_enable();
 903}
 904
 905static unsigned xen_convert_trap_info(const struct desc_ptr *desc,
 906				      struct trap_info *traps, bool full)
 907{
 908	unsigned in, out, count;
 909
 910	count = (desc->size+1) / sizeof(gate_desc);
 911	BUG_ON(count > 256);
 912
 913	for (in = out = 0; in < count; in++) {
 914		gate_desc *entry = (gate_desc *)(desc->address) + in;
 915
 916		if (cvt_gate_to_trap(in, entry, &traps[out]) || full)
 917			out++;
 918	}
 919
 920	return out;
 921}
 922
 923void xen_copy_trap_info(struct trap_info *traps)
 924{
 925	const struct desc_ptr *desc = this_cpu_ptr(&idt_desc);
 926
 927	xen_convert_trap_info(desc, traps, true);
 928}
 929
 930/* Load a new IDT into Xen.  In principle this can be per-CPU, so we
 931   hold a spinlock to protect the static traps[] array (static because
 932   it avoids allocation, and saves stack space). */
 933static void xen_load_idt(const struct desc_ptr *desc)
 934{
 935	static DEFINE_SPINLOCK(lock);
 936	static struct trap_info traps[257];
 937	static const struct trap_info zero = { };
 938	unsigned out;
 939
 940	trace_xen_cpu_load_idt(desc);
 941
 942	spin_lock(&lock);
 943
 944	memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc));
 945
 946	out = xen_convert_trap_info(desc, traps, false);
 947	traps[out] = zero;
 948
 949	xen_mc_flush();
 950	if (HYPERVISOR_set_trap_table(traps))
 951		BUG();
 952
 953	spin_unlock(&lock);
 954}
 955
 956/* Write a GDT descriptor entry.  Ignore LDT descriptors, since
 957   they're handled differently. */
 958static void xen_write_gdt_entry(struct desc_struct *dt, int entry,
 959				const void *desc, int type)
 960{
 961	trace_xen_cpu_write_gdt_entry(dt, entry, desc, type);
 962
 963	preempt_disable();
 964
 965	switch (type) {
 966	case DESC_LDT:
 967	case DESC_TSS:
 968		/* ignore */
 969		break;
 970
 971	default: {
 972		xmaddr_t maddr = arbitrary_virt_to_machine(&dt[entry]);
 973
 974		xen_mc_flush();
 975		if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc))
 976			BUG();
 977	}
 978
 979	}
 980
 981	preempt_enable();
 982}
 983
 984/*
 985 * Version of write_gdt_entry for use at early boot-time needed to
 986 * update an entry as simply as possible.
 987 */
 988static void __init xen_write_gdt_entry_boot(struct desc_struct *dt, int entry,
 989					    const void *desc, int type)
 990{
 991	trace_xen_cpu_write_gdt_entry(dt, entry, desc, type);
 992
 993	switch (type) {
 994	case DESC_LDT:
 995	case DESC_TSS:
 996		/* ignore */
 997		break;
 998
 999	default: {
1000		xmaddr_t maddr = virt_to_machine(&dt[entry]);
1001
1002		if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc))
1003			dt[entry] = *(struct desc_struct *)desc;
1004	}
1005
1006	}
1007}
1008
1009static void xen_load_sp0(unsigned long sp0)
1010{
1011	struct multicall_space mcs;
1012
1013	mcs = xen_mc_entry(0);
1014	MULTI_stack_switch(mcs.mc, __KERNEL_DS, sp0);
1015	xen_mc_issue(XEN_LAZY_CPU);
1016	this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
1017}
1018
1019#ifdef CONFIG_X86_IOPL_IOPERM
1020static void xen_invalidate_io_bitmap(void)
1021{
1022	struct physdev_set_iobitmap iobitmap = {
1023		.bitmap = NULL,
1024		.nr_ports = 0,
1025	};
1026
1027	native_tss_invalidate_io_bitmap();
1028	HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap);
1029}
1030
1031static void xen_update_io_bitmap(void)
1032{
1033	struct physdev_set_iobitmap iobitmap;
1034	struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
1035
1036	native_tss_update_io_bitmap();
1037
1038	iobitmap.bitmap = (uint8_t *)(&tss->x86_tss) +
1039			  tss->x86_tss.io_bitmap_base;
1040	if (tss->x86_tss.io_bitmap_base == IO_BITMAP_OFFSET_INVALID)
1041		iobitmap.nr_ports = 0;
1042	else
1043		iobitmap.nr_ports = IO_BITMAP_BITS;
1044
1045	HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap);
1046}
1047#endif
1048
1049static void xen_io_delay(void)
1050{
1051}
1052
1053static DEFINE_PER_CPU(unsigned long, xen_cr0_value);
1054
1055static unsigned long xen_read_cr0(void)
1056{
1057	unsigned long cr0 = this_cpu_read(xen_cr0_value);
1058
1059	if (unlikely(cr0 == 0)) {
1060		cr0 = native_read_cr0();
1061		this_cpu_write(xen_cr0_value, cr0);
1062	}
1063
1064	return cr0;
1065}
1066
1067static void xen_write_cr0(unsigned long cr0)
1068{
1069	struct multicall_space mcs;
1070
1071	this_cpu_write(xen_cr0_value, cr0);
1072
1073	/* Only pay attention to cr0.TS; everything else is
1074	   ignored. */
1075	mcs = xen_mc_entry(0);
1076
1077	MULTI_fpu_taskswitch(mcs.mc, (cr0 & X86_CR0_TS) != 0);
1078
1079	xen_mc_issue(XEN_LAZY_CPU);
1080}
1081
1082static void xen_write_cr4(unsigned long cr4)
1083{
1084	cr4 &= ~(X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PCE);
1085
1086	native_write_cr4(cr4);
1087}
1088
1089static u64 xen_do_read_msr(u32 msr, int *err)
1090{
1091	u64 val = 0;	/* Avoid uninitialized value for safe variant. */
1092
1093	if (pmu_msr_chk_emulated(msr, &val, true))
1094		return val;
1095
1096	if (err)
1097		*err = native_read_msr_safe(msr, &val);
1098	else
1099		val = native_read_msr(msr);
1100
1101	switch (msr) {
1102	case MSR_IA32_APICBASE:
1103		val &= ~X2APIC_ENABLE;
1104		if (smp_processor_id() == 0)
1105			val |= MSR_IA32_APICBASE_BSP;
1106		else
1107			val &= ~MSR_IA32_APICBASE_BSP;
1108		break;
1109	}
1110	return val;
1111}
1112
1113static void set_seg(u32 which, u64 base)
1114{
1115	if (HYPERVISOR_set_segment_base(which, base))
1116		WARN(1, "Xen set_segment_base(%u, %llx) failed\n", which, base);
1117}
1118
1119/*
1120 * Support write_msr_safe() and write_msr() semantics.
1121 * With err == NULL write_msr() semantics are selected.
1122 * Supplying an err pointer requires err to be pre-initialized with 0.
1123 */
1124static void xen_do_write_msr(u32 msr, u64 val, int *err)
1125{
1126	switch (msr) {
1127	case MSR_FS_BASE:
1128		set_seg(SEGBASE_FS, val);
1129		break;
1130
1131	case MSR_KERNEL_GS_BASE:
1132		set_seg(SEGBASE_GS_USER, val);
1133		break;
1134
1135	case MSR_GS_BASE:
1136		set_seg(SEGBASE_GS_KERNEL, val);
1137		break;
1138
1139	case MSR_STAR:
1140	case MSR_CSTAR:
1141	case MSR_LSTAR:
1142	case MSR_SYSCALL_MASK:
1143	case MSR_IA32_SYSENTER_CS:
1144	case MSR_IA32_SYSENTER_ESP:
1145	case MSR_IA32_SYSENTER_EIP:
1146		/* Fast syscall setup is all done in hypercalls, so
1147		   these are all ignored.  Stub them out here to stop
1148		   Xen console noise. */
1149		break;
1150
1151	default:
1152		if (pmu_msr_chk_emulated(msr, &val, false))
1153			return;
1154
1155		if (err)
1156			*err = native_write_msr_safe(msr, val);
1157		else
1158			native_write_msr(msr, val);
1159	}
1160}
1161
1162static int xen_read_msr_safe(u32 msr, u64 *val)
1163{
1164	int err = 0;
1165
1166	*val = xen_do_read_msr(msr, &err);
1167	return err;
1168}
1169
1170static int xen_write_msr_safe(u32 msr, u64 val)
1171{
1172	int err = 0;
1173
1174	xen_do_write_msr(msr, val, &err);
1175
1176	return err;
1177}
1178
1179static u64 xen_read_msr(u32 msr)
1180{
1181	int err = 0;
1182
1183	return xen_do_read_msr(msr, xen_msr_safe ? &err : NULL);
1184}
1185
1186static void xen_write_msr(u32 msr, u64 val)
1187{
1188	int err;
1189
1190	xen_do_write_msr(msr, val, xen_msr_safe ? &err : NULL);
1191}
1192
1193/* This is called once we have the cpu_possible_mask */
1194void __init xen_setup_vcpu_info_placement(void)
1195{
1196	int cpu;
1197
1198	for_each_possible_cpu(cpu) {
1199		/* Set up direct vCPU id mapping for PV guests. */
1200		per_cpu(xen_vcpu_id, cpu) = cpu;
1201		xen_vcpu_setup(cpu);
1202	}
1203
1204	pv_ops.irq.save_fl = __PV_IS_CALLEE_SAVE(xen_save_fl_direct);
1205	pv_ops.irq.irq_disable = __PV_IS_CALLEE_SAVE(xen_irq_disable_direct);
1206	pv_ops.irq.irq_enable = __PV_IS_CALLEE_SAVE(xen_irq_enable_direct);
1207	pv_ops.mmu.read_cr2 = __PV_IS_CALLEE_SAVE(xen_read_cr2_direct);
1208}
1209
1210static const struct pv_info xen_info __initconst = {
1211	.extra_user_64bit_cs = FLAT_USER_CS64,
1212	.name = "Xen",
1213};
1214
1215static const typeof(pv_ops) xen_cpu_ops __initconst = {
1216	.cpu = {
1217		.cpuid = xen_cpuid,
1218
1219		.set_debugreg = xen_set_debugreg,
1220		.get_debugreg = xen_get_debugreg,
1221
1222		.read_cr0 = xen_read_cr0,
1223		.write_cr0 = xen_write_cr0,
1224
1225		.write_cr4 = xen_write_cr4,
1226
1227		.read_msr = xen_read_msr,
1228		.write_msr = xen_write_msr,
1229
1230		.read_msr_safe = xen_read_msr_safe,
1231		.write_msr_safe = xen_write_msr_safe,
1232
1233		.read_pmc = xen_read_pmc,
1234
1235		.load_tr_desc = paravirt_nop,
1236		.set_ldt = xen_set_ldt,
1237		.load_gdt = xen_load_gdt,
1238		.load_idt = xen_load_idt,
1239		.load_tls = xen_load_tls,
1240		.load_gs_index = xen_load_gs_index,
1241
1242		.alloc_ldt = xen_alloc_ldt,
1243		.free_ldt = xen_free_ldt,
1244
1245		.store_tr = xen_store_tr,
1246
1247		.write_ldt_entry = xen_write_ldt_entry,
1248		.write_gdt_entry = xen_write_gdt_entry,
1249		.write_idt_entry = xen_write_idt_entry,
1250		.load_sp0 = xen_load_sp0,
1251
1252#ifdef CONFIG_X86_IOPL_IOPERM
1253		.invalidate_io_bitmap = xen_invalidate_io_bitmap,
1254		.update_io_bitmap = xen_update_io_bitmap,
1255#endif
1256		.io_delay = xen_io_delay,
1257
1258		.start_context_switch = xen_start_context_switch,
1259		.end_context_switch = xen_end_context_switch,
1260	},
1261};
1262
1263static void xen_restart(char *msg)
1264{
1265	xen_reboot(SHUTDOWN_reboot);
1266}
1267
1268static void xen_machine_halt(void)
1269{
1270	xen_reboot(SHUTDOWN_poweroff);
1271}
1272
1273static void xen_machine_power_off(void)
1274{
1275	do_kernel_power_off();
1276	xen_reboot(SHUTDOWN_poweroff);
1277}
1278
1279static void xen_crash_shutdown(struct pt_regs *regs)
1280{
1281	xen_reboot(SHUTDOWN_crash);
1282}
1283
1284static const struct machine_ops xen_machine_ops __initconst = {
1285	.restart = xen_restart,
1286	.halt = xen_machine_halt,
1287	.power_off = xen_machine_power_off,
1288	.shutdown = xen_machine_halt,
1289	.crash_shutdown = xen_crash_shutdown,
1290	.emergency_restart = xen_emergency_restart,
1291};
1292
1293static unsigned char xen_get_nmi_reason(void)
1294{
1295	unsigned char reason = 0;
1296
1297	/* Construct a value which looks like it came from port 0x61. */
1298	if (test_bit(_XEN_NMIREASON_io_error,
1299		     &HYPERVISOR_shared_info->arch.nmi_reason))
1300		reason |= NMI_REASON_IOCHK;
1301	if (test_bit(_XEN_NMIREASON_pci_serr,
1302		     &HYPERVISOR_shared_info->arch.nmi_reason))
1303		reason |= NMI_REASON_SERR;
1304
1305	return reason;
1306}
1307
1308static void __init xen_boot_params_init_edd(void)
1309{
1310#if IS_ENABLED(CONFIG_EDD)
1311	struct xen_platform_op op;
1312	struct edd_info *edd_info;
1313	u32 *mbr_signature;
1314	unsigned nr;
1315	int ret;
1316
1317	edd_info = boot_params.eddbuf;
1318	mbr_signature = boot_params.edd_mbr_sig_buffer;
1319
1320	op.cmd = XENPF_firmware_info;
1321
1322	op.u.firmware_info.type = XEN_FW_DISK_INFO;
1323	for (nr = 0; nr < EDDMAXNR; nr++) {
1324		struct edd_info *info = edd_info + nr;
1325
1326		op.u.firmware_info.index = nr;
1327		info->params.length = sizeof(info->params);
1328		set_xen_guest_handle(op.u.firmware_info.u.disk_info.edd_params,
1329				     &info->params);
1330		ret = HYPERVISOR_platform_op(&op);
1331		if (ret)
1332			break;
1333
1334#define C(x) info->x = op.u.firmware_info.u.disk_info.x
1335		C(device);
1336		C(version);
1337		C(interface_support);
1338		C(legacy_max_cylinder);
1339		C(legacy_max_head);
1340		C(legacy_sectors_per_track);
1341#undef C
1342	}
1343	boot_params.eddbuf_entries = nr;
1344
1345	op.u.firmware_info.type = XEN_FW_DISK_MBR_SIGNATURE;
1346	for (nr = 0; nr < EDD_MBR_SIG_MAX; nr++) {
1347		op.u.firmware_info.index = nr;
1348		ret = HYPERVISOR_platform_op(&op);
1349		if (ret)
1350			break;
1351		mbr_signature[nr] = op.u.firmware_info.u.disk_mbr_signature.mbr_signature;
1352	}
1353	boot_params.edd_mbr_sig_buf_entries = nr;
1354#endif
1355}
1356
1357/*
1358 * Set up the GDT and segment registers for -fstack-protector.  Until
1359 * we do this, we have to be careful not to call any stack-protected
1360 * function, which is most of the kernel.
1361 */
1362static void __init xen_setup_gdt(int cpu)
1363{
1364	pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry_boot;
1365	pv_ops.cpu.load_gdt = xen_load_gdt_boot;
1366
1367	switch_gdt_and_percpu_base(cpu);
1368
1369	pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry;
1370	pv_ops.cpu.load_gdt = xen_load_gdt;
1371}
1372
1373static void __init xen_dom0_set_legacy_features(void)
1374{
1375	x86_platform.legacy.rtc = 1;
1376}
1377
1378static void __init xen_domu_set_legacy_features(void)
1379{
1380	x86_platform.legacy.rtc = 0;
1381}
1382
1383extern void early_xen_iret_patch(void);
1384
1385/* First C function to be called on Xen boot */
1386asmlinkage __visible void __init xen_start_kernel(struct start_info *si)
1387{
1388	struct physdev_set_iopl set_iopl;
1389	unsigned long initrd_start = 0;
1390	int rc;
1391
1392	if (!si)
1393		return;
1394
1395	clear_bss();
1396
1397	xen_start_info = si;
1398
1399	__text_gen_insn(&early_xen_iret_patch,
1400			JMP32_INSN_OPCODE, &early_xen_iret_patch, &xen_iret,
1401			JMP32_INSN_SIZE);
1402
1403	xen_domain_type = XEN_PV_DOMAIN;
1404	setup_force_cpu_cap(X86_FEATURE_XENPV);
1405	xen_start_flags = xen_start_info->flags;
1406	/* Interrupts are guaranteed to be off initially. */
1407	early_boot_irqs_disabled = true;
1408	static_call_update_early(xen_hypercall, xen_hypercall_pv);
1409
1410	xen_setup_features();
1411
1412	/* Install Xen paravirt ops */
1413	pv_info = xen_info;
1414	pv_ops.cpu = xen_cpu_ops.cpu;
1415	xen_init_irq_ops();
1416
1417	/*
1418	 * Setup xen_vcpu early because it is needed for
1419	 * local_irq_disable(), irqs_disabled(), e.g. in printk().
1420	 *
1421	 * Don't do the full vcpu_info placement stuff until we have
1422	 * the cpu_possible_mask and a non-dummy shared_info.
1423	 */
1424	xen_vcpu_info_reset(0);
1425
1426	x86_platform.get_nmi_reason = xen_get_nmi_reason;
1427	x86_platform.realmode_reserve = x86_init_noop;
1428	x86_platform.realmode_init = x86_init_noop;
1429
1430	x86_init.resources.memory_setup = xen_memory_setup;
1431	x86_init.irqs.intr_mode_select	= x86_init_noop;
1432	x86_init.irqs.intr_mode_init	= x86_64_probe_apic;
1433	x86_init.oem.arch_setup = xen_arch_setup;
1434	x86_init.oem.banner = xen_banner;
1435	x86_init.hyper.init_platform = xen_pv_init_platform;
1436	x86_init.hyper.guest_late_init = xen_pv_guest_late_init;
1437
1438	/*
1439	 * Set up some pagetable state before starting to set any ptes.
1440	 */
1441
1442	xen_setup_machphys_mapping();
1443	xen_init_mmu_ops();
1444
1445	/* Prevent unwanted bits from being set in PTEs. */
1446	__supported_pte_mask &= ~_PAGE_GLOBAL;
1447	__default_kernel_pte_mask &= ~_PAGE_GLOBAL;
1448
1449	/* Get mfn list */
1450	xen_build_dynamic_phys_to_machine();
1451
1452	/* Work out if we support NX */
1453	get_cpu_cap(&boot_cpu_data);
1454	x86_configure_nx();
1455
1456	/*
1457	 * Set up kernel GDT and segment registers, mainly so that
1458	 * -fstack-protector code can be executed.
1459	 */
1460	xen_setup_gdt(0);
1461
1462	/* Determine virtual and physical address sizes */
1463	get_cpu_address_sizes(&boot_cpu_data);
1464
1465	/* Let's presume PV guests always boot on vCPU with id 0. */
1466	per_cpu(xen_vcpu_id, 0) = 0;
1467
1468	idt_setup_early_handler();
1469
1470	xen_init_capabilities();
1471
1472	/*
1473	 * set up the basic apic ops.
1474	 */
1475	xen_init_apic();
1476
1477	machine_ops = xen_machine_ops;
1478
1479	/*
1480	 * The only reliable way to retain the initial address of the
1481	 * percpu gdt_page is to remember it here, so we can go and
1482	 * mark it RW later, when the initial percpu area is freed.
1483	 */
1484	xen_initial_gdt = &per_cpu(gdt_page, 0);
1485
1486	xen_smp_init();
1487
1488#ifdef CONFIG_ACPI_NUMA
1489	/*
1490	 * The pages we from Xen are not related to machine pages, so
1491	 * any NUMA information the kernel tries to get from ACPI will
1492	 * be meaningless.  Prevent it from trying.
1493	 */
1494	disable_srat();
1495#endif
1496	WARN_ON(xen_cpuhp_setup(xen_cpu_up_prepare_pv, xen_cpu_dead_pv));
1497
1498	local_irq_disable();
1499
1500	xen_raw_console_write("mapping kernel into physical memory\n");
1501	xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base,
1502				   xen_start_info->nr_pages);
1503	xen_reserve_special_pages();
1504
1505	/*
1506	 * We used to do this in xen_arch_setup, but that is too late
1507	 * on AMD were early_cpu_init (run before ->arch_setup()) calls
1508	 * early_amd_init which pokes 0xcf8 port.
1509	 */
1510	set_iopl.iopl = 1;
1511	rc = HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl);
1512	if (rc != 0)
1513		xen_raw_printk("physdev_op failed %d\n", rc);
1514
1515
1516	if (xen_start_info->mod_start) {
1517	    if (xen_start_info->flags & SIF_MOD_START_PFN)
1518		initrd_start = PFN_PHYS(xen_start_info->mod_start);
1519	    else
1520		initrd_start = __pa(xen_start_info->mod_start);
1521	}
1522
1523	/* Poke various useful things into boot_params */
1524	boot_params.hdr.type_of_loader = (9 << 4) | 0;
1525	boot_params.hdr.ramdisk_image = initrd_start;
1526	boot_params.hdr.ramdisk_size = xen_start_info->mod_len;
1527	boot_params.hdr.cmd_line_ptr = __pa(xen_start_info->cmd_line);
1528	boot_params.hdr.hardware_subarch = X86_SUBARCH_XEN;
1529
1530	if (!xen_initial_domain()) {
1531		if (pci_xen)
1532			x86_init.pci.arch_init = pci_xen_init;
1533		x86_platform.set_legacy_features =
1534				xen_domu_set_legacy_features;
1535	} else {
1536		const struct dom0_vga_console_info *info =
1537			(void *)((char *)xen_start_info +
1538				 xen_start_info->console.dom0.info_off);
1539		struct xen_platform_op op = {
1540			.cmd = XENPF_firmware_info,
1541			.interface_version = XENPF_INTERFACE_VERSION,
1542			.u.firmware_info.type = XEN_FW_KBD_SHIFT_FLAGS,
1543		};
1544
1545		x86_platform.set_legacy_features =
1546				xen_dom0_set_legacy_features;
1547		xen_init_vga(info, xen_start_info->console.dom0.info_size,
1548			     &boot_params.screen_info);
1549		xen_start_info->console.domU.mfn = 0;
1550		xen_start_info->console.domU.evtchn = 0;
1551
1552		if (HYPERVISOR_platform_op(&op) == 0)
1553			boot_params.kbd_status = op.u.firmware_info.u.kbd_shift_flags;
1554
1555		/* Make sure ACS will be enabled */
1556		pci_request_acs();
1557
1558		xen_acpi_sleep_register();
1559
1560		xen_boot_params_init_edd();
1561
1562#ifdef CONFIG_ACPI
1563		/*
1564		 * Disable selecting "Firmware First mode" for correctable
1565		 * memory errors, as this is the duty of the hypervisor to
1566		 * decide.
1567		 */
1568		acpi_disable_cmcff = 1;
1569#endif
1570	}
1571
1572	xen_add_preferred_consoles();
1573
1574#ifdef CONFIG_PCI
1575	/* PCI BIOS service won't work from a PV guest. */
1576	pci_probe &= ~PCI_PROBE_BIOS;
1577#endif
1578	xen_raw_console_write("about to get started...\n");
1579
1580	/* We need this for printk timestamps */
1581	xen_setup_runstate_info(0);
1582
1583	xen_efi_init(&boot_params);
1584
1585	/* Start the world */
1586	cr4_init_shadow(); /* 32b kernel does this in i386_start_kernel() */
1587	x86_64_start_reservations((char *)__pa_symbol(&boot_params));
1588}
1589
1590static int xen_cpu_up_prepare_pv(unsigned int cpu)
1591{
1592	int rc;
1593
1594	if (per_cpu(xen_vcpu, cpu) == NULL)
1595		return -ENODEV;
1596
1597	xen_setup_timer(cpu);
1598
1599	rc = xen_smp_intr_init(cpu);
1600	if (rc) {
1601		WARN(1, "xen_smp_intr_init() for CPU %d failed: %d\n",
1602		     cpu, rc);
1603		return rc;
1604	}
1605
1606	rc = xen_smp_intr_init_pv(cpu);
1607	if (rc) {
1608		WARN(1, "xen_smp_intr_init_pv() for CPU %d failed: %d\n",
1609		     cpu, rc);
1610		return rc;
1611	}
1612
1613	return 0;
1614}
1615
1616static int xen_cpu_dead_pv(unsigned int cpu)
1617{
1618	xen_smp_intr_free(cpu);
1619	xen_smp_intr_free_pv(cpu);
1620
1621	xen_teardown_timer(cpu);
1622
1623	return 0;
1624}
1625
1626static uint32_t __init xen_platform_pv(void)
1627{
1628	if (xen_pv_domain())
1629		return xen_cpuid_base();
1630
1631	return 0;
1632}
1633
1634const __initconst struct hypervisor_x86 x86_hyper_xen_pv = {
1635	.name                   = "Xen PV",
1636	.detect                 = xen_platform_pv,
1637	.type			= X86_HYPER_XEN_PV,
1638	.runtime.pin_vcpu       = xen_pin_vcpu,
1639	.ignore_nopv		= true,
1640};