cpu.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Suspend support specific for i386/x86-64.
  4 *
  5 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
  6 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
  7 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
  8 */
  9
 10#include <linux/suspend.h>
 11#include <linux/export.h>
 12#include <linux/smp.h>
 13#include <linux/perf_event.h>
 14#include <linux/tboot.h>
 15#include <linux/dmi.h>
 16#include <linux/pgtable.h>
 17
 18#include <asm/proto.h>
 19#include <asm/mtrr.h>
 20#include <asm/page.h>
 21#include <asm/mce.h>
 22#include <asm/suspend.h>
 23#include <asm/fpu/api.h>
 24#include <asm/debugreg.h>
 25#include <asm/cpu.h>
 26#include <asm/cacheinfo.h>
 27#include <asm/mmu_context.h>
 28#include <asm/cpu_device_id.h>
 29#include <asm/microcode.h>
 30#include <asm/msr.h>
 31#include <asm/fred.h>
 32
 33#ifdef CONFIG_X86_32
 34__visible unsigned long saved_context_ebx;
 35__visible unsigned long saved_context_esp, saved_context_ebp;
 36__visible unsigned long saved_context_esi, saved_context_edi;
 37__visible unsigned long saved_context_eflags;
 38#endif
 39struct saved_context saved_context;
 40
 41static void msr_save_context(struct saved_context *ctxt)
 42{
 43	struct saved_msr *msr = ctxt->saved_msrs.array;
 44	struct saved_msr *end = msr + ctxt->saved_msrs.num;
 45
 46	while (msr < end) {
 47		if (msr->valid)
 48			rdmsrq(msr->info.msr_no, msr->info.reg.q);
 49		msr++;
 50	}
 51}
 52
 53static void msr_restore_context(struct saved_context *ctxt)
 54{
 55	struct saved_msr *msr = ctxt->saved_msrs.array;
 56	struct saved_msr *end = msr + ctxt->saved_msrs.num;
 57
 58	while (msr < end) {
 59		if (msr->valid)
 60			wrmsrq(msr->info.msr_no, msr->info.reg.q);
 61		msr++;
 62	}
 63}
 64
 65/**
 66 * __save_processor_state() - Save CPU registers before creating a
 67 *                             hibernation image and before restoring
 68 *                             the memory state from it
 69 * @ctxt: Structure to store the registers contents in.
 70 *
 71 * NOTE: If there is a CPU register the modification of which by the
 72 * boot kernel (ie. the kernel used for loading the hibernation image)
 73 * might affect the operations of the restored target kernel (ie. the one
 74 * saved in the hibernation image), then its contents must be saved by this
 75 * function.  In other words, if kernel A is hibernated and different
 76 * kernel B is used for loading the hibernation image into memory, the
 77 * kernel A's __save_processor_state() function must save all registers
 78 * needed by kernel A, so that it can operate correctly after the resume
 79 * regardless of what kernel B does in the meantime.
 80 */
 81static void __save_processor_state(struct saved_context *ctxt)
 82{
 83#ifdef CONFIG_X86_32
 84	mtrr_save_fixed_ranges(NULL);
 85#endif
 86	kernel_fpu_begin();
 87
 88	/*
 89	 * descriptor tables
 90	 */
 91	store_idt(&ctxt->idt);
 92
 93	/*
 94	 * We save it here, but restore it only in the hibernate case.
 95	 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
 96	 * mode in "secondary_startup_64". In 32-bit mode it is done via
 97	 * 'pmode_gdt' in wakeup_start.
 98	 */
 99	ctxt->gdt_desc.size = GDT_SIZE - 1;
100	ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_rw(smp_processor_id());
101
102	store_tr(ctxt->tr);
103
104	/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
105	/*
106	 * segment registers
107	 */
108	savesegment(gs, ctxt->gs);
109#ifdef CONFIG_X86_64
110	savesegment(fs, ctxt->fs);
111	savesegment(ds, ctxt->ds);
112	savesegment(es, ctxt->es);
113
114	rdmsrq(MSR_FS_BASE, ctxt->fs_base);
115	rdmsrq(MSR_GS_BASE, ctxt->kernelmode_gs_base);
116	rdmsrq(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
117	mtrr_save_fixed_ranges(NULL);
118
119	rdmsrq(MSR_EFER, ctxt->efer);
120#endif
121
122	/*
123	 * control registers
124	 */
125	ctxt->cr0 = read_cr0();
126	ctxt->cr2 = read_cr2();
127	ctxt->cr3 = __read_cr3();
128	ctxt->cr4 = __read_cr4();
129	ctxt->misc_enable_saved = !rdmsrq_safe(MSR_IA32_MISC_ENABLE,
130					       &ctxt->misc_enable);
131	msr_save_context(ctxt);
132}
133
134/* Needed by apm.c */
135void save_processor_state(void)
136{
137	__save_processor_state(&saved_context);
138	x86_platform.save_sched_clock_state();
139}
140#ifdef CONFIG_X86_32
141EXPORT_SYMBOL(save_processor_state);
142#endif
143
144static void do_fpu_end(void)
145{
146	/*
147	 * Restore FPU regs if necessary.
148	 */
149	kernel_fpu_end();
150}
151
152static void fix_processor_context(void)
153{
154	int cpu = smp_processor_id();
155#ifdef CONFIG_X86_64
156	struct desc_struct *desc = get_cpu_gdt_rw(cpu);
157	tss_desc tss;
158#endif
159
160	/*
161	 * We need to reload TR, which requires that we change the
162	 * GDT entry to indicate "available" first.
163	 *
164	 * XXX: This could probably all be replaced by a call to
165	 * force_reload_TR().
166	 */
167	set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
168
169#ifdef CONFIG_X86_64
170	memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
171	tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
172	write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
173
174	syscall_init();				/* This sets MSR_*STAR and related */
175#else
176	if (boot_cpu_has(X86_FEATURE_SEP))
177		enable_sep_cpu();
178#endif
179	load_TR_desc();				/* This does ltr */
180	load_mm_ldt(current->active_mm);	/* This does lldt */
181	initialize_tlbstate_and_flush();
182
183	fpu__resume_cpu();
184
185	/* The processor is back on the direct GDT, load back the fixmap */
186	load_fixmap_gdt(cpu);
187}
188
189/**
190 * __restore_processor_state() - Restore the contents of CPU registers saved
191 *                               by __save_processor_state()
192 * @ctxt: Structure to load the registers contents from.
193 *
194 * The asm code that gets us here will have restored a usable GDT, although
195 * it will be pointing to the wrong alias.
196 */
197static void notrace __restore_processor_state(struct saved_context *ctxt)
198{
199	struct cpuinfo_x86 *c;
200
201	if (ctxt->misc_enable_saved)
202		wrmsrq(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
203	/*
204	 * control registers
205	 */
206	/* cr4 was introduced in the Pentium CPU */
207#ifdef CONFIG_X86_32
208	if (ctxt->cr4)
209		__write_cr4(ctxt->cr4);
210#else
211/* CONFIG X86_64 */
212	wrmsrq(MSR_EFER, ctxt->efer);
213	__write_cr4(ctxt->cr4);
214#endif
215	write_cr3(ctxt->cr3);
216	write_cr2(ctxt->cr2);
217	write_cr0(ctxt->cr0);
218
219	/* Restore the IDT. */
220	load_idt(&ctxt->idt);
221
222	/*
223	 * Just in case the asm code got us here with the SS, DS, or ES
224	 * out of sync with the GDT, update them.
225	 */
226	loadsegment(ss, __KERNEL_DS);
227	loadsegment(ds, __USER_DS);
228	loadsegment(es, __USER_DS);
229
230	/*
231	 * Restore percpu access.  Percpu access can happen in exception
232	 * handlers or in complicated helpers like load_gs_index().
233	 */
234#ifdef CONFIG_X86_64
235	wrmsrq(MSR_GS_BASE, ctxt->kernelmode_gs_base);
236
237	/*
238	 * Reinitialize FRED to ensure the FRED MSRs contain the same values
239	 * as before hibernation.
240	 *
241	 * Note, the setup of FRED RSPs requires access to percpu data
242	 * structures.  Therefore, FRED reinitialization can only occur after
243	 * the percpu access pointer (i.e., MSR_GS_BASE) is restored.
244	 */
245	if (ctxt->cr4 & X86_CR4_FRED) {
246		cpu_init_fred_exceptions();
247		cpu_init_fred_rsps();
248	}
249#else
250	loadsegment(fs, __KERNEL_PERCPU);
251#endif
252
253	/* Restore the TSS, RO GDT, LDT, and usermode-relevant MSRs. */
254	fix_processor_context();
255
256	/*
257	 * Now that we have descriptor tables fully restored and working
258	 * exception handling, restore the usermode segments.
259	 */
260#ifdef CONFIG_X86_64
261	loadsegment(ds, ctxt->es);
262	loadsegment(es, ctxt->es);
263	loadsegment(fs, ctxt->fs);
264	load_gs_index(ctxt->gs);
265
266	/*
267	 * Restore FSBASE and GSBASE after restoring the selectors, since
268	 * restoring the selectors clobbers the bases.  Keep in mind
269	 * that MSR_KERNEL_GS_BASE is horribly misnamed.
270	 */
271	wrmsrq(MSR_FS_BASE, ctxt->fs_base);
272	wrmsrq(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
273#else
274	loadsegment(gs, ctxt->gs);
275#endif
276
277	do_fpu_end();
278	tsc_verify_tsc_adjust(true);
279	x86_platform.restore_sched_clock_state();
280	cache_bp_restore();
281	perf_restore_debug_store();
282
283	c = &cpu_data(smp_processor_id());
284	if (cpu_has(c, X86_FEATURE_MSR_IA32_FEAT_CTL))
285		init_ia32_feat_ctl(c);
286
287	microcode_bsp_resume();
288
289	/*
290	 * This needs to happen after the microcode has been updated upon resume
291	 * because some of the MSRs are "emulated" in microcode.
292	 */
293	msr_restore_context(ctxt);
294}
295
296/* Needed by apm.c */
297void notrace restore_processor_state(void)
298{
299	__restore_processor_state(&saved_context);
300}
301#ifdef CONFIG_X86_32
302EXPORT_SYMBOL(restore_processor_state);
303#endif
304
305#if defined(CONFIG_HIBERNATION) && defined(CONFIG_HOTPLUG_CPU)
306static void __noreturn resume_play_dead(void)
307{
308	play_dead_common();
309	tboot_shutdown(TB_SHUTDOWN_WFS);
310	hlt_play_dead();
311}
312
313int hibernate_resume_nonboot_cpu_disable(void)
314{
315	void (*play_dead)(void) = smp_ops.play_dead;
316	int ret;
317
318	/*
319	 * Ensure that MONITOR/MWAIT will not be used in the "play dead" loop
320	 * during hibernate image restoration, because it is likely that the
321	 * monitored address will be actually written to at that time and then
322	 * the "dead" CPU will attempt to execute instructions again, but the
323	 * address in its instruction pointer may not be possible to resolve
324	 * any more at that point (the page tables used by it previously may
325	 * have been overwritten by hibernate image data).
326	 *
327	 * First, make sure that we wake up all the potentially disabled SMT
328	 * threads which have been initially brought up and then put into
329	 * mwait/cpuidle sleep.
330	 * Those will be put to proper (not interfering with hibernation
331	 * resume) sleep afterwards, and the resumed kernel will decide itself
332	 * what to do with them.
333	 */
334	ret = cpuhp_smt_enable();
335	if (ret)
336		return ret;
337	smp_ops.play_dead = resume_play_dead;
338	ret = freeze_secondary_cpus(0);
339	smp_ops.play_dead = play_dead;
340	return ret;
341}
342#endif
343
344/*
345 * When bsp_check() is called in hibernate and suspend, cpu hotplug
346 * is disabled already. So it's unnecessary to handle race condition between
347 * cpumask query and cpu hotplug.
348 */
349static int bsp_check(void)
350{
351	if (cpumask_first(cpu_online_mask) != 0) {
352		pr_warn("CPU0 is offline.\n");
353		return -ENODEV;
354	}
355
356	return 0;
357}
358
359static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
360			   void *ptr)
361{
362	int ret = 0;
363
364	switch (action) {
365	case PM_SUSPEND_PREPARE:
366	case PM_HIBERNATION_PREPARE:
367		ret = bsp_check();
368		break;
369	default:
370		break;
371	}
372	return notifier_from_errno(ret);
373}
374
375static int __init bsp_pm_check_init(void)
376{
377	/*
378	 * Set this bsp_pm_callback as lower priority than
379	 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
380	 * earlier to disable cpu hotplug before bsp online check.
381	 */
382	pm_notifier(bsp_pm_callback, -INT_MAX);
383	return 0;
384}
385
386core_initcall(bsp_pm_check_init);
387
388static int msr_build_context(const u32 *msr_id, const int num)
389{
390	struct saved_msrs *saved_msrs = &saved_context.saved_msrs;
391	struct saved_msr *msr_array;
392	int total_num;
393	int i, j;
394
395	total_num = saved_msrs->num + num;
396
397	msr_array = kmalloc_array(total_num, sizeof(struct saved_msr), GFP_KERNEL);
398	if (!msr_array) {
399		pr_err("x86/pm: Can not allocate memory to save/restore MSRs during suspend.\n");
400		return -ENOMEM;
401	}
402
403	if (saved_msrs->array) {
404		/*
405		 * Multiple callbacks can invoke this function, so copy any
406		 * MSR save requests from previous invocations.
407		 */
408		memcpy(msr_array, saved_msrs->array,
409		       sizeof(struct saved_msr) * saved_msrs->num);
410
411		kfree(saved_msrs->array);
412	}
413
414	for (i = saved_msrs->num, j = 0; i < total_num; i++, j++) {
415		u64 dummy;
416
417		msr_array[i].info.msr_no	= msr_id[j];
418		msr_array[i].valid		= !rdmsrq_safe(msr_id[j], &dummy);
419		msr_array[i].info.reg.q		= 0;
420	}
421	saved_msrs->num   = total_num;
422	saved_msrs->array = msr_array;
423
424	return 0;
425}
426
427/*
428 * The following sections are a quirk framework for problematic BIOSen:
429 * Sometimes MSRs are modified by the BIOSen after suspended to
430 * RAM, this might cause unexpected behavior after wakeup.
431 * Thus we save/restore these specified MSRs across suspend/resume
432 * in order to work around it.
433 *
434 * For any further problematic BIOSen/platforms,
435 * please add your own function similar to msr_initialize_bdw.
436 */
437static int msr_initialize_bdw(const struct dmi_system_id *d)
438{
439	/* Add any extra MSR ids into this array. */
440	u32 bdw_msr_id[] = { MSR_IA32_THERM_CONTROL };
441
442	pr_info("x86/pm: %s detected, MSR saving is needed during suspending.\n", d->ident);
443	return msr_build_context(bdw_msr_id, ARRAY_SIZE(bdw_msr_id));
444}
445
446static const struct dmi_system_id msr_save_dmi_table[] = {
447	{
448	 .callback = msr_initialize_bdw,
449	 .ident = "BROADWELL BDX_EP",
450	 .matches = {
451		DMI_MATCH(DMI_PRODUCT_NAME, "GRANTLEY"),
452		DMI_MATCH(DMI_PRODUCT_VERSION, "E63448-400"),
453		},
454	},
455	{}
456};
457
458static int msr_save_cpuid_features(const struct x86_cpu_id *c)
459{
460	u32 cpuid_msr_id[] = {
461		MSR_AMD64_CPUID_FN_1,
462	};
463
464	pr_info("x86/pm: family %#hx cpu detected, MSR saving is needed during suspending.\n",
465		c->family);
466
467	return msr_build_context(cpuid_msr_id, ARRAY_SIZE(cpuid_msr_id));
468}
469
470static const struct x86_cpu_id msr_save_cpu_table[] = {
471	X86_MATCH_VENDOR_FAM(AMD, 0x15, &msr_save_cpuid_features),
472	X86_MATCH_VENDOR_FAM(AMD, 0x16, &msr_save_cpuid_features),
473	{}
474};
475
476typedef int (*pm_cpu_match_t)(const struct x86_cpu_id *);
477static int pm_cpu_check(const struct x86_cpu_id *c)
478{
479	const struct x86_cpu_id *m;
480	int ret = 0;
481
482	m = x86_match_cpu(msr_save_cpu_table);
483	if (m) {
484		pm_cpu_match_t fn;
485
486		fn = (pm_cpu_match_t)m->driver_data;
487		ret = fn(m);
488	}
489
490	return ret;
491}
492
493static void pm_save_spec_msr(void)
494{
495	struct msr_enumeration {
496		u32 msr_no;
497		u32 feature;
498	} msr_enum[] = {
499		{ MSR_IA32_SPEC_CTRL,	 X86_FEATURE_MSR_SPEC_CTRL },
500		{ MSR_IA32_TSX_CTRL,	 X86_FEATURE_MSR_TSX_CTRL },
501		{ MSR_TSX_FORCE_ABORT,	 X86_FEATURE_TSX_FORCE_ABORT },
502		{ MSR_IA32_MCU_OPT_CTRL, X86_FEATURE_SRBDS_CTRL },
503		{ MSR_AMD64_LS_CFG,	 X86_FEATURE_LS_CFG_SSBD },
504		{ MSR_AMD64_DE_CFG,	 X86_FEATURE_LFENCE_RDTSC },
505	};
506	int i;
507
508	for (i = 0; i < ARRAY_SIZE(msr_enum); i++) {
509		if (boot_cpu_has(msr_enum[i].feature))
510			msr_build_context(&msr_enum[i].msr_no, 1);
511	}
512}
513
514static int pm_check_save_msr(void)
515{
516	dmi_check_system(msr_save_dmi_table);
517	pm_cpu_check(msr_save_cpu_table);
518	pm_save_spec_msr();
519
520	return 0;
521}
522
523device_initcall(pm_check_save_msr);