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bpf_jit_comp.c
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linux-6.19.14/arch/x86/net/bpf_jit_comp.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * BPF JIT compiler 4 * 5 * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com) 6 * Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com 7 */ 8#include <linux/netdevice.h> 9#include <linux/filter.h> 10#include <linux/if_vlan.h> 11#include <linux/bitfield.h> 12#include <linux/bpf.h> 13#include <linux/memory.h> 14#include <linux/sort.h> 15#include <asm/extable.h> 16#include <asm/ftrace.h> 17#include <asm/set_memory.h> 18#include <asm/nospec-branch.h> 19#include <asm/text-patching.h> 20#include <asm/unwind.h> 21#include <asm/cfi.h> 22 23static bool all_callee_regs_used[4] = {true, true, true, true}; 24 25static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len) 26{ 27 if (len == 1) 28 *ptr = bytes; 29 else if (len == 2) 30 *(u16 *)ptr = bytes; 31 else { 32 *(u32 *)ptr = bytes; 33 barrier(); 34 } 35 return ptr + len; 36} 37 38#define EMIT(bytes, len) \ 39 do { prog = emit_code(prog, bytes, len); } while (0) 40 41#define EMIT1(b1) EMIT(b1, 1) 42#define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2) 43#define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3) 44#define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4) 45#define EMIT5(b1, b2, b3, b4, b5) \ 46 do { EMIT1(b1); EMIT4(b2, b3, b4, b5); } while (0) 47 48#define EMIT1_off32(b1, off) \ 49 do { EMIT1(b1); EMIT(off, 4); } while (0) 50#define EMIT2_off32(b1, b2, off) \ 51 do { EMIT2(b1, b2); EMIT(off, 4); } while (0) 52#define EMIT3_off32(b1, b2, b3, off) \ 53 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0) 54#define EMIT4_off32(b1, b2, b3, b4, off) \ 55 do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0) 56 57#ifdef CONFIG_X86_KERNEL_IBT 58#define EMIT_ENDBR() EMIT(gen_endbr(), 4) 59#define EMIT_ENDBR_POISON() EMIT(gen_endbr_poison(), 4) 60#else 61#define EMIT_ENDBR() 62#define EMIT_ENDBR_POISON() 63#endif 64 65static bool is_imm8(int value) 66{ 67 return value <= 127 && value >= -128; 68} 69 70/* 71 * Let us limit the positive offset to be <= 123. 72 * This is to ensure eventual jit convergence For the following patterns: 73 * ... 74 * pass4, final_proglen=4391: 75 * ... 76 * 20e: 48 85 ff test rdi,rdi 77 * 211: 74 7d je 0x290 78 * 213: 48 8b 77 00 mov rsi,QWORD PTR [rdi+0x0] 79 * ... 80 * 289: 48 85 ff test rdi,rdi 81 * 28c: 74 17 je 0x2a5 82 * 28e: e9 7f ff ff ff jmp 0x212 83 * 293: bf 03 00 00 00 mov edi,0x3 84 * Note that insn at 0x211 is 2-byte cond jump insn for offset 0x7d (-125) 85 * and insn at 0x28e is 5-byte jmp insn with offset -129. 86 * 87 * pass5, final_proglen=4392: 88 * ... 89 * 20e: 48 85 ff test rdi,rdi 90 * 211: 0f 84 80 00 00 00 je 0x297 91 * 217: 48 8b 77 00 mov rsi,QWORD PTR [rdi+0x0] 92 * ... 93 * 28d: 48 85 ff test rdi,rdi 94 * 290: 74 1a je 0x2ac 95 * 292: eb 84 jmp 0x218 96 * 294: bf 03 00 00 00 mov edi,0x3 97 * Note that insn at 0x211 is 6-byte cond jump insn now since its offset 98 * becomes 0x80 based on previous round (0x293 - 0x213 = 0x80). 99 * At the same time, insn at 0x292 is a 2-byte insn since its offset is 100 * -124. 101 * 102 * pass6 will repeat the same code as in pass4 and this will prevent 103 * eventual convergence. 104 * 105 * To fix this issue, we need to break je (2->6 bytes) <-> jmp (5->2 bytes) 106 * cycle in the above. In the above example je offset <= 0x7c should work. 107 * 108 * For other cases, je <-> je needs offset <= 0x7b to avoid no convergence 109 * issue. For jmp <-> je and jmp <-> jmp cases, jmp offset <= 0x7c should 110 * avoid no convergence issue. 111 * 112 * Overall, let us limit the positive offset for 8bit cond/uncond jmp insn 113 * to maximum 123 (0x7b). This way, the jit pass can eventually converge. 114 */ 115static bool is_imm8_jmp_offset(int value) 116{ 117 return value <= 123 && value >= -128; 118} 119 120static bool is_simm32(s64 value) 121{ 122 return value == (s64)(s32)value; 123} 124 125static bool is_uimm32(u64 value) 126{ 127 return value == (u64)(u32)value; 128} 129 130/* mov dst, src */ 131#define EMIT_mov(DST, SRC) \ 132 do { \ 133 if (DST != SRC) \ 134 EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \ 135 } while (0) 136 137static int bpf_size_to_x86_bytes(int bpf_size) 138{ 139 if (bpf_size == BPF_W) 140 return 4; 141 else if (bpf_size == BPF_H) 142 return 2; 143 else if (bpf_size == BPF_B) 144 return 1; 145 else if (bpf_size == BPF_DW) 146 return 4; /* imm32 */ 147 else 148 return 0; 149} 150 151/* 152 * List of x86 cond jumps opcodes (. + s8) 153 * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32) 154 */ 155#define X86_JB 0x72 156#define X86_JAE 0x73 157#define X86_JE 0x74 158#define X86_JNE 0x75 159#define X86_JBE 0x76 160#define X86_JA 0x77 161#define X86_JL 0x7C 162#define X86_JGE 0x7D 163#define X86_JLE 0x7E 164#define X86_JG 0x7F 165 166/* Pick a register outside of BPF range for JIT internal work */ 167#define AUX_REG (MAX_BPF_JIT_REG + 1) 168#define X86_REG_R9 (MAX_BPF_JIT_REG + 2) 169#define X86_REG_R12 (MAX_BPF_JIT_REG + 3) 170 171/* 172 * The following table maps BPF registers to x86-64 registers. 173 * 174 * x86-64 register R12 is unused, since if used as base address 175 * register in load/store instructions, it always needs an 176 * extra byte of encoding and is callee saved. 177 * 178 * x86-64 register R9 is not used by BPF programs, but can be used by BPF 179 * trampoline. x86-64 register R10 is used for blinding (if enabled). 180 */ 181static const int reg2hex[] = { 182 [BPF_REG_0] = 0, /* RAX */ 183 [BPF_REG_1] = 7, /* RDI */ 184 [BPF_REG_2] = 6, /* RSI */ 185 [BPF_REG_3] = 2, /* RDX */ 186 [BPF_REG_4] = 1, /* RCX */ 187 [BPF_REG_5] = 0, /* R8 */ 188 [BPF_REG_6] = 3, /* RBX callee saved */ 189 [BPF_REG_7] = 5, /* R13 callee saved */ 190 [BPF_REG_8] = 6, /* R14 callee saved */ 191 [BPF_REG_9] = 7, /* R15 callee saved */ 192 [BPF_REG_FP] = 5, /* RBP readonly */ 193 [BPF_REG_AX] = 2, /* R10 temp register */ 194 [AUX_REG] = 3, /* R11 temp register */ 195 [X86_REG_R9] = 1, /* R9 register, 6th function argument */ 196 [X86_REG_R12] = 4, /* R12 callee saved */ 197}; 198 199static const int reg2pt_regs[] = { 200 [BPF_REG_0] = offsetof(struct pt_regs, ax), 201 [BPF_REG_1] = offsetof(struct pt_regs, di), 202 [BPF_REG_2] = offsetof(struct pt_regs, si), 203 [BPF_REG_3] = offsetof(struct pt_regs, dx), 204 [BPF_REG_4] = offsetof(struct pt_regs, cx), 205 [BPF_REG_5] = offsetof(struct pt_regs, r8), 206 [BPF_REG_6] = offsetof(struct pt_regs, bx), 207 [BPF_REG_7] = offsetof(struct pt_regs, r13), 208 [BPF_REG_8] = offsetof(struct pt_regs, r14), 209 [BPF_REG_9] = offsetof(struct pt_regs, r15), 210}; 211 212/* 213 * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15 214 * which need extra byte of encoding. 215 * rax,rcx,...,rbp have simpler encoding 216 */ 217static bool is_ereg(u32 reg) 218{ 219 return (1 << reg) & (BIT(BPF_REG_5) | 220 BIT(AUX_REG) | 221 BIT(BPF_REG_7) | 222 BIT(BPF_REG_8) | 223 BIT(BPF_REG_9) | 224 BIT(X86_REG_R9) | 225 BIT(X86_REG_R12) | 226 BIT(BPF_REG_AX)); 227} 228 229/* 230 * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64 231 * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte 232 * of encoding. al,cl,dl,bl have simpler encoding. 233 */ 234static bool is_ereg_8l(u32 reg) 235{ 236 return is_ereg(reg) || 237 (1 << reg) & (BIT(BPF_REG_1) | 238 BIT(BPF_REG_2) | 239 BIT(BPF_REG_FP)); 240} 241 242static bool is_axreg(u32 reg) 243{ 244 return reg == BPF_REG_0; 245} 246 247/* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */ 248static u8 add_1mod(u8 byte, u32 reg) 249{ 250 if (is_ereg(reg)) 251 byte |= 1; 252 return byte; 253} 254 255static u8 add_2mod(u8 byte, u32 r1, u32 r2) 256{ 257 if (is_ereg(r1)) 258 byte |= 1; 259 if (is_ereg(r2)) 260 byte |= 4; 261 return byte; 262} 263 264static u8 add_3mod(u8 byte, u32 r1, u32 r2, u32 index) 265{ 266 if (is_ereg(r1)) 267 byte |= 1; 268 if (is_ereg(index)) 269 byte |= 2; 270 if (is_ereg(r2)) 271 byte |= 4; 272 return byte; 273} 274 275/* Encode 'dst_reg' register into x86-64 opcode 'byte' */ 276static u8 add_1reg(u8 byte, u32 dst_reg) 277{ 278 return byte + reg2hex[dst_reg]; 279} 280 281/* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */ 282static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg) 283{ 284 return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3); 285} 286 287/* Some 1-byte opcodes for binary ALU operations */ 288static u8 simple_alu_opcodes[] = { 289 [BPF_ADD] = 0x01, 290 [BPF_SUB] = 0x29, 291 [BPF_AND] = 0x21, 292 [BPF_OR] = 0x09, 293 [BPF_XOR] = 0x31, 294 [BPF_LSH] = 0xE0, 295 [BPF_RSH] = 0xE8, 296 [BPF_ARSH] = 0xF8, 297}; 298 299static void jit_fill_hole(void *area, unsigned int size) 300{ 301 /* Fill whole space with INT3 instructions */ 302 memset(area, 0xcc, size); 303} 304 305int bpf_arch_text_invalidate(void *dst, size_t len) 306{ 307 return IS_ERR_OR_NULL(text_poke_set(dst, 0xcc, len)); 308} 309 310struct jit_context { 311 int cleanup_addr; /* Epilogue code offset */ 312 313 /* 314 * Program specific offsets of labels in the code; these rely on the 315 * JIT doing at least 2 passes, recording the position on the first 316 * pass, only to generate the correct offset on the second pass. 317 */ 318 int tail_call_direct_label; 319 int tail_call_indirect_label; 320}; 321 322/* Maximum number of bytes emitted while JITing one eBPF insn */ 323#define BPF_MAX_INSN_SIZE 128 324#define BPF_INSN_SAFETY 64 325 326/* Number of bytes emit_patch() needs to generate instructions */ 327#define X86_PATCH_SIZE 5 328/* Number of bytes that will be skipped on tailcall */ 329#define X86_TAIL_CALL_OFFSET (12 + ENDBR_INSN_SIZE) 330 331static void push_r9(u8 **pprog) 332{ 333 u8 *prog = *pprog; 334 335 EMIT2(0x41, 0x51); /* push r9 */ 336 *pprog = prog; 337} 338 339static void pop_r9(u8 **pprog) 340{ 341 u8 *prog = *pprog; 342 343 EMIT2(0x41, 0x59); /* pop r9 */ 344 *pprog = prog; 345} 346 347static void push_r12(u8 **pprog) 348{ 349 u8 *prog = *pprog; 350 351 EMIT2(0x41, 0x54); /* push r12 */ 352 *pprog = prog; 353} 354 355static void push_callee_regs(u8 **pprog, bool *callee_regs_used) 356{ 357 u8 *prog = *pprog; 358 359 if (callee_regs_used[0]) 360 EMIT1(0x53); /* push rbx */ 361 if (callee_regs_used[1]) 362 EMIT2(0x41, 0x55); /* push r13 */ 363 if (callee_regs_used[2]) 364 EMIT2(0x41, 0x56); /* push r14 */ 365 if (callee_regs_used[3]) 366 EMIT2(0x41, 0x57); /* push r15 */ 367 *pprog = prog; 368} 369 370static void pop_r12(u8 **pprog) 371{ 372 u8 *prog = *pprog; 373 374 EMIT2(0x41, 0x5C); /* pop r12 */ 375 *pprog = prog; 376} 377 378static void pop_callee_regs(u8 **pprog, bool *callee_regs_used) 379{ 380 u8 *prog = *pprog; 381 382 if (callee_regs_used[3]) 383 EMIT2(0x41, 0x5F); /* pop r15 */ 384 if (callee_regs_used[2]) 385 EMIT2(0x41, 0x5E); /* pop r14 */ 386 if (callee_regs_used[1]) 387 EMIT2(0x41, 0x5D); /* pop r13 */ 388 if (callee_regs_used[0]) 389 EMIT1(0x5B); /* pop rbx */ 390 *pprog = prog; 391} 392 393static void emit_nops(u8 **pprog, int len) 394{ 395 u8 *prog = *pprog; 396 int i, noplen; 397 398 while (len > 0) { 399 noplen = len; 400 401 if (noplen > ASM_NOP_MAX) 402 noplen = ASM_NOP_MAX; 403 404 for (i = 0; i < noplen; i++) 405 EMIT1(x86_nops[noplen][i]); 406 len -= noplen; 407 } 408 409 *pprog = prog; 410} 411 412/* 413 * Emit the various CFI preambles, see asm/cfi.h and the comments about FineIBT 414 * in arch/x86/kernel/alternative.c 415 */ 416static int emit_call(u8 **prog, void *func, void *ip); 417 418static void emit_fineibt(u8 **pprog, u8 *ip, u32 hash, int arity) 419{ 420 u8 *prog = *pprog; 421 422 EMIT_ENDBR(); 423 EMIT1_off32(0x2d, hash); /* subl $hash, %eax */ 424 if (cfi_bhi) { 425 EMIT2(0x2e, 0x2e); /* cs cs */ 426 emit_call(&prog, __bhi_args[arity], ip + 11); 427 } else { 428 EMIT3_off32(0x2e, 0x0f, 0x85, 3); /* jne.d32,pn 3 */ 429 } 430 EMIT_ENDBR_POISON(); 431 432 *pprog = prog; 433} 434 435static void emit_kcfi(u8 **pprog, u32 hash) 436{ 437 u8 *prog = *pprog; 438 439 EMIT1_off32(0xb8, hash); /* movl $hash, %eax */ 440#ifdef CONFIG_CALL_PADDING 441 for (int i = 0; i < CONFIG_FUNCTION_PADDING_CFI; i++) 442 EMIT1(0x90); 443#endif 444 EMIT_ENDBR(); 445 446 *pprog = prog; 447} 448 449static void emit_cfi(u8 **pprog, u8 *ip, u32 hash, int arity) 450{ 451 u8 *prog = *pprog; 452 453 switch (cfi_mode) { 454 case CFI_FINEIBT: 455 emit_fineibt(&prog, ip, hash, arity); 456 break; 457 458 case CFI_KCFI: 459 emit_kcfi(&prog, hash); 460 break; 461 462 default: 463 EMIT_ENDBR(); 464 break; 465 } 466 467 *pprog = prog; 468} 469 470static void emit_prologue_tail_call(u8 **pprog, bool is_subprog) 471{ 472 u8 *prog = *pprog; 473 474 if (!is_subprog) { 475 /* cmp rax, MAX_TAIL_CALL_CNT */ 476 EMIT4(0x48, 0x83, 0xF8, MAX_TAIL_CALL_CNT); 477 EMIT2(X86_JA, 6); /* ja 6 */ 478 /* rax is tail_call_cnt if <= MAX_TAIL_CALL_CNT. 479 * case1: entry of main prog. 480 * case2: tail callee of main prog. 481 */ 482 EMIT1(0x50); /* push rax */ 483 /* Make rax as tail_call_cnt_ptr. */ 484 EMIT3(0x48, 0x89, 0xE0); /* mov rax, rsp */ 485 EMIT2(0xEB, 1); /* jmp 1 */ 486 /* rax is tail_call_cnt_ptr if > MAX_TAIL_CALL_CNT. 487 * case: tail callee of subprog. 488 */ 489 EMIT1(0x50); /* push rax */ 490 /* push tail_call_cnt_ptr */ 491 EMIT1(0x50); /* push rax */ 492 } else { /* is_subprog */ 493 /* rax is tail_call_cnt_ptr. */ 494 EMIT1(0x50); /* push rax */ 495 EMIT1(0x50); /* push rax */ 496 } 497 498 *pprog = prog; 499} 500 501/* 502 * Emit x86-64 prologue code for BPF program. 503 * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes 504 * while jumping to another program 505 */ 506static void emit_prologue(u8 **pprog, u8 *ip, u32 stack_depth, bool ebpf_from_cbpf, 507 bool tail_call_reachable, bool is_subprog, 508 bool is_exception_cb) 509{ 510 u8 *prog = *pprog; 511 512 if (is_subprog) { 513 emit_cfi(&prog, ip, cfi_bpf_subprog_hash, 5); 514 } else { 515 emit_cfi(&prog, ip, cfi_bpf_hash, 1); 516 } 517 /* BPF trampoline can be made to work without these nops, 518 * but let's waste 5 bytes for now and optimize later 519 */ 520 emit_nops(&prog, X86_PATCH_SIZE); 521 if (!ebpf_from_cbpf) { 522 if (tail_call_reachable && !is_subprog) 523 /* When it's the entry of the whole tailcall context, 524 * zeroing rax means initialising tail_call_cnt. 525 */ 526 EMIT3(0x48, 0x31, 0xC0); /* xor rax, rax */ 527 else 528 /* Keep the same instruction layout. */ 529 emit_nops(&prog, 3); /* nop3 */ 530 } 531 /* Exception callback receives FP as third parameter */ 532 if (is_exception_cb) { 533 EMIT3(0x48, 0x89, 0xF4); /* mov rsp, rsi */ 534 EMIT3(0x48, 0x89, 0xD5); /* mov rbp, rdx */ 535 /* The main frame must have exception_boundary as true, so we 536 * first restore those callee-saved regs from stack, before 537 * reusing the stack frame. 538 */ 539 pop_callee_regs(&prog, all_callee_regs_used); 540 pop_r12(&prog); 541 /* Reset the stack frame. */ 542 EMIT3(0x48, 0x89, 0xEC); /* mov rsp, rbp */ 543 } else { 544 EMIT1(0x55); /* push rbp */ 545 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */ 546 } 547 548 /* X86_TAIL_CALL_OFFSET is here */ 549 EMIT_ENDBR(); 550 551 /* sub rsp, rounded_stack_depth */ 552 if (stack_depth) 553 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8)); 554 if (tail_call_reachable) 555 emit_prologue_tail_call(&prog, is_subprog); 556 *pprog = prog; 557} 558 559static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode) 560{ 561 u8 *prog = *pprog; 562 s64 offset; 563 564 offset = func - (ip + X86_PATCH_SIZE); 565 if (!is_simm32(offset)) { 566 pr_err("Target call %p is out of range\n", func); 567 return -ERANGE; 568 } 569 EMIT1_off32(opcode, offset); 570 *pprog = prog; 571 return 0; 572} 573 574static int emit_call(u8 **pprog, void *func, void *ip) 575{ 576 return emit_patch(pprog, func, ip, 0xE8); 577} 578 579static int emit_rsb_call(u8 **pprog, void *func, void *ip) 580{ 581 OPTIMIZER_HIDE_VAR(func); 582 ip += x86_call_depth_emit_accounting(pprog, func, ip); 583 return emit_patch(pprog, func, ip, 0xE8); 584} 585 586static int emit_jump(u8 **pprog, void *func, void *ip) 587{ 588 return emit_patch(pprog, func, ip, 0xE9); 589} 590 591static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type old_t, 592 enum bpf_text_poke_type new_t, 593 void *old_addr, void *new_addr) 594{ 595 const u8 *nop_insn = x86_nops[5]; 596 u8 old_insn[X86_PATCH_SIZE]; 597 u8 new_insn[X86_PATCH_SIZE]; 598 u8 *prog; 599 int ret; 600 601 memcpy(old_insn, nop_insn, X86_PATCH_SIZE); 602 if (old_t != BPF_MOD_NOP && old_addr) { 603 prog = old_insn; 604 ret = old_t == BPF_MOD_CALL ? 605 emit_call(&prog, old_addr, ip) : 606 emit_jump(&prog, old_addr, ip); 607 if (ret) 608 return ret; 609 } 610 611 memcpy(new_insn, nop_insn, X86_PATCH_SIZE); 612 if (new_t != BPF_MOD_NOP && new_addr) { 613 prog = new_insn; 614 ret = new_t == BPF_MOD_CALL ? 615 emit_call(&prog, new_addr, ip) : 616 emit_jump(&prog, new_addr, ip); 617 if (ret) 618 return ret; 619 } 620 621 ret = -EBUSY; 622 mutex_lock(&text_mutex); 623 if (memcmp(ip, old_insn, X86_PATCH_SIZE)) 624 goto out; 625 ret = 1; 626 if (memcmp(ip, new_insn, X86_PATCH_SIZE)) { 627 smp_text_poke_single(ip, new_insn, X86_PATCH_SIZE, NULL); 628 ret = 0; 629 } 630out: 631 mutex_unlock(&text_mutex); 632 return ret; 633} 634 635int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type old_t, 636 enum bpf_text_poke_type new_t, void *old_addr, 637 void *new_addr) 638{ 639 if (!is_kernel_text((long)ip) && 640 !is_bpf_text_address((long)ip)) 641 /* BPF poking in modules is not supported */ 642 return -EINVAL; 643 644 /* 645 * See emit_prologue(), for IBT builds the trampoline hook is preceded 646 * with an ENDBR instruction. 647 */ 648 if (is_endbr(ip)) 649 ip += ENDBR_INSN_SIZE; 650 651 return __bpf_arch_text_poke(ip, old_t, new_t, old_addr, new_addr); 652} 653 654#define EMIT_LFENCE() EMIT3(0x0F, 0xAE, 0xE8) 655 656static void __emit_indirect_jump(u8 **pprog, int reg, bool ereg) 657{ 658 u8 *prog = *pprog; 659 660 if (ereg) 661 EMIT1(0x41); 662 663 EMIT2(0xFF, 0xE0 + reg); 664 665 *pprog = prog; 666} 667 668static void emit_indirect_jump(u8 **pprog, int bpf_reg, u8 *ip) 669{ 670 u8 *prog = *pprog; 671 int reg = reg2hex[bpf_reg]; 672 bool ereg = is_ereg(bpf_reg); 673 674 if (cpu_feature_enabled(X86_FEATURE_INDIRECT_THUNK_ITS)) { 675 OPTIMIZER_HIDE_VAR(reg); 676 emit_jump(&prog, its_static_thunk(reg + 8*ereg), ip); 677 } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) { 678 EMIT_LFENCE(); 679 __emit_indirect_jump(&prog, reg, ereg); 680 } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) { 681 OPTIMIZER_HIDE_VAR(reg); 682 if (cpu_feature_enabled(X86_FEATURE_CALL_DEPTH)) 683 emit_jump(&prog, &__x86_indirect_jump_thunk_array[reg + 8*ereg], ip); 684 else 685 emit_jump(&prog, &__x86_indirect_thunk_array[reg + 8*ereg], ip); 686 } else { 687 __emit_indirect_jump(&prog, reg, ereg); 688 if (IS_ENABLED(CONFIG_MITIGATION_RETPOLINE) || IS_ENABLED(CONFIG_MITIGATION_SLS)) 689 EMIT1(0xCC); /* int3 */ 690 } 691 692 *pprog = prog; 693} 694 695static void emit_return(u8 **pprog, u8 *ip) 696{ 697 u8 *prog = *pprog; 698 699 if (cpu_wants_rethunk()) { 700 emit_jump(&prog, x86_return_thunk, ip); 701 } else { 702 EMIT1(0xC3); /* ret */ 703 if (IS_ENABLED(CONFIG_MITIGATION_SLS)) 704 EMIT1(0xCC); /* int3 */ 705 } 706 707 *pprog = prog; 708} 709 710#define BPF_TAIL_CALL_CNT_PTR_STACK_OFF(stack) (-16 - round_up(stack, 8)) 711 712/* 713 * Generate the following code: 714 * 715 * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ... 716 * if (index >= array->map.max_entries) 717 * goto out; 718 * if ((*tcc_ptr)++ >= MAX_TAIL_CALL_CNT) 719 * goto out; 720 * prog = array->ptrs[index]; 721 * if (prog == NULL) 722 * goto out; 723 * goto *(prog->bpf_func + prologue_size); 724 * out: 725 */ 726static void emit_bpf_tail_call_indirect(struct bpf_prog *bpf_prog, 727 u8 **pprog, bool *callee_regs_used, 728 u32 stack_depth, u8 *ip, 729 struct jit_context *ctx) 730{ 731 int tcc_ptr_off = BPF_TAIL_CALL_CNT_PTR_STACK_OFF(stack_depth); 732 u8 *prog = *pprog, *start = *pprog; 733 int offset; 734 735 /* 736 * rdi - pointer to ctx 737 * rsi - pointer to bpf_array 738 * rdx - index in bpf_array 739 */ 740 741 /* 742 * if (index >= array->map.max_entries) 743 * goto out; 744 */ 745 EMIT2(0x89, 0xD2); /* mov edx, edx */ 746 EMIT3(0x39, 0x56, /* cmp dword ptr [rsi + 16], edx */ 747 offsetof(struct bpf_array, map.max_entries)); 748 749 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 750 EMIT2(X86_JBE, offset); /* jbe out */ 751 752 /* 753 * if ((*tcc_ptr)++ >= MAX_TAIL_CALL_CNT) 754 * goto out; 755 */ 756 EMIT3_off32(0x48, 0x8B, 0x85, tcc_ptr_off); /* mov rax, qword ptr [rbp - tcc_ptr_off] */ 757 EMIT4(0x48, 0x83, 0x38, MAX_TAIL_CALL_CNT); /* cmp qword ptr [rax], MAX_TAIL_CALL_CNT */ 758 759 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 760 EMIT2(X86_JAE, offset); /* jae out */ 761 762 /* prog = array->ptrs[index]; */ 763 EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6, /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */ 764 offsetof(struct bpf_array, ptrs)); 765 766 /* 767 * if (prog == NULL) 768 * goto out; 769 */ 770 EMIT3(0x48, 0x85, 0xC9); /* test rcx,rcx */ 771 772 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 773 EMIT2(X86_JE, offset); /* je out */ 774 775 /* Inc tail_call_cnt if the slot is populated. */ 776 EMIT4(0x48, 0x83, 0x00, 0x01); /* add qword ptr [rax], 1 */ 777 778 if (bpf_prog->aux->exception_boundary) { 779 pop_callee_regs(&prog, all_callee_regs_used); 780 pop_r12(&prog); 781 } else { 782 pop_callee_regs(&prog, callee_regs_used); 783 if (bpf_arena_get_kern_vm_start(bpf_prog->aux->arena)) 784 pop_r12(&prog); 785 } 786 787 /* Pop tail_call_cnt_ptr. */ 788 EMIT1(0x58); /* pop rax */ 789 /* Pop tail_call_cnt, if it's main prog. 790 * Pop tail_call_cnt_ptr, if it's subprog. 791 */ 792 EMIT1(0x58); /* pop rax */ 793 if (stack_depth) 794 EMIT3_off32(0x48, 0x81, 0xC4, /* add rsp, sd */ 795 round_up(stack_depth, 8)); 796 797 /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */ 798 EMIT4(0x48, 0x8B, 0x49, /* mov rcx, qword ptr [rcx + 32] */ 799 offsetof(struct bpf_prog, bpf_func)); 800 EMIT4(0x48, 0x83, 0xC1, /* add rcx, X86_TAIL_CALL_OFFSET */ 801 X86_TAIL_CALL_OFFSET); 802 /* 803 * Now we're ready to jump into next BPF program 804 * rdi == ctx (1st arg) 805 * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET 806 */ 807 emit_indirect_jump(&prog, BPF_REG_4 /* R4 -> rcx */, ip + (prog - start)); 808 809 /* out: */ 810 ctx->tail_call_indirect_label = prog - start; 811 *pprog = prog; 812} 813 814static void emit_bpf_tail_call_direct(struct bpf_prog *bpf_prog, 815 struct bpf_jit_poke_descriptor *poke, 816 u8 **pprog, u8 *ip, 817 bool *callee_regs_used, u32 stack_depth, 818 struct jit_context *ctx) 819{ 820 int tcc_ptr_off = BPF_TAIL_CALL_CNT_PTR_STACK_OFF(stack_depth); 821 u8 *prog = *pprog, *start = *pprog; 822 int offset; 823 824 /* 825 * if ((*tcc_ptr)++ >= MAX_TAIL_CALL_CNT) 826 * goto out; 827 */ 828 EMIT3_off32(0x48, 0x8B, 0x85, tcc_ptr_off); /* mov rax, qword ptr [rbp - tcc_ptr_off] */ 829 EMIT4(0x48, 0x83, 0x38, MAX_TAIL_CALL_CNT); /* cmp qword ptr [rax], MAX_TAIL_CALL_CNT */ 830 831 offset = ctx->tail_call_direct_label - (prog + 2 - start); 832 EMIT2(X86_JAE, offset); /* jae out */ 833 834 poke->tailcall_bypass = ip + (prog - start); 835 poke->adj_off = X86_TAIL_CALL_OFFSET; 836 poke->tailcall_target = ip + ctx->tail_call_direct_label - X86_PATCH_SIZE; 837 poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE; 838 839 emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE, 840 poke->tailcall_bypass); 841 842 /* Inc tail_call_cnt if the slot is populated. */ 843 EMIT4(0x48, 0x83, 0x00, 0x01); /* add qword ptr [rax], 1 */ 844 845 if (bpf_prog->aux->exception_boundary) { 846 pop_callee_regs(&prog, all_callee_regs_used); 847 pop_r12(&prog); 848 } else { 849 pop_callee_regs(&prog, callee_regs_used); 850 if (bpf_arena_get_kern_vm_start(bpf_prog->aux->arena)) 851 pop_r12(&prog); 852 } 853 854 /* Pop tail_call_cnt_ptr. */ 855 EMIT1(0x58); /* pop rax */ 856 /* Pop tail_call_cnt, if it's main prog. 857 * Pop tail_call_cnt_ptr, if it's subprog. 858 */ 859 EMIT1(0x58); /* pop rax */ 860 if (stack_depth) 861 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8)); 862 863 emit_nops(&prog, X86_PATCH_SIZE); 864 865 /* out: */ 866 ctx->tail_call_direct_label = prog - start; 867 868 *pprog = prog; 869} 870 871static void bpf_tail_call_direct_fixup(struct bpf_prog *prog) 872{ 873 struct bpf_jit_poke_descriptor *poke; 874 struct bpf_array *array; 875 struct bpf_prog *target; 876 int i, ret; 877 878 for (i = 0; i < prog->aux->size_poke_tab; i++) { 879 poke = &prog->aux->poke_tab[i]; 880 if (poke->aux && poke->aux != prog->aux) 881 continue; 882 883 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable)); 884 885 if (poke->reason != BPF_POKE_REASON_TAIL_CALL) 886 continue; 887 888 array = container_of(poke->tail_call.map, struct bpf_array, map); 889 mutex_lock(&array->aux->poke_mutex); 890 target = array->ptrs[poke->tail_call.key]; 891 if (target) { 892 ret = __bpf_arch_text_poke(poke->tailcall_target, 893 BPF_MOD_NOP, BPF_MOD_JUMP, 894 NULL, 895 (u8 *)target->bpf_func + 896 poke->adj_off); 897 BUG_ON(ret < 0); 898 ret = __bpf_arch_text_poke(poke->tailcall_bypass, 899 BPF_MOD_JUMP, BPF_MOD_NOP, 900 (u8 *)poke->tailcall_target + 901 X86_PATCH_SIZE, NULL); 902 BUG_ON(ret < 0); 903 } 904 WRITE_ONCE(poke->tailcall_target_stable, true); 905 mutex_unlock(&array->aux->poke_mutex); 906 } 907} 908 909static void emit_mov_imm32(u8 **pprog, bool sign_propagate, 910 u32 dst_reg, const u32 imm32) 911{ 912 u8 *prog = *pprog; 913 u8 b1, b2, b3; 914 915 /* 916 * Optimization: if imm32 is positive, use 'mov %eax, imm32' 917 * (which zero-extends imm32) to save 2 bytes. 918 */ 919 if (sign_propagate && (s32)imm32 < 0) { 920 /* 'mov %rax, imm32' sign extends imm32 */ 921 b1 = add_1mod(0x48, dst_reg); 922 b2 = 0xC7; 923 b3 = 0xC0; 924 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32); 925 goto done; 926 } 927 928 /* 929 * Optimization: if imm32 is zero, use 'xor %eax, %eax' 930 * to save 3 bytes. 931 */ 932 if (imm32 == 0) { 933 if (is_ereg(dst_reg)) 934 EMIT1(add_2mod(0x40, dst_reg, dst_reg)); 935 b2 = 0x31; /* xor */ 936 b3 = 0xC0; 937 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg)); 938 goto done; 939 } 940 941 /* mov %eax, imm32 */ 942 if (is_ereg(dst_reg)) 943 EMIT1(add_1mod(0x40, dst_reg)); 944 EMIT1_off32(add_1reg(0xB8, dst_reg), imm32); 945done: 946 *pprog = prog; 947} 948 949static void emit_mov_imm64(u8 **pprog, u32 dst_reg, 950 const u32 imm32_hi, const u32 imm32_lo) 951{ 952 u64 imm64 = ((u64)imm32_hi << 32) | (u32)imm32_lo; 953 u8 *prog = *pprog; 954 955 if (is_uimm32(imm64)) { 956 /* 957 * For emitting plain u32, where sign bit must not be 958 * propagated LLVM tends to load imm64 over mov32 959 * directly, so save couple of bytes by just doing 960 * 'mov %eax, imm32' instead. 961 */ 962 emit_mov_imm32(&prog, false, dst_reg, imm32_lo); 963 } else if (is_simm32(imm64)) { 964 emit_mov_imm32(&prog, true, dst_reg, imm32_lo); 965 } else { 966 /* movabsq rax, imm64 */ 967 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg)); 968 EMIT(imm32_lo, 4); 969 EMIT(imm32_hi, 4); 970 } 971 972 *pprog = prog; 973} 974 975static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg) 976{ 977 u8 *prog = *pprog; 978 979 if (is64) { 980 /* mov dst, src */ 981 EMIT_mov(dst_reg, src_reg); 982 } else { 983 /* mov32 dst, src */ 984 if (is_ereg(dst_reg) || is_ereg(src_reg)) 985 EMIT1(add_2mod(0x40, dst_reg, src_reg)); 986 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg)); 987 } 988 989 *pprog = prog; 990} 991 992static void emit_movsx_reg(u8 **pprog, int num_bits, bool is64, u32 dst_reg, 993 u32 src_reg) 994{ 995 u8 *prog = *pprog; 996 997 if (is64) { 998 /* movs[b,w,l]q dst, src */ 999 if (num_bits == 8) 1000 EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbe, 1001 add_2reg(0xC0, src_reg, dst_reg)); 1002 else if (num_bits == 16) 1003 EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbf, 1004 add_2reg(0xC0, src_reg, dst_reg)); 1005 else if (num_bits == 32) 1006 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x63, 1007 add_2reg(0xC0, src_reg, dst_reg)); 1008 } else { 1009 /* movs[b,w]l dst, src */ 1010 if (num_bits == 8) { 1011 EMIT4(add_2mod(0x40, src_reg, dst_reg), 0x0f, 0xbe, 1012 add_2reg(0xC0, src_reg, dst_reg)); 1013 } else if (num_bits == 16) { 1014 if (is_ereg(dst_reg) || is_ereg(src_reg)) 1015 EMIT1(add_2mod(0x40, src_reg, dst_reg)); 1016 EMIT3(add_2mod(0x0f, src_reg, dst_reg), 0xbf, 1017 add_2reg(0xC0, src_reg, dst_reg)); 1018 } 1019 } 1020 1021 *pprog = prog; 1022} 1023 1024/* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */ 1025static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off) 1026{ 1027 u8 *prog = *pprog; 1028 1029 if (is_imm8(off)) { 1030 /* 1-byte signed displacement. 1031 * 1032 * If off == 0 we could skip this and save one extra byte, but 1033 * special case of x86 R13 which always needs an offset is not 1034 * worth the hassle 1035 */ 1036 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off); 1037 } else { 1038 /* 4-byte signed displacement */ 1039 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off); 1040 } 1041 *pprog = prog; 1042} 1043 1044static void emit_insn_suffix_SIB(u8 **pprog, u32 ptr_reg, u32 val_reg, u32 index_reg, int off) 1045{ 1046 u8 *prog = *pprog; 1047 1048 if (is_imm8(off)) { 1049 EMIT3(add_2reg(0x44, BPF_REG_0, val_reg), add_2reg(0, ptr_reg, index_reg) /* SIB */, off); 1050 } else { 1051 EMIT2_off32(add_2reg(0x84, BPF_REG_0, val_reg), add_2reg(0, ptr_reg, index_reg) /* SIB */, off); 1052 } 1053 *pprog = prog; 1054} 1055 1056/* 1057 * Emit a REX byte if it will be necessary to address these registers 1058 */ 1059static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64) 1060{ 1061 u8 *prog = *pprog; 1062 1063 if (is64) 1064 EMIT1(add_2mod(0x48, dst_reg, src_reg)); 1065 else if (is_ereg(dst_reg) || is_ereg(src_reg)) 1066 EMIT1(add_2mod(0x40, dst_reg, src_reg)); 1067 *pprog = prog; 1068} 1069 1070/* 1071 * Similar version of maybe_emit_mod() for a single register 1072 */ 1073static void maybe_emit_1mod(u8 **pprog, u32 reg, bool is64) 1074{ 1075 u8 *prog = *pprog; 1076 1077 if (is64) 1078 EMIT1(add_1mod(0x48, reg)); 1079 else if (is_ereg(reg)) 1080 EMIT1(add_1mod(0x40, reg)); 1081 *pprog = prog; 1082} 1083 1084/* LDX: dst_reg = *(u8*)(src_reg + off) */ 1085static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1086{ 1087 u8 *prog = *pprog; 1088 1089 switch (size) { 1090 case BPF_B: 1091 /* Emit 'movzx rax, byte ptr [rax + off]' */ 1092 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6); 1093 break; 1094 case BPF_H: 1095 /* Emit 'movzx rax, word ptr [rax + off]' */ 1096 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7); 1097 break; 1098 case BPF_W: 1099 /* Emit 'mov eax, dword ptr [rax+0x14]' */ 1100 if (is_ereg(dst_reg) || is_ereg(src_reg)) 1101 EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B); 1102 else 1103 EMIT1(0x8B); 1104 break; 1105 case BPF_DW: 1106 /* Emit 'mov rax, qword ptr [rax+0x14]' */ 1107 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B); 1108 break; 1109 } 1110 emit_insn_suffix(&prog, src_reg, dst_reg, off); 1111 *pprog = prog; 1112} 1113 1114/* LDSX: dst_reg = *(s8*)(src_reg + off) */ 1115static void emit_ldsx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1116{ 1117 u8 *prog = *pprog; 1118 1119 switch (size) { 1120 case BPF_B: 1121 /* Emit 'movsx rax, byte ptr [rax + off]' */ 1122 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xBE); 1123 break; 1124 case BPF_H: 1125 /* Emit 'movsx rax, word ptr [rax + off]' */ 1126 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xBF); 1127 break; 1128 case BPF_W: 1129 /* Emit 'movsx rax, dword ptr [rax+0x14]' */ 1130 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x63); 1131 break; 1132 } 1133 emit_insn_suffix(&prog, src_reg, dst_reg, off); 1134 *pprog = prog; 1135} 1136 1137static void emit_ldx_index(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, u32 index_reg, int off) 1138{ 1139 u8 *prog = *pprog; 1140 1141 switch (size) { 1142 case BPF_B: 1143 /* movzx rax, byte ptr [rax + r12 + off] */ 1144 EMIT3(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x0F, 0xB6); 1145 break; 1146 case BPF_H: 1147 /* movzx rax, word ptr [rax + r12 + off] */ 1148 EMIT3(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x0F, 0xB7); 1149 break; 1150 case BPF_W: 1151 /* mov eax, dword ptr [rax + r12 + off] */ 1152 EMIT2(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x8B); 1153 break; 1154 case BPF_DW: 1155 /* mov rax, qword ptr [rax + r12 + off] */ 1156 EMIT2(add_3mod(0x48, src_reg, dst_reg, index_reg), 0x8B); 1157 break; 1158 } 1159 emit_insn_suffix_SIB(&prog, src_reg, dst_reg, index_reg, off); 1160 *pprog = prog; 1161} 1162 1163static void emit_ldsx_index(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, u32 index_reg, int off) 1164{ 1165 u8 *prog = *pprog; 1166 1167 switch (size) { 1168 case BPF_B: 1169 /* movsx rax, byte ptr [rax + r12 + off] */ 1170 EMIT3(add_3mod(0x48, src_reg, dst_reg, index_reg), 0x0F, 0xBE); 1171 break; 1172 case BPF_H: 1173 /* movsx rax, word ptr [rax + r12 + off] */ 1174 EMIT3(add_3mod(0x48, src_reg, dst_reg, index_reg), 0x0F, 0xBF); 1175 break; 1176 case BPF_W: 1177 /* movsx rax, dword ptr [rax + r12 + off] */ 1178 EMIT2(add_3mod(0x48, src_reg, dst_reg, index_reg), 0x63); 1179 break; 1180 } 1181 emit_insn_suffix_SIB(&prog, src_reg, dst_reg, index_reg, off); 1182 *pprog = prog; 1183} 1184 1185static void emit_ldx_r12(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1186{ 1187 emit_ldx_index(pprog, size, dst_reg, src_reg, X86_REG_R12, off); 1188} 1189 1190static void emit_ldsx_r12(u8 **prog, u32 size, u32 dst_reg, u32 src_reg, int off) 1191{ 1192 emit_ldsx_index(prog, size, dst_reg, src_reg, X86_REG_R12, off); 1193} 1194 1195/* STX: *(u8*)(dst_reg + off) = src_reg */ 1196static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1197{ 1198 u8 *prog = *pprog; 1199 1200 switch (size) { 1201 case BPF_B: 1202 /* Emit 'mov byte ptr [rax + off], al' */ 1203 if (is_ereg(dst_reg) || is_ereg_8l(src_reg)) 1204 /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */ 1205 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88); 1206 else 1207 EMIT1(0x88); 1208 break; 1209 case BPF_H: 1210 if (is_ereg(dst_reg) || is_ereg(src_reg)) 1211 EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89); 1212 else 1213 EMIT2(0x66, 0x89); 1214 break; 1215 case BPF_W: 1216 if (is_ereg(dst_reg) || is_ereg(src_reg)) 1217 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89); 1218 else 1219 EMIT1(0x89); 1220 break; 1221 case BPF_DW: 1222 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89); 1223 break; 1224 } 1225 emit_insn_suffix(&prog, dst_reg, src_reg, off); 1226 *pprog = prog; 1227} 1228 1229/* STX: *(u8*)(dst_reg + index_reg + off) = src_reg */ 1230static void emit_stx_index(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, u32 index_reg, int off) 1231{ 1232 u8 *prog = *pprog; 1233 1234 switch (size) { 1235 case BPF_B: 1236 /* mov byte ptr [rax + r12 + off], al */ 1237 EMIT2(add_3mod(0x40, dst_reg, src_reg, index_reg), 0x88); 1238 break; 1239 case BPF_H: 1240 /* mov word ptr [rax + r12 + off], ax */ 1241 EMIT3(0x66, add_3mod(0x40, dst_reg, src_reg, index_reg), 0x89); 1242 break; 1243 case BPF_W: 1244 /* mov dword ptr [rax + r12 + 1], eax */ 1245 EMIT2(add_3mod(0x40, dst_reg, src_reg, index_reg), 0x89); 1246 break; 1247 case BPF_DW: 1248 /* mov qword ptr [rax + r12 + 1], rax */ 1249 EMIT2(add_3mod(0x48, dst_reg, src_reg, index_reg), 0x89); 1250 break; 1251 } 1252 emit_insn_suffix_SIB(&prog, dst_reg, src_reg, index_reg, off); 1253 *pprog = prog; 1254} 1255 1256static void emit_stx_r12(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1257{ 1258 emit_stx_index(pprog, size, dst_reg, src_reg, X86_REG_R12, off); 1259} 1260 1261/* ST: *(u8*)(dst_reg + index_reg + off) = imm32 */ 1262static void emit_st_index(u8 **pprog, u32 size, u32 dst_reg, u32 index_reg, int off, int imm) 1263{ 1264 u8 *prog = *pprog; 1265 1266 switch (size) { 1267 case BPF_B: 1268 /* mov byte ptr [rax + r12 + off], imm8 */ 1269 EMIT2(add_3mod(0x40, dst_reg, 0, index_reg), 0xC6); 1270 break; 1271 case BPF_H: 1272 /* mov word ptr [rax + r12 + off], imm16 */ 1273 EMIT3(0x66, add_3mod(0x40, dst_reg, 0, index_reg), 0xC7); 1274 break; 1275 case BPF_W: 1276 /* mov dword ptr [rax + r12 + 1], imm32 */ 1277 EMIT2(add_3mod(0x40, dst_reg, 0, index_reg), 0xC7); 1278 break; 1279 case BPF_DW: 1280 /* mov qword ptr [rax + r12 + 1], imm32 */ 1281 EMIT2(add_3mod(0x48, dst_reg, 0, index_reg), 0xC7); 1282 break; 1283 } 1284 emit_insn_suffix_SIB(&prog, dst_reg, 0, index_reg, off); 1285 EMIT(imm, bpf_size_to_x86_bytes(size)); 1286 *pprog = prog; 1287} 1288 1289static void emit_st_r12(u8 **pprog, u32 size, u32 dst_reg, int off, int imm) 1290{ 1291 emit_st_index(pprog, size, dst_reg, X86_REG_R12, off, imm); 1292} 1293 1294static int emit_atomic_rmw(u8 **pprog, u32 atomic_op, 1295 u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size) 1296{ 1297 u8 *prog = *pprog; 1298 1299 EMIT1(0xF0); /* lock prefix */ 1300 1301 maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW); 1302 1303 /* emit opcode */ 1304 switch (atomic_op) { 1305 case BPF_ADD: 1306 case BPF_AND: 1307 case BPF_OR: 1308 case BPF_XOR: 1309 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */ 1310 EMIT1(simple_alu_opcodes[atomic_op]); 1311 break; 1312 case BPF_ADD | BPF_FETCH: 1313 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */ 1314 EMIT2(0x0F, 0xC1); 1315 break; 1316 case BPF_XCHG: 1317 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */ 1318 EMIT1(0x87); 1319 break; 1320 case BPF_CMPXCHG: 1321 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */ 1322 EMIT2(0x0F, 0xB1); 1323 break; 1324 default: 1325 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op); 1326 return -EFAULT; 1327 } 1328 1329 emit_insn_suffix(&prog, dst_reg, src_reg, off); 1330 1331 *pprog = prog; 1332 return 0; 1333} 1334 1335static int emit_atomic_rmw_index(u8 **pprog, u32 atomic_op, u32 size, 1336 u32 dst_reg, u32 src_reg, u32 index_reg, 1337 int off) 1338{ 1339 u8 *prog = *pprog; 1340 1341 EMIT1(0xF0); /* lock prefix */ 1342 switch (size) { 1343 case BPF_W: 1344 EMIT1(add_3mod(0x40, dst_reg, src_reg, index_reg)); 1345 break; 1346 case BPF_DW: 1347 EMIT1(add_3mod(0x48, dst_reg, src_reg, index_reg)); 1348 break; 1349 default: 1350 pr_err("bpf_jit: 1- and 2-byte RMW atomics are not supported\n"); 1351 return -EFAULT; 1352 } 1353 1354 /* emit opcode */ 1355 switch (atomic_op) { 1356 case BPF_ADD: 1357 case BPF_AND: 1358 case BPF_OR: 1359 case BPF_XOR: 1360 /* lock *(u32/u64*)(dst_reg + idx_reg + off) <op>= src_reg */ 1361 EMIT1(simple_alu_opcodes[atomic_op]); 1362 break; 1363 case BPF_ADD | BPF_FETCH: 1364 /* src_reg = atomic_fetch_add(dst_reg + idx_reg + off, src_reg); */ 1365 EMIT2(0x0F, 0xC1); 1366 break; 1367 case BPF_XCHG: 1368 /* src_reg = atomic_xchg(dst_reg + idx_reg + off, src_reg); */ 1369 EMIT1(0x87); 1370 break; 1371 case BPF_CMPXCHG: 1372 /* r0 = atomic_cmpxchg(dst_reg + idx_reg + off, r0, src_reg); */ 1373 EMIT2(0x0F, 0xB1); 1374 break; 1375 default: 1376 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op); 1377 return -EFAULT; 1378 } 1379 emit_insn_suffix_SIB(&prog, dst_reg, src_reg, index_reg, off); 1380 *pprog = prog; 1381 return 0; 1382} 1383 1384static int emit_atomic_ld_st(u8 **pprog, u32 atomic_op, u32 dst_reg, 1385 u32 src_reg, s16 off, u8 bpf_size) 1386{ 1387 switch (atomic_op) { 1388 case BPF_LOAD_ACQ: 1389 /* dst_reg = smp_load_acquire(src_reg + off16) */ 1390 emit_ldx(pprog, bpf_size, dst_reg, src_reg, off); 1391 break; 1392 case BPF_STORE_REL: 1393 /* smp_store_release(dst_reg + off16, src_reg) */ 1394 emit_stx(pprog, bpf_size, dst_reg, src_reg, off); 1395 break; 1396 default: 1397 pr_err("bpf_jit: unknown atomic load/store opcode %02x\n", 1398 atomic_op); 1399 return -EFAULT; 1400 } 1401 1402 return 0; 1403} 1404 1405static int emit_atomic_ld_st_index(u8 **pprog, u32 atomic_op, u32 size, 1406 u32 dst_reg, u32 src_reg, u32 index_reg, 1407 int off) 1408{ 1409 switch (atomic_op) { 1410 case BPF_LOAD_ACQ: 1411 /* dst_reg = smp_load_acquire(src_reg + idx_reg + off16) */ 1412 emit_ldx_index(pprog, size, dst_reg, src_reg, index_reg, off); 1413 break; 1414 case BPF_STORE_REL: 1415 /* smp_store_release(dst_reg + idx_reg + off16, src_reg) */ 1416 emit_stx_index(pprog, size, dst_reg, src_reg, index_reg, off); 1417 break; 1418 default: 1419 pr_err("bpf_jit: unknown atomic load/store opcode %02x\n", 1420 atomic_op); 1421 return -EFAULT; 1422 } 1423 1424 return 0; 1425} 1426 1427/* 1428 * Metadata encoding for exception handling in JITed code. 1429 * 1430 * Format of `fixup` and `data` fields in `struct exception_table_entry`: 1431 * 1432 * Bit layout of `fixup` (32-bit): 1433 * 1434 * +-----------+--------+-----------+---------+----------+ 1435 * | 31 | 30-24 | 23-16 | 15-8 | 7-0 | 1436 * | | | | | | 1437 * | ARENA_ACC | Unused | ARENA_REG | DST_REG | INSN_LEN | 1438 * +-----------+--------+-----------+---------+----------+ 1439 * 1440 * - INSN_LEN (8 bits): Length of faulting insn (max x86 insn = 15 bytes (fits in 8 bits)). 1441 * - DST_REG (8 bits): Offset of dst_reg from reg2pt_regs[] (max offset = 112 (fits in 8 bits)). 1442 * This is set to DONT_CLEAR if the insn is a store. 1443 * - ARENA_REG (8 bits): Offset of the register that is used to calculate the 1444 * address for load/store when accessing the arena region. 1445 * - ARENA_ACCESS (1 bit): This bit is set when the faulting instruction accessed the arena region. 1446 * 1447 * Bit layout of `data` (32-bit): 1448 * 1449 * +--------------+--------+--------------+ 1450 * | 31-16 | 15-8 | 7-0 | 1451 * | | | | 1452 * | ARENA_OFFSET | Unused | EX_TYPE_BPF | 1453 * +--------------+--------+--------------+ 1454 * 1455 * - ARENA_OFFSET (16 bits): Offset used to calculate the address for load/store when 1456 * accessing the arena region. 1457 */ 1458 1459#define DONT_CLEAR 1 1460#define FIXUP_INSN_LEN_MASK GENMASK(7, 0) 1461#define FIXUP_REG_MASK GENMASK(15, 8) 1462#define FIXUP_ARENA_REG_MASK GENMASK(23, 16) 1463#define FIXUP_ARENA_ACCESS BIT(31) 1464#define DATA_ARENA_OFFSET_MASK GENMASK(31, 16) 1465 1466bool ex_handler_bpf(const struct exception_table_entry *x, struct pt_regs *regs) 1467{ 1468 u32 reg = FIELD_GET(FIXUP_REG_MASK, x->fixup); 1469 u32 insn_len = FIELD_GET(FIXUP_INSN_LEN_MASK, x->fixup); 1470 bool is_arena = !!(x->fixup & FIXUP_ARENA_ACCESS); 1471 bool is_write = (reg == DONT_CLEAR); 1472 unsigned long addr; 1473 s16 off; 1474 u32 arena_reg; 1475 1476 if (is_arena) { 1477 arena_reg = FIELD_GET(FIXUP_ARENA_REG_MASK, x->fixup); 1478 off = FIELD_GET(DATA_ARENA_OFFSET_MASK, x->data); 1479 addr = *(unsigned long *)((void *)regs + arena_reg) + off; 1480 bpf_prog_report_arena_violation(is_write, addr, regs->ip); 1481 } 1482 1483 /* jump over faulting load and clear dest register */ 1484 if (reg != DONT_CLEAR) 1485 *(unsigned long *)((void *)regs + reg) = 0; 1486 regs->ip += insn_len; 1487 1488 return true; 1489} 1490 1491static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt, 1492 bool *regs_used) 1493{ 1494 int i; 1495 1496 for (i = 1; i <= insn_cnt; i++, insn++) { 1497 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6) 1498 regs_used[0] = true; 1499 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7) 1500 regs_used[1] = true; 1501 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8) 1502 regs_used[2] = true; 1503 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9) 1504 regs_used[3] = true; 1505 } 1506} 1507 1508/* emit the 3-byte VEX prefix 1509 * 1510 * r: same as rex.r, extra bit for ModRM reg field 1511 * x: same as rex.x, extra bit for SIB index field 1512 * b: same as rex.b, extra bit for ModRM r/m, or SIB base 1513 * m: opcode map select, encoding escape bytes e.g. 0x0f38 1514 * w: same as rex.w (32 bit or 64 bit) or opcode specific 1515 * src_reg2: additional source reg (encoded as BPF reg) 1516 * l: vector length (128 bit or 256 bit) or reserved 1517 * pp: opcode prefix (none, 0x66, 0xf2 or 0xf3) 1518 */ 1519static void emit_3vex(u8 **pprog, bool r, bool x, bool b, u8 m, 1520 bool w, u8 src_reg2, bool l, u8 pp) 1521{ 1522 u8 *prog = *pprog; 1523 const u8 b0 = 0xc4; /* first byte of 3-byte VEX prefix */ 1524 u8 b1, b2; 1525 u8 vvvv = reg2hex[src_reg2]; 1526 1527 /* reg2hex gives only the lower 3 bit of vvvv */ 1528 if (is_ereg(src_reg2)) 1529 vvvv |= 1 << 3; 1530 1531 /* 1532 * 2nd byte of 3-byte VEX prefix 1533 * ~ means bit inverted encoding 1534 * 1535 * 7 0 1536 * +---+---+---+---+---+---+---+---+ 1537 * |~R |~X |~B | m | 1538 * +---+---+---+---+---+---+---+---+ 1539 */ 1540 b1 = (!r << 7) | (!x << 6) | (!b << 5) | (m & 0x1f); 1541 /* 1542 * 3rd byte of 3-byte VEX prefix 1543 * 1544 * 7 0 1545 * +---+---+---+---+---+---+---+---+ 1546 * | W | ~vvvv | L | pp | 1547 * +---+---+---+---+---+---+---+---+ 1548 */ 1549 b2 = (w << 7) | ((~vvvv & 0xf) << 3) | (l << 2) | (pp & 3); 1550 1551 EMIT3(b0, b1, b2); 1552 *pprog = prog; 1553} 1554 1555/* emit BMI2 shift instruction */ 1556static void emit_shiftx(u8 **pprog, u32 dst_reg, u8 src_reg, bool is64, u8 op) 1557{ 1558 u8 *prog = *pprog; 1559 bool r = is_ereg(dst_reg); 1560 u8 m = 2; /* escape code 0f38 */ 1561 1562 emit_3vex(&prog, r, false, r, m, is64, src_reg, false, op); 1563 EMIT2(0xf7, add_2reg(0xC0, dst_reg, dst_reg)); 1564 *pprog = prog; 1565} 1566 1567static void emit_priv_frame_ptr(u8 **pprog, void __percpu *priv_frame_ptr) 1568{ 1569 u8 *prog = *pprog; 1570 1571 /* movabs r9, priv_frame_ptr */ 1572 emit_mov_imm64(&prog, X86_REG_R9, (__force long) priv_frame_ptr >> 32, 1573 (u32) (__force long) priv_frame_ptr); 1574 1575#ifdef CONFIG_SMP 1576 /* add <r9>, gs:[<off>] */ 1577 EMIT2(0x65, 0x4c); 1578 EMIT3(0x03, 0x0c, 0x25); 1579 EMIT((u32)(unsigned long)&this_cpu_off, 4); 1580#endif 1581 1582 *pprog = prog; 1583} 1584 1585#define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp))) 1586 1587#define __LOAD_TCC_PTR(off) \ 1588 EMIT3_off32(0x48, 0x8B, 0x85, off) 1589/* mov rax, qword ptr [rbp - rounded_stack_depth - 16] */ 1590#define LOAD_TAIL_CALL_CNT_PTR(stack) \ 1591 __LOAD_TCC_PTR(BPF_TAIL_CALL_CNT_PTR_STACK_OFF(stack)) 1592 1593/* Memory size/value to protect private stack overflow/underflow */ 1594#define PRIV_STACK_GUARD_SZ 8 1595#define PRIV_STACK_GUARD_VAL 0xEB9F12345678eb9fULL 1596 1597static int emit_spectre_bhb_barrier(u8 **pprog, u8 *ip, 1598 struct bpf_prog *bpf_prog) 1599{ 1600 u8 *prog = *pprog; 1601 u8 *func; 1602 1603 if (cpu_feature_enabled(X86_FEATURE_CLEAR_BHB_LOOP)) { 1604 /* The clearing sequence clobbers eax and ecx. */ 1605 EMIT1(0x50); /* push rax */ 1606 EMIT1(0x51); /* push rcx */ 1607 ip += 2; 1608 1609 func = (u8 *)clear_bhb_loop; 1610 ip += x86_call_depth_emit_accounting(&prog, func, ip); 1611 1612 if (emit_call(&prog, func, ip)) 1613 return -EINVAL; 1614 EMIT1(0x59); /* pop rcx */ 1615 EMIT1(0x58); /* pop rax */ 1616 } 1617 /* Insert IBHF instruction */ 1618 if ((cpu_feature_enabled(X86_FEATURE_CLEAR_BHB_LOOP) && 1619 cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) || 1620 cpu_feature_enabled(X86_FEATURE_CLEAR_BHB_HW)) { 1621 /* 1622 * Add an Indirect Branch History Fence (IBHF). IBHF acts as a 1623 * fence preventing branch history from before the fence from 1624 * affecting indirect branches after the fence. This is 1625 * specifically used in cBPF jitted code to prevent Intra-mode 1626 * BHI attacks. The IBHF instruction is designed to be a NOP on 1627 * hardware that doesn't need or support it. The REP and REX.W 1628 * prefixes are required by the microcode, and they also ensure 1629 * that the NOP is unlikely to be used in existing code. 1630 * 1631 * IBHF is not a valid instruction in 32-bit mode. 1632 */ 1633 EMIT5(0xF3, 0x48, 0x0F, 0x1E, 0xF8); /* ibhf */ 1634 } 1635 *pprog = prog; 1636 return 0; 1637} 1638 1639static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image, 1640 int oldproglen, struct jit_context *ctx, bool jmp_padding) 1641{ 1642 bool tail_call_reachable = bpf_prog->aux->tail_call_reachable; 1643 struct bpf_insn *insn = bpf_prog->insnsi; 1644 bool callee_regs_used[4] = {}; 1645 int insn_cnt = bpf_prog->len; 1646 bool seen_exit = false; 1647 u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY]; 1648 void __percpu *priv_frame_ptr = NULL; 1649 u64 arena_vm_start, user_vm_start; 1650 void __percpu *priv_stack_ptr; 1651 int i, excnt = 0; 1652 int ilen, proglen = 0; 1653 u8 *prog = temp; 1654 u32 stack_depth; 1655 int err; 1656 1657 stack_depth = bpf_prog->aux->stack_depth; 1658 priv_stack_ptr = bpf_prog->aux->priv_stack_ptr; 1659 if (priv_stack_ptr) { 1660 priv_frame_ptr = priv_stack_ptr + PRIV_STACK_GUARD_SZ + round_up(stack_depth, 8); 1661 stack_depth = 0; 1662 } 1663 1664 arena_vm_start = bpf_arena_get_kern_vm_start(bpf_prog->aux->arena); 1665 user_vm_start = bpf_arena_get_user_vm_start(bpf_prog->aux->arena); 1666 1667 detect_reg_usage(insn, insn_cnt, callee_regs_used); 1668 1669 emit_prologue(&prog, image, stack_depth, 1670 bpf_prog_was_classic(bpf_prog), tail_call_reachable, 1671 bpf_is_subprog(bpf_prog), bpf_prog->aux->exception_cb); 1672 1673 bpf_prog->aux->ksym.fp_start = prog - temp; 1674 1675 /* Exception callback will clobber callee regs for its own use, and 1676 * restore the original callee regs from main prog's stack frame. 1677 */ 1678 if (bpf_prog->aux->exception_boundary) { 1679 /* We also need to save r12, which is not mapped to any BPF 1680 * register, as we throw after entry into the kernel, which may 1681 * overwrite r12. 1682 */ 1683 push_r12(&prog); 1684 push_callee_regs(&prog, all_callee_regs_used); 1685 } else { 1686 if (arena_vm_start) 1687 push_r12(&prog); 1688 push_callee_regs(&prog, callee_regs_used); 1689 } 1690 if (arena_vm_start) 1691 emit_mov_imm64(&prog, X86_REG_R12, 1692 arena_vm_start >> 32, (u32) arena_vm_start); 1693 1694 if (priv_frame_ptr) 1695 emit_priv_frame_ptr(&prog, priv_frame_ptr); 1696 1697 ilen = prog - temp; 1698 if (rw_image) 1699 memcpy(rw_image + proglen, temp, ilen); 1700 proglen += ilen; 1701 addrs[0] = proglen; 1702 prog = temp; 1703 1704 for (i = 1; i <= insn_cnt; i++, insn++) { 1705 const s32 imm32 = insn->imm; 1706 u32 dst_reg = insn->dst_reg; 1707 u32 src_reg = insn->src_reg; 1708 u8 b2 = 0, b3 = 0; 1709 u8 *start_of_ldx; 1710 s64 jmp_offset; 1711 s16 insn_off; 1712 u8 jmp_cond; 1713 u8 *func; 1714 int nops; 1715 1716 if (priv_frame_ptr) { 1717 if (src_reg == BPF_REG_FP) 1718 src_reg = X86_REG_R9; 1719 1720 if (dst_reg == BPF_REG_FP) 1721 dst_reg = X86_REG_R9; 1722 } 1723 1724 switch (insn->code) { 1725 /* ALU */ 1726 case BPF_ALU | BPF_ADD | BPF_X: 1727 case BPF_ALU | BPF_SUB | BPF_X: 1728 case BPF_ALU | BPF_AND | BPF_X: 1729 case BPF_ALU | BPF_OR | BPF_X: 1730 case BPF_ALU | BPF_XOR | BPF_X: 1731 case BPF_ALU64 | BPF_ADD | BPF_X: 1732 case BPF_ALU64 | BPF_SUB | BPF_X: 1733 case BPF_ALU64 | BPF_AND | BPF_X: 1734 case BPF_ALU64 | BPF_OR | BPF_X: 1735 case BPF_ALU64 | BPF_XOR | BPF_X: 1736 maybe_emit_mod(&prog, dst_reg, src_reg, 1737 BPF_CLASS(insn->code) == BPF_ALU64); 1738 b2 = simple_alu_opcodes[BPF_OP(insn->code)]; 1739 EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg)); 1740 break; 1741 1742 case BPF_ALU64 | BPF_MOV | BPF_X: 1743 if (insn_is_cast_user(insn)) { 1744 if (dst_reg != src_reg) 1745 /* 32-bit mov */ 1746 emit_mov_reg(&prog, false, dst_reg, src_reg); 1747 /* shl dst_reg, 32 */ 1748 maybe_emit_1mod(&prog, dst_reg, true); 1749 EMIT3(0xC1, add_1reg(0xE0, dst_reg), 32); 1750 1751 /* or dst_reg, user_vm_start */ 1752 maybe_emit_1mod(&prog, dst_reg, true); 1753 if (is_axreg(dst_reg)) 1754 EMIT1_off32(0x0D, user_vm_start >> 32); 1755 else 1756 EMIT2_off32(0x81, add_1reg(0xC8, dst_reg), user_vm_start >> 32); 1757 1758 /* rol dst_reg, 32 */ 1759 maybe_emit_1mod(&prog, dst_reg, true); 1760 EMIT3(0xC1, add_1reg(0xC0, dst_reg), 32); 1761 1762 /* xor r11, r11 */ 1763 EMIT3(0x4D, 0x31, 0xDB); 1764 1765 /* test dst_reg32, dst_reg32; check if lower 32-bit are zero */ 1766 maybe_emit_mod(&prog, dst_reg, dst_reg, false); 1767 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg)); 1768 1769 /* cmove r11, dst_reg; if so, set dst_reg to zero */ 1770 /* WARNING: Intel swapped src/dst register encoding in CMOVcc !!! */ 1771 maybe_emit_mod(&prog, AUX_REG, dst_reg, true); 1772 EMIT3(0x0F, 0x44, add_2reg(0xC0, AUX_REG, dst_reg)); 1773 break; 1774 } else if (insn_is_mov_percpu_addr(insn)) { 1775 /* mov <dst>, <src> (if necessary) */ 1776 EMIT_mov(dst_reg, src_reg); 1777#ifdef CONFIG_SMP 1778 /* add <dst>, gs:[<off>] */ 1779 EMIT2(0x65, add_1mod(0x48, dst_reg)); 1780 EMIT3(0x03, add_2reg(0x04, 0, dst_reg), 0x25); 1781 EMIT((u32)(unsigned long)&this_cpu_off, 4); 1782#endif 1783 break; 1784 } 1785 fallthrough; 1786 case BPF_ALU | BPF_MOV | BPF_X: 1787 if (insn->off == 0) 1788 emit_mov_reg(&prog, 1789 BPF_CLASS(insn->code) == BPF_ALU64, 1790 dst_reg, src_reg); 1791 else 1792 emit_movsx_reg(&prog, insn->off, 1793 BPF_CLASS(insn->code) == BPF_ALU64, 1794 dst_reg, src_reg); 1795 break; 1796 1797 /* neg dst */ 1798 case BPF_ALU | BPF_NEG: 1799 case BPF_ALU64 | BPF_NEG: 1800 maybe_emit_1mod(&prog, dst_reg, 1801 BPF_CLASS(insn->code) == BPF_ALU64); 1802 EMIT2(0xF7, add_1reg(0xD8, dst_reg)); 1803 break; 1804 1805 case BPF_ALU | BPF_ADD | BPF_K: 1806 case BPF_ALU | BPF_SUB | BPF_K: 1807 case BPF_ALU | BPF_AND | BPF_K: 1808 case BPF_ALU | BPF_OR | BPF_K: 1809 case BPF_ALU | BPF_XOR | BPF_K: 1810 case BPF_ALU64 | BPF_ADD | BPF_K: 1811 case BPF_ALU64 | BPF_SUB | BPF_K: 1812 case BPF_ALU64 | BPF_AND | BPF_K: 1813 case BPF_ALU64 | BPF_OR | BPF_K: 1814 case BPF_ALU64 | BPF_XOR | BPF_K: 1815 maybe_emit_1mod(&prog, dst_reg, 1816 BPF_CLASS(insn->code) == BPF_ALU64); 1817 1818 /* 1819 * b3 holds 'normal' opcode, b2 short form only valid 1820 * in case dst is eax/rax. 1821 */ 1822 switch (BPF_OP(insn->code)) { 1823 case BPF_ADD: 1824 b3 = 0xC0; 1825 b2 = 0x05; 1826 break; 1827 case BPF_SUB: 1828 b3 = 0xE8; 1829 b2 = 0x2D; 1830 break; 1831 case BPF_AND: 1832 b3 = 0xE0; 1833 b2 = 0x25; 1834 break; 1835 case BPF_OR: 1836 b3 = 0xC8; 1837 b2 = 0x0D; 1838 break; 1839 case BPF_XOR: 1840 b3 = 0xF0; 1841 b2 = 0x35; 1842 break; 1843 } 1844 1845 if (is_imm8(imm32)) 1846 EMIT3(0x83, add_1reg(b3, dst_reg), imm32); 1847 else if (is_axreg(dst_reg)) 1848 EMIT1_off32(b2, imm32); 1849 else 1850 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32); 1851 break; 1852 1853 case BPF_ALU64 | BPF_MOV | BPF_K: 1854 case BPF_ALU | BPF_MOV | BPF_K: 1855 emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64, 1856 dst_reg, imm32); 1857 break; 1858 1859 case BPF_LD | BPF_IMM | BPF_DW: 1860 emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm); 1861 insn++; 1862 i++; 1863 break; 1864 1865 /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */ 1866 case BPF_ALU | BPF_MOD | BPF_X: 1867 case BPF_ALU | BPF_DIV | BPF_X: 1868 case BPF_ALU | BPF_MOD | BPF_K: 1869 case BPF_ALU | BPF_DIV | BPF_K: 1870 case BPF_ALU64 | BPF_MOD | BPF_X: 1871 case BPF_ALU64 | BPF_DIV | BPF_X: 1872 case BPF_ALU64 | BPF_MOD | BPF_K: 1873 case BPF_ALU64 | BPF_DIV | BPF_K: { 1874 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64; 1875 1876 if (dst_reg != BPF_REG_0) 1877 EMIT1(0x50); /* push rax */ 1878 if (dst_reg != BPF_REG_3) 1879 EMIT1(0x52); /* push rdx */ 1880 1881 if (BPF_SRC(insn->code) == BPF_X) { 1882 if (src_reg == BPF_REG_0 || 1883 src_reg == BPF_REG_3) { 1884 /* mov r11, src_reg */ 1885 EMIT_mov(AUX_REG, src_reg); 1886 src_reg = AUX_REG; 1887 } 1888 } else { 1889 /* mov r11, imm32 */ 1890 EMIT3_off32(0x49, 0xC7, 0xC3, imm32); 1891 src_reg = AUX_REG; 1892 } 1893 1894 if (dst_reg != BPF_REG_0) 1895 /* mov rax, dst_reg */ 1896 emit_mov_reg(&prog, is64, BPF_REG_0, dst_reg); 1897 1898 if (insn->off == 0) { 1899 /* 1900 * xor edx, edx 1901 * equivalent to 'xor rdx, rdx', but one byte less 1902 */ 1903 EMIT2(0x31, 0xd2); 1904 1905 /* div src_reg */ 1906 maybe_emit_1mod(&prog, src_reg, is64); 1907 EMIT2(0xF7, add_1reg(0xF0, src_reg)); 1908 } else { 1909 if (BPF_CLASS(insn->code) == BPF_ALU) 1910 EMIT1(0x99); /* cdq */ 1911 else 1912 EMIT2(0x48, 0x99); /* cqo */ 1913 1914 /* idiv src_reg */ 1915 maybe_emit_1mod(&prog, src_reg, is64); 1916 EMIT2(0xF7, add_1reg(0xF8, src_reg)); 1917 } 1918 1919 if (BPF_OP(insn->code) == BPF_MOD && 1920 dst_reg != BPF_REG_3) 1921 /* mov dst_reg, rdx */ 1922 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_3); 1923 else if (BPF_OP(insn->code) == BPF_DIV && 1924 dst_reg != BPF_REG_0) 1925 /* mov dst_reg, rax */ 1926 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_0); 1927 1928 if (dst_reg != BPF_REG_3) 1929 EMIT1(0x5A); /* pop rdx */ 1930 if (dst_reg != BPF_REG_0) 1931 EMIT1(0x58); /* pop rax */ 1932 break; 1933 } 1934 1935 case BPF_ALU | BPF_MUL | BPF_K: 1936 case BPF_ALU64 | BPF_MUL | BPF_K: 1937 maybe_emit_mod(&prog, dst_reg, dst_reg, 1938 BPF_CLASS(insn->code) == BPF_ALU64); 1939 1940 if (is_imm8(imm32)) 1941 /* imul dst_reg, dst_reg, imm8 */ 1942 EMIT3(0x6B, add_2reg(0xC0, dst_reg, dst_reg), 1943 imm32); 1944 else 1945 /* imul dst_reg, dst_reg, imm32 */ 1946 EMIT2_off32(0x69, 1947 add_2reg(0xC0, dst_reg, dst_reg), 1948 imm32); 1949 break; 1950 1951 case BPF_ALU | BPF_MUL | BPF_X: 1952 case BPF_ALU64 | BPF_MUL | BPF_X: 1953 maybe_emit_mod(&prog, src_reg, dst_reg, 1954 BPF_CLASS(insn->code) == BPF_ALU64); 1955 1956 /* imul dst_reg, src_reg */ 1957 EMIT3(0x0F, 0xAF, add_2reg(0xC0, src_reg, dst_reg)); 1958 break; 1959 1960 /* Shifts */ 1961 case BPF_ALU | BPF_LSH | BPF_K: 1962 case BPF_ALU | BPF_RSH | BPF_K: 1963 case BPF_ALU | BPF_ARSH | BPF_K: 1964 case BPF_ALU64 | BPF_LSH | BPF_K: 1965 case BPF_ALU64 | BPF_RSH | BPF_K: 1966 case BPF_ALU64 | BPF_ARSH | BPF_K: 1967 maybe_emit_1mod(&prog, dst_reg, 1968 BPF_CLASS(insn->code) == BPF_ALU64); 1969 1970 b3 = simple_alu_opcodes[BPF_OP(insn->code)]; 1971 if (imm32 == 1) 1972 EMIT2(0xD1, add_1reg(b3, dst_reg)); 1973 else 1974 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32); 1975 break; 1976 1977 case BPF_ALU | BPF_LSH | BPF_X: 1978 case BPF_ALU | BPF_RSH | BPF_X: 1979 case BPF_ALU | BPF_ARSH | BPF_X: 1980 case BPF_ALU64 | BPF_LSH | BPF_X: 1981 case BPF_ALU64 | BPF_RSH | BPF_X: 1982 case BPF_ALU64 | BPF_ARSH | BPF_X: 1983 /* BMI2 shifts aren't better when shift count is already in rcx */ 1984 if (boot_cpu_has(X86_FEATURE_BMI2) && src_reg != BPF_REG_4) { 1985 /* shrx/sarx/shlx dst_reg, dst_reg, src_reg */ 1986 bool w = (BPF_CLASS(insn->code) == BPF_ALU64); 1987 u8 op; 1988 1989 switch (BPF_OP(insn->code)) { 1990 case BPF_LSH: 1991 op = 1; /* prefix 0x66 */ 1992 break; 1993 case BPF_RSH: 1994 op = 3; /* prefix 0xf2 */ 1995 break; 1996 case BPF_ARSH: 1997 op = 2; /* prefix 0xf3 */ 1998 break; 1999 } 2000 2001 emit_shiftx(&prog, dst_reg, src_reg, w, op); 2002 2003 break; 2004 } 2005 2006 if (src_reg != BPF_REG_4) { /* common case */ 2007 /* Check for bad case when dst_reg == rcx */ 2008 if (dst_reg == BPF_REG_4) { 2009 /* mov r11, dst_reg */ 2010 EMIT_mov(AUX_REG, dst_reg); 2011 dst_reg = AUX_REG; 2012 } else { 2013 EMIT1(0x51); /* push rcx */ 2014 } 2015 /* mov rcx, src_reg */ 2016 EMIT_mov(BPF_REG_4, src_reg); 2017 } 2018 2019 /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */ 2020 maybe_emit_1mod(&prog, dst_reg, 2021 BPF_CLASS(insn->code) == BPF_ALU64); 2022 2023 b3 = simple_alu_opcodes[BPF_OP(insn->code)]; 2024 EMIT2(0xD3, add_1reg(b3, dst_reg)); 2025 2026 if (src_reg != BPF_REG_4) { 2027 if (insn->dst_reg == BPF_REG_4) 2028 /* mov dst_reg, r11 */ 2029 EMIT_mov(insn->dst_reg, AUX_REG); 2030 else 2031 EMIT1(0x59); /* pop rcx */ 2032 } 2033 2034 break; 2035 2036 case BPF_ALU | BPF_END | BPF_FROM_BE: 2037 case BPF_ALU64 | BPF_END | BPF_FROM_LE: 2038 switch (imm32) { 2039 case 16: 2040 /* Emit 'ror %ax, 8' to swap lower 2 bytes */ 2041 EMIT1(0x66); 2042 if (is_ereg(dst_reg)) 2043 EMIT1(0x41); 2044 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8); 2045 2046 /* Emit 'movzwl eax, ax' */ 2047 if (is_ereg(dst_reg)) 2048 EMIT3(0x45, 0x0F, 0xB7); 2049 else 2050 EMIT2(0x0F, 0xB7); 2051 EMIT1(add_2reg(0xC0, dst_reg, dst_reg)); 2052 break; 2053 case 32: 2054 /* Emit 'bswap eax' to swap lower 4 bytes */ 2055 if (is_ereg(dst_reg)) 2056 EMIT2(0x41, 0x0F); 2057 else 2058 EMIT1(0x0F); 2059 EMIT1(add_1reg(0xC8, dst_reg)); 2060 break; 2061 case 64: 2062 /* Emit 'bswap rax' to swap 8 bytes */ 2063 EMIT3(add_1mod(0x48, dst_reg), 0x0F, 2064 add_1reg(0xC8, dst_reg)); 2065 break; 2066 } 2067 break; 2068 2069 case BPF_ALU | BPF_END | BPF_FROM_LE: 2070 switch (imm32) { 2071 case 16: 2072 /* 2073 * Emit 'movzwl eax, ax' to zero extend 16-bit 2074 * into 64 bit 2075 */ 2076 if (is_ereg(dst_reg)) 2077 EMIT3(0x45, 0x0F, 0xB7); 2078 else 2079 EMIT2(0x0F, 0xB7); 2080 EMIT1(add_2reg(0xC0, dst_reg, dst_reg)); 2081 break; 2082 case 32: 2083 /* Emit 'mov eax, eax' to clear upper 32-bits */ 2084 if (is_ereg(dst_reg)) 2085 EMIT1(0x45); 2086 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg)); 2087 break; 2088 case 64: 2089 /* nop */ 2090 break; 2091 } 2092 break; 2093 2094 /* speculation barrier */ 2095 case BPF_ST | BPF_NOSPEC: 2096 EMIT_LFENCE(); 2097 break; 2098 2099 /* ST: *(u8*)(dst_reg + off) = imm */ 2100 case BPF_ST | BPF_MEM | BPF_B: 2101 if (is_ereg(dst_reg)) 2102 EMIT2(0x41, 0xC6); 2103 else 2104 EMIT1(0xC6); 2105 goto st; 2106 case BPF_ST | BPF_MEM | BPF_H: 2107 if (is_ereg(dst_reg)) 2108 EMIT3(0x66, 0x41, 0xC7); 2109 else 2110 EMIT2(0x66, 0xC7); 2111 goto st; 2112 case BPF_ST | BPF_MEM | BPF_W: 2113 if (is_ereg(dst_reg)) 2114 EMIT2(0x41, 0xC7); 2115 else 2116 EMIT1(0xC7); 2117 goto st; 2118 case BPF_ST | BPF_MEM | BPF_DW: 2119 EMIT2(add_1mod(0x48, dst_reg), 0xC7); 2120 2121st: if (is_imm8(insn->off)) 2122 EMIT2(add_1reg(0x40, dst_reg), insn->off); 2123 else 2124 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off); 2125 2126 EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code))); 2127 break; 2128 2129 /* STX: *(u8*)(dst_reg + off) = src_reg */ 2130 case BPF_STX | BPF_MEM | BPF_B: 2131 case BPF_STX | BPF_MEM | BPF_H: 2132 case BPF_STX | BPF_MEM | BPF_W: 2133 case BPF_STX | BPF_MEM | BPF_DW: 2134 emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); 2135 break; 2136 2137 case BPF_ST | BPF_PROBE_MEM32 | BPF_B: 2138 case BPF_ST | BPF_PROBE_MEM32 | BPF_H: 2139 case BPF_ST | BPF_PROBE_MEM32 | BPF_W: 2140 case BPF_ST | BPF_PROBE_MEM32 | BPF_DW: 2141 start_of_ldx = prog; 2142 emit_st_r12(&prog, BPF_SIZE(insn->code), dst_reg, insn->off, insn->imm); 2143 goto populate_extable; 2144 2145 /* LDX: dst_reg = *(u8*)(src_reg + r12 + off) */ 2146 case BPF_LDX | BPF_PROBE_MEM32 | BPF_B: 2147 case BPF_LDX | BPF_PROBE_MEM32 | BPF_H: 2148 case BPF_LDX | BPF_PROBE_MEM32 | BPF_W: 2149 case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW: 2150 case BPF_LDX | BPF_PROBE_MEM32SX | BPF_B: 2151 case BPF_LDX | BPF_PROBE_MEM32SX | BPF_H: 2152 case BPF_LDX | BPF_PROBE_MEM32SX | BPF_W: 2153 case BPF_STX | BPF_PROBE_MEM32 | BPF_B: 2154 case BPF_STX | BPF_PROBE_MEM32 | BPF_H: 2155 case BPF_STX | BPF_PROBE_MEM32 | BPF_W: 2156 case BPF_STX | BPF_PROBE_MEM32 | BPF_DW: 2157 start_of_ldx = prog; 2158 if (BPF_CLASS(insn->code) == BPF_LDX) { 2159 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32SX) 2160 emit_ldsx_r12(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); 2161 else 2162 emit_ldx_r12(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); 2163 } else { 2164 emit_stx_r12(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); 2165 } 2166populate_extable: 2167 { 2168 struct exception_table_entry *ex; 2169 u8 *_insn = image + proglen + (start_of_ldx - temp); 2170 u32 arena_reg, fixup_reg; 2171 s64 delta; 2172 2173 if (!bpf_prog->aux->extable) 2174 break; 2175 2176 if (excnt >= bpf_prog->aux->num_exentries) { 2177 pr_err("mem32 extable bug\n"); 2178 return -EFAULT; 2179 } 2180 ex = &bpf_prog->aux->extable[excnt++]; 2181 2182 delta = _insn - (u8 *)&ex->insn; 2183 /* switch ex to rw buffer for writes */ 2184 ex = (void *)rw_image + ((void *)ex - (void *)image); 2185 2186 ex->insn = delta; 2187 2188 ex->data = EX_TYPE_BPF; 2189 2190 /* 2191 * src_reg/dst_reg holds the address in the arena region with upper 2192 * 32-bits being zero because of a preceding addr_space_cast(r<n>, 2193 * 0x0, 0x1) instruction. This address is adjusted with the addition 2194 * of arena_vm_start (see the implementation of BPF_PROBE_MEM32 and 2195 * BPF_PROBE_ATOMIC) before being used for the memory access. Pass 2196 * the reg holding the unmodified 32-bit address to 2197 * ex_handler_bpf(). 2198 */ 2199 if (BPF_CLASS(insn->code) == BPF_LDX) { 2200 arena_reg = reg2pt_regs[src_reg]; 2201 fixup_reg = reg2pt_regs[dst_reg]; 2202 } else { 2203 arena_reg = reg2pt_regs[dst_reg]; 2204 fixup_reg = DONT_CLEAR; 2205 } 2206 2207 ex->fixup = FIELD_PREP(FIXUP_INSN_LEN_MASK, prog - start_of_ldx) | 2208 FIELD_PREP(FIXUP_ARENA_REG_MASK, arena_reg) | 2209 FIELD_PREP(FIXUP_REG_MASK, fixup_reg); 2210 ex->fixup |= FIXUP_ARENA_ACCESS; 2211 2212 ex->data |= FIELD_PREP(DATA_ARENA_OFFSET_MASK, insn->off); 2213 } 2214 break; 2215 2216 /* LDX: dst_reg = *(u8*)(src_reg + off) */ 2217 case BPF_LDX | BPF_MEM | BPF_B: 2218 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 2219 case BPF_LDX | BPF_MEM | BPF_H: 2220 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 2221 case BPF_LDX | BPF_MEM | BPF_W: 2222 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 2223 case BPF_LDX | BPF_MEM | BPF_DW: 2224 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 2225 /* LDXS: dst_reg = *(s8*)(src_reg + off) */ 2226 case BPF_LDX | BPF_MEMSX | BPF_B: 2227 case BPF_LDX | BPF_MEMSX | BPF_H: 2228 case BPF_LDX | BPF_MEMSX | BPF_W: 2229 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B: 2230 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H: 2231 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W: 2232 insn_off = insn->off; 2233 2234 if (BPF_MODE(insn->code) == BPF_PROBE_MEM || 2235 BPF_MODE(insn->code) == BPF_PROBE_MEMSX) { 2236 /* Conservatively check that src_reg + insn->off is a kernel address: 2237 * src_reg + insn->off > TASK_SIZE_MAX + PAGE_SIZE 2238 * and 2239 * src_reg + insn->off < VSYSCALL_ADDR 2240 */ 2241 2242 u64 limit = TASK_SIZE_MAX + PAGE_SIZE - VSYSCALL_ADDR; 2243 u8 *end_of_jmp; 2244 2245 /* movabsq r10, VSYSCALL_ADDR */ 2246 emit_mov_imm64(&prog, BPF_REG_AX, (long)VSYSCALL_ADDR >> 32, 2247 (u32)(long)VSYSCALL_ADDR); 2248 2249 /* mov src_reg, r11 */ 2250 EMIT_mov(AUX_REG, src_reg); 2251 2252 if (insn->off) { 2253 /* add r11, insn->off */ 2254 maybe_emit_1mod(&prog, AUX_REG, true); 2255 EMIT2_off32(0x81, add_1reg(0xC0, AUX_REG), insn->off); 2256 } 2257 2258 /* sub r11, r10 */ 2259 maybe_emit_mod(&prog, AUX_REG, BPF_REG_AX, true); 2260 EMIT2(0x29, add_2reg(0xC0, AUX_REG, BPF_REG_AX)); 2261 2262 /* movabsq r10, limit */ 2263 emit_mov_imm64(&prog, BPF_REG_AX, (long)limit >> 32, 2264 (u32)(long)limit); 2265 2266 /* cmp r10, r11 */ 2267 maybe_emit_mod(&prog, AUX_REG, BPF_REG_AX, true); 2268 EMIT2(0x39, add_2reg(0xC0, AUX_REG, BPF_REG_AX)); 2269 2270 /* if unsigned '>', goto load */ 2271 EMIT2(X86_JA, 0); 2272 end_of_jmp = prog; 2273 2274 /* xor dst_reg, dst_reg */ 2275 emit_mov_imm32(&prog, false, dst_reg, 0); 2276 /* jmp byte_after_ldx */ 2277 EMIT2(0xEB, 0); 2278 2279 /* populate jmp_offset for JAE above to jump to start_of_ldx */ 2280 start_of_ldx = prog; 2281 end_of_jmp[-1] = start_of_ldx - end_of_jmp; 2282 } 2283 if (BPF_MODE(insn->code) == BPF_PROBE_MEMSX || 2284 BPF_MODE(insn->code) == BPF_MEMSX) 2285 emit_ldsx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off); 2286 else 2287 emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off); 2288 if (BPF_MODE(insn->code) == BPF_PROBE_MEM || 2289 BPF_MODE(insn->code) == BPF_PROBE_MEMSX) { 2290 struct exception_table_entry *ex; 2291 u8 *_insn = image + proglen + (start_of_ldx - temp); 2292 s64 delta; 2293 2294 /* populate jmp_offset for JMP above */ 2295 start_of_ldx[-1] = prog - start_of_ldx; 2296 2297 if (!bpf_prog->aux->extable) 2298 break; 2299 2300 if (excnt >= bpf_prog->aux->num_exentries) { 2301 pr_err("ex gen bug\n"); 2302 return -EFAULT; 2303 } 2304 ex = &bpf_prog->aux->extable[excnt++]; 2305 2306 delta = _insn - (u8 *)&ex->insn; 2307 if (!is_simm32(delta)) { 2308 pr_err("extable->insn doesn't fit into 32-bit\n"); 2309 return -EFAULT; 2310 } 2311 /* switch ex to rw buffer for writes */ 2312 ex = (void *)rw_image + ((void *)ex - (void *)image); 2313 2314 ex->insn = delta; 2315 2316 ex->data = EX_TYPE_BPF; 2317 2318 if (dst_reg > BPF_REG_9) { 2319 pr_err("verifier error\n"); 2320 return -EFAULT; 2321 } 2322 /* 2323 * Compute size of x86 insn and its target dest x86 register. 2324 * ex_handler_bpf() will use lower 8 bits to adjust 2325 * pt_regs->ip to jump over this x86 instruction 2326 * and upper bits to figure out which pt_regs to zero out. 2327 * End result: x86 insn "mov rbx, qword ptr [rax+0x14]" 2328 * of 4 bytes will be ignored and rbx will be zero inited. 2329 */ 2330 ex->fixup = FIELD_PREP(FIXUP_INSN_LEN_MASK, prog - start_of_ldx) | 2331 FIELD_PREP(FIXUP_REG_MASK, reg2pt_regs[dst_reg]); 2332 } 2333 break; 2334 2335 case BPF_STX | BPF_ATOMIC | BPF_B: 2336 case BPF_STX | BPF_ATOMIC | BPF_H: 2337 if (!bpf_atomic_is_load_store(insn)) { 2338 pr_err("bpf_jit: 1- and 2-byte RMW atomics are not supported\n"); 2339 return -EFAULT; 2340 } 2341 fallthrough; 2342 case BPF_STX | BPF_ATOMIC | BPF_W: 2343 case BPF_STX | BPF_ATOMIC | BPF_DW: 2344 if (insn->imm == (BPF_AND | BPF_FETCH) || 2345 insn->imm == (BPF_OR | BPF_FETCH) || 2346 insn->imm == (BPF_XOR | BPF_FETCH)) { 2347 bool is64 = BPF_SIZE(insn->code) == BPF_DW; 2348 u32 real_src_reg = src_reg; 2349 u32 real_dst_reg = dst_reg; 2350 u8 *branch_target; 2351 2352 /* 2353 * Can't be implemented with a single x86 insn. 2354 * Need to do a CMPXCHG loop. 2355 */ 2356 2357 /* Will need RAX as a CMPXCHG operand so save R0 */ 2358 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0); 2359 if (src_reg == BPF_REG_0) 2360 real_src_reg = BPF_REG_AX; 2361 if (dst_reg == BPF_REG_0) 2362 real_dst_reg = BPF_REG_AX; 2363 2364 branch_target = prog; 2365 /* Load old value */ 2366 emit_ldx(&prog, BPF_SIZE(insn->code), 2367 BPF_REG_0, real_dst_reg, insn->off); 2368 /* 2369 * Perform the (commutative) operation locally, 2370 * put the result in the AUX_REG. 2371 */ 2372 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0); 2373 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64); 2374 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)], 2375 add_2reg(0xC0, AUX_REG, real_src_reg)); 2376 /* Attempt to swap in new value */ 2377 err = emit_atomic_rmw(&prog, BPF_CMPXCHG, 2378 real_dst_reg, AUX_REG, 2379 insn->off, 2380 BPF_SIZE(insn->code)); 2381 if (WARN_ON(err)) 2382 return err; 2383 /* 2384 * ZF tells us whether we won the race. If it's 2385 * cleared we need to try again. 2386 */ 2387 EMIT2(X86_JNE, -(prog - branch_target) - 2); 2388 /* Return the pre-modification value */ 2389 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0); 2390 /* Restore R0 after clobbering RAX */ 2391 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX); 2392 break; 2393 } 2394 2395 if (bpf_atomic_is_load_store(insn)) 2396 err = emit_atomic_ld_st(&prog, insn->imm, dst_reg, src_reg, 2397 insn->off, BPF_SIZE(insn->code)); 2398 else 2399 err = emit_atomic_rmw(&prog, insn->imm, dst_reg, src_reg, 2400 insn->off, BPF_SIZE(insn->code)); 2401 if (err) 2402 return err; 2403 break; 2404 2405 case BPF_STX | BPF_PROBE_ATOMIC | BPF_B: 2406 case BPF_STX | BPF_PROBE_ATOMIC | BPF_H: 2407 if (!bpf_atomic_is_load_store(insn)) { 2408 pr_err("bpf_jit: 1- and 2-byte RMW atomics are not supported\n"); 2409 return -EFAULT; 2410 } 2411 fallthrough; 2412 case BPF_STX | BPF_PROBE_ATOMIC | BPF_W: 2413 case BPF_STX | BPF_PROBE_ATOMIC | BPF_DW: 2414 start_of_ldx = prog; 2415 2416 if (bpf_atomic_is_load_store(insn)) 2417 err = emit_atomic_ld_st_index(&prog, insn->imm, 2418 BPF_SIZE(insn->code), dst_reg, 2419 src_reg, X86_REG_R12, insn->off); 2420 else 2421 err = emit_atomic_rmw_index(&prog, insn->imm, BPF_SIZE(insn->code), 2422 dst_reg, src_reg, X86_REG_R12, 2423 insn->off); 2424 if (err) 2425 return err; 2426 goto populate_extable; 2427 2428 /* call */ 2429 case BPF_JMP | BPF_CALL: { 2430 u8 *ip = image + addrs[i - 1]; 2431 2432 func = (u8 *) __bpf_call_base + imm32; 2433 if (src_reg == BPF_PSEUDO_CALL && tail_call_reachable) { 2434 LOAD_TAIL_CALL_CNT_PTR(stack_depth); 2435 ip += 7; 2436 } 2437 if (!imm32) 2438 return -EINVAL; 2439 if (priv_frame_ptr) { 2440 push_r9(&prog); 2441 ip += 2; 2442 } 2443 ip += x86_call_depth_emit_accounting(&prog, func, ip); 2444 if (emit_call(&prog, func, ip)) 2445 return -EINVAL; 2446 if (priv_frame_ptr) 2447 pop_r9(&prog); 2448 break; 2449 } 2450 2451 case BPF_JMP | BPF_TAIL_CALL: 2452 if (imm32) 2453 emit_bpf_tail_call_direct(bpf_prog, 2454 &bpf_prog->aux->poke_tab[imm32 - 1], 2455 &prog, image + addrs[i - 1], 2456 callee_regs_used, 2457 stack_depth, 2458 ctx); 2459 else 2460 emit_bpf_tail_call_indirect(bpf_prog, 2461 &prog, 2462 callee_regs_used, 2463 stack_depth, 2464 image + addrs[i - 1], 2465 ctx); 2466 break; 2467 2468 /* cond jump */ 2469 case BPF_JMP | BPF_JEQ | BPF_X: 2470 case BPF_JMP | BPF_JNE | BPF_X: 2471 case BPF_JMP | BPF_JGT | BPF_X: 2472 case BPF_JMP | BPF_JLT | BPF_X: 2473 case BPF_JMP | BPF_JGE | BPF_X: 2474 case BPF_JMP | BPF_JLE | BPF_X: 2475 case BPF_JMP | BPF_JSGT | BPF_X: 2476 case BPF_JMP | BPF_JSLT | BPF_X: 2477 case BPF_JMP | BPF_JSGE | BPF_X: 2478 case BPF_JMP | BPF_JSLE | BPF_X: 2479 case BPF_JMP32 | BPF_JEQ | BPF_X: 2480 case BPF_JMP32 | BPF_JNE | BPF_X: 2481 case BPF_JMP32 | BPF_JGT | BPF_X: 2482 case BPF_JMP32 | BPF_JLT | BPF_X: 2483 case BPF_JMP32 | BPF_JGE | BPF_X: 2484 case BPF_JMP32 | BPF_JLE | BPF_X: 2485 case BPF_JMP32 | BPF_JSGT | BPF_X: 2486 case BPF_JMP32 | BPF_JSLT | BPF_X: 2487 case BPF_JMP32 | BPF_JSGE | BPF_X: 2488 case BPF_JMP32 | BPF_JSLE | BPF_X: 2489 /* cmp dst_reg, src_reg */ 2490 maybe_emit_mod(&prog, dst_reg, src_reg, 2491 BPF_CLASS(insn->code) == BPF_JMP); 2492 EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg)); 2493 goto emit_cond_jmp; 2494 2495 case BPF_JMP | BPF_JSET | BPF_X: 2496 case BPF_JMP32 | BPF_JSET | BPF_X: 2497 /* test dst_reg, src_reg */ 2498 maybe_emit_mod(&prog, dst_reg, src_reg, 2499 BPF_CLASS(insn->code) == BPF_JMP); 2500 EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg)); 2501 goto emit_cond_jmp; 2502 2503 case BPF_JMP | BPF_JSET | BPF_K: 2504 case BPF_JMP32 | BPF_JSET | BPF_K: 2505 /* test dst_reg, imm32 */ 2506 maybe_emit_1mod(&prog, dst_reg, 2507 BPF_CLASS(insn->code) == BPF_JMP); 2508 EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32); 2509 goto emit_cond_jmp; 2510 2511 case BPF_JMP | BPF_JEQ | BPF_K: 2512 case BPF_JMP | BPF_JNE | BPF_K: 2513 case BPF_JMP | BPF_JGT | BPF_K: 2514 case BPF_JMP | BPF_JLT | BPF_K: 2515 case BPF_JMP | BPF_JGE | BPF_K: 2516 case BPF_JMP | BPF_JLE | BPF_K: 2517 case BPF_JMP | BPF_JSGT | BPF_K: 2518 case BPF_JMP | BPF_JSLT | BPF_K: 2519 case BPF_JMP | BPF_JSGE | BPF_K: 2520 case BPF_JMP | BPF_JSLE | BPF_K: 2521 case BPF_JMP32 | BPF_JEQ | BPF_K: 2522 case BPF_JMP32 | BPF_JNE | BPF_K: 2523 case BPF_JMP32 | BPF_JGT | BPF_K: 2524 case BPF_JMP32 | BPF_JLT | BPF_K: 2525 case BPF_JMP32 | BPF_JGE | BPF_K: 2526 case BPF_JMP32 | BPF_JLE | BPF_K: 2527 case BPF_JMP32 | BPF_JSGT | BPF_K: 2528 case BPF_JMP32 | BPF_JSLT | BPF_K: 2529 case BPF_JMP32 | BPF_JSGE | BPF_K: 2530 case BPF_JMP32 | BPF_JSLE | BPF_K: 2531 /* test dst_reg, dst_reg to save one extra byte */ 2532 if (imm32 == 0) { 2533 maybe_emit_mod(&prog, dst_reg, dst_reg, 2534 BPF_CLASS(insn->code) == BPF_JMP); 2535 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg)); 2536 goto emit_cond_jmp; 2537 } 2538 2539 /* cmp dst_reg, imm8/32 */ 2540 maybe_emit_1mod(&prog, dst_reg, 2541 BPF_CLASS(insn->code) == BPF_JMP); 2542 2543 if (is_imm8(imm32)) 2544 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32); 2545 else 2546 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32); 2547 2548emit_cond_jmp: /* Convert BPF opcode to x86 */ 2549 switch (BPF_OP(insn->code)) { 2550 case BPF_JEQ: 2551 jmp_cond = X86_JE; 2552 break; 2553 case BPF_JSET: 2554 case BPF_JNE: 2555 jmp_cond = X86_JNE; 2556 break; 2557 case BPF_JGT: 2558 /* GT is unsigned '>', JA in x86 */ 2559 jmp_cond = X86_JA; 2560 break; 2561 case BPF_JLT: 2562 /* LT is unsigned '<', JB in x86 */ 2563 jmp_cond = X86_JB; 2564 break; 2565 case BPF_JGE: 2566 /* GE is unsigned '>=', JAE in x86 */ 2567 jmp_cond = X86_JAE; 2568 break; 2569 case BPF_JLE: 2570 /* LE is unsigned '<=', JBE in x86 */ 2571 jmp_cond = X86_JBE; 2572 break; 2573 case BPF_JSGT: 2574 /* Signed '>', GT in x86 */ 2575 jmp_cond = X86_JG; 2576 break; 2577 case BPF_JSLT: 2578 /* Signed '<', LT in x86 */ 2579 jmp_cond = X86_JL; 2580 break; 2581 case BPF_JSGE: 2582 /* Signed '>=', GE in x86 */ 2583 jmp_cond = X86_JGE; 2584 break; 2585 case BPF_JSLE: 2586 /* Signed '<=', LE in x86 */ 2587 jmp_cond = X86_JLE; 2588 break; 2589 default: /* to silence GCC warning */ 2590 return -EFAULT; 2591 } 2592 jmp_offset = addrs[i + insn->off] - addrs[i]; 2593 if (is_imm8_jmp_offset(jmp_offset)) { 2594 if (jmp_padding) { 2595 /* To keep the jmp_offset valid, the extra bytes are 2596 * padded before the jump insn, so we subtract the 2597 * 2 bytes of jmp_cond insn from INSN_SZ_DIFF. 2598 * 2599 * If the previous pass already emits an imm8 2600 * jmp_cond, then this BPF insn won't shrink, so 2601 * "nops" is 0. 2602 * 2603 * On the other hand, if the previous pass emits an 2604 * imm32 jmp_cond, the extra 4 bytes(*) is padded to 2605 * keep the image from shrinking further. 2606 * 2607 * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond 2608 * is 2 bytes, so the size difference is 4 bytes. 2609 */ 2610 nops = INSN_SZ_DIFF - 2; 2611 if (nops != 0 && nops != 4) { 2612 pr_err("unexpected jmp_cond padding: %d bytes\n", 2613 nops); 2614 return -EFAULT; 2615 } 2616 emit_nops(&prog, nops); 2617 } 2618 EMIT2(jmp_cond, jmp_offset); 2619 } else if (is_simm32(jmp_offset)) { 2620 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset); 2621 } else { 2622 pr_err("cond_jmp gen bug %llx\n", jmp_offset); 2623 return -EFAULT; 2624 } 2625 2626 break; 2627 2628 case BPF_JMP | BPF_JA | BPF_X: 2629 emit_indirect_jump(&prog, insn->dst_reg, image + addrs[i - 1]); 2630 break; 2631 case BPF_JMP | BPF_JA: 2632 case BPF_JMP32 | BPF_JA: 2633 if (BPF_CLASS(insn->code) == BPF_JMP) { 2634 if (insn->off == -1) 2635 /* -1 jmp instructions will always jump 2636 * backwards two bytes. Explicitly handling 2637 * this case avoids wasting too many passes 2638 * when there are long sequences of replaced 2639 * dead code. 2640 */ 2641 jmp_offset = -2; 2642 else 2643 jmp_offset = addrs[i + insn->off] - addrs[i]; 2644 } else { 2645 if (insn->imm == -1) 2646 jmp_offset = -2; 2647 else 2648 jmp_offset = addrs[i + insn->imm] - addrs[i]; 2649 } 2650 2651 if (!jmp_offset) { 2652 /* 2653 * If jmp_padding is enabled, the extra nops will 2654 * be inserted. Otherwise, optimize out nop jumps. 2655 */ 2656 if (jmp_padding) { 2657 /* There are 3 possible conditions. 2658 * (1) This BPF_JA is already optimized out in 2659 * the previous run, so there is no need 2660 * to pad any extra byte (0 byte). 2661 * (2) The previous pass emits an imm8 jmp, 2662 * so we pad 2 bytes to match the previous 2663 * insn size. 2664 * (3) Similarly, the previous pass emits an 2665 * imm32 jmp, and 5 bytes is padded. 2666 */ 2667 nops = INSN_SZ_DIFF; 2668 if (nops != 0 && nops != 2 && nops != 5) { 2669 pr_err("unexpected nop jump padding: %d bytes\n", 2670 nops); 2671 return -EFAULT; 2672 } 2673 emit_nops(&prog, nops); 2674 } 2675 break; 2676 } 2677emit_jmp: 2678 if (is_imm8_jmp_offset(jmp_offset)) { 2679 if (jmp_padding) { 2680 /* To avoid breaking jmp_offset, the extra bytes 2681 * are padded before the actual jmp insn, so 2682 * 2 bytes is subtracted from INSN_SZ_DIFF. 2683 * 2684 * If the previous pass already emits an imm8 2685 * jmp, there is nothing to pad (0 byte). 2686 * 2687 * If it emits an imm32 jmp (5 bytes) previously 2688 * and now an imm8 jmp (2 bytes), then we pad 2689 * (5 - 2 = 3) bytes to stop the image from 2690 * shrinking further. 2691 */ 2692 nops = INSN_SZ_DIFF - 2; 2693 if (nops != 0 && nops != 3) { 2694 pr_err("unexpected jump padding: %d bytes\n", 2695 nops); 2696 return -EFAULT; 2697 } 2698 emit_nops(&prog, INSN_SZ_DIFF - 2); 2699 } 2700 EMIT2(0xEB, jmp_offset); 2701 } else if (is_simm32(jmp_offset)) { 2702 EMIT1_off32(0xE9, jmp_offset); 2703 } else { 2704 pr_err("jmp gen bug %llx\n", jmp_offset); 2705 return -EFAULT; 2706 } 2707 break; 2708 2709 case BPF_JMP | BPF_EXIT: 2710 if (seen_exit) { 2711 jmp_offset = ctx->cleanup_addr - addrs[i]; 2712 goto emit_jmp; 2713 } 2714 seen_exit = true; 2715 /* Update cleanup_addr */ 2716 ctx->cleanup_addr = proglen; 2717 if (bpf_prog_was_classic(bpf_prog) && 2718 !ns_capable_noaudit(&init_user_ns, CAP_SYS_ADMIN)) { 2719 u8 *ip = image + addrs[i - 1]; 2720 2721 if (emit_spectre_bhb_barrier(&prog, ip, bpf_prog)) 2722 return -EINVAL; 2723 } 2724 if (bpf_prog->aux->exception_boundary) { 2725 pop_callee_regs(&prog, all_callee_regs_used); 2726 pop_r12(&prog); 2727 } else { 2728 pop_callee_regs(&prog, callee_regs_used); 2729 if (arena_vm_start) 2730 pop_r12(&prog); 2731 } 2732 EMIT1(0xC9); /* leave */ 2733 bpf_prog->aux->ksym.fp_end = prog - temp; 2734 2735 emit_return(&prog, image + addrs[i - 1] + (prog - temp)); 2736 break; 2737 2738 default: 2739 /* 2740 * By design x86-64 JIT should support all BPF instructions. 2741 * This error will be seen if new instruction was added 2742 * to the interpreter, but not to the JIT, or if there is 2743 * junk in bpf_prog. 2744 */ 2745 pr_err("bpf_jit: unknown opcode %02x\n", insn->code); 2746 return -EINVAL; 2747 } 2748 2749 ilen = prog - temp; 2750 if (ilen > BPF_MAX_INSN_SIZE) { 2751 pr_err("bpf_jit: fatal insn size error\n"); 2752 return -EFAULT; 2753 } 2754 2755 if (image) { 2756 /* 2757 * When populating the image, assert that: 2758 * 2759 * i) We do not write beyond the allocated space, and 2760 * ii) addrs[i] did not change from the prior run, in order 2761 * to validate assumptions made for computing branch 2762 * displacements. 2763 */ 2764 if (unlikely(proglen + ilen > oldproglen || 2765 proglen + ilen != addrs[i])) { 2766 pr_err("bpf_jit: fatal error\n"); 2767 return -EFAULT; 2768 } 2769 memcpy(rw_image + proglen, temp, ilen); 2770 } 2771 proglen += ilen; 2772 addrs[i] = proglen; 2773 prog = temp; 2774 } 2775 2776 if (image && excnt != bpf_prog->aux->num_exentries) { 2777 pr_err("extable is not populated\n"); 2778 return -EFAULT; 2779 } 2780 return proglen; 2781} 2782 2783static void clean_stack_garbage(const struct btf_func_model *m, 2784 u8 **pprog, int nr_stack_slots, 2785 int stack_size) 2786{ 2787 int arg_size, off; 2788 u8 *prog; 2789 2790 /* Generally speaking, the compiler will pass the arguments 2791 * on-stack with "push" instruction, which will take 8-byte 2792 * on the stack. In this case, there won't be garbage values 2793 * while we copy the arguments from origin stack frame to current 2794 * in BPF_DW. 2795 * 2796 * However, sometimes the compiler will only allocate 4-byte on 2797 * the stack for the arguments. For now, this case will only 2798 * happen if there is only one argument on-stack and its size 2799 * not more than 4 byte. In this case, there will be garbage 2800 * values on the upper 4-byte where we store the argument on 2801 * current stack frame. 2802 * 2803 * arguments on origin stack: 2804 * 2805 * stack_arg_1(4-byte) xxx(4-byte) 2806 * 2807 * what we copy: 2808 * 2809 * stack_arg_1(8-byte): stack_arg_1(origin) xxx 2810 * 2811 * and the xxx is the garbage values which we should clean here. 2812 */ 2813 if (nr_stack_slots != 1) 2814 return; 2815 2816 /* the size of the last argument */ 2817 arg_size = m->arg_size[m->nr_args - 1]; 2818 if (arg_size <= 4) { 2819 off = -(stack_size - 4); 2820 prog = *pprog; 2821 /* mov DWORD PTR [rbp + off], 0 */ 2822 if (!is_imm8(off)) 2823 EMIT2_off32(0xC7, 0x85, off); 2824 else 2825 EMIT3(0xC7, 0x45, off); 2826 EMIT(0, 4); 2827 *pprog = prog; 2828 } 2829} 2830 2831/* get the count of the regs that are used to pass arguments */ 2832static int get_nr_used_regs(const struct btf_func_model *m) 2833{ 2834 int i, arg_regs, nr_used_regs = 0; 2835 2836 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) { 2837 arg_regs = (m->arg_size[i] + 7) / 8; 2838 if (nr_used_regs + arg_regs <= 6) 2839 nr_used_regs += arg_regs; 2840 2841 if (nr_used_regs >= 6) 2842 break; 2843 } 2844 2845 return nr_used_regs; 2846} 2847 2848static void save_args(const struct btf_func_model *m, u8 **prog, 2849 int stack_size, bool for_call_origin, u32 flags) 2850{ 2851 int arg_regs, first_off = 0, nr_regs = 0, nr_stack_slots = 0; 2852 bool use_jmp = bpf_trampoline_use_jmp(flags); 2853 int i, j; 2854 2855 /* Store function arguments to stack. 2856 * For a function that accepts two pointers the sequence will be: 2857 * mov QWORD PTR [rbp-0x10],rdi 2858 * mov QWORD PTR [rbp-0x8],rsi 2859 */ 2860 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) { 2861 arg_regs = (m->arg_size[i] + 7) / 8; 2862 2863 /* According to the research of Yonghong, struct members 2864 * should be all in register or all on the stack. 2865 * Meanwhile, the compiler will pass the argument on regs 2866 * if the remaining regs can hold the argument. 2867 * 2868 * Disorder of the args can happen. For example: 2869 * 2870 * struct foo_struct { 2871 * long a; 2872 * int b; 2873 * }; 2874 * int foo(char, char, char, char, char, struct foo_struct, 2875 * char); 2876 * 2877 * the arg1-5,arg7 will be passed by regs, and arg6 will 2878 * by stack. 2879 */ 2880 if (nr_regs + arg_regs > 6) { 2881 /* copy function arguments from origin stack frame 2882 * into current stack frame. 2883 * 2884 * The starting address of the arguments on-stack 2885 * is: 2886 * rbp + 8(push rbp) + 2887 * 8(return addr of origin call) + 2888 * 8(return addr of the caller) 2889 * which means: rbp + 24 2890 */ 2891 for (j = 0; j < arg_regs; j++) { 2892 emit_ldx(prog, BPF_DW, BPF_REG_0, BPF_REG_FP, 2893 nr_stack_slots * 8 + 16 + (!use_jmp) * 8); 2894 emit_stx(prog, BPF_DW, BPF_REG_FP, BPF_REG_0, 2895 -stack_size); 2896 2897 if (!nr_stack_slots) 2898 first_off = stack_size; 2899 stack_size -= 8; 2900 nr_stack_slots++; 2901 } 2902 } else { 2903 /* Only copy the arguments on-stack to current 2904 * 'stack_size' and ignore the regs, used to 2905 * prepare the arguments on-stack for origin call. 2906 */ 2907 if (for_call_origin) { 2908 nr_regs += arg_regs; 2909 continue; 2910 } 2911 2912 /* copy the arguments from regs into stack */ 2913 for (j = 0; j < arg_regs; j++) { 2914 emit_stx(prog, BPF_DW, BPF_REG_FP, 2915 nr_regs == 5 ? X86_REG_R9 : BPF_REG_1 + nr_regs, 2916 -stack_size); 2917 stack_size -= 8; 2918 nr_regs++; 2919 } 2920 } 2921 } 2922 2923 clean_stack_garbage(m, prog, nr_stack_slots, first_off); 2924} 2925 2926static void restore_regs(const struct btf_func_model *m, u8 **prog, 2927 int stack_size) 2928{ 2929 int i, j, arg_regs, nr_regs = 0; 2930 2931 /* Restore function arguments from stack. 2932 * For a function that accepts two pointers the sequence will be: 2933 * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10] 2934 * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8] 2935 * 2936 * The logic here is similar to what we do in save_args() 2937 */ 2938 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) { 2939 arg_regs = (m->arg_size[i] + 7) / 8; 2940 if (nr_regs + arg_regs <= 6) { 2941 for (j = 0; j < arg_regs; j++) { 2942 emit_ldx(prog, BPF_DW, 2943 nr_regs == 5 ? X86_REG_R9 : BPF_REG_1 + nr_regs, 2944 BPF_REG_FP, 2945 -stack_size); 2946 stack_size -= 8; 2947 nr_regs++; 2948 } 2949 } else { 2950 stack_size -= 8 * arg_regs; 2951 } 2952 2953 if (nr_regs >= 6) 2954 break; 2955 } 2956} 2957 2958static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog, 2959 struct bpf_tramp_link *l, int stack_size, 2960 int run_ctx_off, bool save_ret, 2961 void *image, void *rw_image) 2962{ 2963 u8 *prog = *pprog; 2964 u8 *jmp_insn; 2965 int ctx_cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie); 2966 struct bpf_prog *p = l->link.prog; 2967 u64 cookie = l->cookie; 2968 2969 /* mov rdi, cookie */ 2970 emit_mov_imm64(&prog, BPF_REG_1, (long) cookie >> 32, (u32) (long) cookie); 2971 2972 /* Prepare struct bpf_tramp_run_ctx. 2973 * 2974 * bpf_tramp_run_ctx is already preserved by 2975 * arch_prepare_bpf_trampoline(). 2976 * 2977 * mov QWORD PTR [rbp - run_ctx_off + ctx_cookie_off], rdi 2978 */ 2979 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_1, -run_ctx_off + ctx_cookie_off); 2980 2981 /* arg1: mov rdi, progs[i] */ 2982 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p); 2983 /* arg2: lea rsi, [rbp - ctx_cookie_off] */ 2984 if (!is_imm8(-run_ctx_off)) 2985 EMIT3_off32(0x48, 0x8D, 0xB5, -run_ctx_off); 2986 else 2987 EMIT4(0x48, 0x8D, 0x75, -run_ctx_off); 2988 2989 if (emit_rsb_call(&prog, bpf_trampoline_enter(p), image + (prog - (u8 *)rw_image))) 2990 return -EINVAL; 2991 /* remember prog start time returned by __bpf_prog_enter */ 2992 emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0); 2993 2994 /* if (__bpf_prog_enter*(prog) == 0) 2995 * goto skip_exec_of_prog; 2996 */ 2997 EMIT3(0x48, 0x85, 0xC0); /* test rax,rax */ 2998 /* emit 2 nops that will be replaced with JE insn */ 2999 jmp_insn = prog; 3000 emit_nops(&prog, 2); 3001 3002 /* arg1: lea rdi, [rbp - stack_size] */ 3003 if (!is_imm8(-stack_size)) 3004 EMIT3_off32(0x48, 0x8D, 0xBD, -stack_size); 3005 else 3006 EMIT4(0x48, 0x8D, 0x7D, -stack_size); 3007 /* arg2: progs[i]->insnsi for interpreter */ 3008 if (!p->jited) 3009 emit_mov_imm64(&prog, BPF_REG_2, 3010 (long) p->insnsi >> 32, 3011 (u32) (long) p->insnsi); 3012 /* call JITed bpf program or interpreter */ 3013 if (emit_rsb_call(&prog, p->bpf_func, image + (prog - (u8 *)rw_image))) 3014 return -EINVAL; 3015 3016 /* 3017 * BPF_TRAMP_MODIFY_RETURN trampolines can modify the return 3018 * of the previous call which is then passed on the stack to 3019 * the next BPF program. 3020 * 3021 * BPF_TRAMP_FENTRY trampoline may need to return the return 3022 * value of BPF_PROG_TYPE_STRUCT_OPS prog. 3023 */ 3024 if (save_ret) 3025 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 3026 3027 /* replace 2 nops with JE insn, since jmp target is known */ 3028 jmp_insn[0] = X86_JE; 3029 jmp_insn[1] = prog - jmp_insn - 2; 3030 3031 /* arg1: mov rdi, progs[i] */ 3032 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p); 3033 /* arg2: mov rsi, rbx <- start time in nsec */ 3034 emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6); 3035 /* arg3: lea rdx, [rbp - run_ctx_off] */ 3036 if (!is_imm8(-run_ctx_off)) 3037 EMIT3_off32(0x48, 0x8D, 0x95, -run_ctx_off); 3038 else 3039 EMIT4(0x48, 0x8D, 0x55, -run_ctx_off); 3040 if (emit_rsb_call(&prog, bpf_trampoline_exit(p), image + (prog - (u8 *)rw_image))) 3041 return -EINVAL; 3042 3043 *pprog = prog; 3044 return 0; 3045} 3046 3047static void emit_align(u8 **pprog, u32 align) 3048{ 3049 u8 *target, *prog = *pprog; 3050 3051 target = PTR_ALIGN(prog, align); 3052 if (target != prog) 3053 emit_nops(&prog, target - prog); 3054 3055 *pprog = prog; 3056} 3057 3058static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond) 3059{ 3060 u8 *prog = *pprog; 3061 s64 offset; 3062 3063 offset = func - (ip + 2 + 4); 3064 if (!is_simm32(offset)) { 3065 pr_err("Target %p is out of range\n", func); 3066 return -EINVAL; 3067 } 3068 EMIT2_off32(0x0F, jmp_cond + 0x10, offset); 3069 *pprog = prog; 3070 return 0; 3071} 3072 3073static int invoke_bpf(const struct btf_func_model *m, u8 **pprog, 3074 struct bpf_tramp_links *tl, int stack_size, 3075 int run_ctx_off, bool save_ret, 3076 void *image, void *rw_image) 3077{ 3078 int i; 3079 u8 *prog = *pprog; 3080 3081 for (i = 0; i < tl->nr_links; i++) { 3082 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, 3083 run_ctx_off, save_ret, image, rw_image)) 3084 return -EINVAL; 3085 } 3086 *pprog = prog; 3087 return 0; 3088} 3089 3090static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog, 3091 struct bpf_tramp_links *tl, int stack_size, 3092 int run_ctx_off, u8 **branches, 3093 void *image, void *rw_image) 3094{ 3095 u8 *prog = *pprog; 3096 int i; 3097 3098 /* The first fmod_ret program will receive a garbage return value. 3099 * Set this to 0 to avoid confusing the program. 3100 */ 3101 emit_mov_imm32(&prog, false, BPF_REG_0, 0); 3102 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 3103 for (i = 0; i < tl->nr_links; i++) { 3104 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, run_ctx_off, true, 3105 image, rw_image)) 3106 return -EINVAL; 3107 3108 /* mod_ret prog stored return value into [rbp - 8]. Emit: 3109 * if (*(u64 *)(rbp - 8) != 0) 3110 * goto do_fexit; 3111 */ 3112 /* cmp QWORD PTR [rbp - 0x8], 0x0 */ 3113 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00); 3114 3115 /* Save the location of the branch and Generate 6 nops 3116 * (4 bytes for an offset and 2 bytes for the jump) These nops 3117 * are replaced with a conditional jump once do_fexit (i.e. the 3118 * start of the fexit invocation) is finalized. 3119 */ 3120 branches[i] = prog; 3121 emit_nops(&prog, 4 + 2); 3122 } 3123 3124 *pprog = prog; 3125 return 0; 3126} 3127 3128/* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */ 3129#define LOAD_TRAMP_TAIL_CALL_CNT_PTR(stack) \ 3130 __LOAD_TCC_PTR(-round_up(stack, 8) - 8) 3131 3132/* Example: 3133 * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev); 3134 * its 'struct btf_func_model' will be nr_args=2 3135 * The assembly code when eth_type_trans is executing after trampoline: 3136 * 3137 * push rbp 3138 * mov rbp, rsp 3139 * sub rsp, 16 // space for skb and dev 3140 * push rbx // temp regs to pass start time 3141 * mov qword ptr [rbp - 16], rdi // save skb pointer to stack 3142 * mov qword ptr [rbp - 8], rsi // save dev pointer to stack 3143 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 3144 * mov rbx, rax // remember start time in bpf stats are enabled 3145 * lea rdi, [rbp - 16] // R1==ctx of bpf prog 3146 * call addr_of_jited_FENTRY_prog 3147 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 3148 * mov rsi, rbx // prog start time 3149 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 3150 * mov rdi, qword ptr [rbp - 16] // restore skb pointer from stack 3151 * mov rsi, qword ptr [rbp - 8] // restore dev pointer from stack 3152 * pop rbx 3153 * leave 3154 * ret 3155 * 3156 * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be 3157 * replaced with 'call generated_bpf_trampoline'. When it returns 3158 * eth_type_trans will continue executing with original skb and dev pointers. 3159 * 3160 * The assembly code when eth_type_trans is called from trampoline: 3161 * 3162 * push rbp 3163 * mov rbp, rsp 3164 * sub rsp, 24 // space for skb, dev, return value 3165 * push rbx // temp regs to pass start time 3166 * mov qword ptr [rbp - 24], rdi // save skb pointer to stack 3167 * mov qword ptr [rbp - 16], rsi // save dev pointer to stack 3168 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 3169 * mov rbx, rax // remember start time if bpf stats are enabled 3170 * lea rdi, [rbp - 24] // R1==ctx of bpf prog 3171 * call addr_of_jited_FENTRY_prog // bpf prog can access skb and dev 3172 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 3173 * mov rsi, rbx // prog start time 3174 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 3175 * mov rdi, qword ptr [rbp - 24] // restore skb pointer from stack 3176 * mov rsi, qword ptr [rbp - 16] // restore dev pointer from stack 3177 * call eth_type_trans+5 // execute body of eth_type_trans 3178 * mov qword ptr [rbp - 8], rax // save return value 3179 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 3180 * mov rbx, rax // remember start time in bpf stats are enabled 3181 * lea rdi, [rbp - 24] // R1==ctx of bpf prog 3182 * call addr_of_jited_FEXIT_prog // bpf prog can access skb, dev, return value 3183 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 3184 * mov rsi, rbx // prog start time 3185 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 3186 * mov rax, qword ptr [rbp - 8] // restore eth_type_trans's return value 3187 * pop rbx 3188 * leave 3189 * add rsp, 8 // skip eth_type_trans's frame 3190 * ret // return to its caller 3191 */ 3192static int __arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *rw_image, 3193 void *rw_image_end, void *image, 3194 const struct btf_func_model *m, u32 flags, 3195 struct bpf_tramp_links *tlinks, 3196 void *func_addr) 3197{ 3198 int i, ret, nr_regs = m->nr_args, stack_size = 0; 3199 int regs_off, nregs_off, ip_off, run_ctx_off, arg_stack_off, rbx_off; 3200 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY]; 3201 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT]; 3202 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN]; 3203 void *orig_call = func_addr; 3204 u8 **branches = NULL; 3205 u8 *prog; 3206 bool save_ret; 3207 3208 /* 3209 * F_INDIRECT is only compatible with F_RET_FENTRY_RET, it is 3210 * explicitly incompatible with F_CALL_ORIG | F_SKIP_FRAME | F_IP_ARG 3211 * because @func_addr. 3212 */ 3213 WARN_ON_ONCE((flags & BPF_TRAMP_F_INDIRECT) && 3214 (flags & ~(BPF_TRAMP_F_INDIRECT | BPF_TRAMP_F_RET_FENTRY_RET))); 3215 3216 /* extra registers for struct arguments */ 3217 for (i = 0; i < m->nr_args; i++) { 3218 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG) 3219 nr_regs += (m->arg_size[i] + 7) / 8 - 1; 3220 } 3221 3222 /* x86-64 supports up to MAX_BPF_FUNC_ARGS arguments. 1-6 3223 * are passed through regs, the remains are through stack. 3224 */ 3225 if (nr_regs > MAX_BPF_FUNC_ARGS) 3226 return -ENOTSUPP; 3227 3228 /* Generated trampoline stack layout: 3229 * 3230 * RBP + 8 [ return address ] 3231 * RBP + 0 [ RBP ] 3232 * 3233 * RBP - 8 [ return value ] BPF_TRAMP_F_CALL_ORIG or 3234 * BPF_TRAMP_F_RET_FENTRY_RET flags 3235 * 3236 * [ reg_argN ] always 3237 * [ ... ] 3238 * RBP - regs_off [ reg_arg1 ] program's ctx pointer 3239 * 3240 * RBP - nregs_off [ regs count ] always 3241 * 3242 * RBP - ip_off [ traced function ] BPF_TRAMP_F_IP_ARG flag 3243 * 3244 * RBP - rbx_off [ rbx value ] always 3245 * 3246 * RBP - run_ctx_off [ bpf_tramp_run_ctx ] 3247 * 3248 * [ stack_argN ] BPF_TRAMP_F_CALL_ORIG 3249 * [ ... ] 3250 * [ stack_arg2 ] 3251 * RBP - arg_stack_off [ stack_arg1 ] 3252 * RSP [ tail_call_cnt_ptr ] BPF_TRAMP_F_TAIL_CALL_CTX 3253 */ 3254 3255 /* room for return value of orig_call or fentry prog */ 3256 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET); 3257 if (save_ret) 3258 stack_size += 8; 3259 3260 stack_size += nr_regs * 8; 3261 regs_off = stack_size; 3262 3263 /* regs count */ 3264 stack_size += 8; 3265 nregs_off = stack_size; 3266 3267 if (flags & BPF_TRAMP_F_IP_ARG) 3268 stack_size += 8; /* room for IP address argument */ 3269 3270 ip_off = stack_size; 3271 3272 stack_size += 8; 3273 rbx_off = stack_size; 3274 3275 stack_size += (sizeof(struct bpf_tramp_run_ctx) + 7) & ~0x7; 3276 run_ctx_off = stack_size; 3277 3278 if (nr_regs > 6 && (flags & BPF_TRAMP_F_CALL_ORIG)) { 3279 /* the space that used to pass arguments on-stack */ 3280 stack_size += (nr_regs - get_nr_used_regs(m)) * 8; 3281 /* make sure the stack pointer is 16-byte aligned if we 3282 * need pass arguments on stack, which means 3283 * [stack_size + 8(rbp) + 8(rip) + 8(origin rip)] 3284 * should be 16-byte aligned. Following code depend on 3285 * that stack_size is already 8-byte aligned. 3286 */ 3287 if (bpf_trampoline_use_jmp(flags)) { 3288 /* no rip in the "jmp" case */ 3289 stack_size += (stack_size % 16) ? 8 : 0; 3290 } else { 3291 stack_size += (stack_size % 16) ? 0 : 8; 3292 } 3293 } 3294 3295 arg_stack_off = stack_size; 3296 3297 if (flags & BPF_TRAMP_F_CALL_ORIG) { 3298 /* skip patched call instruction and point orig_call to actual 3299 * body of the kernel function. 3300 */ 3301 if (is_endbr(orig_call)) 3302 orig_call += ENDBR_INSN_SIZE; 3303 orig_call += X86_PATCH_SIZE; 3304 } 3305 3306 prog = rw_image; 3307 3308 if (flags & BPF_TRAMP_F_INDIRECT) { 3309 /* 3310 * Indirect call for bpf_struct_ops 3311 */ 3312 emit_cfi(&prog, image, 3313 cfi_get_func_hash(func_addr), 3314 cfi_get_func_arity(func_addr)); 3315 } else { 3316 /* 3317 * Direct-call fentry stub, as such it needs accounting for the 3318 * __fentry__ call. 3319 */ 3320 x86_call_depth_emit_accounting(&prog, NULL, image); 3321 } 3322 EMIT1(0x55); /* push rbp */ 3323 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */ 3324 if (im) 3325 im->ksym.fp_start = prog - (u8 *)rw_image; 3326 3327 if (!is_imm8(stack_size)) { 3328 /* sub rsp, stack_size */ 3329 EMIT3_off32(0x48, 0x81, 0xEC, stack_size); 3330 } else { 3331 /* sub rsp, stack_size */ 3332 EMIT4(0x48, 0x83, 0xEC, stack_size); 3333 } 3334 if (flags & BPF_TRAMP_F_TAIL_CALL_CTX) 3335 EMIT1(0x50); /* push rax */ 3336 /* mov QWORD PTR [rbp - rbx_off], rbx */ 3337 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_6, -rbx_off); 3338 3339 /* Store number of argument registers of the traced function: 3340 * mov rax, nr_regs 3341 * mov QWORD PTR [rbp - nregs_off], rax 3342 */ 3343 emit_mov_imm64(&prog, BPF_REG_0, 0, (u32) nr_regs); 3344 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -nregs_off); 3345 3346 if (flags & BPF_TRAMP_F_IP_ARG) { 3347 /* Store IP address of the traced function: 3348 * movabsq rax, func_addr 3349 * mov QWORD PTR [rbp - ip_off], rax 3350 */ 3351 emit_mov_imm64(&prog, BPF_REG_0, (long) func_addr >> 32, (u32) (long) func_addr); 3352 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -ip_off); 3353 } 3354 3355 save_args(m, &prog, regs_off, false, flags); 3356 3357 if (flags & BPF_TRAMP_F_CALL_ORIG) { 3358 /* arg1: mov rdi, im */ 3359 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im); 3360 if (emit_rsb_call(&prog, __bpf_tramp_enter, 3361 image + (prog - (u8 *)rw_image))) { 3362 ret = -EINVAL; 3363 goto cleanup; 3364 } 3365 } 3366 3367 if (fentry->nr_links) { 3368 if (invoke_bpf(m, &prog, fentry, regs_off, run_ctx_off, 3369 flags & BPF_TRAMP_F_RET_FENTRY_RET, image, rw_image)) 3370 return -EINVAL; 3371 } 3372 3373 if (fmod_ret->nr_links) { 3374 branches = kcalloc(fmod_ret->nr_links, sizeof(u8 *), 3375 GFP_KERNEL); 3376 if (!branches) 3377 return -ENOMEM; 3378 3379 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, regs_off, 3380 run_ctx_off, branches, image, rw_image)) { 3381 ret = -EINVAL; 3382 goto cleanup; 3383 } 3384 } 3385 3386 if (flags & BPF_TRAMP_F_CALL_ORIG) { 3387 restore_regs(m, &prog, regs_off); 3388 save_args(m, &prog, arg_stack_off, true, flags); 3389 3390 if (flags & BPF_TRAMP_F_TAIL_CALL_CTX) { 3391 /* Before calling the original function, load the 3392 * tail_call_cnt_ptr from stack to rax. 3393 */ 3394 LOAD_TRAMP_TAIL_CALL_CNT_PTR(stack_size); 3395 } 3396 3397 if (flags & BPF_TRAMP_F_ORIG_STACK) { 3398 emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, 8); 3399 EMIT2(0xff, 0xd3); /* call *rbx */ 3400 } else { 3401 /* call original function */ 3402 if (emit_rsb_call(&prog, orig_call, image + (prog - (u8 *)rw_image))) { 3403 ret = -EINVAL; 3404 goto cleanup; 3405 } 3406 } 3407 /* remember return value in a stack for bpf prog to access */ 3408 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 3409 im->ip_after_call = image + (prog - (u8 *)rw_image); 3410 emit_nops(&prog, X86_PATCH_SIZE); 3411 } 3412 3413 if (fmod_ret->nr_links) { 3414 /* From Intel 64 and IA-32 Architectures Optimization 3415 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler 3416 * Coding Rule 11: All branch targets should be 16-byte 3417 * aligned. 3418 */ 3419 emit_align(&prog, 16); 3420 /* Update the branches saved in invoke_bpf_mod_ret with the 3421 * aligned address of do_fexit. 3422 */ 3423 for (i = 0; i < fmod_ret->nr_links; i++) { 3424 emit_cond_near_jump(&branches[i], image + (prog - (u8 *)rw_image), 3425 image + (branches[i] - (u8 *)rw_image), X86_JNE); 3426 } 3427 } 3428 3429 if (fexit->nr_links) { 3430 if (invoke_bpf(m, &prog, fexit, regs_off, run_ctx_off, 3431 false, image, rw_image)) { 3432 ret = -EINVAL; 3433 goto cleanup; 3434 } 3435 } 3436 3437 if (flags & BPF_TRAMP_F_RESTORE_REGS) 3438 restore_regs(m, &prog, regs_off); 3439 3440 /* This needs to be done regardless. If there were fmod_ret programs, 3441 * the return value is only updated on the stack and still needs to be 3442 * restored to R0. 3443 */ 3444 if (flags & BPF_TRAMP_F_CALL_ORIG) { 3445 im->ip_epilogue = image + (prog - (u8 *)rw_image); 3446 /* arg1: mov rdi, im */ 3447 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im); 3448 if (emit_rsb_call(&prog, __bpf_tramp_exit, image + (prog - (u8 *)rw_image))) { 3449 ret = -EINVAL; 3450 goto cleanup; 3451 } 3452 } else if (flags & BPF_TRAMP_F_TAIL_CALL_CTX) { 3453 /* Before running the original function, load the 3454 * tail_call_cnt_ptr from stack to rax. 3455 */ 3456 LOAD_TRAMP_TAIL_CALL_CNT_PTR(stack_size); 3457 } 3458 3459 /* restore return value of orig_call or fentry prog back into RAX */ 3460 if (save_ret) 3461 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8); 3462 3463 emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, -rbx_off); 3464 3465 EMIT1(0xC9); /* leave */ 3466 if (im) 3467 im->ksym.fp_end = prog - (u8 *)rw_image; 3468 3469 if (flags & BPF_TRAMP_F_SKIP_FRAME) { 3470 /* skip our return address and return to parent */ 3471 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */ 3472 } 3473 emit_return(&prog, image + (prog - (u8 *)rw_image)); 3474 /* Make sure the trampoline generation logic doesn't overflow */ 3475 if (WARN_ON_ONCE(prog > (u8 *)rw_image_end - BPF_INSN_SAFETY)) { 3476 ret = -EFAULT; 3477 goto cleanup; 3478 } 3479 ret = prog - (u8 *)rw_image + BPF_INSN_SAFETY; 3480 3481cleanup: 3482 kfree(branches); 3483 return ret; 3484} 3485 3486void *arch_alloc_bpf_trampoline(unsigned int size) 3487{ 3488 return bpf_prog_pack_alloc(size, jit_fill_hole); 3489} 3490 3491void arch_free_bpf_trampoline(void *image, unsigned int size) 3492{ 3493 bpf_prog_pack_free(image, size); 3494} 3495 3496int arch_protect_bpf_trampoline(void *image, unsigned int size) 3497{ 3498 return 0; 3499} 3500 3501int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end, 3502 const struct btf_func_model *m, u32 flags, 3503 struct bpf_tramp_links *tlinks, 3504 void *func_addr) 3505{ 3506 void *rw_image, *tmp; 3507 int ret; 3508 u32 size = image_end - image; 3509 3510 /* rw_image doesn't need to be in module memory range, so we can 3511 * use kvmalloc. 3512 */ 3513 rw_image = kvmalloc(size, GFP_KERNEL); 3514 if (!rw_image) 3515 return -ENOMEM; 3516 3517 ret = __arch_prepare_bpf_trampoline(im, rw_image, rw_image + size, image, m, 3518 flags, tlinks, func_addr); 3519 if (ret < 0) 3520 goto out; 3521 3522 tmp = bpf_arch_text_copy(image, rw_image, size); 3523 if (IS_ERR(tmp)) 3524 ret = PTR_ERR(tmp); 3525out: 3526 kvfree(rw_image); 3527 return ret; 3528} 3529 3530int arch_bpf_trampoline_size(const struct btf_func_model *m, u32 flags, 3531 struct bpf_tramp_links *tlinks, void *func_addr) 3532{ 3533 struct bpf_tramp_image im; 3534 void *image; 3535 int ret; 3536 3537 /* Allocate a temporary buffer for __arch_prepare_bpf_trampoline(). 3538 * This will NOT cause fragmentation in direct map, as we do not 3539 * call set_memory_*() on this buffer. 3540 * 3541 * We cannot use kvmalloc here, because we need image to be in 3542 * module memory range. 3543 */ 3544 image = bpf_jit_alloc_exec(PAGE_SIZE); 3545 if (!image) 3546 return -ENOMEM; 3547 3548 ret = __arch_prepare_bpf_trampoline(&im, image, image + PAGE_SIZE, image, 3549 m, flags, tlinks, func_addr); 3550 bpf_jit_free_exec(image); 3551 return ret; 3552} 3553 3554static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs, u8 *image, u8 *buf) 3555{ 3556 u8 *jg_reloc, *prog = *pprog; 3557 int pivot, err, jg_bytes = 1; 3558 s64 jg_offset; 3559 3560 if (a == b) { 3561 /* Leaf node of recursion, i.e. not a range of indices 3562 * anymore. 3563 */ 3564 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */ 3565 if (!is_simm32(progs[a])) 3566 return -1; 3567 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), 3568 progs[a]); 3569 err = emit_cond_near_jump(&prog, /* je func */ 3570 (void *)progs[a], image + (prog - buf), 3571 X86_JE); 3572 if (err) 3573 return err; 3574 3575 emit_indirect_jump(&prog, BPF_REG_3 /* R3 -> rdx */, image + (prog - buf)); 3576 3577 *pprog = prog; 3578 return 0; 3579 } 3580 3581 /* Not a leaf node, so we pivot, and recursively descend into 3582 * the lower and upper ranges. 3583 */ 3584 pivot = (b - a) / 2; 3585 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */ 3586 if (!is_simm32(progs[a + pivot])) 3587 return -1; 3588 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]); 3589 3590 if (pivot > 2) { /* jg upper_part */ 3591 /* Require near jump. */ 3592 jg_bytes = 4; 3593 EMIT2_off32(0x0F, X86_JG + 0x10, 0); 3594 } else { 3595 EMIT2(X86_JG, 0); 3596 } 3597 jg_reloc = prog; 3598 3599 err = emit_bpf_dispatcher(&prog, a, a + pivot, /* emit lower_part */ 3600 progs, image, buf); 3601 if (err) 3602 return err; 3603 3604 /* From Intel 64 and IA-32 Architectures Optimization 3605 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler 3606 * Coding Rule 11: All branch targets should be 16-byte 3607 * aligned. 3608 */ 3609 emit_align(&prog, 16); 3610 jg_offset = prog - jg_reloc; 3611 emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes); 3612 3613 err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */ 3614 b, progs, image, buf); 3615 if (err) 3616 return err; 3617 3618 *pprog = prog; 3619 return 0; 3620} 3621 3622static int cmp_ips(const void *a, const void *b) 3623{ 3624 const s64 *ipa = a; 3625 const s64 *ipb = b; 3626 3627 if (*ipa > *ipb) 3628 return 1; 3629 if (*ipa < *ipb) 3630 return -1; 3631 return 0; 3632} 3633 3634int arch_prepare_bpf_dispatcher(void *image, void *buf, s64 *funcs, int num_funcs) 3635{ 3636 u8 *prog = buf; 3637 3638 sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL); 3639 return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs, image, buf); 3640} 3641 3642static void priv_stack_init_guard(void __percpu *priv_stack_ptr, int alloc_size) 3643{ 3644 int cpu, underflow_idx = (alloc_size - PRIV_STACK_GUARD_SZ) >> 3; 3645 u64 *stack_ptr; 3646 3647 for_each_possible_cpu(cpu) { 3648 stack_ptr = per_cpu_ptr(priv_stack_ptr, cpu); 3649 stack_ptr[0] = PRIV_STACK_GUARD_VAL; 3650 stack_ptr[underflow_idx] = PRIV_STACK_GUARD_VAL; 3651 } 3652} 3653 3654static void priv_stack_check_guard(void __percpu *priv_stack_ptr, int alloc_size, 3655 struct bpf_prog *prog) 3656{ 3657 int cpu, underflow_idx = (alloc_size - PRIV_STACK_GUARD_SZ) >> 3; 3658 u64 *stack_ptr; 3659 3660 for_each_possible_cpu(cpu) { 3661 stack_ptr = per_cpu_ptr(priv_stack_ptr, cpu); 3662 if (stack_ptr[0] != PRIV_STACK_GUARD_VAL || 3663 stack_ptr[underflow_idx] != PRIV_STACK_GUARD_VAL) { 3664 pr_err("BPF private stack overflow/underflow detected for prog %sx\n", 3665 bpf_jit_get_prog_name(prog)); 3666 break; 3667 } 3668 } 3669} 3670 3671struct x64_jit_data { 3672 struct bpf_binary_header *rw_header; 3673 struct bpf_binary_header *header; 3674 int *addrs; 3675 u8 *image; 3676 int proglen; 3677 struct jit_context ctx; 3678}; 3679 3680#define MAX_PASSES 20 3681#define PADDING_PASSES (MAX_PASSES - 5) 3682 3683struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog) 3684{ 3685 struct bpf_binary_header *rw_header = NULL; 3686 struct bpf_binary_header *header = NULL; 3687 struct bpf_prog *tmp, *orig_prog = prog; 3688 void __percpu *priv_stack_ptr = NULL; 3689 struct x64_jit_data *jit_data; 3690 int priv_stack_alloc_sz; 3691 int proglen, oldproglen = 0; 3692 struct jit_context ctx = {}; 3693 bool tmp_blinded = false; 3694 bool extra_pass = false; 3695 bool padding = false; 3696 u8 *rw_image = NULL; 3697 u8 *image = NULL; 3698 int *addrs; 3699 int pass; 3700 int i; 3701 3702 if (!prog->jit_requested) 3703 return orig_prog; 3704 3705 tmp = bpf_jit_blind_constants(prog); 3706 /* 3707 * If blinding was requested and we failed during blinding, 3708 * we must fall back to the interpreter. 3709 */ 3710 if (IS_ERR(tmp)) 3711 return orig_prog; 3712 if (tmp != prog) { 3713 tmp_blinded = true; 3714 prog = tmp; 3715 } 3716 3717 jit_data = prog->aux->jit_data; 3718 if (!jit_data) { 3719 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL); 3720 if (!jit_data) { 3721 prog = orig_prog; 3722 goto out; 3723 } 3724 prog->aux->jit_data = jit_data; 3725 } 3726 priv_stack_ptr = prog->aux->priv_stack_ptr; 3727 if (!priv_stack_ptr && prog->aux->jits_use_priv_stack) { 3728 /* Allocate actual private stack size with verifier-calculated 3729 * stack size plus two memory guards to protect overflow and 3730 * underflow. 3731 */ 3732 priv_stack_alloc_sz = round_up(prog->aux->stack_depth, 8) + 3733 2 * PRIV_STACK_GUARD_SZ; 3734 priv_stack_ptr = __alloc_percpu_gfp(priv_stack_alloc_sz, 8, GFP_KERNEL); 3735 if (!priv_stack_ptr) { 3736 prog = orig_prog; 3737 goto out_priv_stack; 3738 } 3739 3740 priv_stack_init_guard(priv_stack_ptr, priv_stack_alloc_sz); 3741 prog->aux->priv_stack_ptr = priv_stack_ptr; 3742 } 3743 addrs = jit_data->addrs; 3744 if (addrs) { 3745 ctx = jit_data->ctx; 3746 oldproglen = jit_data->proglen; 3747 image = jit_data->image; 3748 header = jit_data->header; 3749 rw_header = jit_data->rw_header; 3750 rw_image = (void *)rw_header + ((void *)image - (void *)header); 3751 extra_pass = true; 3752 padding = true; 3753 goto skip_init_addrs; 3754 } 3755 addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL); 3756 if (!addrs) { 3757 prog = orig_prog; 3758 goto out_addrs; 3759 } 3760 3761 /* 3762 * Before first pass, make a rough estimation of addrs[] 3763 * each BPF instruction is translated to less than 64 bytes 3764 */ 3765 for (proglen = 0, i = 0; i <= prog->len; i++) { 3766 proglen += 64; 3767 addrs[i] = proglen; 3768 } 3769 ctx.cleanup_addr = proglen; 3770skip_init_addrs: 3771 3772 /* 3773 * JITed image shrinks with every pass and the loop iterates 3774 * until the image stops shrinking. Very large BPF programs 3775 * may converge on the last pass. In such case do one more 3776 * pass to emit the final image. 3777 */ 3778 for (pass = 0; pass < MAX_PASSES || image; pass++) { 3779 if (!padding && pass >= PADDING_PASSES) 3780 padding = true; 3781 proglen = do_jit(prog, addrs, image, rw_image, oldproglen, &ctx, padding); 3782 if (proglen <= 0) { 3783out_image: 3784 image = NULL; 3785 if (header) { 3786 bpf_arch_text_copy(&header->size, &rw_header->size, 3787 sizeof(rw_header->size)); 3788 bpf_jit_binary_pack_free(header, rw_header); 3789 } 3790 /* Fall back to interpreter mode */ 3791 prog = orig_prog; 3792 if (extra_pass) { 3793 prog->bpf_func = NULL; 3794 prog->jited = 0; 3795 prog->jited_len = 0; 3796 } 3797 goto out_addrs; 3798 } 3799 if (image) { 3800 if (proglen != oldproglen) { 3801 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n", 3802 proglen, oldproglen); 3803 goto out_image; 3804 } 3805 break; 3806 } 3807 if (proglen == oldproglen) { 3808 /* 3809 * The number of entries in extable is the number of BPF_LDX 3810 * insns that access kernel memory via "pointer to BTF type". 3811 * The verifier changed their opcode from LDX|MEM|size 3812 * to LDX|PROBE_MEM|size to make JITing easier. 3813 */ 3814 u32 align = __alignof__(struct exception_table_entry); 3815 u32 extable_size = prog->aux->num_exentries * 3816 sizeof(struct exception_table_entry); 3817 3818 /* allocate module memory for x86 insns and extable */ 3819 header = bpf_jit_binary_pack_alloc(roundup(proglen, align) + extable_size, 3820 &image, align, &rw_header, &rw_image, 3821 jit_fill_hole); 3822 if (!header) { 3823 prog = orig_prog; 3824 goto out_addrs; 3825 } 3826 prog->aux->extable = (void *) image + roundup(proglen, align); 3827 } 3828 oldproglen = proglen; 3829 cond_resched(); 3830 } 3831 3832 if (bpf_jit_enable > 1) 3833 bpf_jit_dump(prog->len, proglen, pass + 1, rw_image); 3834 3835 if (image) { 3836 if (!prog->is_func || extra_pass) { 3837 /* 3838 * bpf_jit_binary_pack_finalize fails in two scenarios: 3839 * 1) header is not pointing to proper module memory; 3840 * 2) the arch doesn't support bpf_arch_text_copy(). 3841 * 3842 * Both cases are serious bugs and justify WARN_ON. 3843 */ 3844 if (WARN_ON(bpf_jit_binary_pack_finalize(header, rw_header))) { 3845 /* header has been freed */ 3846 header = NULL; 3847 goto out_image; 3848 } 3849 3850 bpf_tail_call_direct_fixup(prog); 3851 } else { 3852 jit_data->addrs = addrs; 3853 jit_data->ctx = ctx; 3854 jit_data->proglen = proglen; 3855 jit_data->image = image; 3856 jit_data->header = header; 3857 jit_data->rw_header = rw_header; 3858 } 3859 3860 /* 3861 * The bpf_prog_update_insn_ptrs function expects addrs to 3862 * point to the first byte of the jitted instruction (unlike 3863 * the bpf_prog_fill_jited_linfo below, which, for historical 3864 * reasons, expects to point to the next instruction) 3865 */ 3866 bpf_prog_update_insn_ptrs(prog, addrs, image); 3867 3868 /* 3869 * ctx.prog_offset is used when CFI preambles put code *before* 3870 * the function. See emit_cfi(). For FineIBT specifically this code 3871 * can also be executed and bpf_prog_kallsyms_add() will 3872 * generate an additional symbol to cover this, hence also 3873 * decrement proglen. 3874 */ 3875 prog->bpf_func = (void *)image + cfi_get_offset(); 3876 prog->jited = 1; 3877 prog->jited_len = proglen - cfi_get_offset(); 3878 } else { 3879 prog = orig_prog; 3880 } 3881 3882 if (!image || !prog->is_func || extra_pass) { 3883 if (image) 3884 bpf_prog_fill_jited_linfo(prog, addrs + 1); 3885out_addrs: 3886 kvfree(addrs); 3887 if (!image && priv_stack_ptr) { 3888 free_percpu(priv_stack_ptr); 3889 prog->aux->priv_stack_ptr = NULL; 3890 } 3891out_priv_stack: 3892 kfree(jit_data); 3893 prog->aux->jit_data = NULL; 3894 } 3895out: 3896 if (tmp_blinded) 3897 bpf_jit_prog_release_other(prog, prog == orig_prog ? 3898 tmp : orig_prog); 3899 return prog; 3900} 3901 3902bool bpf_jit_supports_kfunc_call(void) 3903{ 3904 return true; 3905} 3906 3907void *bpf_arch_text_copy(void *dst, void *src, size_t len) 3908{ 3909 if (text_poke_copy(dst, src, len) == NULL) 3910 return ERR_PTR(-EINVAL); 3911 return dst; 3912} 3913 3914/* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */ 3915bool bpf_jit_supports_subprog_tailcalls(void) 3916{ 3917 return true; 3918} 3919 3920bool bpf_jit_supports_percpu_insn(void) 3921{ 3922 return true; 3923} 3924 3925void bpf_jit_free(struct bpf_prog *prog) 3926{ 3927 if (prog->jited) { 3928 struct x64_jit_data *jit_data = prog->aux->jit_data; 3929 struct bpf_binary_header *hdr; 3930 void __percpu *priv_stack_ptr; 3931 int priv_stack_alloc_sz; 3932 3933 /* 3934 * If we fail the final pass of JIT (from jit_subprogs), 3935 * the program may not be finalized yet. Call finalize here 3936 * before freeing it. 3937 */ 3938 if (jit_data) { 3939 bpf_jit_binary_pack_finalize(jit_data->header, 3940 jit_data->rw_header); 3941 kvfree(jit_data->addrs); 3942 kfree(jit_data); 3943 } 3944 prog->bpf_func = (void *)prog->bpf_func - cfi_get_offset(); 3945 hdr = bpf_jit_binary_pack_hdr(prog); 3946 bpf_jit_binary_pack_free(hdr, NULL); 3947 priv_stack_ptr = prog->aux->priv_stack_ptr; 3948 if (priv_stack_ptr) { 3949 priv_stack_alloc_sz = round_up(prog->aux->stack_depth, 8) + 3950 2 * PRIV_STACK_GUARD_SZ; 3951 priv_stack_check_guard(priv_stack_ptr, priv_stack_alloc_sz, prog); 3952 free_percpu(prog->aux->priv_stack_ptr); 3953 } 3954 WARN_ON_ONCE(!bpf_prog_kallsyms_verify_off(prog)); 3955 } 3956 3957 bpf_prog_unlock_free(prog); 3958} 3959 3960bool bpf_jit_supports_exceptions(void) 3961{ 3962 /* We unwind through both kernel frames (starting from within bpf_throw 3963 * call) and BPF frames. Therefore we require ORC unwinder to be enabled 3964 * to walk kernel frames and reach BPF frames in the stack trace. 3965 */ 3966 return IS_ENABLED(CONFIG_UNWINDER_ORC); 3967} 3968 3969bool bpf_jit_supports_private_stack(void) 3970{ 3971 return true; 3972} 3973 3974void arch_bpf_stack_walk(bool (*consume_fn)(void *cookie, u64 ip, u64 sp, u64 bp), void *cookie) 3975{ 3976#if defined(CONFIG_UNWINDER_ORC) 3977 struct unwind_state state; 3978 unsigned long addr; 3979 3980 for (unwind_start(&state, current, NULL, NULL); !unwind_done(&state); 3981 unwind_next_frame(&state)) { 3982 addr = unwind_get_return_address(&state); 3983 if (!addr || !consume_fn(cookie, (u64)addr, (u64)state.sp, (u64)state.bp)) 3984 break; 3985 } 3986 return; 3987#endif 3988} 3989 3990void bpf_arch_poke_desc_update(struct bpf_jit_poke_descriptor *poke, 3991 struct bpf_prog *new, struct bpf_prog *old) 3992{ 3993 u8 *old_addr, *new_addr, *old_bypass_addr; 3994 enum bpf_text_poke_type t; 3995 int ret; 3996 3997 old_bypass_addr = old ? NULL : poke->bypass_addr; 3998 old_addr = old ? (u8 *)old->bpf_func + poke->adj_off : NULL; 3999 new_addr = new ? (u8 *)new->bpf_func + poke->adj_off : NULL; 4000 4001 /* 4002 * On program loading or teardown, the program's kallsym entry 4003 * might not be in place, so we use __bpf_arch_text_poke to skip 4004 * the kallsyms check. 4005 */ 4006 if (new) { 4007 t = old_addr ? BPF_MOD_JUMP : BPF_MOD_NOP; 4008 ret = __bpf_arch_text_poke(poke->tailcall_target, 4009 t, BPF_MOD_JUMP, 4010 old_addr, new_addr); 4011 BUG_ON(ret < 0); 4012 if (!old) { 4013 ret = __bpf_arch_text_poke(poke->tailcall_bypass, 4014 BPF_MOD_JUMP, BPF_MOD_NOP, 4015 poke->bypass_addr, 4016 NULL); 4017 BUG_ON(ret < 0); 4018 } 4019 } else { 4020 t = old_bypass_addr ? BPF_MOD_JUMP : BPF_MOD_NOP; 4021 ret = __bpf_arch_text_poke(poke->tailcall_bypass, 4022 t, BPF_MOD_JUMP, old_bypass_addr, 4023 poke->bypass_addr); 4024 BUG_ON(ret < 0); 4025 /* let other CPUs finish the execution of program 4026 * so that it will not possible to expose them 4027 * to invalid nop, stack unwind, nop state 4028 */ 4029 if (!ret) 4030 synchronize_rcu(); 4031 t = old_addr ? BPF_MOD_JUMP : BPF_MOD_NOP; 4032 ret = __bpf_arch_text_poke(poke->tailcall_target, 4033 t, BPF_MOD_NOP, old_addr, NULL); 4034 BUG_ON(ret < 0); 4035 } 4036} 4037 4038bool bpf_jit_supports_arena(void) 4039{ 4040 return true; 4041} 4042 4043bool bpf_jit_supports_insn(struct bpf_insn *insn, bool in_arena) 4044{ 4045 if (!in_arena) 4046 return true; 4047 switch (insn->code) { 4048 case BPF_STX | BPF_ATOMIC | BPF_W: 4049 case BPF_STX | BPF_ATOMIC | BPF_DW: 4050 if (insn->imm == (BPF_AND | BPF_FETCH) || 4051 insn->imm == (BPF_OR | BPF_FETCH) || 4052 insn->imm == (BPF_XOR | BPF_FETCH)) 4053 return false; 4054 } 4055 return true; 4056} 4057 4058bool bpf_jit_supports_ptr_xchg(void) 4059{ 4060 return true; 4061} 4062 4063/* x86-64 JIT emits its own code to filter user addresses so return 0 here */ 4064u64 bpf_arch_uaddress_limit(void) 4065{ 4066 return 0; 4067} 4068 4069bool bpf_jit_supports_timed_may_goto(void) 4070{ 4071 return true; 4072}
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