lapic.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2#ifndef __KVM_X86_LAPIC_H
  3#define __KVM_X86_LAPIC_H
  4
  5#include <kvm/iodev.h>
  6
  7#include <asm/apic.h>
  8
  9#include <linux/kvm_host.h>
 10
 11#include "hyperv.h"
 12#include "smm.h"
 13
 14#define KVM_APIC_INIT		0
 15#define KVM_APIC_SIPI		1
 16
 17#define APIC_SHORT_MASK			0xc0000
 18#define APIC_DEST_NOSHORT		0x0
 19#define APIC_DEST_MASK			0x800
 20
 21#define APIC_BUS_CYCLE_NS_DEFAULT	1
 22
 23#define APIC_BROADCAST			0xFF
 24#define X2APIC_BROADCAST		0xFFFFFFFFul
 25
 26#define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
 27
 28enum lapic_mode {
 29	LAPIC_MODE_DISABLED = 0,
 30	LAPIC_MODE_INVALID = X2APIC_ENABLE,
 31	LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
 32	LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
 33};
 34
 35enum lapic_lvt_entry {
 36	LVT_TIMER,
 37	LVT_THERMAL_MONITOR,
 38	LVT_PERFORMANCE_COUNTER,
 39	LVT_LINT0,
 40	LVT_LINT1,
 41	LVT_ERROR,
 42	LVT_CMCI,
 43
 44	KVM_APIC_MAX_NR_LVT_ENTRIES,
 45};
 46
 47#define APIC_LVTx(x) ((x) == LVT_CMCI ? APIC_LVTCMCI : APIC_LVTT + 0x10 * (x))
 48
 49struct kvm_timer {
 50	struct hrtimer timer;
 51	s64 period; 				/* unit: ns */
 52	ktime_t target_expiration;
 53	u32 timer_mode;
 54	u32 timer_mode_mask;
 55	u64 tscdeadline;
 56	u64 expired_tscdeadline;
 57	u32 timer_advance_ns;
 58	atomic_t pending;			/* accumulated triggered timers */
 59	bool hv_timer_in_use;
 60};
 61
 62struct kvm_lapic {
 63	unsigned long base_address;
 64	struct kvm_io_device dev;
 65	struct kvm_timer lapic_timer;
 66	u32 divide_count;
 67	struct kvm_vcpu *vcpu;
 68	bool apicv_active;
 69	bool sw_enabled;
 70	bool irr_pending;
 71	bool lvt0_in_nmi_mode;
 72	/* Select registers in the vAPIC cannot be read/written. */
 73	bool guest_apic_protected;
 74	/* Number of bits set in ISR. */
 75	s16 isr_count;
 76	/* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
 77	int highest_isr_cache;
 78	/**
 79	 * APIC register page.  The layout matches the register layout seen by
 80	 * the guest 1:1, because it is accessed by the vmx microcode.
 81	 * Note: Only one register, the TPR, is used by the microcode.
 82	 */
 83	void *regs;
 84	gpa_t vapic_addr;
 85	struct gfn_to_hva_cache vapic_cache;
 86	unsigned long pending_events;
 87	unsigned int sipi_vector;
 88	int nr_lvt_entries;
 89};
 90
 91struct dest_map;
 92
 93int kvm_create_lapic(struct kvm_vcpu *vcpu);
 94void kvm_free_lapic(struct kvm_vcpu *vcpu);
 95
 96int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
 97void kvm_apic_ack_interrupt(struct kvm_vcpu *vcpu, int vector);
 98int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
 99int kvm_apic_accept_events(struct kvm_vcpu *vcpu);
100void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
101u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
102void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
103void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
104void kvm_apic_set_version(struct kvm_vcpu *vcpu);
105void kvm_apic_after_set_mcg_cap(struct kvm_vcpu *vcpu);
106bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
107			   int shorthand, unsigned int dest, int dest_mode);
108void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec);
109bool __kvm_apic_update_irr(unsigned long *pir, void *regs, int *max_irr);
110bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, unsigned long *pir, int *max_irr);
111void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
112int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
113		     struct dest_map *dest_map);
114int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
115void kvm_apic_update_apicv(struct kvm_vcpu *vcpu);
116int kvm_alloc_apic_access_page(struct kvm *kvm);
117void kvm_inhibit_apic_access_page(struct kvm_vcpu *vcpu);
118
119bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
120		struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
121int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
122			     struct kvm_lapic_irq *irq,
123			     struct dest_map *dest_map);
124void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
125
126int kvm_apic_set_base(struct kvm_vcpu *vcpu, u64 value, bool host_initiated);
127int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
128int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
129void kvm_apic_update_hwapic_isr(struct kvm_vcpu *vcpu);
130int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
131
132u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
133void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
134
135void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
136void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
137
138int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
139void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
140void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
141
142int kvm_x2apic_icr_write_fast(struct kvm_lapic *apic, u64 data);
143int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
144int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
145
146int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
147int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
148
149int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
150void kvm_lapic_exit(void);
151
152u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);
153
154static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
155{
156	apic_set_vector(vec, apic->regs + APIC_IRR);
157	/*
158	 * irr_pending must be true if any interrupt is pending; set it after
159	 * APIC_IRR to avoid race with apic_clear_irr
160	 */
161	apic->irr_pending = true;
162}
163
164static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
165{
166	return apic_get_reg(apic->regs, reg_off);
167}
168
169DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
170
171static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
172{
173	if (static_branch_unlikely(&kvm_has_noapic_vcpu))
174		return vcpu->arch.apic;
175	return true;
176}
177
178extern struct static_key_false_deferred apic_hw_disabled;
179
180static inline bool kvm_apic_hw_enabled(struct kvm_lapic *apic)
181{
182	if (static_branch_unlikely(&apic_hw_disabled.key))
183		return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
184	return true;
185}
186
187extern struct static_key_false_deferred apic_sw_disabled;
188
189static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
190{
191	if (static_branch_unlikely(&apic_sw_disabled.key))
192		return apic->sw_enabled;
193	return true;
194}
195
196static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
197{
198	return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
199}
200
201static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
202{
203	return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
204}
205
206static inline int apic_x2apic_mode(struct kvm_lapic *apic)
207{
208	return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
209}
210
211static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
212{
213	return lapic_in_kernel(vcpu) && vcpu->arch.apic->apicv_active;
214}
215
216static inline bool kvm_apic_has_pending_init_or_sipi(struct kvm_vcpu *vcpu)
217{
218	return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
219}
220
221static inline bool kvm_apic_init_sipi_allowed(struct kvm_vcpu *vcpu)
222{
223	return !is_smm(vcpu) &&
224	       !kvm_x86_call(apic_init_signal_blocked)(vcpu);
225}
226
227static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
228{
229	return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
230}
231
232bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
233
234bool kvm_lapic_suppress_eoi_broadcast(struct kvm_lapic *apic);
235
236void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
237
238void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
239			      unsigned long *vcpu_bitmap);
240
241bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq,
242			     struct kvm_vcpu **dest_vcpu);
243void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
244void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
245void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
246bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
247void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
248
249static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
250{
251	return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
252}
253
254static inline enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
255{
256	return kvm_apic_mode(vcpu->arch.apic_base);
257}
258
259static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
260{
261	return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
262}
263
264#endif