generic.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong
   4 * because MTRRs can span up to 40 bits (36bits on most modern x86)
   5 */
   6
   7#include <linux/export.h>
   8#include <linux/init.h>
   9#include <linux/io.h>
  10#include <linux/mm.h>
  11#include <linux/cc_platform.h>
  12#include <linux/string_choices.h>
  13#include <asm/processor-flags.h>
  14#include <asm/cacheinfo.h>
  15#include <asm/cpufeature.h>
  16#include <asm/cpu_device_id.h>
  17#include <asm/hypervisor.h>
  18#include <asm/mshyperv.h>
  19#include <asm/tlbflush.h>
  20#include <asm/mtrr.h>
  21#include <asm/msr.h>
  22#include <asm/memtype.h>
  23
  24#include "mtrr.h"
  25
  26struct fixed_range_block {
  27	int base_msr;		/* start address of an MTRR block */
  28	int ranges;		/* number of MTRRs in this block  */
  29};
  30
  31static struct fixed_range_block fixed_range_blocks[] = {
  32	{ MSR_MTRRfix64K_00000, 1 }, /* one   64k MTRR  */
  33	{ MSR_MTRRfix16K_80000, 2 }, /* two   16k MTRRs */
  34	{ MSR_MTRRfix4K_C0000,  8 }, /* eight  4k MTRRs */
  35	{}
  36};
  37
  38struct cache_map {
  39	u64 start;
  40	u64 end;
  41	u64 flags;
  42	u64 type:8;
  43	u64 fixed:1;
  44};
  45
  46bool mtrr_debug;
  47
  48static int __init mtrr_param_setup(char *str)
  49{
  50	int rc = 0;
  51
  52	if (!str)
  53		return -EINVAL;
  54	if (!strcmp(str, "debug"))
  55		mtrr_debug = true;
  56	else
  57		rc = -EINVAL;
  58
  59	return rc;
  60}
  61early_param("mtrr", mtrr_param_setup);
  62
  63/*
  64 * CACHE_MAP_MAX is the maximum number of memory ranges in cache_map, where
  65 * no 2 adjacent ranges have the same cache mode (those would be merged).
  66 * The number is based on the worst case:
  67 * - no two adjacent fixed MTRRs share the same cache mode
  68 * - one variable MTRR is spanning a huge area with mode WB
  69 * - 255 variable MTRRs with mode UC all overlap with the WB MTRR, creating 2
  70 *   additional ranges each (result like "ababababa...aba" with a = WB, b = UC),
  71 *   accounting for MTRR_MAX_VAR_RANGES * 2 - 1 range entries
  72 * - a TOP_MEM2 area (even with overlapping an UC MTRR can't add 2 range entries
  73 *   to the possible maximum, as it always starts at 4GB, thus it can't be in
  74 *   the middle of that MTRR, unless that MTRR starts at 0, which would remove
  75 *   the initial "a" from the "abababa" pattern above)
  76 * The map won't contain ranges with no matching MTRR (those fall back to the
  77 * default cache mode).
  78 */
  79#define CACHE_MAP_MAX	(MTRR_NUM_FIXED_RANGES + MTRR_MAX_VAR_RANGES * 2)
  80
  81static struct cache_map init_cache_map[CACHE_MAP_MAX] __initdata;
  82static struct cache_map *cache_map __refdata = init_cache_map;
  83static unsigned int cache_map_size = CACHE_MAP_MAX;
  84static unsigned int cache_map_n;
  85static unsigned int cache_map_fixed;
  86
  87static unsigned long smp_changes_mask;
  88static int mtrr_state_set;
  89u64 mtrr_tom2;
  90
  91struct mtrr_state_type mtrr_state;
  92
  93/* Reserved bits in the high portion of the MTRRphysBaseN MSR. */
  94u32 phys_hi_rsvd;
  95
  96/*
  97 * BIOS is expected to clear MtrrFixDramModEn bit, see for example
  98 * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD
  99 * Opteron Processors" (26094 Rev. 3.30 February 2006), section
 100 * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set
 101 * to 1 during BIOS initialization of the fixed MTRRs, then cleared to
 102 * 0 for operation."
 103 */
 104static inline void k8_check_syscfg_dram_mod_en(void)
 105{
 106	u32 lo, hi;
 107
 108	if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
 109	      (boot_cpu_data.x86 >= 0x0f)))
 110		return;
 111
 112	if (cc_platform_has(CC_ATTR_HOST_SEV_SNP))
 113		return;
 114
 115	rdmsr(MSR_AMD64_SYSCFG, lo, hi);
 116	if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) {
 117		pr_err(FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
 118		       " not cleared by BIOS, clearing this bit\n",
 119		       smp_processor_id());
 120		lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
 121		mtrr_wrmsr(MSR_AMD64_SYSCFG, lo, hi);
 122	}
 123}
 124
 125/* Get the size of contiguous MTRR range */
 126static u64 get_mtrr_size(u64 mask)
 127{
 128	u64 size;
 129
 130	mask |= (u64)phys_hi_rsvd << 32;
 131	size = -mask;
 132
 133	return size;
 134}
 135
 136static u8 get_var_mtrr_state(unsigned int reg, u64 *start, u64 *size)
 137{
 138	struct mtrr_var_range *mtrr = mtrr_state.var_ranges + reg;
 139
 140	if (!(mtrr->mask_lo & MTRR_PHYSMASK_V))
 141		return MTRR_TYPE_INVALID;
 142
 143	*start = (((u64)mtrr->base_hi) << 32) + (mtrr->base_lo & PAGE_MASK);
 144	*size = get_mtrr_size((((u64)mtrr->mask_hi) << 32) +
 145			      (mtrr->mask_lo & PAGE_MASK));
 146
 147	return mtrr->base_lo & MTRR_PHYSBASE_TYPE;
 148}
 149
 150static u8 get_effective_type(u8 type1, u8 type2)
 151{
 152	if (type1 == MTRR_TYPE_UNCACHABLE || type2 == MTRR_TYPE_UNCACHABLE)
 153		return MTRR_TYPE_UNCACHABLE;
 154
 155	if ((type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH) ||
 156	    (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK))
 157		return MTRR_TYPE_WRTHROUGH;
 158
 159	if (type1 != type2)
 160		return MTRR_TYPE_UNCACHABLE;
 161
 162	return type1;
 163}
 164
 165static void rm_map_entry_at(int idx)
 166{
 167	cache_map_n--;
 168	if (cache_map_n > idx) {
 169		memmove(cache_map + idx, cache_map + idx + 1,
 170			sizeof(*cache_map) * (cache_map_n - idx));
 171	}
 172}
 173
 174/*
 175 * Add an entry into cache_map at a specific index.  Merges adjacent entries if
 176 * appropriate.  Return the number of merges for correcting the scan index
 177 * (this is needed as merging will reduce the number of entries, which will
 178 * result in skipping entries in future iterations if the scan index isn't
 179 * corrected).
 180 * Note that the corrected index can never go below -1 (resulting in being 0 in
 181 * the next scan iteration), as "2" is returned only if the current index is
 182 * larger than zero.
 183 */
 184static int add_map_entry_at(u64 start, u64 end, u8 type, int idx)
 185{
 186	bool merge_prev = false, merge_next = false;
 187
 188	if (start >= end)
 189		return 0;
 190
 191	if (idx > 0) {
 192		struct cache_map *prev = cache_map + idx - 1;
 193
 194		if (!prev->fixed && start == prev->end && type == prev->type)
 195			merge_prev = true;
 196	}
 197
 198	if (idx < cache_map_n) {
 199		struct cache_map *next = cache_map + idx;
 200
 201		if (!next->fixed && end == next->start && type == next->type)
 202			merge_next = true;
 203	}
 204
 205	if (merge_prev && merge_next) {
 206		cache_map[idx - 1].end = cache_map[idx].end;
 207		rm_map_entry_at(idx);
 208		return 2;
 209	}
 210	if (merge_prev) {
 211		cache_map[idx - 1].end = end;
 212		return 1;
 213	}
 214	if (merge_next) {
 215		cache_map[idx].start = start;
 216		return 1;
 217	}
 218
 219	/* Sanity check: the array should NEVER be too small! */
 220	if (cache_map_n == cache_map_size) {
 221		WARN(1, "MTRR cache mode memory map exhausted!\n");
 222		cache_map_n = cache_map_fixed;
 223		return 0;
 224	}
 225
 226	if (cache_map_n > idx) {
 227		memmove(cache_map + idx + 1, cache_map + idx,
 228			sizeof(*cache_map) * (cache_map_n - idx));
 229	}
 230
 231	cache_map[idx].start = start;
 232	cache_map[idx].end = end;
 233	cache_map[idx].type = type;
 234	cache_map[idx].fixed = 0;
 235	cache_map_n++;
 236
 237	return 0;
 238}
 239
 240/* Clear a part of an entry. Return 1 if start of entry is still valid. */
 241static int clr_map_range_at(u64 start, u64 end, int idx)
 242{
 243	int ret = start != cache_map[idx].start;
 244	u64 tmp;
 245
 246	if (start == cache_map[idx].start && end == cache_map[idx].end) {
 247		rm_map_entry_at(idx);
 248	} else if (start == cache_map[idx].start) {
 249		cache_map[idx].start = end;
 250	} else if (end == cache_map[idx].end) {
 251		cache_map[idx].end = start;
 252	} else {
 253		tmp = cache_map[idx].end;
 254		cache_map[idx].end = start;
 255		add_map_entry_at(end, tmp, cache_map[idx].type, idx + 1);
 256	}
 257
 258	return ret;
 259}
 260
 261/*
 262 * Add MTRR to the map.  The current map is scanned and each part of the MTRR
 263 * either overlapping with an existing entry or with a hole in the map is
 264 * handled separately.
 265 */
 266static void add_map_entry(u64 start, u64 end, u8 type)
 267{
 268	u8 new_type, old_type;
 269	u64 tmp;
 270	int i;
 271
 272	for (i = 0; i < cache_map_n && start < end; i++) {
 273		if (start >= cache_map[i].end)
 274			continue;
 275
 276		if (start < cache_map[i].start) {
 277			/* Region start has no overlap. */
 278			tmp = min(end, cache_map[i].start);
 279			i -= add_map_entry_at(start, tmp,  type, i);
 280			start = tmp;
 281			continue;
 282		}
 283
 284		new_type = get_effective_type(type, cache_map[i].type);
 285		old_type = cache_map[i].type;
 286
 287		if (cache_map[i].fixed || new_type == old_type) {
 288			/* Cut off start of new entry. */
 289			start = cache_map[i].end;
 290			continue;
 291		}
 292
 293		/* Handle only overlapping part of region. */
 294		tmp = min(end, cache_map[i].end);
 295		i += clr_map_range_at(start, tmp, i);
 296		i -= add_map_entry_at(start, tmp, new_type, i);
 297		start = tmp;
 298	}
 299
 300	/* Add rest of region after last map entry (rest might be empty). */
 301	add_map_entry_at(start, end, type, i);
 302}
 303
 304/* Add variable MTRRs to cache map. */
 305static void map_add_var(void)
 306{
 307	u64 start, size;
 308	unsigned int i;
 309	u8 type;
 310
 311	/*
 312	 * Add AMD TOP_MEM2 area.  Can't be added in mtrr_build_map(), as it
 313	 * needs to be added again when rebuilding the map due to potentially
 314	 * having moved as a result of variable MTRRs for memory below 4GB.
 315	 */
 316	if (mtrr_tom2) {
 317		add_map_entry(BIT_ULL(32), mtrr_tom2, MTRR_TYPE_WRBACK);
 318		cache_map[cache_map_n - 1].fixed = 1;
 319	}
 320
 321	for (i = 0; i < num_var_ranges; i++) {
 322		type = get_var_mtrr_state(i, &start, &size);
 323		if (type != MTRR_TYPE_INVALID)
 324			add_map_entry(start, start + size, type);
 325	}
 326}
 327
 328/*
 329 * Rebuild map by replacing variable entries.  Needs to be called when MTRR
 330 * registers are being changed after boot, as such changes could include
 331 * removals of registers, which are complicated to handle without rebuild of
 332 * the map.
 333 */
 334void generic_rebuild_map(void)
 335{
 336	if (mtrr_if != &generic_mtrr_ops)
 337		return;
 338
 339	cache_map_n = cache_map_fixed;
 340
 341	map_add_var();
 342}
 343
 344static unsigned int __init get_cache_map_size(void)
 345{
 346	return cache_map_fixed + 2 * num_var_ranges + (mtrr_tom2 != 0);
 347}
 348
 349/* Build the cache_map containing the cache modes per memory range. */
 350void __init mtrr_build_map(void)
 351{
 352	u64 start, end, size;
 353	unsigned int i;
 354	u8 type;
 355
 356	/* Add fixed MTRRs, optimize for adjacent entries with same type. */
 357	if (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED) {
 358		/*
 359		 * Start with 64k size fixed entries, preset 1st one (hence the
 360		 * loop below is starting with index 1).
 361		 */
 362		start = 0;
 363		end = size = 0x10000;
 364		type = mtrr_state.fixed_ranges[0];
 365
 366		for (i = 1; i < MTRR_NUM_FIXED_RANGES; i++) {
 367			/* 8 64k entries, then 16 16k ones, rest 4k. */
 368			if (i == 8 || i == 24)
 369				size >>= 2;
 370
 371			if (mtrr_state.fixed_ranges[i] != type) {
 372				add_map_entry(start, end, type);
 373				start = end;
 374				type = mtrr_state.fixed_ranges[i];
 375			}
 376			end += size;
 377		}
 378		add_map_entry(start, end, type);
 379	}
 380
 381	/* Mark fixed, they take precedence. */
 382	for (i = 0; i < cache_map_n; i++)
 383		cache_map[i].fixed = 1;
 384	cache_map_fixed = cache_map_n;
 385
 386	map_add_var();
 387
 388	pr_info("MTRR map: %u entries (%u fixed + %u variable; max %u), built from %u variable MTRRs\n",
 389		cache_map_n, cache_map_fixed, cache_map_n - cache_map_fixed,
 390		get_cache_map_size(), num_var_ranges + (mtrr_tom2 != 0));
 391
 392	if (mtrr_debug) {
 393		for (i = 0; i < cache_map_n; i++) {
 394			pr_info("%3u: %016llx-%016llx %s\n", i,
 395				cache_map[i].start, cache_map[i].end - 1,
 396				mtrr_attrib_to_str(cache_map[i].type));
 397		}
 398	}
 399}
 400
 401/* Copy the cache_map from __initdata memory to dynamically allocated one. */
 402void __init mtrr_copy_map(void)
 403{
 404	unsigned int new_size = get_cache_map_size();
 405
 406	if (!mtrr_state.enabled || !new_size) {
 407		cache_map = NULL;
 408		return;
 409	}
 410
 411	mutex_lock(&mtrr_mutex);
 412
 413	cache_map = kcalloc(new_size, sizeof(*cache_map), GFP_KERNEL);
 414	if (cache_map) {
 415		memmove(cache_map, init_cache_map,
 416			cache_map_n * sizeof(*cache_map));
 417		cache_map_size = new_size;
 418	} else {
 419		mtrr_state.enabled = 0;
 420		pr_err("MTRRs disabled due to allocation failure for lookup map.\n");
 421	}
 422
 423	mutex_unlock(&mtrr_mutex);
 424}
 425
 426/**
 427 * guest_force_mtrr_state - set static MTRR state for a guest
 428 *
 429 * Used to set MTRR state via different means (e.g. with data obtained from
 430 * a hypervisor).
 431 * Is allowed only for special cases when running virtualized. Must be called
 432 * from the x86_init.hyper.init_platform() hook.  It can be called only once.
 433 * The MTRR state can't be changed afterwards.  To ensure that, X86_FEATURE_MTRR
 434 * is cleared.
 435 *
 436 * @var: MTRR variable range array to use
 437 * @num_var: length of the @var array
 438 * @def_type: default caching type
 439 */
 440void guest_force_mtrr_state(struct mtrr_var_range *var, unsigned int num_var,
 441			    mtrr_type def_type)
 442{
 443	unsigned int i;
 444
 445	/* Only allowed to be called once before mtrr_bp_init(). */
 446	if (WARN_ON_ONCE(mtrr_state_set))
 447		return;
 448
 449	/* Only allowed when running virtualized. */
 450	if (!cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
 451		return;
 452
 453	/*
 454	 * Only allowed for special virtualization cases:
 455	 * - when running as Hyper-V, SEV-SNP guest using vTOM
 456	 * - when running as Xen PV guest
 457	 * - when running as SEV-SNP or TDX guest to avoid unnecessary
 458	 *   VMM communication/Virtualization exceptions (#VC, #VE)
 459	 */
 460	if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP) &&
 461	    !hv_is_isolation_supported() &&
 462	    !cpu_feature_enabled(X86_FEATURE_XENPV) &&
 463	    !cpu_feature_enabled(X86_FEATURE_TDX_GUEST))
 464		return;
 465
 466	/* Disable MTRR in order to disable MTRR modifications. */
 467	setup_clear_cpu_cap(X86_FEATURE_MTRR);
 468
 469	if (var) {
 470		if (num_var > MTRR_MAX_VAR_RANGES) {
 471			pr_warn("Trying to overwrite MTRR state with %u variable entries\n",
 472				num_var);
 473			num_var = MTRR_MAX_VAR_RANGES;
 474		}
 475		for (i = 0; i < num_var; i++)
 476			mtrr_state.var_ranges[i] = var[i];
 477		num_var_ranges = num_var;
 478	}
 479
 480	mtrr_state.def_type = def_type;
 481	mtrr_state.enabled |= MTRR_STATE_MTRR_ENABLED;
 482
 483	mtrr_state_set = 1;
 484}
 485
 486static u8 type_merge(u8 type, u8 new_type, u8 *uniform)
 487{
 488	u8 effective_type;
 489
 490	if (type == MTRR_TYPE_INVALID)
 491		return new_type;
 492
 493	effective_type = get_effective_type(type, new_type);
 494	if (type != effective_type)
 495		*uniform = 0;
 496
 497	return effective_type;
 498}
 499
 500/**
 501 * mtrr_type_lookup - look up memory type in MTRR
 502 *
 503 * @start: Begin of the physical address range
 504 * @end: End of the physical address range
 505 * @uniform: output argument:
 506 *  - 1: the returned MTRR type is valid for the whole region
 507 *  - 0: otherwise
 508 *
 509 * Return Values:
 510 * MTRR_TYPE_(type)  - The effective MTRR type for the region
 511 * MTRR_TYPE_INVALID - MTRR is disabled
 512 */
 513u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform)
 514{
 515	u8 type = MTRR_TYPE_INVALID;
 516	unsigned int i;
 517
 518	if (!mtrr_state_set) {
 519		/* Uniformity is unknown. */
 520		*uniform = 0;
 521		return MTRR_TYPE_UNCACHABLE;
 522	}
 523
 524	*uniform = 1;
 525
 526	if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED))
 527		return MTRR_TYPE_UNCACHABLE;
 528
 529	for (i = 0; i < cache_map_n && start < end; i++) {
 530		/* Region after current map entry? -> continue with next one. */
 531		if (start >= cache_map[i].end)
 532			continue;
 533
 534		/* Start of region not covered by current map entry? */
 535		if (start < cache_map[i].start) {
 536			/* At least some part of region has default type. */
 537			type = type_merge(type, mtrr_state.def_type, uniform);
 538			/* End of region not covered, too? -> lookup done. */
 539			if (end <= cache_map[i].start)
 540				return type;
 541		}
 542
 543		/* At least part of region covered by map entry. */
 544		type = type_merge(type, cache_map[i].type, uniform);
 545
 546		start = cache_map[i].end;
 547	}
 548
 549	/* End of region past last entry in map? -> use default type. */
 550	if (start < end)
 551		type = type_merge(type, mtrr_state.def_type, uniform);
 552
 553	return type;
 554}
 555
 556/* Get the MSR pair relating to a var range */
 557static void
 558get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
 559{
 560	rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
 561	rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
 562}
 563
 564/* Fill the MSR pair relating to a var range */
 565void fill_mtrr_var_range(unsigned int index,
 566		u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi)
 567{
 568	struct mtrr_var_range *vr;
 569
 570	vr = mtrr_state.var_ranges;
 571
 572	vr[index].base_lo = base_lo;
 573	vr[index].base_hi = base_hi;
 574	vr[index].mask_lo = mask_lo;
 575	vr[index].mask_hi = mask_hi;
 576}
 577
 578static void get_fixed_ranges(mtrr_type *frs)
 579{
 580	unsigned int *p = (unsigned int *)frs;
 581	int i;
 582
 583	k8_check_syscfg_dram_mod_en();
 584
 585	rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]);
 586
 587	for (i = 0; i < 2; i++)
 588		rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]);
 589	for (i = 0; i < 8; i++)
 590		rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]);
 591}
 592
 593void mtrr_save_fixed_ranges(void *info)
 594{
 595	if (mtrr_state.have_fixed)
 596		get_fixed_ranges(mtrr_state.fixed_ranges);
 597}
 598
 599static unsigned __initdata last_fixed_start;
 600static unsigned __initdata last_fixed_end;
 601static mtrr_type __initdata last_fixed_type;
 602
 603static void __init print_fixed_last(void)
 604{
 605	if (!last_fixed_end)
 606		return;
 607
 608	pr_info("  %05X-%05X %s\n", last_fixed_start,
 609		last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type));
 610
 611	last_fixed_end = 0;
 612}
 613
 614static void __init update_fixed_last(unsigned base, unsigned end,
 615				     mtrr_type type)
 616{
 617	last_fixed_start = base;
 618	last_fixed_end = end;
 619	last_fixed_type = type;
 620}
 621
 622static void __init
 623print_fixed(unsigned base, unsigned step, const mtrr_type *types)
 624{
 625	unsigned i;
 626
 627	for (i = 0; i < 8; ++i, ++types, base += step) {
 628		if (last_fixed_end == 0) {
 629			update_fixed_last(base, base + step, *types);
 630			continue;
 631		}
 632		if (last_fixed_end == base && last_fixed_type == *types) {
 633			last_fixed_end = base + step;
 634			continue;
 635		}
 636		/* new segments: gap or different type */
 637		print_fixed_last();
 638		update_fixed_last(base, base + step, *types);
 639	}
 640}
 641
 642static void __init print_mtrr_state(void)
 643{
 644	unsigned int i;
 645	int high_width;
 646
 647	pr_info("MTRR default type: %s\n",
 648		mtrr_attrib_to_str(mtrr_state.def_type));
 649	if (mtrr_state.have_fixed) {
 650		pr_info("MTRR fixed ranges %s:\n",
 651			str_enabled_disabled(
 652			 (mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED) &&
 653			 (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)));
 654		print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0);
 655		for (i = 0; i < 2; ++i)
 656			print_fixed(0x80000 + i * 0x20000, 0x04000,
 657				    mtrr_state.fixed_ranges + (i + 1) * 8);
 658		for (i = 0; i < 8; ++i)
 659			print_fixed(0xC0000 + i * 0x08000, 0x01000,
 660				    mtrr_state.fixed_ranges + (i + 3) * 8);
 661
 662		/* tail */
 663		print_fixed_last();
 664	}
 665	pr_info("MTRR variable ranges %s:\n",
 666		str_enabled_disabled(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED));
 667	high_width = (boot_cpu_data.x86_phys_bits - (32 - PAGE_SHIFT) + 3) / 4;
 668
 669	for (i = 0; i < num_var_ranges; ++i) {
 670		if (mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V)
 671			pr_info("  %u base %0*X%05X000 mask %0*X%05X000 %s\n",
 672				i,
 673				high_width,
 674				mtrr_state.var_ranges[i].base_hi,
 675				mtrr_state.var_ranges[i].base_lo >> 12,
 676				high_width,
 677				mtrr_state.var_ranges[i].mask_hi,
 678				mtrr_state.var_ranges[i].mask_lo >> 12,
 679				mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo &
 680						    MTRR_PHYSBASE_TYPE));
 681		else
 682			pr_info("  %u disabled\n", i);
 683	}
 684	if (mtrr_tom2)
 685		pr_info("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);
 686}
 687
 688/* Grab all of the MTRR state for this CPU into *state */
 689bool __init get_mtrr_state(void)
 690{
 691	struct mtrr_var_range *vrs;
 692	unsigned lo, dummy;
 693	unsigned int i;
 694
 695	vrs = mtrr_state.var_ranges;
 696
 697	rdmsr(MSR_MTRRcap, lo, dummy);
 698	mtrr_state.have_fixed = lo & MTRR_CAP_FIX;
 699
 700	for (i = 0; i < num_var_ranges; i++)
 701		get_mtrr_var_range(i, &vrs[i]);
 702	if (mtrr_state.have_fixed)
 703		get_fixed_ranges(mtrr_state.fixed_ranges);
 704
 705	rdmsr(MSR_MTRRdefType, lo, dummy);
 706	mtrr_state.def_type = lo & MTRR_DEF_TYPE_TYPE;
 707	mtrr_state.enabled = (lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT;
 708
 709	if (amd_special_default_mtrr()) {
 710		unsigned low, high;
 711
 712		/* TOP_MEM2 */
 713		rdmsr(MSR_K8_TOP_MEM2, low, high);
 714		mtrr_tom2 = high;
 715		mtrr_tom2 <<= 32;
 716		mtrr_tom2 |= low;
 717		mtrr_tom2 &= 0xffffff800000ULL;
 718	}
 719
 720	if (mtrr_debug)
 721		print_mtrr_state();
 722
 723	mtrr_state_set = 1;
 724
 725	return !!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED);
 726}
 727
 728/* Some BIOS's are messed up and don't set all MTRRs the same! */
 729void __init mtrr_state_warn(void)
 730{
 731	unsigned long mask = smp_changes_mask;
 732
 733	if (!mask)
 734		return;
 735	if (mask & MTRR_CHANGE_MASK_FIXED)
 736		pr_warn("mtrr: your CPUs had inconsistent fixed MTRR settings\n");
 737	if (mask & MTRR_CHANGE_MASK_VARIABLE)
 738		pr_warn("mtrr: your CPUs had inconsistent variable MTRR settings\n");
 739	if (mask & MTRR_CHANGE_MASK_DEFTYPE)
 740		pr_warn("mtrr: your CPUs had inconsistent MTRRdefType settings\n");
 741
 742	pr_info("mtrr: probably your BIOS does not setup all CPUs.\n");
 743	pr_info("mtrr: corrected configuration.\n");
 744}
 745
 746/*
 747 * Doesn't attempt to pass an error out to MTRR users
 748 * because it's quite complicated in some cases and probably not
 749 * worth it because the best error handling is to ignore it.
 750 */
 751void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)
 752{
 753	if (wrmsr_safe(msr, a, b) < 0) {
 754		pr_err("MTRR: CPU %u: Writing MSR %x to %x:%x failed\n",
 755			smp_processor_id(), msr, a, b);
 756	}
 757}
 758
 759/**
 760 * set_fixed_range - checks & updates a fixed-range MTRR if it
 761 *		     differs from the value it should have
 762 * @msr: MSR address of the MTTR which should be checked and updated
 763 * @changed: pointer which indicates whether the MTRR needed to be changed
 764 * @msrwords: pointer to the MSR values which the MSR should have
 765 */
 766static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
 767{
 768	unsigned lo, hi;
 769
 770	rdmsr(msr, lo, hi);
 771
 772	if (lo != msrwords[0] || hi != msrwords[1]) {
 773		mtrr_wrmsr(msr, msrwords[0], msrwords[1]);
 774		*changed = true;
 775	}
 776}
 777
 778/**
 779 * generic_get_free_region - Get a free MTRR.
 780 * @base: The starting (base) address of the region.
 781 * @size: The size (in bytes) of the region.
 782 * @replace_reg: mtrr index to be replaced; set to invalid value if none.
 783 *
 784 * Returns: The index of the region on success, else negative on error.
 785 */
 786int
 787generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
 788{
 789	unsigned long lbase, lsize;
 790	mtrr_type ltype;
 791	int i, max;
 792
 793	max = num_var_ranges;
 794	if (replace_reg >= 0 && replace_reg < max)
 795		return replace_reg;
 796
 797	for (i = 0; i < max; ++i) {
 798		mtrr_if->get(i, &lbase, &lsize, &ltype);
 799		if (lsize == 0)
 800			return i;
 801	}
 802
 803	return -ENOSPC;
 804}
 805
 806static void generic_get_mtrr(unsigned int reg, unsigned long *base,
 807			     unsigned long *size, mtrr_type *type)
 808{
 809	u32 mask_lo, mask_hi, base_lo, base_hi;
 810	unsigned int hi;
 811	u64 tmp, mask;
 812
 813	/*
 814	 * get_mtrr doesn't need to update mtrr_state, also it could be called
 815	 * from any cpu, so try to print it out directly.
 816	 */
 817	get_cpu();
 818
 819	rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
 820
 821	if (!(mask_lo & MTRR_PHYSMASK_V)) {
 822		/*  Invalid (i.e. free) range */
 823		*base = 0;
 824		*size = 0;
 825		*type = 0;
 826		goto out_put_cpu;
 827	}
 828
 829	rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
 830
 831	/* Work out the shifted address mask: */
 832	tmp = (u64)mask_hi << 32 | (mask_lo & PAGE_MASK);
 833	mask = (u64)phys_hi_rsvd << 32 | tmp;
 834
 835	/* Expand tmp with high bits to all 1s: */
 836	hi = fls64(tmp);
 837	if (hi > 0) {
 838		tmp |= ~((1ULL<<(hi - 1)) - 1);
 839
 840		if (tmp != mask) {
 841			pr_warn("mtrr: your BIOS has configured an incorrect mask, fixing it.\n");
 842			add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 843			mask = tmp;
 844		}
 845	}
 846
 847	/*
 848	 * This works correctly if size is a power of two, i.e. a
 849	 * contiguous range:
 850	 */
 851	*size = -mask >> PAGE_SHIFT;
 852	*base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
 853	*type = base_lo & MTRR_PHYSBASE_TYPE;
 854
 855out_put_cpu:
 856	put_cpu();
 857}
 858
 859/**
 860 * set_fixed_ranges - checks & updates the fixed-range MTRRs if they
 861 *		      differ from the saved set
 862 * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges()
 863 */
 864static int set_fixed_ranges(mtrr_type *frs)
 865{
 866	unsigned long long *saved = (unsigned long long *)frs;
 867	bool changed = false;
 868	int block = -1, range;
 869
 870	k8_check_syscfg_dram_mod_en();
 871
 872	while (fixed_range_blocks[++block].ranges) {
 873		for (range = 0; range < fixed_range_blocks[block].ranges; range++)
 874			set_fixed_range(fixed_range_blocks[block].base_msr + range,
 875					&changed, (unsigned int *)saved++);
 876	}
 877
 878	return changed;
 879}
 880
 881/*
 882 * Set the MSR pair relating to a var range.
 883 * Returns true if changes are made.
 884 */
 885static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
 886{
 887	unsigned int lo, hi;
 888	bool changed = false;
 889
 890	rdmsr(MTRRphysBase_MSR(index), lo, hi);
 891	if ((vr->base_lo & ~MTRR_PHYSBASE_RSVD) != (lo & ~MTRR_PHYSBASE_RSVD)
 892	    || (vr->base_hi & ~phys_hi_rsvd) != (hi & ~phys_hi_rsvd)) {
 893
 894		mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
 895		changed = true;
 896	}
 897
 898	rdmsr(MTRRphysMask_MSR(index), lo, hi);
 899
 900	if ((vr->mask_lo & ~MTRR_PHYSMASK_RSVD) != (lo & ~MTRR_PHYSMASK_RSVD)
 901	    || (vr->mask_hi & ~phys_hi_rsvd) != (hi & ~phys_hi_rsvd)) {
 902		mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
 903		changed = true;
 904	}
 905	return changed;
 906}
 907
 908static u32 deftype_lo, deftype_hi;
 909
 910/**
 911 * set_mtrr_state - Set the MTRR state for this CPU.
 912 *
 913 * NOTE: The CPU must already be in a safe state for MTRR changes, including
 914 *       measures that only a single CPU can be active in set_mtrr_state() in
 915 *       order to not be subject to races for usage of deftype_lo. This is
 916 *       accomplished by taking cache_disable_lock.
 917 * RETURNS: 0 if no changes made, else a mask indicating what was changed.
 918 */
 919static unsigned long set_mtrr_state(void)
 920{
 921	unsigned long change_mask = 0;
 922	unsigned int i;
 923
 924	for (i = 0; i < num_var_ranges; i++) {
 925		if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i]))
 926			change_mask |= MTRR_CHANGE_MASK_VARIABLE;
 927	}
 928
 929	if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges))
 930		change_mask |= MTRR_CHANGE_MASK_FIXED;
 931
 932	/*
 933	 * Set_mtrr_restore restores the old value of MTRRdefType,
 934	 * so to set it we fiddle with the saved value:
 935	 */
 936	if ((deftype_lo & MTRR_DEF_TYPE_TYPE) != mtrr_state.def_type ||
 937	    ((deftype_lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT) != mtrr_state.enabled) {
 938
 939		deftype_lo = (deftype_lo & MTRR_DEF_TYPE_DISABLE) |
 940			     mtrr_state.def_type |
 941			     (mtrr_state.enabled << MTRR_STATE_SHIFT);
 942		change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
 943	}
 944
 945	return change_mask;
 946}
 947
 948void mtrr_disable(void)
 949{
 950	/* Save MTRR state */
 951	rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
 952
 953	/* Disable MTRRs, and set the default type to uncached */
 954	mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & MTRR_DEF_TYPE_DISABLE, deftype_hi);
 955}
 956
 957void mtrr_enable(void)
 958{
 959	/* Intel (P6) standard MTRRs */
 960	mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
 961}
 962
 963void mtrr_generic_set_state(void)
 964{
 965	unsigned long mask, count;
 966
 967	/* Actually set the state */
 968	mask = set_mtrr_state();
 969
 970	/* Use the atomic bitops to update the global mask */
 971	for (count = 0; count < sizeof(mask) * 8; ++count) {
 972		if (mask & 0x01)
 973			set_bit(count, &smp_changes_mask);
 974		mask >>= 1;
 975	}
 976}
 977
 978/**
 979 * generic_set_mtrr - set variable MTRR register on the local CPU.
 980 *
 981 * @reg: The register to set.
 982 * @base: The base address of the region.
 983 * @size: The size of the region. If this is 0 the region is disabled.
 984 * @type: The type of the region.
 985 *
 986 * Returns nothing.
 987 */
 988static void generic_set_mtrr(unsigned int reg, unsigned long base,
 989			     unsigned long size, mtrr_type type)
 990{
 991	unsigned long flags;
 992	struct mtrr_var_range *vr;
 993
 994	vr = &mtrr_state.var_ranges[reg];
 995
 996	local_irq_save(flags);
 997	cache_disable();
 998
 999	if (size == 0) {
1000		/*
1001		 * The invalid bit is kept in the mask, so we simply
1002		 * clear the relevant mask register to disable a range.
1003		 */
1004		mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0);
1005		memset(vr, 0, sizeof(struct mtrr_var_range));
1006	} else {
1007		vr->base_lo = base << PAGE_SHIFT | type;
1008		vr->base_hi = (base >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd;
1009		vr->mask_lo = -size << PAGE_SHIFT | MTRR_PHYSMASK_V;
1010		vr->mask_hi = (-size >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd;
1011
1012		mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi);
1013		mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi);
1014	}
1015
1016	cache_enable();
1017	local_irq_restore(flags);
1018}
1019
1020int generic_validate_add_page(unsigned long base, unsigned long size,
1021			      unsigned int type)
1022{
1023	unsigned long lbase, last;
1024
1025	/*
1026	 * For Intel PPro stepping <= 7
1027	 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF
1028	 */
1029	if (mtrr_if == &generic_mtrr_ops && boot_cpu_data.x86_vfm == INTEL_PENTIUM_PRO &&
1030	    boot_cpu_data.x86_stepping <= 7) {
1031		if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
1032			pr_warn("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
1033			return -EINVAL;
1034		}
1035		if (!(base + size < 0x70000 || base > 0x7003F) &&
1036		    (type == MTRR_TYPE_WRCOMB
1037		     || type == MTRR_TYPE_WRBACK)) {
1038			pr_warn("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");
1039			return -EINVAL;
1040		}
1041	}
1042
1043	/*
1044	 * Check upper bits of base and last are equal and lower bits are 0
1045	 * for base and 1 for last
1046	 */
1047	last = base + size - 1;
1048	for (lbase = base; !(lbase & 1) && (last & 1);
1049	     lbase = lbase >> 1, last = last >> 1)
1050		;
1051	if (lbase != last) {
1052		pr_warn("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size);
1053		return -EINVAL;
1054	}
1055	return 0;
1056}
1057
1058static int generic_have_wrcomb(void)
1059{
1060	unsigned long config, dummy;
1061	rdmsr(MSR_MTRRcap, config, dummy);
1062	return config & MTRR_CAP_WC;
1063}
1064
1065int positive_have_wrcomb(void)
1066{
1067	return 1;
1068}
1069
1070/*
1071 * Generic structure...
1072 */
1073const struct mtrr_ops generic_mtrr_ops = {
1074	.get			= generic_get_mtrr,
1075	.get_free_region	= generic_get_free_region,
1076	.set			= generic_set_mtrr,
1077	.validate_add_page	= generic_validate_add_page,
1078	.have_wrcomb		= generic_have_wrcomb,
1079};