cpuid.h

  1/******************************************************************************
  2 * arch-x86/cpuid.h
  3 *
  4 * CPUID interface to Xen.
  5 *
  6 * Permission is hereby granted, free of charge, to any person obtaining a copy
  7 * of this software and associated documentation files (the "Software"), to
  8 * deal in the Software without restriction, including without limitation the
  9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
 10 * sell copies of the Software, and to permit persons to whom the Software is
 11 * furnished to do so, subject to the following conditions:
 12 *
 13 * The above copyright notice and this permission notice shall be included in
 14 * all copies or substantial portions of the Software.
 15 *
 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 22 * DEALINGS IN THE SOFTWARE.
 23 *
 24 * Copyright (c) 2007 Citrix Systems, Inc.
 25 *
 26 * Authors:
 27 *    Keir Fraser <keir@xen.org>
 28 */
 29
 30#ifndef __XEN_PUBLIC_ARCH_X86_CPUID_H__
 31#define __XEN_PUBLIC_ARCH_X86_CPUID_H__
 32
 33/*
 34 * For compatibility with other hypervisor interfaces, the Xen cpuid leaves
 35 * can be found at the first otherwise unused 0x100 aligned boundary starting
 36 * from 0x40000000.
 37 *
 38 * e.g If viridian extensions are enabled for an HVM domain, the Xen cpuid
 39 * leaves will start at 0x40000100
 40 */
 41
 42#define XEN_CPUID_FIRST_LEAF 0x40000000
 43#define XEN_CPUID_LEAF(i)    (XEN_CPUID_FIRST_LEAF + (i))
 44
 45/*
 46 * Leaf 1 (0x40000x00)
 47 * EAX: Largest Xen-information leaf. All leaves up to an including @EAX
 48 *      are supported by the Xen host.
 49 * EBX-EDX: "XenVMMXenVMM" signature, allowing positive identification
 50 *      of a Xen host.
 51 */
 52#define XEN_CPUID_SIGNATURE_EBX 0x566e6558 /* "XenV" */
 53#define XEN_CPUID_SIGNATURE_ECX 0x65584d4d /* "MMXe" */
 54#define XEN_CPUID_SIGNATURE_EDX 0x4d4d566e /* "nVMM" */
 55
 56/*
 57 * Leaf 2 (0x40000x01)
 58 * EAX[31:16]: Xen major version.
 59 * EAX[15: 0]: Xen minor version.
 60 * EBX-EDX: Reserved (currently all zeroes).
 61 */
 62
 63/*
 64 * Leaf 3 (0x40000x02)
 65 * EAX: Number of hypercall transfer pages. This register is always guaranteed
 66 *      to specify one hypercall page.
 67 * EBX: Base address of Xen-specific MSRs.
 68 * ECX: Features 1. Unused bits are set to zero.
 69 * EDX: Features 2. Unused bits are set to zero.
 70 */
 71
 72/* Does the host support MMU_PT_UPDATE_PRESERVE_AD for this guest? */
 73#define _XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD 0
 74#define XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD  (1u<<0)
 75
 76/*
 77 * Leaf 4 (0x40000x03)
 78 * Sub-leaf 0: EAX: bit 0: emulated tsc
 79 *                  bit 1: host tsc is known to be reliable
 80 *                  bit 2: RDTSCP instruction available
 81 *             EBX: tsc_mode: 0=default (emulate if necessary), 1=emulate,
 82 *                            2=no emulation, 3=no emulation + TSC_AUX support
 83 *             ECX: guest tsc frequency in kHz
 84 *             EDX: guest tsc incarnation (migration count)
 85 * Sub-leaf 1: EAX: tsc offset low part
 86 *             EBX: tsc offset high part
 87 *             ECX: multiplicator for tsc->ns conversion
 88 *             EDX: shift amount for tsc->ns conversion
 89 * Sub-leaf 2: EAX: host tsc frequency in kHz
 90 */
 91
 92#define XEN_CPUID_TSC_EMULATED               (1u << 0)
 93#define XEN_CPUID_HOST_TSC_RELIABLE          (1u << 1)
 94#define XEN_CPUID_RDTSCP_INSTR_AVAIL         (1u << 2)
 95
 96#define XEN_CPUID_TSC_MODE_DEFAULT           (0)
 97#define XEN_CPUID_TSC_MODE_ALWAYS_EMULATE    (1u)
 98#define XEN_CPUID_TSC_MODE_NEVER_EMULATE     (2u)
 99#define XEN_CPUID_TSC_MODE_PVRDTSCP          (3u)
100
101/*
102 * Leaf 5 (0x40000x04)
103 * HVM-specific features
104 * Sub-leaf 0: EAX: Features
105 * Sub-leaf 0: EBX: vcpu id (iff EAX has XEN_HVM_CPUID_VCPU_ID_PRESENT flag)
106 * Sub-leaf 0: ECX: domain id (iff EAX has XEN_HVM_CPUID_DOMID_PRESENT flag)
107 */
108#define XEN_HVM_CPUID_APIC_ACCESS_VIRT (1u << 0) /* Virtualized APIC registers */
109#define XEN_HVM_CPUID_X2APIC_VIRT      (1u << 1) /* Virtualized x2APIC accesses */
110/* Memory mapped from other domains has valid IOMMU entries */
111#define XEN_HVM_CPUID_IOMMU_MAPPINGS   (1u << 2)
112#define XEN_HVM_CPUID_VCPU_ID_PRESENT  (1u << 3) /* vcpu id is present in EBX */
113#define XEN_HVM_CPUID_DOMID_PRESENT    (1u << 4) /* domid is present in ECX */
114/*
115 * With interrupt format set to 0 (non-remappable) bits 55:49 from the
116 * IO-APIC RTE and bits 11:5 from the MSI address can be used to store
117 * high bits for the Destination ID. This expands the Destination ID
118 * field from 8 to 15 bits, allowing to target APIC IDs up 32768.
119 */
120#define XEN_HVM_CPUID_EXT_DEST_ID      (1u << 5)
121/*
122 * Per-vCPU event channel upcalls work correctly with physical IRQs
123 * bound to event channels.
124 */
125#define XEN_HVM_CPUID_UPCALL_VECTOR    (1u << 6)
126
127/*
128 * Leaf 6 (0x40000x05)
129 * PV-specific parameters
130 * Sub-leaf 0: EAX: max available sub-leaf
131 * Sub-leaf 0: EBX: bits 0-7: max machine address width
132 */
133
134/* Max. address width in bits taking memory hotplug into account. */
135#define XEN_CPUID_MACHINE_ADDRESS_WIDTH_MASK (0xffu << 0)
136
137#define XEN_CPUID_MAX_NUM_LEAVES 5
138
139#endif /* __XEN_PUBLIC_ARCH_X86_CPUID_H__ */