thread_info.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* thread_info.h: low-level thread information
  3 *
  4 * Copyright (C) 2002  David Howells (dhowells@redhat.com)
  5 * - Incorporating suggestions made by Linus Torvalds and Dave Miller
  6 */
  7
  8#ifndef _ASM_X86_THREAD_INFO_H
  9#define _ASM_X86_THREAD_INFO_H
 10
 11#include <linux/compiler.h>
 12#include <asm/page.h>
 13#include <asm/percpu.h>
 14#include <asm/types.h>
 15
 16/*
 17 * TOP_OF_KERNEL_STACK_PADDING is a number of unused bytes that we
 18 * reserve at the top of the kernel stack.  We do it because of a nasty
 19 * 32-bit corner case.  On x86_32, the hardware stack frame is
 20 * variable-length.  Except for vm86 mode, struct pt_regs assumes a
 21 * maximum-length frame.  If we enter from CPL 0, the top 8 bytes of
 22 * pt_regs don't actually exist.  Ordinarily this doesn't matter, but it
 23 * does in at least one case:
 24 *
 25 * If we take an NMI early enough in SYSENTER, then we can end up with
 26 * pt_regs that extends above sp0.  On the way out, in the espfix code,
 27 * we can read the saved SS value, but that value will be above sp0.
 28 * Without this offset, that can result in a page fault.  (We are
 29 * careful that, in this case, the value we read doesn't matter.)
 30 *
 31 * In vm86 mode, the hardware frame is much longer still, so add 16
 32 * bytes to make room for the real-mode segments.
 33 *
 34 * x86-64 has a fixed-length stack frame, but it depends on whether
 35 * or not FRED is enabled. Future versions of FRED might make this
 36 * dynamic, but for now it is always 2 words longer.
 37 */
 38#ifdef CONFIG_X86_32
 39# ifdef CONFIG_VM86
 40#  define TOP_OF_KERNEL_STACK_PADDING 16
 41# else
 42#  define TOP_OF_KERNEL_STACK_PADDING 8
 43# endif
 44#else /* x86-64 */
 45# ifdef CONFIG_X86_FRED
 46#  define TOP_OF_KERNEL_STACK_PADDING (2 * 8)
 47# else
 48#  define TOP_OF_KERNEL_STACK_PADDING 0
 49# endif
 50#endif
 51
 52/*
 53 * low level task data that entry.S needs immediate access to
 54 * - this struct should fit entirely inside of one cache line
 55 * - this struct shares the supervisor stack pages
 56 */
 57#ifndef __ASSEMBLER__
 58struct task_struct;
 59#include <asm/cpufeature.h>
 60#include <linux/atomic.h>
 61
 62struct thread_info {
 63	unsigned long		flags;		/* low level flags */
 64	unsigned long		syscall_work;	/* SYSCALL_WORK_ flags */
 65	u32			status;		/* thread synchronous flags */
 66#ifdef CONFIG_SMP
 67	u32			cpu;		/* current CPU */
 68#endif
 69};
 70
 71#define INIT_THREAD_INFO(tsk)			\
 72{						\
 73	.flags		= 0,			\
 74}
 75
 76#else /* !__ASSEMBLER__ */
 77
 78#include <asm/asm-offsets.h>
 79
 80#endif
 81
 82/*
 83 * Tell the generic TIF infrastructure which bits x86 supports
 84 */
 85#define HAVE_TIF_NEED_RESCHED_LAZY
 86#define HAVE_TIF_POLLING_NRFLAG
 87#define HAVE_TIF_SINGLESTEP
 88
 89#include <asm-generic/thread_info_tif.h>
 90
 91/* Architecture specific TIF space starts at 16 */
 92#define TIF_SSBD		16	/* Speculative store bypass disable */
 93#define TIF_SPEC_IB		17	/* Indirect branch speculation mitigation */
 94#define TIF_SPEC_L1D_FLUSH	18	/* Flush L1D on mm switches (processes) */
 95#define TIF_NEED_FPU_LOAD	19	/* load FPU on return to userspace */
 96#define TIF_NOCPUID		20	/* CPUID is not accessible in userland */
 97#define TIF_NOTSC		21	/* TSC is not accessible in userland */
 98#define TIF_IO_BITMAP		22	/* uses I/O bitmap */
 99#define TIF_SPEC_FORCE_UPDATE	23	/* Force speculation MSR update in context switch */
100#define TIF_FORCED_TF		24	/* true if TF in eflags artificially */
101#define TIF_SINGLESTEP		25	/* reenable singlestep on user return*/
102#define TIF_BLOCKSTEP		26	/* set when we want DEBUGCTLMSR_BTF */
103#define TIF_LAZY_MMU_UPDATES	27	/* task is updating the mmu lazily */
104#define TIF_ADDR32		28	/* 32-bit address space on 64 bits */
105
106#define _TIF_SSBD		BIT(TIF_SSBD)
107#define _TIF_SPEC_IB		BIT(TIF_SPEC_IB)
108#define _TIF_SPEC_L1D_FLUSH	BIT(TIF_SPEC_L1D_FLUSH)
109#define _TIF_NEED_FPU_LOAD	BIT(TIF_NEED_FPU_LOAD)
110#define _TIF_NOCPUID		BIT(TIF_NOCPUID)
111#define _TIF_NOTSC		BIT(TIF_NOTSC)
112#define _TIF_IO_BITMAP		BIT(TIF_IO_BITMAP)
113#define _TIF_SPEC_FORCE_UPDATE	BIT(TIF_SPEC_FORCE_UPDATE)
114#define _TIF_FORCED_TF		BIT(TIF_FORCED_TF)
115#define _TIF_BLOCKSTEP		BIT(TIF_BLOCKSTEP)
116#define _TIF_SINGLESTEP		BIT(TIF_SINGLESTEP)
117#define _TIF_LAZY_MMU_UPDATES	BIT(TIF_LAZY_MMU_UPDATES)
118#define _TIF_ADDR32		BIT(TIF_ADDR32)
119
120/* flags to check in __switch_to() */
121#define _TIF_WORK_CTXSW_BASE					\
122	(_TIF_NOCPUID | _TIF_NOTSC | _TIF_BLOCKSTEP |		\
123	 _TIF_SSBD | _TIF_SPEC_FORCE_UPDATE)
124
125/*
126 * Avoid calls to __switch_to_xtra() on UP as STIBP is not evaluated.
127 */
128#ifdef CONFIG_SMP
129# define _TIF_WORK_CTXSW	(_TIF_WORK_CTXSW_BASE | _TIF_SPEC_IB)
130#else
131# define _TIF_WORK_CTXSW	(_TIF_WORK_CTXSW_BASE)
132#endif
133
134#ifdef CONFIG_X86_IOPL_IOPERM
135# define _TIF_WORK_CTXSW_PREV	(_TIF_WORK_CTXSW| _TIF_USER_RETURN_NOTIFY | \
136				 _TIF_IO_BITMAP)
137#else
138# define _TIF_WORK_CTXSW_PREV	(_TIF_WORK_CTXSW| _TIF_USER_RETURN_NOTIFY)
139#endif
140
141#define _TIF_WORK_CTXSW_NEXT	(_TIF_WORK_CTXSW)
142
143#define STACK_WARN		(THREAD_SIZE/8)
144
145/*
146 * macros/functions for gaining access to the thread information structure
147 *
148 * preempt_count needs to be 1 initially, until the scheduler is functional.
149 */
150#ifndef __ASSEMBLER__
151
152/*
153 * Walks up the stack frames to make sure that the specified object is
154 * entirely contained by a single stack frame.
155 *
156 * Returns:
157 *	GOOD_FRAME	if within a frame
158 *	BAD_STACK	if placed across a frame boundary (or outside stack)
159 *	NOT_STACK	unable to determine (no frame pointers, etc)
160 *
161 * This function reads pointers from the stack and dereferences them. The
162 * pointers may not have their KMSAN shadow set up properly, which may result
163 * in false positive reports. Disable instrumentation to avoid those.
164 */
165__no_kmsan_checks
166static inline int arch_within_stack_frames(const void * const stack,
167					   const void * const stackend,
168					   const void *obj, unsigned long len)
169{
170#if defined(CONFIG_FRAME_POINTER)
171	const void *frame = NULL;
172	const void *oldframe;
173
174	oldframe = __builtin_frame_address(1);
175	if (oldframe)
176		frame = __builtin_frame_address(2);
177	/*
178	 * low ----------------------------------------------> high
179	 * [saved bp][saved ip][args][local vars][saved bp][saved ip]
180	 *                     ^----------------^
181	 *               allow copies only within here
182	 */
183	while (stack <= frame && frame < stackend) {
184		/*
185		 * If obj + len extends past the last frame, this
186		 * check won't pass and the next frame will be 0,
187		 * causing us to bail out and correctly report
188		 * the copy as invalid.
189		 */
190		if (obj + len <= frame)
191			return obj >= oldframe + 2 * sizeof(void *) ?
192				GOOD_FRAME : BAD_STACK;
193		oldframe = frame;
194		frame = *(const void * const *)frame;
195	}
196	return BAD_STACK;
197#else
198	return NOT_STACK;
199#endif
200}
201
202#endif  /* !__ASSEMBLER__ */
203
204/*
205 * Thread-synchronous status.
206 *
207 * This is different from the flags in that nobody else
208 * ever touches our thread-synchronous status, so we don't
209 * have to worry about atomic accesses.
210 */
211#define TS_COMPAT		0x0002	/* 32bit syscall active (64BIT)*/
212
213#ifndef __ASSEMBLER__
214#ifdef CONFIG_COMPAT
215#define TS_I386_REGS_POKED	0x0004	/* regs poked by 32-bit ptracer */
216
217#define arch_set_restart_data(restart)	\
218	do { restart->arch_data = current_thread_info()->status; } while (0)
219
220#endif
221
222#ifdef CONFIG_X86_32
223#define in_ia32_syscall() true
224#else
225#define in_ia32_syscall() (IS_ENABLED(CONFIG_IA32_EMULATION) && \
226			   current_thread_info()->status & TS_COMPAT)
227#endif
228
229extern void arch_setup_new_exec(void);
230#define arch_setup_new_exec arch_setup_new_exec
231#endif	/* !__ASSEMBLER__ */
232
233#endif /* _ASM_X86_THREAD_INFO_H */