mce.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2#ifndef _ASM_X86_MCE_H
  3#define _ASM_X86_MCE_H
  4
  5#include <uapi/asm/mce.h>
  6
  7/*
  8 * Machine Check support for x86
  9 */
 10
 11/* MCG_CAP register defines */
 12#define MCG_BANKCNT_MASK	0xff         /* Number of Banks */
 13#define MCG_CTL_P		BIT_ULL(8)   /* MCG_CTL register available */
 14#define MCG_EXT_P		BIT_ULL(9)   /* Extended registers available */
 15#define MCG_CMCI_P		BIT_ULL(10)  /* CMCI supported */
 16#define MCG_SEAM_NR		BIT_ULL(12)  /* MCG_STATUS_SEAM_NR supported */
 17#define MCG_EXT_CNT_MASK	0xff0000     /* Number of Extended registers */
 18#define MCG_EXT_CNT_SHIFT	16
 19#define MCG_EXT_CNT(c)		(((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
 20#define MCG_SER_P		BIT_ULL(24)  /* MCA recovery/new status bits */
 21#define MCG_ELOG_P		BIT_ULL(26)  /* Extended error log supported */
 22#define MCG_LMCE_P		BIT_ULL(27)  /* Local machine check supported */
 23
 24/* MCG_STATUS register defines */
 25#define MCG_STATUS_RIPV		BIT_ULL(0)   /* restart ip valid */
 26#define MCG_STATUS_EIPV		BIT_ULL(1)   /* ip points to correct instruction */
 27#define MCG_STATUS_MCIP		BIT_ULL(2)   /* machine check in progress */
 28#define MCG_STATUS_LMCES	BIT_ULL(3)   /* LMCE signaled */
 29#define MCG_STATUS_SEAM_NR	BIT_ULL(12)  /* Machine check inside SEAM non-root mode */
 30
 31/* MCG_EXT_CTL register defines */
 32#define MCG_EXT_CTL_LMCE_EN	BIT_ULL(0) /* Enable LMCE */
 33
 34/* MCi_STATUS register defines */
 35#define MCI_STATUS_VAL		BIT_ULL(63)  /* valid error */
 36#define MCI_STATUS_OVER		BIT_ULL(62)  /* previous errors lost */
 37#define MCI_STATUS_UC		BIT_ULL(61)  /* uncorrected error */
 38#define MCI_STATUS_EN		BIT_ULL(60)  /* error enabled */
 39#define MCI_STATUS_MISCV	BIT_ULL(59)  /* misc error reg. valid */
 40#define MCI_STATUS_ADDRV	BIT_ULL(58)  /* addr reg. valid */
 41#define MCI_STATUS_PCC		BIT_ULL(57)  /* processor context corrupt */
 42#define MCI_STATUS_S		BIT_ULL(56)  /* Signaled machine check */
 43#define MCI_STATUS_AR		BIT_ULL(55)  /* Action required */
 44#define MCI_STATUS_CEC_SHIFT	38           /* Corrected Error Count */
 45#define MCI_STATUS_CEC_MASK	GENMASK_ULL(52,38)
 46#define MCI_STATUS_CEC(c)	(((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)
 47#define MCI_STATUS_MSCOD(m)	(((m) >> 16) & 0xffff)
 48
 49/* AMD-specific bits */
 50#define MCI_STATUS_TCC		BIT_ULL(55)  /* Task context corrupt */
 51#define MCI_STATUS_PADDRV	BIT_ULL(54)  /* Valid System Physical Address */
 52#define MCI_STATUS_SYNDV	BIT_ULL(53)  /* synd reg. valid */
 53#define MCI_STATUS_DEFERRED	BIT_ULL(44)  /* uncorrected error, deferred exception */
 54#define MCI_STATUS_POISON	BIT_ULL(43)  /* access poisonous data */
 55#define MCI_STATUS_SCRUB	BIT_ULL(40)  /* Error detected during scrub operation */
 56
 57/*
 58 * McaX field if set indicates a given bank supports MCA extensions:
 59 *  - Deferred error interrupt type is specifiable by bank.
 60 *  - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
 61 *    But should not be used to determine MSR numbers.
 62 *  - TCC bit is present in MCx_STATUS.
 63 */
 64#define MCI_CONFIG_MCAX		0x1
 65#define MCI_CONFIG_FRUTEXT	BIT_ULL(9)
 66#define MCI_CONFIG_PADDRV	BIT_ULL(11)
 67#define MCI_IPID_MCATYPE	0xFFFF0000
 68#define MCI_IPID_HWID		0xFFF
 69
 70/*
 71 * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
 72 * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
 73 * errors to indicate that errors are being filtered by hardware.
 74 * We should mask out bit 12 when looking for specific signatures
 75 * of uncorrected errors - so the F bit is deliberately skipped
 76 * in this #define.
 77 */
 78#define MCACOD		  0xefff     /* MCA Error Code */
 79
 80/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
 81#define MCACOD_SCRUB	0x00C0	/* 0xC0-0xCF Memory Scrubbing */
 82#define MCACOD_SCRUBMSK	0xeff0	/* Skip bit 12 ('F' bit) */
 83#define MCACOD_L3WB	0x017A	/* L3 Explicit Writeback */
 84#define MCACOD_DATA	0x0134	/* Data Load */
 85#define MCACOD_INSTR	0x0150	/* Instruction Fetch */
 86
 87/* MCi_MISC register defines */
 88#define MCI_MISC_ADDR_LSB(m)	((m) & 0x3f)
 89#define MCI_MISC_ADDR_MODE(m)	(((m) >> 6) & 7)
 90#define  MCI_MISC_ADDR_SEGOFF	0	/* segment offset */
 91#define  MCI_MISC_ADDR_LINEAR	1	/* linear address */
 92#define  MCI_MISC_ADDR_PHYS	2	/* physical address */
 93#define  MCI_MISC_ADDR_MEM	3	/* memory address */
 94#define  MCI_MISC_ADDR_GENERIC	7	/* generic */
 95
 96/* MCi_ADDR register defines */
 97#define MCI_ADDR_PHYSADDR	GENMASK_ULL(boot_cpu_data.x86_phys_bits - 1, 0)
 98
 99/* CTL2 register defines */
100#define MCI_CTL2_CMCI_EN		BIT_ULL(30)
101#define MCI_CTL2_CMCI_THRESHOLD_MASK	0x7fffULL
102
103#define MCJ_CTX_MASK		3
104#define MCJ_CTX(flags)		((flags) & MCJ_CTX_MASK)
105#define MCJ_CTX_RANDOM		0    /* inject context: random */
106#define MCJ_CTX_PROCESS		0x1  /* inject context: process */
107#define MCJ_CTX_IRQ		0x2  /* inject context: IRQ */
108#define MCJ_NMI_BROADCAST	0x4  /* do NMI broadcasting */
109#define MCJ_EXCEPTION		0x8  /* raise as exception */
110#define MCJ_IRQ_BROADCAST	0x10 /* do IRQ broadcasting */
111
112#define MCE_OVERFLOW 0		/* bit 0 in flags means overflow */
113
114#define MCE_LOG_MIN_LEN 32U
115#define MCE_LOG_SIGNATURE	"MACHINECHECK"
116
117/* AMD Scalable MCA */
118#define MSR_AMD64_SMCA_MC0_CTL		0xc0002000
119#define MSR_AMD64_SMCA_MC0_STATUS	0xc0002001
120#define MSR_AMD64_SMCA_MC0_ADDR		0xc0002002
121#define MSR_AMD64_SMCA_MC0_MISC0	0xc0002003
122#define MSR_AMD64_SMCA_MC0_CONFIG	0xc0002004
123#define MSR_AMD64_SMCA_MC0_IPID		0xc0002005
124#define MSR_AMD64_SMCA_MC0_SYND		0xc0002006
125#define MSR_AMD64_SMCA_MC0_DESTAT	0xc0002008
126#define MSR_AMD64_SMCA_MC0_DEADDR	0xc0002009
127#define MSR_AMD64_SMCA_MC0_MISC1	0xc000200a
128/* Registers MISC2 to MISC4 are at offsets B to D. */
129#define MSR_AMD64_SMCA_MC0_SYND1	0xc000200e
130#define MSR_AMD64_SMCA_MC0_SYND2	0xc000200f
131#define MSR_AMD64_SMCA_MCx_CTL(x)	(MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
132#define MSR_AMD64_SMCA_MCx_STATUS(x)	(MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
133#define MSR_AMD64_SMCA_MCx_ADDR(x)	(MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
134#define MSR_AMD64_SMCA_MCx_MISC(x)	(MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
135#define MSR_AMD64_SMCA_MCx_CONFIG(x)	(MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
136#define MSR_AMD64_SMCA_MCx_IPID(x)	(MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
137#define MSR_AMD64_SMCA_MCx_SYND(x)	(MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))
138#define MSR_AMD64_SMCA_MCx_DESTAT(x)	(MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
139#define MSR_AMD64_SMCA_MCx_DEADDR(x)	(MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
140#define MSR_AMD64_SMCA_MCx_MISCy(x, y)	((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
141#define MSR_AMD64_SMCA_MCx_SYND1(x)	(MSR_AMD64_SMCA_MC0_SYND1 + 0x10*(x))
142#define MSR_AMD64_SMCA_MCx_SYND2(x)	(MSR_AMD64_SMCA_MC0_SYND2 + 0x10*(x))
143
144#define XEC(x, mask)			(((x) >> 16) & mask)
145
146/* mce.kflags flag bits for logging etc. */
147#define	MCE_HANDLED_CEC		BIT_ULL(0)
148#define	MCE_HANDLED_UC		BIT_ULL(1)
149#define	MCE_HANDLED_EXTLOG	BIT_ULL(2)
150#define	MCE_HANDLED_NFIT	BIT_ULL(3)
151#define	MCE_HANDLED_EDAC	BIT_ULL(4)
152#define	MCE_HANDLED_MCELOG	BIT_ULL(5)
153
154/*
155 * Indicates an MCE which has happened in kernel space but from
156 * which the kernel can recover simply by executing fixup_exception()
157 * so that an error is returned to the caller of the function that
158 * hit the machine check.
159 */
160#define MCE_IN_KERNEL_RECOV	BIT_ULL(6)
161
162/*
163 * Indicates an MCE that happened in kernel space while copying data
164 * from user. In this case fixup_exception() gets the kernel to the
165 * error exit for the copy function. Machine check handler can then
166 * treat it like a fault taken in user mode.
167 */
168#define MCE_IN_KERNEL_COPYIN	BIT_ULL(7)
169
170/*
171 * Indicates that handler should check and clear Deferred error registers
172 * rather than common ones.
173 */
174#define MCE_CHECK_DFR_REGS	BIT_ULL(8)
175
176/*
177 * This structure contains all data related to the MCE log.  Also
178 * carries a signature to make it easier to find from external
179 * debugging tools.  Each entry is only valid when its finished flag
180 * is set.
181 */
182struct mce_log_buffer {
183	char signature[12]; /* "MACHINECHECK" */
184	unsigned len;	    /* = elements in .mce_entry[] */
185	unsigned next;
186	unsigned flags;
187	unsigned recordlen;	/* length of struct mce */
188	struct mce entry[];
189};
190
191/* Highest last */
192enum mce_notifier_prios {
193	MCE_PRIO_LOWEST,
194	MCE_PRIO_MCELOG,
195	MCE_PRIO_EDAC,
196	MCE_PRIO_NFIT,
197	MCE_PRIO_EXTLOG,
198	MCE_PRIO_UC,
199	MCE_PRIO_EARLY,
200	MCE_PRIO_CEC,
201	MCE_PRIO_HIGHEST = MCE_PRIO_CEC
202};
203
204/**
205 * struct mce_hw_err - Hardware Error Record.
206 * @m:		Machine Check record.
207 * @vendor:	Vendor-specific error information.
208 *
209 * Vendor-specific fields should not be added to struct mce. Instead, vendors
210 * should export their vendor-specific data through their structure in the
211 * vendor union below.
212 *
213 * AMD's vendor data is parsed by error decoding tools for supplemental error
214 * information. Thus, current offsets of existing fields must be maintained.
215 * Only add new fields at the end of AMD's vendor structure.
216 */
217struct mce_hw_err {
218	struct mce m;
219
220	union vendor_info {
221		struct {
222			u64 synd1;		/* MCA_SYND1 MSR */
223			u64 synd2;		/* MCA_SYND2 MSR */
224		} amd;
225	} vendor;
226};
227
228#define	to_mce_hw_err(mce) container_of(mce, struct mce_hw_err, m)
229
230struct notifier_block;
231extern void mce_register_decode_chain(struct notifier_block *nb);
232extern void mce_unregister_decode_chain(struct notifier_block *nb);
233
234#include <linux/percpu.h>
235#include <linux/atomic.h>
236
237extern int mce_p5_enabled;
238
239#ifdef CONFIG_ARCH_HAS_COPY_MC
240extern void enable_copy_mc_fragile(void);
241unsigned long __must_check copy_mc_fragile(void *dst, const void *src, unsigned cnt);
242#else
243static inline void enable_copy_mc_fragile(void)
244{
245}
246#endif
247
248struct cper_ia_proc_ctx;
249
250#ifdef CONFIG_X86_MCE
251int mcheck_init(void);
252void mca_bsp_init(struct cpuinfo_x86 *c);
253void mcheck_cpu_init(struct cpuinfo_x86 *c);
254void mcheck_cpu_clear(struct cpuinfo_x86 *c);
255int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
256			       u64 lapic_id);
257#else
258static inline int mcheck_init(void) { return 0; }
259static inline void mca_bsp_init(struct cpuinfo_x86 *c) {}
260static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
261static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
262static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
263					     u64 lapic_id) { return -EINVAL; }
264#endif
265
266void mce_prep_record(struct mce_hw_err *err);
267void mce_log(struct mce_hw_err *err);
268DECLARE_PER_CPU(struct device *, mce_device);
269
270/* Maximum number of MCA banks per CPU. */
271#define MAX_NR_BANKS 64
272
273#ifdef CONFIG_X86_MCE_INTEL
274void mce_intel_feature_init(struct cpuinfo_x86 *c);
275void mce_intel_feature_clear(struct cpuinfo_x86 *c);
276void cmci_clear(void);
277void cmci_reenable(void);
278void cmci_rediscover(void);
279void cmci_recheck(void);
280#else
281static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
282static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
283static inline void cmci_clear(void) {}
284static inline void cmci_reenable(void) {}
285static inline void cmci_rediscover(void) {}
286static inline void cmci_recheck(void) {}
287#endif
288
289bool mce_available(struct cpuinfo_x86 *c);
290bool mce_is_memory_error(struct mce *m);
291bool mce_is_correctable(struct mce *m);
292bool mce_usable_address(struct mce *m);
293
294DECLARE_PER_CPU(unsigned, mce_exception_count);
295DECLARE_PER_CPU(unsigned, mce_poll_count);
296
297typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
298DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
299
300enum mcp_flags {
301	MCP_TIMESTAMP	= BIT(0),	/* log time stamp */
302	MCP_UC		= BIT(1),	/* log uncorrected errors */
303	MCP_QUEUE_LOG	= BIT(2),	/* only queue to genpool */
304};
305
306void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
307
308DECLARE_PER_CPU(struct mce, injectm);
309
310/* Disable CMCI/polling for MCA bank claimed by firmware */
311extern void mce_disable_bank(int bank);
312
313#ifdef CONFIG_X86_MCE_THRESHOLD
314void mce_save_apei_thr_limit(u32 thr_limit);
315#else
316static inline void mce_save_apei_thr_limit(u32 thr_limit) { }
317#endif /* CONFIG_X86_MCE_THRESHOLD */
318
319/*
320 * Exception handler
321 */
322void do_machine_check(struct pt_regs *pt_regs);
323
324/*
325 * Threshold handler
326 */
327extern void (*mce_threshold_vector)(void);
328
329/* Deferred error interrupt handler */
330extern void (*deferred_error_int_vector)(void);
331
332/*
333 * Used by APEI to report memory error via /dev/mcelog
334 */
335
336struct cper_sec_mem_err;
337extern void apei_mce_report_mem_error(int corrected,
338				      struct cper_sec_mem_err *mem_err);
339
340/*
341 * Enumerate new IP types and HWID values in AMD processors which support
342 * Scalable MCA.
343 */
344#ifdef CONFIG_X86_MCE_AMD
345
346/* These may be used by multiple smca_hwid_mcatypes */
347enum smca_bank_types {
348	SMCA_LS = 0,	/* Load Store */
349	SMCA_LS_V2,
350	SMCA_IF,	/* Instruction Fetch */
351	SMCA_L2_CACHE,	/* L2 Cache */
352	SMCA_DE,	/* Decoder Unit */
353	SMCA_RESERVED,	/* Reserved */
354	SMCA_EX,	/* Execution Unit */
355	SMCA_FP,	/* Floating Point */
356	SMCA_L3_CACHE,	/* L3 Cache */
357	SMCA_CS,	/* Coherent Slave */
358	SMCA_CS_V2,
359	SMCA_PIE,	/* Power, Interrupts, etc. */
360	SMCA_UMC,	/* Unified Memory Controller */
361	SMCA_UMC_V2,
362	SMCA_MA_LLC,	/* Memory Attached Last Level Cache */
363	SMCA_PB,	/* Parameter Block */
364	SMCA_PSP,	/* Platform Security Processor */
365	SMCA_PSP_V2,
366	SMCA_SMU,	/* System Management Unit */
367	SMCA_SMU_V2,
368	SMCA_MP5,	/* Microprocessor 5 Unit */
369	SMCA_MPDMA,	/* MPDMA Unit */
370	SMCA_NBIO,	/* Northbridge IO Unit */
371	SMCA_PCIE,	/* PCI Express Unit */
372	SMCA_PCIE_V2,
373	SMCA_XGMI_PCS,	/* xGMI PCS Unit */
374	SMCA_NBIF,	/* NBIF Unit */
375	SMCA_SHUB,	/* System HUB Unit */
376	SMCA_SATA,	/* SATA Unit */
377	SMCA_USB,	/* USB Unit */
378	SMCA_USR_DP,	/* Ultra Short Reach Data Plane Controller */
379	SMCA_USR_CP,	/* Ultra Short Reach Control Plane Controller */
380	SMCA_GMI_PCS,	/* GMI PCS Unit */
381	SMCA_XGMI_PHY,	/* xGMI PHY Unit */
382	SMCA_WAFL_PHY,	/* WAFL PHY Unit */
383	SMCA_GMI_PHY,	/* GMI PHY Unit */
384	N_SMCA_BANK_TYPES
385};
386
387extern bool amd_mce_is_memory_error(struct mce *m);
388
389void mce_amd_feature_init(struct cpuinfo_x86 *c);
390enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank);
391#else
392static inline bool amd_mce_is_memory_error(struct mce *m)		{ return false; };
393static inline void mce_amd_feature_init(struct cpuinfo_x86 *c)		{ }
394#endif
395
396unsigned long copy_mc_fragile_handle_tail(char *to, char *from, unsigned len);
397
398#endif /* _ASM_X86_MCE_H */