types.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2#ifndef _ASM_X86_CPUID_TYPES_H
  3#define _ASM_X86_CPUID_TYPES_H
  4
  5#include <linux/build_bug.h>
  6#include <linux/types.h>
  7
  8/*
  9 * Types for raw CPUID access:
 10 */
 11
 12struct cpuid_regs {
 13	u32 eax;
 14	u32 ebx;
 15	u32 ecx;
 16	u32 edx;
 17};
 18
 19enum cpuid_regs_idx {
 20	CPUID_EAX = 0,
 21	CPUID_EBX,
 22	CPUID_ECX,
 23	CPUID_EDX,
 24};
 25
 26#define CPUID_LEAF_MWAIT	0x05
 27#define CPUID_LEAF_DCA		0x09
 28#define CPUID_LEAF_XSTATE	0x0d
 29#define CPUID_LEAF_TSC		0x15
 30#define CPUID_LEAF_FREQ		0x16
 31#define CPUID_LEAF_TILE		0x1d
 32
 33/*
 34 * Types for CPUID(0x2) parsing:
 35 */
 36
 37struct leaf_0x2_reg {
 38		u32		: 31,
 39			invalid	: 1;
 40};
 41
 42union leaf_0x2_regs {
 43	struct leaf_0x2_reg	reg[4];
 44	u32			regv[4];
 45	u8			desc[16];
 46};
 47
 48/*
 49 * Leaf 0x2 1-byte descriptors' cache types
 50 * To be used for their mappings at cpuid_0x2_table[]
 51 *
 52 * Start at 1 since type 0 is reserved for HW byte descriptors which are
 53 * not recognized by the kernel; i.e., those without an explicit mapping.
 54 */
 55enum _cache_table_type {
 56	CACHE_L1_INST		= 1,
 57	CACHE_L1_DATA,
 58	CACHE_L2,
 59	CACHE_L3
 60	/* Adjust __TLB_TABLE_TYPE_BEGIN before adding more types */
 61} __packed;
 62#ifndef __CHECKER__
 63static_assert(sizeof(enum _cache_table_type) == 1);
 64#endif
 65
 66/*
 67 * Ensure that leaf 0x2 cache and TLB type values do not intersect,
 68 * since they share the same type field at struct cpuid_0x2_table.
 69 */
 70#define __TLB_TABLE_TYPE_BEGIN		(CACHE_L3 + 1)
 71
 72/*
 73 * Leaf 0x2 1-byte descriptors' TLB types
 74 * To be used for their mappings at cpuid_0x2_table[]
 75 */
 76enum _tlb_table_type {
 77	TLB_INST_4K		= __TLB_TABLE_TYPE_BEGIN,
 78	TLB_INST_4M,
 79	TLB_INST_2M_4M,
 80	TLB_INST_ALL,
 81
 82	TLB_DATA_4K,
 83	TLB_DATA_4M,
 84	TLB_DATA_2M_4M,
 85	TLB_DATA_4K_4M,
 86	TLB_DATA_1G,
 87	TLB_DATA_1G_2M_4M,
 88
 89	TLB_DATA0_4K,
 90	TLB_DATA0_4M,
 91	TLB_DATA0_2M_4M,
 92
 93	STLB_4K,
 94	STLB_4K_2M,
 95} __packed;
 96#ifndef __CHECKER__
 97static_assert(sizeof(enum _tlb_table_type) == 1);
 98#endif
 99
100/*
101 * Combined parsing table for leaf 0x2 cache and TLB descriptors.
102 */
103
104struct leaf_0x2_table {
105	union {
106		enum _cache_table_type	c_type;
107		enum _tlb_table_type	t_type;
108	};
109	union {
110		short			c_size;
111		short			entries;
112	};
113};
114
115extern const struct leaf_0x2_table cpuid_0x2_table[256];
116
117/*
118 * All of leaf 0x2's one-byte TLB descriptors implies the same number of entries
119 * for their respective TLB types.  TLB descriptor 0x63 is an exception: it
120 * implies 4 dTLB entries for 1GB pages and 32 dTLB entries for 2MB or 4MB pages.
121 *
122 * Encode that descriptor's dTLB entry count for 2MB/4MB pages here, as the entry
123 * count for dTLB 1GB pages is already encoded at the cpuid_0x2_table[]'s mapping.
124 */
125#define TLB_0x63_2M_4M_ENTRIES		32
126
127#endif /* _ASM_X86_CPUID_TYPES_H */