FILE
uncore_snbep.c
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linux-6.19.14/arch/x86/events/intel/uncore_snbep.c
1// SPDX-License-Identifier: GPL-2.0 2/* SandyBridge-EP/IvyTown uncore support */ 3#include <asm/cpu_device_id.h> 4#include <asm/msr.h> 5#include "uncore.h" 6#include "uncore_discovery.h" 7 8/* SNB-EP pci bus to socket mapping */ 9#define SNBEP_CPUNODEID 0x40 10#define SNBEP_GIDNIDMAP 0x54 11 12/* SNB-EP Box level control */ 13#define SNBEP_PMON_BOX_CTL_RST_CTRL (1 << 0) 14#define SNBEP_PMON_BOX_CTL_RST_CTRS (1 << 1) 15#define SNBEP_PMON_BOX_CTL_FRZ (1 << 8) 16#define SNBEP_PMON_BOX_CTL_FRZ_EN (1 << 16) 17#define SNBEP_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \ 18 SNBEP_PMON_BOX_CTL_RST_CTRS | \ 19 SNBEP_PMON_BOX_CTL_FRZ_EN) 20/* SNB-EP event control */ 21#define SNBEP_PMON_CTL_EV_SEL_MASK 0x000000ff 22#define SNBEP_PMON_CTL_UMASK_MASK 0x0000ff00 23#define SNBEP_PMON_CTL_RST (1 << 17) 24#define SNBEP_PMON_CTL_EDGE_DET (1 << 18) 25#define SNBEP_PMON_CTL_EV_SEL_EXT (1 << 21) 26#define SNBEP_PMON_CTL_EN (1 << 22) 27#define SNBEP_PMON_CTL_INVERT (1 << 23) 28#define SNBEP_PMON_CTL_TRESH_MASK 0xff000000 29#define SNBEP_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \ 30 SNBEP_PMON_CTL_UMASK_MASK | \ 31 SNBEP_PMON_CTL_EDGE_DET | \ 32 SNBEP_PMON_CTL_INVERT | \ 33 SNBEP_PMON_CTL_TRESH_MASK) 34 35/* SNB-EP Ubox event control */ 36#define SNBEP_U_MSR_PMON_CTL_TRESH_MASK 0x1f000000 37#define SNBEP_U_MSR_PMON_RAW_EVENT_MASK \ 38 (SNBEP_PMON_CTL_EV_SEL_MASK | \ 39 SNBEP_PMON_CTL_UMASK_MASK | \ 40 SNBEP_PMON_CTL_EDGE_DET | \ 41 SNBEP_PMON_CTL_INVERT | \ 42 SNBEP_U_MSR_PMON_CTL_TRESH_MASK) 43 44#define SNBEP_CBO_PMON_CTL_TID_EN (1 << 19) 45#define SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \ 46 SNBEP_CBO_PMON_CTL_TID_EN) 47 48/* SNB-EP PCU event control */ 49#define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK 0x0000c000 50#define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK 0x1f000000 51#define SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT (1 << 30) 52#define SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET (1 << 31) 53#define SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK \ 54 (SNBEP_PMON_CTL_EV_SEL_MASK | \ 55 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ 56 SNBEP_PMON_CTL_EDGE_DET | \ 57 SNBEP_PMON_CTL_INVERT | \ 58 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \ 59 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \ 60 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET) 61 62#define SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK \ 63 (SNBEP_PMON_RAW_EVENT_MASK | \ 64 SNBEP_PMON_CTL_EV_SEL_EXT) 65 66/* SNB-EP pci control register */ 67#define SNBEP_PCI_PMON_BOX_CTL 0xf4 68#define SNBEP_PCI_PMON_CTL0 0xd8 69/* SNB-EP pci counter register */ 70#define SNBEP_PCI_PMON_CTR0 0xa0 71 72/* SNB-EP home agent register */ 73#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0 0x40 74#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1 0x44 75#define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH 0x48 76/* SNB-EP memory controller register */ 77#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL 0xf0 78#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR 0xd0 79/* SNB-EP QPI register */ 80#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0 0x228 81#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1 0x22c 82#define SNBEP_Q_Py_PCI_PMON_PKT_MASK0 0x238 83#define SNBEP_Q_Py_PCI_PMON_PKT_MASK1 0x23c 84 85/* SNB-EP Ubox register */ 86#define SNBEP_U_MSR_PMON_CTR0 0xc16 87#define SNBEP_U_MSR_PMON_CTL0 0xc10 88 89#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL 0xc08 90#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR 0xc09 91 92/* SNB-EP Cbo register */ 93#define SNBEP_C0_MSR_PMON_CTR0 0xd16 94#define SNBEP_C0_MSR_PMON_CTL0 0xd10 95#define SNBEP_C0_MSR_PMON_BOX_CTL 0xd04 96#define SNBEP_C0_MSR_PMON_BOX_FILTER 0xd14 97#define SNBEP_CBO_MSR_OFFSET 0x20 98 99#define SNBEP_CB0_MSR_PMON_BOX_FILTER_TID 0x1f 100#define SNBEP_CB0_MSR_PMON_BOX_FILTER_NID 0x3fc00 101#define SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE 0x7c0000 102#define SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC 0xff800000 103 104#define SNBEP_CBO_EVENT_EXTRA_REG(e, m, i) { \ 105 .event = (e), \ 106 .msr = SNBEP_C0_MSR_PMON_BOX_FILTER, \ 107 .config_mask = (m), \ 108 .idx = (i) \ 109} 110 111/* SNB-EP PCU register */ 112#define SNBEP_PCU_MSR_PMON_CTR0 0xc36 113#define SNBEP_PCU_MSR_PMON_CTL0 0xc30 114#define SNBEP_PCU_MSR_PMON_BOX_CTL 0xc24 115#define SNBEP_PCU_MSR_PMON_BOX_FILTER 0xc34 116#define SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK 0xffffffff 117#define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc 118#define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd 119 120/* IVBEP event control */ 121#define IVBEP_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \ 122 SNBEP_PMON_BOX_CTL_RST_CTRS) 123#define IVBEP_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \ 124 SNBEP_PMON_CTL_UMASK_MASK | \ 125 SNBEP_PMON_CTL_EDGE_DET | \ 126 SNBEP_PMON_CTL_TRESH_MASK) 127/* IVBEP Ubox */ 128#define IVBEP_U_MSR_PMON_GLOBAL_CTL 0xc00 129#define IVBEP_U_PMON_GLOBAL_FRZ_ALL (1 << 31) 130#define IVBEP_U_PMON_GLOBAL_UNFRZ_ALL (1 << 29) 131 132#define IVBEP_U_MSR_PMON_RAW_EVENT_MASK \ 133 (SNBEP_PMON_CTL_EV_SEL_MASK | \ 134 SNBEP_PMON_CTL_UMASK_MASK | \ 135 SNBEP_PMON_CTL_EDGE_DET | \ 136 SNBEP_U_MSR_PMON_CTL_TRESH_MASK) 137/* IVBEP Cbo */ 138#define IVBEP_CBO_MSR_PMON_RAW_EVENT_MASK (IVBEP_PMON_RAW_EVENT_MASK | \ 139 SNBEP_CBO_PMON_CTL_TID_EN) 140 141#define IVBEP_CB0_MSR_PMON_BOX_FILTER_TID (0x1fULL << 0) 142#define IVBEP_CB0_MSR_PMON_BOX_FILTER_LINK (0xfULL << 5) 143#define IVBEP_CB0_MSR_PMON_BOX_FILTER_STATE (0x3fULL << 17) 144#define IVBEP_CB0_MSR_PMON_BOX_FILTER_NID (0xffffULL << 32) 145#define IVBEP_CB0_MSR_PMON_BOX_FILTER_OPC (0x1ffULL << 52) 146#define IVBEP_CB0_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61) 147#define IVBEP_CB0_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62) 148#define IVBEP_CB0_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63) 149 150/* IVBEP home agent */ 151#define IVBEP_HA_PCI_PMON_CTL_Q_OCC_RST (1 << 16) 152#define IVBEP_HA_PCI_PMON_RAW_EVENT_MASK \ 153 (IVBEP_PMON_RAW_EVENT_MASK | \ 154 IVBEP_HA_PCI_PMON_CTL_Q_OCC_RST) 155/* IVBEP PCU */ 156#define IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK \ 157 (SNBEP_PMON_CTL_EV_SEL_MASK | \ 158 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ 159 SNBEP_PMON_CTL_EDGE_DET | \ 160 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \ 161 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \ 162 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET) 163/* IVBEP QPI */ 164#define IVBEP_QPI_PCI_PMON_RAW_EVENT_MASK \ 165 (IVBEP_PMON_RAW_EVENT_MASK | \ 166 SNBEP_PMON_CTL_EV_SEL_EXT) 167 168#define __BITS_VALUE(x, i, n) ((typeof(x))(((x) >> ((i) * (n))) & \ 169 ((1ULL << (n)) - 1))) 170 171/* Haswell-EP Ubox */ 172#define HSWEP_U_MSR_PMON_CTR0 0x709 173#define HSWEP_U_MSR_PMON_CTL0 0x705 174#define HSWEP_U_MSR_PMON_FILTER 0x707 175 176#define HSWEP_U_MSR_PMON_UCLK_FIXED_CTL 0x703 177#define HSWEP_U_MSR_PMON_UCLK_FIXED_CTR 0x704 178 179#define HSWEP_U_MSR_PMON_BOX_FILTER_TID (0x1 << 0) 180#define HSWEP_U_MSR_PMON_BOX_FILTER_CID (0x1fULL << 1) 181#define HSWEP_U_MSR_PMON_BOX_FILTER_MASK \ 182 (HSWEP_U_MSR_PMON_BOX_FILTER_TID | \ 183 HSWEP_U_MSR_PMON_BOX_FILTER_CID) 184 185/* Haswell-EP CBo */ 186#define HSWEP_C0_MSR_PMON_CTR0 0xe08 187#define HSWEP_C0_MSR_PMON_CTL0 0xe01 188#define HSWEP_C0_MSR_PMON_BOX_CTL 0xe00 189#define HSWEP_C0_MSR_PMON_BOX_FILTER0 0xe05 190#define HSWEP_CBO_MSR_OFFSET 0x10 191 192 193#define HSWEP_CB0_MSR_PMON_BOX_FILTER_TID (0x3fULL << 0) 194#define HSWEP_CB0_MSR_PMON_BOX_FILTER_LINK (0xfULL << 6) 195#define HSWEP_CB0_MSR_PMON_BOX_FILTER_STATE (0x7fULL << 17) 196#define HSWEP_CB0_MSR_PMON_BOX_FILTER_NID (0xffffULL << 32) 197#define HSWEP_CB0_MSR_PMON_BOX_FILTER_OPC (0x1ffULL << 52) 198#define HSWEP_CB0_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61) 199#define HSWEP_CB0_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62) 200#define HSWEP_CB0_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63) 201 202 203/* Haswell-EP Sbox */ 204#define HSWEP_S0_MSR_PMON_CTR0 0x726 205#define HSWEP_S0_MSR_PMON_CTL0 0x721 206#define HSWEP_S0_MSR_PMON_BOX_CTL 0x720 207#define HSWEP_SBOX_MSR_OFFSET 0xa 208#define HSWEP_S_MSR_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \ 209 SNBEP_CBO_PMON_CTL_TID_EN) 210 211/* Haswell-EP PCU */ 212#define HSWEP_PCU_MSR_PMON_CTR0 0x717 213#define HSWEP_PCU_MSR_PMON_CTL0 0x711 214#define HSWEP_PCU_MSR_PMON_BOX_CTL 0x710 215#define HSWEP_PCU_MSR_PMON_BOX_FILTER 0x715 216 217/* KNL Ubox */ 218#define KNL_U_MSR_PMON_RAW_EVENT_MASK \ 219 (SNBEP_U_MSR_PMON_RAW_EVENT_MASK | \ 220 SNBEP_CBO_PMON_CTL_TID_EN) 221/* KNL CHA */ 222#define KNL_CHA_MSR_OFFSET 0xc 223#define KNL_CHA_MSR_PMON_CTL_QOR (1 << 16) 224#define KNL_CHA_MSR_PMON_RAW_EVENT_MASK \ 225 (SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK | \ 226 KNL_CHA_MSR_PMON_CTL_QOR) 227#define KNL_CHA_MSR_PMON_BOX_FILTER_TID 0x1ff 228#define KNL_CHA_MSR_PMON_BOX_FILTER_STATE (7 << 18) 229#define KNL_CHA_MSR_PMON_BOX_FILTER_OP (0xfffffe2aULL << 32) 230#define KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE (0x1ULL << 32) 231#define KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE (0x1ULL << 33) 232#define KNL_CHA_MSR_PMON_BOX_FILTER_NNC (0x1ULL << 37) 233 234/* KNL EDC/MC UCLK */ 235#define KNL_UCLK_MSR_PMON_CTR0_LOW 0x400 236#define KNL_UCLK_MSR_PMON_CTL0 0x420 237#define KNL_UCLK_MSR_PMON_BOX_CTL 0x430 238#define KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW 0x44c 239#define KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL 0x454 240#define KNL_PMON_FIXED_CTL_EN 0x1 241 242/* KNL EDC */ 243#define KNL_EDC0_ECLK_MSR_PMON_CTR0_LOW 0xa00 244#define KNL_EDC0_ECLK_MSR_PMON_CTL0 0xa20 245#define KNL_EDC0_ECLK_MSR_PMON_BOX_CTL 0xa30 246#define KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_LOW 0xa3c 247#define KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_CTL 0xa44 248 249/* KNL MC */ 250#define KNL_MC0_CH0_MSR_PMON_CTR0_LOW 0xb00 251#define KNL_MC0_CH0_MSR_PMON_CTL0 0xb20 252#define KNL_MC0_CH0_MSR_PMON_BOX_CTL 0xb30 253#define KNL_MC0_CH0_MSR_PMON_FIXED_LOW 0xb3c 254#define KNL_MC0_CH0_MSR_PMON_FIXED_CTL 0xb44 255 256/* KNL IRP */ 257#define KNL_IRP_PCI_PMON_BOX_CTL 0xf0 258#define KNL_IRP_PCI_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \ 259 KNL_CHA_MSR_PMON_CTL_QOR) 260/* KNL PCU */ 261#define KNL_PCU_PMON_CTL_EV_SEL_MASK 0x0000007f 262#define KNL_PCU_PMON_CTL_USE_OCC_CTR (1 << 7) 263#define KNL_PCU_MSR_PMON_CTL_TRESH_MASK 0x3f000000 264#define KNL_PCU_MSR_PMON_RAW_EVENT_MASK \ 265 (KNL_PCU_PMON_CTL_EV_SEL_MASK | \ 266 KNL_PCU_PMON_CTL_USE_OCC_CTR | \ 267 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ 268 SNBEP_PMON_CTL_EDGE_DET | \ 269 SNBEP_CBO_PMON_CTL_TID_EN | \ 270 SNBEP_PMON_CTL_INVERT | \ 271 KNL_PCU_MSR_PMON_CTL_TRESH_MASK | \ 272 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \ 273 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET) 274 275/* SKX pci bus to socket mapping */ 276#define SKX_CPUNODEID 0xc0 277#define SKX_GIDNIDMAP 0xd4 278 279/* 280 * The CPU_BUS_NUMBER MSR returns the values of the respective CPUBUSNO CSR 281 * that BIOS programmed. MSR has package scope. 282 * | Bit | Default | Description 283 * | [63] | 00h | VALID - When set, indicates the CPU bus 284 * numbers have been initialized. (RO) 285 * |[62:48]| --- | Reserved 286 * |[47:40]| 00h | BUS_NUM_5 - Return the bus number BIOS assigned 287 * CPUBUSNO(5). (RO) 288 * |[39:32]| 00h | BUS_NUM_4 - Return the bus number BIOS assigned 289 * CPUBUSNO(4). (RO) 290 * |[31:24]| 00h | BUS_NUM_3 - Return the bus number BIOS assigned 291 * CPUBUSNO(3). (RO) 292 * |[23:16]| 00h | BUS_NUM_2 - Return the bus number BIOS assigned 293 * CPUBUSNO(2). (RO) 294 * |[15:8] | 00h | BUS_NUM_1 - Return the bus number BIOS assigned 295 * CPUBUSNO(1). (RO) 296 * | [7:0] | 00h | BUS_NUM_0 - Return the bus number BIOS assigned 297 * CPUBUSNO(0). (RO) 298 */ 299#define SKX_MSR_CPU_BUS_NUMBER 0x300 300#define SKX_MSR_CPU_BUS_VALID_BIT (1ULL << 63) 301#define BUS_NUM_STRIDE 8 302 303/* SKX CHA */ 304#define SKX_CHA_MSR_PMON_BOX_FILTER_TID (0x1ffULL << 0) 305#define SKX_CHA_MSR_PMON_BOX_FILTER_LINK (0xfULL << 9) 306#define SKX_CHA_MSR_PMON_BOX_FILTER_STATE (0x3ffULL << 17) 307#define SKX_CHA_MSR_PMON_BOX_FILTER_REM (0x1ULL << 32) 308#define SKX_CHA_MSR_PMON_BOX_FILTER_LOC (0x1ULL << 33) 309#define SKX_CHA_MSR_PMON_BOX_FILTER_ALL_OPC (0x1ULL << 35) 310#define SKX_CHA_MSR_PMON_BOX_FILTER_NM (0x1ULL << 36) 311#define SKX_CHA_MSR_PMON_BOX_FILTER_NOT_NM (0x1ULL << 37) 312#define SKX_CHA_MSR_PMON_BOX_FILTER_OPC0 (0x3ffULL << 41) 313#define SKX_CHA_MSR_PMON_BOX_FILTER_OPC1 (0x3ffULL << 51) 314#define SKX_CHA_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61) 315#define SKX_CHA_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62) 316#define SKX_CHA_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63) 317 318/* SKX IIO */ 319#define SKX_IIO0_MSR_PMON_CTL0 0xa48 320#define SKX_IIO0_MSR_PMON_CTR0 0xa41 321#define SKX_IIO0_MSR_PMON_BOX_CTL 0xa40 322#define SKX_IIO_MSR_OFFSET 0x20 323 324#define SKX_PMON_CTL_TRESH_MASK (0xff << 24) 325#define SKX_PMON_CTL_TRESH_MASK_EXT (0xf) 326#define SKX_PMON_CTL_CH_MASK (0xff << 4) 327#define SKX_PMON_CTL_FC_MASK (0x7 << 12) 328#define SKX_IIO_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \ 329 SNBEP_PMON_CTL_UMASK_MASK | \ 330 SNBEP_PMON_CTL_EDGE_DET | \ 331 SNBEP_PMON_CTL_INVERT | \ 332 SKX_PMON_CTL_TRESH_MASK) 333#define SKX_IIO_PMON_RAW_EVENT_MASK_EXT (SKX_PMON_CTL_TRESH_MASK_EXT | \ 334 SKX_PMON_CTL_CH_MASK | \ 335 SKX_PMON_CTL_FC_MASK) 336 337/* SKX IRP */ 338#define SKX_IRP0_MSR_PMON_CTL0 0xa5b 339#define SKX_IRP0_MSR_PMON_CTR0 0xa59 340#define SKX_IRP0_MSR_PMON_BOX_CTL 0xa58 341#define SKX_IRP_MSR_OFFSET 0x20 342 343/* SKX UPI */ 344#define SKX_UPI_PCI_PMON_CTL0 0x350 345#define SKX_UPI_PCI_PMON_CTR0 0x318 346#define SKX_UPI_PCI_PMON_BOX_CTL 0x378 347#define SKX_UPI_CTL_UMASK_EXT 0xffefff 348 349/* SKX M2M */ 350#define SKX_M2M_PCI_PMON_CTL0 0x228 351#define SKX_M2M_PCI_PMON_CTR0 0x200 352#define SKX_M2M_PCI_PMON_BOX_CTL 0x258 353 354/* Memory Map registers device ID */ 355#define SNR_ICX_MESH2IIO_MMAP_DID 0x9a2 356#define SNR_ICX_SAD_CONTROL_CFG 0x3f4 357 358/* Getting I/O stack id in SAD_COTROL_CFG notation */ 359#define SAD_CONTROL_STACK_ID(data) (((data) >> 4) & 0x7) 360 361/* SNR Ubox */ 362#define SNR_U_MSR_PMON_CTR0 0x1f98 363#define SNR_U_MSR_PMON_CTL0 0x1f91 364#define SNR_U_MSR_PMON_UCLK_FIXED_CTL 0x1f93 365#define SNR_U_MSR_PMON_UCLK_FIXED_CTR 0x1f94 366 367/* SNR CHA */ 368#define SNR_CHA_RAW_EVENT_MASK_EXT 0x3ffffff 369#define SNR_CHA_MSR_PMON_CTL0 0x1c01 370#define SNR_CHA_MSR_PMON_CTR0 0x1c08 371#define SNR_CHA_MSR_PMON_BOX_CTL 0x1c00 372#define SNR_C0_MSR_PMON_BOX_FILTER0 0x1c05 373 374 375/* SNR IIO */ 376#define SNR_IIO_MSR_PMON_CTL0 0x1e08 377#define SNR_IIO_MSR_PMON_CTR0 0x1e01 378#define SNR_IIO_MSR_PMON_BOX_CTL 0x1e00 379#define SNR_IIO_MSR_OFFSET 0x10 380#define SNR_IIO_PMON_RAW_EVENT_MASK_EXT 0x7ffff 381 382/* SNR IRP */ 383#define SNR_IRP0_MSR_PMON_CTL0 0x1ea8 384#define SNR_IRP0_MSR_PMON_CTR0 0x1ea1 385#define SNR_IRP0_MSR_PMON_BOX_CTL 0x1ea0 386#define SNR_IRP_MSR_OFFSET 0x10 387 388/* SNR M2PCIE */ 389#define SNR_M2PCIE_MSR_PMON_CTL0 0x1e58 390#define SNR_M2PCIE_MSR_PMON_CTR0 0x1e51 391#define SNR_M2PCIE_MSR_PMON_BOX_CTL 0x1e50 392#define SNR_M2PCIE_MSR_OFFSET 0x10 393 394/* SNR PCU */ 395#define SNR_PCU_MSR_PMON_CTL0 0x1ef1 396#define SNR_PCU_MSR_PMON_CTR0 0x1ef8 397#define SNR_PCU_MSR_PMON_BOX_CTL 0x1ef0 398#define SNR_PCU_MSR_PMON_BOX_FILTER 0x1efc 399 400/* SNR M2M */ 401#define SNR_M2M_PCI_PMON_CTL0 0x468 402#define SNR_M2M_PCI_PMON_CTR0 0x440 403#define SNR_M2M_PCI_PMON_BOX_CTL 0x438 404#define SNR_M2M_PCI_PMON_UMASK_EXT 0xff 405 406/* SNR PCIE3 */ 407#define SNR_PCIE3_PCI_PMON_CTL0 0x508 408#define SNR_PCIE3_PCI_PMON_CTR0 0x4e8 409#define SNR_PCIE3_PCI_PMON_BOX_CTL 0x4e0 410 411/* SNR IMC */ 412#define SNR_IMC_MMIO_PMON_FIXED_CTL 0x54 413#define SNR_IMC_MMIO_PMON_FIXED_CTR 0x38 414#define SNR_IMC_MMIO_PMON_CTL0 0x40 415#define SNR_IMC_MMIO_PMON_CTR0 0x8 416#define SNR_IMC_MMIO_PMON_BOX_CTL 0x22800 417#define SNR_IMC_MMIO_OFFSET 0x4000 418#define SNR_IMC_MMIO_SIZE 0x4000 419#define SNR_IMC_MMIO_BASE_OFFSET 0xd0 420#define SNR_IMC_MMIO_BASE_MASK 0x1FFFFFFF 421#define SNR_IMC_MMIO_MEM0_OFFSET 0xd8 422#define SNR_IMC_MMIO_MEM0_MASK 0x7FF 423 424/* ICX CHA */ 425#define ICX_C34_MSR_PMON_CTR0 0xb68 426#define ICX_C34_MSR_PMON_CTL0 0xb61 427#define ICX_C34_MSR_PMON_BOX_CTL 0xb60 428#define ICX_C34_MSR_PMON_BOX_FILTER0 0xb65 429 430/* ICX IIO */ 431#define ICX_IIO_MSR_PMON_CTL0 0xa58 432#define ICX_IIO_MSR_PMON_CTR0 0xa51 433#define ICX_IIO_MSR_PMON_BOX_CTL 0xa50 434 435/* ICX IRP */ 436#define ICX_IRP0_MSR_PMON_CTL0 0xa4d 437#define ICX_IRP0_MSR_PMON_CTR0 0xa4b 438#define ICX_IRP0_MSR_PMON_BOX_CTL 0xa4a 439 440/* ICX M2PCIE */ 441#define ICX_M2PCIE_MSR_PMON_CTL0 0xa46 442#define ICX_M2PCIE_MSR_PMON_CTR0 0xa41 443#define ICX_M2PCIE_MSR_PMON_BOX_CTL 0xa40 444 445/* ICX UPI */ 446#define ICX_UPI_PCI_PMON_CTL0 0x350 447#define ICX_UPI_PCI_PMON_CTR0 0x320 448#define ICX_UPI_PCI_PMON_BOX_CTL 0x318 449#define ICX_UPI_CTL_UMASK_EXT 0xffffff 450#define ICX_UBOX_DID 0x3450 451 452/* ICX M3UPI*/ 453#define ICX_M3UPI_PCI_PMON_CTL0 0xd8 454#define ICX_M3UPI_PCI_PMON_CTR0 0xa8 455#define ICX_M3UPI_PCI_PMON_BOX_CTL 0xa0 456 457/* ICX IMC */ 458#define ICX_NUMBER_IMC_CHN 3 459#define ICX_IMC_MEM_STRIDE 0x4 460 461/* SPR */ 462#define SPR_RAW_EVENT_MASK_EXT 0xffffff 463#define SPR_UBOX_DID 0x3250 464 465/* SPR CHA */ 466#define SPR_CHA_EVENT_MASK_EXT 0xffffffff 467#define SPR_CHA_PMON_CTL_TID_EN (1 << 16) 468#define SPR_CHA_PMON_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \ 469 SPR_CHA_PMON_CTL_TID_EN) 470#define SPR_CHA_PMON_BOX_FILTER_TID 0x3ff 471 472#define SPR_C0_MSR_PMON_BOX_FILTER0 0x200e 473 474DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7"); 475DEFINE_UNCORE_FORMAT_ATTR(event2, event, "config:0-6"); 476DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21"); 477DEFINE_UNCORE_FORMAT_ATTR(use_occ_ctr, use_occ_ctr, "config:7"); 478DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15"); 479DEFINE_UNCORE_FORMAT_ATTR(umask_ext, umask, "config:8-15,32-43,45-55"); 480DEFINE_UNCORE_FORMAT_ATTR(umask_ext2, umask, "config:8-15,32-57"); 481DEFINE_UNCORE_FORMAT_ATTR(umask_ext3, umask, "config:8-15,32-39"); 482DEFINE_UNCORE_FORMAT_ATTR(umask_ext4, umask, "config:8-15,32-55"); 483DEFINE_UNCORE_FORMAT_ATTR(umask_ext5, umask, "config:8-15,32-63"); 484DEFINE_UNCORE_FORMAT_ATTR(qor, qor, "config:16"); 485DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18"); 486DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19"); 487DEFINE_UNCORE_FORMAT_ATTR(tid_en2, tid_en, "config:16"); 488DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23"); 489DEFINE_UNCORE_FORMAT_ATTR(thresh9, thresh, "config:24-35"); 490DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31"); 491DEFINE_UNCORE_FORMAT_ATTR(thresh6, thresh, "config:24-29"); 492DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28"); 493DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15"); 494DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30"); 495DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51"); 496DEFINE_UNCORE_FORMAT_ATTR(occ_edge_det, occ_edge_det, "config:31"); 497DEFINE_UNCORE_FORMAT_ATTR(ch_mask, ch_mask, "config:36-43"); 498DEFINE_UNCORE_FORMAT_ATTR(ch_mask2, ch_mask, "config:36-47"); 499DEFINE_UNCORE_FORMAT_ATTR(fc_mask, fc_mask, "config:44-46"); 500DEFINE_UNCORE_FORMAT_ATTR(fc_mask2, fc_mask, "config:48-50"); 501DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4"); 502DEFINE_UNCORE_FORMAT_ATTR(filter_tid2, filter_tid, "config1:0"); 503DEFINE_UNCORE_FORMAT_ATTR(filter_tid3, filter_tid, "config1:0-5"); 504DEFINE_UNCORE_FORMAT_ATTR(filter_tid4, filter_tid, "config1:0-8"); 505DEFINE_UNCORE_FORMAT_ATTR(filter_tid5, filter_tid, "config1:0-9"); 506DEFINE_UNCORE_FORMAT_ATTR(filter_cid, filter_cid, "config1:5"); 507DEFINE_UNCORE_FORMAT_ATTR(filter_link, filter_link, "config1:5-8"); 508DEFINE_UNCORE_FORMAT_ATTR(filter_link2, filter_link, "config1:6-8"); 509DEFINE_UNCORE_FORMAT_ATTR(filter_link3, filter_link, "config1:12"); 510DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17"); 511DEFINE_UNCORE_FORMAT_ATTR(filter_nid2, filter_nid, "config1:32-47"); 512DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22"); 513DEFINE_UNCORE_FORMAT_ATTR(filter_state2, filter_state, "config1:17-22"); 514DEFINE_UNCORE_FORMAT_ATTR(filter_state3, filter_state, "config1:17-23"); 515DEFINE_UNCORE_FORMAT_ATTR(filter_state4, filter_state, "config1:18-20"); 516DEFINE_UNCORE_FORMAT_ATTR(filter_state5, filter_state, "config1:17-26"); 517DEFINE_UNCORE_FORMAT_ATTR(filter_rem, filter_rem, "config1:32"); 518DEFINE_UNCORE_FORMAT_ATTR(filter_loc, filter_loc, "config1:33"); 519DEFINE_UNCORE_FORMAT_ATTR(filter_nm, filter_nm, "config1:36"); 520DEFINE_UNCORE_FORMAT_ATTR(filter_not_nm, filter_not_nm, "config1:37"); 521DEFINE_UNCORE_FORMAT_ATTR(filter_local, filter_local, "config1:33"); 522DEFINE_UNCORE_FORMAT_ATTR(filter_all_op, filter_all_op, "config1:35"); 523DEFINE_UNCORE_FORMAT_ATTR(filter_nnm, filter_nnm, "config1:37"); 524DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31"); 525DEFINE_UNCORE_FORMAT_ATTR(filter_opc2, filter_opc, "config1:52-60"); 526DEFINE_UNCORE_FORMAT_ATTR(filter_opc3, filter_opc, "config1:41-60"); 527DEFINE_UNCORE_FORMAT_ATTR(filter_opc_0, filter_opc0, "config1:41-50"); 528DEFINE_UNCORE_FORMAT_ATTR(filter_opc_1, filter_opc1, "config1:51-60"); 529DEFINE_UNCORE_FORMAT_ATTR(filter_nc, filter_nc, "config1:62"); 530DEFINE_UNCORE_FORMAT_ATTR(filter_c6, filter_c6, "config1:61"); 531DEFINE_UNCORE_FORMAT_ATTR(filter_isoc, filter_isoc, "config1:63"); 532DEFINE_UNCORE_FORMAT_ATTR(filter_band0, filter_band0, "config1:0-7"); 533DEFINE_UNCORE_FORMAT_ATTR(filter_band1, filter_band1, "config1:8-15"); 534DEFINE_UNCORE_FORMAT_ATTR(filter_band2, filter_band2, "config1:16-23"); 535DEFINE_UNCORE_FORMAT_ATTR(filter_band3, filter_band3, "config1:24-31"); 536DEFINE_UNCORE_FORMAT_ATTR(match_rds, match_rds, "config1:48-51"); 537DEFINE_UNCORE_FORMAT_ATTR(match_rnid30, match_rnid30, "config1:32-35"); 538DEFINE_UNCORE_FORMAT_ATTR(match_rnid4, match_rnid4, "config1:31"); 539DEFINE_UNCORE_FORMAT_ATTR(match_dnid, match_dnid, "config1:13-17"); 540DEFINE_UNCORE_FORMAT_ATTR(match_mc, match_mc, "config1:9-12"); 541DEFINE_UNCORE_FORMAT_ATTR(match_opc, match_opc, "config1:5-8"); 542DEFINE_UNCORE_FORMAT_ATTR(match_vnw, match_vnw, "config1:3-4"); 543DEFINE_UNCORE_FORMAT_ATTR(match0, match0, "config1:0-31"); 544DEFINE_UNCORE_FORMAT_ATTR(match1, match1, "config1:32-63"); 545DEFINE_UNCORE_FORMAT_ATTR(mask_rds, mask_rds, "config2:48-51"); 546DEFINE_UNCORE_FORMAT_ATTR(mask_rnid30, mask_rnid30, "config2:32-35"); 547DEFINE_UNCORE_FORMAT_ATTR(mask_rnid4, mask_rnid4, "config2:31"); 548DEFINE_UNCORE_FORMAT_ATTR(mask_dnid, mask_dnid, "config2:13-17"); 549DEFINE_UNCORE_FORMAT_ATTR(mask_mc, mask_mc, "config2:9-12"); 550DEFINE_UNCORE_FORMAT_ATTR(mask_opc, mask_opc, "config2:5-8"); 551DEFINE_UNCORE_FORMAT_ATTR(mask_vnw, mask_vnw, "config2:3-4"); 552DEFINE_UNCORE_FORMAT_ATTR(mask0, mask0, "config2:0-31"); 553DEFINE_UNCORE_FORMAT_ATTR(mask1, mask1, "config2:32-63"); 554 555static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box) 556{ 557 struct pci_dev *pdev = box->pci_dev; 558 int box_ctl = uncore_pci_box_ctl(box); 559 u32 config = 0; 560 561 if (!pci_read_config_dword(pdev, box_ctl, &config)) { 562 config |= SNBEP_PMON_BOX_CTL_FRZ; 563 pci_write_config_dword(pdev, box_ctl, config); 564 } 565} 566 567static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box) 568{ 569 struct pci_dev *pdev = box->pci_dev; 570 int box_ctl = uncore_pci_box_ctl(box); 571 u32 config = 0; 572 573 if (!pci_read_config_dword(pdev, box_ctl, &config)) { 574 config &= ~SNBEP_PMON_BOX_CTL_FRZ; 575 pci_write_config_dword(pdev, box_ctl, config); 576 } 577} 578 579static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box, struct perf_event *event) 580{ 581 struct pci_dev *pdev = box->pci_dev; 582 struct hw_perf_event *hwc = &event->hw; 583 584 pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 585} 586 587static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box, struct perf_event *event) 588{ 589 struct pci_dev *pdev = box->pci_dev; 590 struct hw_perf_event *hwc = &event->hw; 591 592 pci_write_config_dword(pdev, hwc->config_base, hwc->config); 593} 594 595static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box, struct perf_event *event) 596{ 597 struct pci_dev *pdev = box->pci_dev; 598 struct hw_perf_event *hwc = &event->hw; 599 u64 count = 0; 600 601 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count); 602 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1); 603 604 return count; 605} 606 607static void snbep_uncore_pci_init_box(struct intel_uncore_box *box) 608{ 609 struct pci_dev *pdev = box->pci_dev; 610 int box_ctl = uncore_pci_box_ctl(box); 611 612 pci_write_config_dword(pdev, box_ctl, SNBEP_PMON_BOX_CTL_INT); 613} 614 615static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box) 616{ 617 u64 config; 618 unsigned msr; 619 620 msr = uncore_msr_box_ctl(box); 621 if (msr) { 622 rdmsrq(msr, config); 623 config |= SNBEP_PMON_BOX_CTL_FRZ; 624 wrmsrq(msr, config); 625 } 626} 627 628static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box) 629{ 630 u64 config; 631 unsigned msr; 632 633 msr = uncore_msr_box_ctl(box); 634 if (msr) { 635 rdmsrq(msr, config); 636 config &= ~SNBEP_PMON_BOX_CTL_FRZ; 637 wrmsrq(msr, config); 638 } 639} 640 641static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) 642{ 643 struct hw_perf_event *hwc = &event->hw; 644 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 645 646 if (reg1->idx != EXTRA_REG_NONE) 647 wrmsrq(reg1->reg, uncore_shared_reg_config(box, 0)); 648 649 wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 650} 651 652static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box, 653 struct perf_event *event) 654{ 655 struct hw_perf_event *hwc = &event->hw; 656 657 wrmsrq(hwc->config_base, hwc->config); 658} 659 660static void snbep_uncore_msr_init_box(struct intel_uncore_box *box) 661{ 662 unsigned msr = uncore_msr_box_ctl(box); 663 664 if (msr) 665 wrmsrq(msr, SNBEP_PMON_BOX_CTL_INT); 666} 667 668static struct attribute *snbep_uncore_formats_attr[] = { 669 &format_attr_event.attr, 670 &format_attr_umask.attr, 671 &format_attr_edge.attr, 672 &format_attr_inv.attr, 673 &format_attr_thresh8.attr, 674 NULL, 675}; 676 677static struct attribute *snbep_uncore_ubox_formats_attr[] = { 678 &format_attr_event.attr, 679 &format_attr_umask.attr, 680 &format_attr_edge.attr, 681 &format_attr_inv.attr, 682 &format_attr_thresh5.attr, 683 NULL, 684}; 685 686static struct attribute *snbep_uncore_cbox_formats_attr[] = { 687 &format_attr_event.attr, 688 &format_attr_umask.attr, 689 &format_attr_edge.attr, 690 &format_attr_tid_en.attr, 691 &format_attr_inv.attr, 692 &format_attr_thresh8.attr, 693 &format_attr_filter_tid.attr, 694 &format_attr_filter_nid.attr, 695 &format_attr_filter_state.attr, 696 &format_attr_filter_opc.attr, 697 NULL, 698}; 699 700static struct attribute *snbep_uncore_pcu_formats_attr[] = { 701 &format_attr_event.attr, 702 &format_attr_occ_sel.attr, 703 &format_attr_edge.attr, 704 &format_attr_inv.attr, 705 &format_attr_thresh5.attr, 706 &format_attr_occ_invert.attr, 707 &format_attr_occ_edge.attr, 708 &format_attr_filter_band0.attr, 709 &format_attr_filter_band1.attr, 710 &format_attr_filter_band2.attr, 711 &format_attr_filter_band3.attr, 712 NULL, 713}; 714 715static struct attribute *snbep_uncore_qpi_formats_attr[] = { 716 &format_attr_event_ext.attr, 717 &format_attr_umask.attr, 718 &format_attr_edge.attr, 719 &format_attr_inv.attr, 720 &format_attr_thresh8.attr, 721 &format_attr_match_rds.attr, 722 &format_attr_match_rnid30.attr, 723 &format_attr_match_rnid4.attr, 724 &format_attr_match_dnid.attr, 725 &format_attr_match_mc.attr, 726 &format_attr_match_opc.attr, 727 &format_attr_match_vnw.attr, 728 &format_attr_match0.attr, 729 &format_attr_match1.attr, 730 &format_attr_mask_rds.attr, 731 &format_attr_mask_rnid30.attr, 732 &format_attr_mask_rnid4.attr, 733 &format_attr_mask_dnid.attr, 734 &format_attr_mask_mc.attr, 735 &format_attr_mask_opc.attr, 736 &format_attr_mask_vnw.attr, 737 &format_attr_mask0.attr, 738 &format_attr_mask1.attr, 739 NULL, 740}; 741 742static struct uncore_event_desc snbep_uncore_imc_events[] = { 743 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"), 744 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"), 745 INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"), 746 INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"), 747 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"), 748 INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"), 749 INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"), 750 { /* end: all zeroes */ }, 751}; 752 753static struct uncore_event_desc snbep_uncore_qpi_events[] = { 754 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x14"), 755 INTEL_UNCORE_EVENT_DESC(txl_flits_active, "event=0x00,umask=0x06"), 756 INTEL_UNCORE_EVENT_DESC(drs_data, "event=0x102,umask=0x08"), 757 INTEL_UNCORE_EVENT_DESC(ncb_data, "event=0x103,umask=0x04"), 758 { /* end: all zeroes */ }, 759}; 760 761static const struct attribute_group snbep_uncore_format_group = { 762 .name = "format", 763 .attrs = snbep_uncore_formats_attr, 764}; 765 766static const struct attribute_group snbep_uncore_ubox_format_group = { 767 .name = "format", 768 .attrs = snbep_uncore_ubox_formats_attr, 769}; 770 771static const struct attribute_group snbep_uncore_cbox_format_group = { 772 .name = "format", 773 .attrs = snbep_uncore_cbox_formats_attr, 774}; 775 776static const struct attribute_group snbep_uncore_pcu_format_group = { 777 .name = "format", 778 .attrs = snbep_uncore_pcu_formats_attr, 779}; 780 781static const struct attribute_group snbep_uncore_qpi_format_group = { 782 .name = "format", 783 .attrs = snbep_uncore_qpi_formats_attr, 784}; 785 786#define __SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \ 787 .disable_box = snbep_uncore_msr_disable_box, \ 788 .enable_box = snbep_uncore_msr_enable_box, \ 789 .disable_event = snbep_uncore_msr_disable_event, \ 790 .enable_event = snbep_uncore_msr_enable_event, \ 791 .read_counter = uncore_msr_read_counter 792 793#define SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \ 794 __SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), \ 795 .init_box = snbep_uncore_msr_init_box \ 796 797static struct intel_uncore_ops snbep_uncore_msr_ops = { 798 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 799}; 800 801#define SNBEP_UNCORE_PCI_OPS_COMMON_INIT() \ 802 .init_box = snbep_uncore_pci_init_box, \ 803 .disable_box = snbep_uncore_pci_disable_box, \ 804 .enable_box = snbep_uncore_pci_enable_box, \ 805 .disable_event = snbep_uncore_pci_disable_event, \ 806 .read_counter = snbep_uncore_pci_read_counter 807 808static struct intel_uncore_ops snbep_uncore_pci_ops = { 809 SNBEP_UNCORE_PCI_OPS_COMMON_INIT(), 810 .enable_event = snbep_uncore_pci_enable_event, \ 811}; 812 813static struct event_constraint snbep_uncore_cbox_constraints[] = { 814 UNCORE_EVENT_CONSTRAINT(0x01, 0x1), 815 UNCORE_EVENT_CONSTRAINT(0x02, 0x3), 816 UNCORE_EVENT_CONSTRAINT(0x04, 0x3), 817 UNCORE_EVENT_CONSTRAINT(0x05, 0x3), 818 UNCORE_EVENT_CONSTRAINT(0x07, 0x3), 819 UNCORE_EVENT_CONSTRAINT(0x09, 0x3), 820 UNCORE_EVENT_CONSTRAINT(0x11, 0x1), 821 UNCORE_EVENT_CONSTRAINT(0x12, 0x3), 822 UNCORE_EVENT_CONSTRAINT(0x13, 0x3), 823 UNCORE_EVENT_CONSTRAINT(0x1b, 0xc), 824 UNCORE_EVENT_CONSTRAINT(0x1c, 0xc), 825 UNCORE_EVENT_CONSTRAINT(0x1d, 0xc), 826 UNCORE_EVENT_CONSTRAINT(0x1e, 0xc), 827 UNCORE_EVENT_CONSTRAINT(0x1f, 0xe), 828 UNCORE_EVENT_CONSTRAINT(0x21, 0x3), 829 UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 830 UNCORE_EVENT_CONSTRAINT(0x31, 0x3), 831 UNCORE_EVENT_CONSTRAINT(0x32, 0x3), 832 UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 833 UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 834 UNCORE_EVENT_CONSTRAINT(0x35, 0x3), 835 UNCORE_EVENT_CONSTRAINT(0x36, 0x1), 836 UNCORE_EVENT_CONSTRAINT(0x37, 0x3), 837 UNCORE_EVENT_CONSTRAINT(0x38, 0x3), 838 UNCORE_EVENT_CONSTRAINT(0x39, 0x3), 839 UNCORE_EVENT_CONSTRAINT(0x3b, 0x1), 840 EVENT_CONSTRAINT_END 841}; 842 843static struct event_constraint snbep_uncore_r2pcie_constraints[] = { 844 UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 845 UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 846 UNCORE_EVENT_CONSTRAINT(0x12, 0x1), 847 UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 848 UNCORE_EVENT_CONSTRAINT(0x24, 0x3), 849 UNCORE_EVENT_CONSTRAINT(0x25, 0x3), 850 UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 851 UNCORE_EVENT_CONSTRAINT(0x32, 0x3), 852 UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 853 UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 854 EVENT_CONSTRAINT_END 855}; 856 857static struct event_constraint snbep_uncore_r3qpi_constraints[] = { 858 UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 859 UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 860 UNCORE_EVENT_CONSTRAINT(0x12, 0x3), 861 UNCORE_EVENT_CONSTRAINT(0x13, 0x1), 862 UNCORE_EVENT_CONSTRAINT(0x20, 0x3), 863 UNCORE_EVENT_CONSTRAINT(0x21, 0x3), 864 UNCORE_EVENT_CONSTRAINT(0x22, 0x3), 865 UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 866 UNCORE_EVENT_CONSTRAINT(0x24, 0x3), 867 UNCORE_EVENT_CONSTRAINT(0x25, 0x3), 868 UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 869 UNCORE_EVENT_CONSTRAINT(0x28, 0x3), 870 UNCORE_EVENT_CONSTRAINT(0x29, 0x3), 871 UNCORE_EVENT_CONSTRAINT(0x2a, 0x3), 872 UNCORE_EVENT_CONSTRAINT(0x2b, 0x3), 873 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), 874 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 875 UNCORE_EVENT_CONSTRAINT(0x2e, 0x3), 876 UNCORE_EVENT_CONSTRAINT(0x2f, 0x3), 877 UNCORE_EVENT_CONSTRAINT(0x30, 0x3), 878 UNCORE_EVENT_CONSTRAINT(0x31, 0x3), 879 UNCORE_EVENT_CONSTRAINT(0x32, 0x3), 880 UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 881 UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 882 UNCORE_EVENT_CONSTRAINT(0x36, 0x3), 883 UNCORE_EVENT_CONSTRAINT(0x37, 0x3), 884 UNCORE_EVENT_CONSTRAINT(0x38, 0x3), 885 UNCORE_EVENT_CONSTRAINT(0x39, 0x3), 886 EVENT_CONSTRAINT_END 887}; 888 889static struct intel_uncore_type snbep_uncore_ubox = { 890 .name = "ubox", 891 .num_counters = 2, 892 .num_boxes = 1, 893 .perf_ctr_bits = 44, 894 .fixed_ctr_bits = 48, 895 .perf_ctr = SNBEP_U_MSR_PMON_CTR0, 896 .event_ctl = SNBEP_U_MSR_PMON_CTL0, 897 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK, 898 .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR, 899 .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL, 900 .ops = &snbep_uncore_msr_ops, 901 .format_group = &snbep_uncore_ubox_format_group, 902}; 903 904static struct extra_reg snbep_uncore_cbox_extra_regs[] = { 905 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN, 906 SNBEP_CBO_PMON_CTL_TID_EN, 0x1), 907 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4), 908 SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0x6), 909 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4), 910 SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0x6), 911 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4), 912 SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0x6), 913 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x6), 914 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x8), 915 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x8), 916 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0xa), 917 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0xa), 918 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x2), 919 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x2), 920 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x2), 921 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x2), 922 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x8), 923 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x8), 924 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0xa), 925 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0xa), 926 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x2), 927 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x2), 928 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x2), 929 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x2), 930 EVENT_EXTRA_END 931}; 932 933static void snbep_cbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event) 934{ 935 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 936 struct intel_uncore_extra_reg *er = &box->shared_regs[0]; 937 int i; 938 939 if (uncore_box_is_fake(box)) 940 return; 941 942 for (i = 0; i < 5; i++) { 943 if (reg1->alloc & (0x1 << i)) 944 atomic_sub(1 << (i * 6), &er->ref); 945 } 946 reg1->alloc = 0; 947} 948 949static struct event_constraint * 950__snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event, 951 u64 (*cbox_filter_mask)(int fields)) 952{ 953 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 954 struct intel_uncore_extra_reg *er = &box->shared_regs[0]; 955 int i, alloc = 0; 956 unsigned long flags; 957 u64 mask; 958 959 if (reg1->idx == EXTRA_REG_NONE) 960 return NULL; 961 962 raw_spin_lock_irqsave(&er->lock, flags); 963 for (i = 0; i < 5; i++) { 964 if (!(reg1->idx & (0x1 << i))) 965 continue; 966 if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i))) 967 continue; 968 969 mask = cbox_filter_mask(0x1 << i); 970 if (!__BITS_VALUE(atomic_read(&er->ref), i, 6) || 971 !((reg1->config ^ er->config) & mask)) { 972 atomic_add(1 << (i * 6), &er->ref); 973 er->config &= ~mask; 974 er->config |= reg1->config & mask; 975 alloc |= (0x1 << i); 976 } else { 977 break; 978 } 979 } 980 raw_spin_unlock_irqrestore(&er->lock, flags); 981 if (i < 5) 982 goto fail; 983 984 if (!uncore_box_is_fake(box)) 985 reg1->alloc |= alloc; 986 987 return NULL; 988fail: 989 for (; i >= 0; i--) { 990 if (alloc & (0x1 << i)) 991 atomic_sub(1 << (i * 6), &er->ref); 992 } 993 return &uncore_constraint_empty; 994} 995 996static u64 snbep_cbox_filter_mask(int fields) 997{ 998 u64 mask = 0; 999 1000 if (fields & 0x1) 1001 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_TID; 1002 if (fields & 0x2) 1003 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_NID; 1004 if (fields & 0x4) 1005 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE; 1006 if (fields & 0x8) 1007 mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC; 1008 1009 return mask; 1010} 1011 1012static struct event_constraint * 1013snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 1014{ 1015 return __snbep_cbox_get_constraint(box, event, snbep_cbox_filter_mask); 1016} 1017 1018static int snbep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event) 1019{ 1020 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 1021 struct extra_reg *er; 1022 int idx = 0; 1023 1024 for (er = snbep_uncore_cbox_extra_regs; er->msr; er++) { 1025 if (er->event != (event->hw.config & er->config_mask)) 1026 continue; 1027 idx |= er->idx; 1028 } 1029 1030 if (idx) { 1031 reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER + 1032 SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx; 1033 reg1->config = event->attr.config1 & snbep_cbox_filter_mask(idx); 1034 reg1->idx = idx; 1035 } 1036 return 0; 1037} 1038 1039static struct intel_uncore_ops snbep_uncore_cbox_ops = { 1040 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 1041 .hw_config = snbep_cbox_hw_config, 1042 .get_constraint = snbep_cbox_get_constraint, 1043 .put_constraint = snbep_cbox_put_constraint, 1044}; 1045 1046static struct intel_uncore_type snbep_uncore_cbox = { 1047 .name = "cbox", 1048 .num_counters = 4, 1049 .num_boxes = 8, 1050 .perf_ctr_bits = 44, 1051 .event_ctl = SNBEP_C0_MSR_PMON_CTL0, 1052 .perf_ctr = SNBEP_C0_MSR_PMON_CTR0, 1053 .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK, 1054 .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL, 1055 .msr_offset = SNBEP_CBO_MSR_OFFSET, 1056 .num_shared_regs = 1, 1057 .constraints = snbep_uncore_cbox_constraints, 1058 .ops = &snbep_uncore_cbox_ops, 1059 .format_group = &snbep_uncore_cbox_format_group, 1060}; 1061 1062static u64 snbep_pcu_alter_er(struct perf_event *event, int new_idx, bool modify) 1063{ 1064 struct hw_perf_event *hwc = &event->hw; 1065 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 1066 u64 config = reg1->config; 1067 1068 if (new_idx > reg1->idx) 1069 config <<= 8 * (new_idx - reg1->idx); 1070 else 1071 config >>= 8 * (reg1->idx - new_idx); 1072 1073 if (modify) { 1074 hwc->config += new_idx - reg1->idx; 1075 reg1->config = config; 1076 reg1->idx = new_idx; 1077 } 1078 return config; 1079} 1080 1081static struct event_constraint * 1082snbep_pcu_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 1083{ 1084 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 1085 struct intel_uncore_extra_reg *er = &box->shared_regs[0]; 1086 unsigned long flags; 1087 int idx = reg1->idx; 1088 u64 mask, config1 = reg1->config; 1089 bool ok = false; 1090 1091 if (reg1->idx == EXTRA_REG_NONE || 1092 (!uncore_box_is_fake(box) && reg1->alloc)) 1093 return NULL; 1094again: 1095 mask = 0xffULL << (idx * 8); 1096 raw_spin_lock_irqsave(&er->lock, flags); 1097 if (!__BITS_VALUE(atomic_read(&er->ref), idx, 8) || 1098 !((config1 ^ er->config) & mask)) { 1099 atomic_add(1 << (idx * 8), &er->ref); 1100 er->config &= ~mask; 1101 er->config |= config1 & mask; 1102 ok = true; 1103 } 1104 raw_spin_unlock_irqrestore(&er->lock, flags); 1105 1106 if (!ok) { 1107 idx = (idx + 1) % 4; 1108 if (idx != reg1->idx) { 1109 config1 = snbep_pcu_alter_er(event, idx, false); 1110 goto again; 1111 } 1112 return &uncore_constraint_empty; 1113 } 1114 1115 if (!uncore_box_is_fake(box)) { 1116 if (idx != reg1->idx) 1117 snbep_pcu_alter_er(event, idx, true); 1118 reg1->alloc = 1; 1119 } 1120 return NULL; 1121} 1122 1123static void snbep_pcu_put_constraint(struct intel_uncore_box *box, struct perf_event *event) 1124{ 1125 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 1126 struct intel_uncore_extra_reg *er = &box->shared_regs[0]; 1127 1128 if (uncore_box_is_fake(box) || !reg1->alloc) 1129 return; 1130 1131 atomic_sub(1 << (reg1->idx * 8), &er->ref); 1132 reg1->alloc = 0; 1133} 1134 1135static int snbep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event) 1136{ 1137 struct hw_perf_event *hwc = &event->hw; 1138 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 1139 int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK; 1140 1141 if (ev_sel >= 0xb && ev_sel <= 0xe) { 1142 reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER; 1143 reg1->idx = ev_sel - 0xb; 1144 reg1->config = event->attr.config1 & (0xff << (reg1->idx * 8)); 1145 } 1146 return 0; 1147} 1148 1149static struct intel_uncore_ops snbep_uncore_pcu_ops = { 1150 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 1151 .hw_config = snbep_pcu_hw_config, 1152 .get_constraint = snbep_pcu_get_constraint, 1153 .put_constraint = snbep_pcu_put_constraint, 1154}; 1155 1156static struct intel_uncore_type snbep_uncore_pcu = { 1157 .name = "pcu", 1158 .num_counters = 4, 1159 .num_boxes = 1, 1160 .perf_ctr_bits = 48, 1161 .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0, 1162 .event_ctl = SNBEP_PCU_MSR_PMON_CTL0, 1163 .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK, 1164 .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL, 1165 .num_shared_regs = 1, 1166 .ops = &snbep_uncore_pcu_ops, 1167 .format_group = &snbep_uncore_pcu_format_group, 1168}; 1169 1170static struct intel_uncore_type *snbep_msr_uncores[] = { 1171 &snbep_uncore_ubox, 1172 &snbep_uncore_cbox, 1173 &snbep_uncore_pcu, 1174 NULL, 1175}; 1176 1177void snbep_uncore_cpu_init(void) 1178{ 1179 if (snbep_uncore_cbox.num_boxes > topology_num_cores_per_package()) 1180 snbep_uncore_cbox.num_boxes = topology_num_cores_per_package(); 1181 uncore_msr_uncores = snbep_msr_uncores; 1182} 1183 1184enum { 1185 SNBEP_PCI_QPI_PORT0_FILTER, 1186 SNBEP_PCI_QPI_PORT1_FILTER, 1187 BDX_PCI_QPI_PORT2_FILTER, 1188}; 1189 1190static int snbep_qpi_hw_config(struct intel_uncore_box *box, struct perf_event *event) 1191{ 1192 struct hw_perf_event *hwc = &event->hw; 1193 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 1194 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; 1195 1196 if ((hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK) == 0x38) { 1197 reg1->idx = 0; 1198 reg1->reg = SNBEP_Q_Py_PCI_PMON_PKT_MATCH0; 1199 reg1->config = event->attr.config1; 1200 reg2->reg = SNBEP_Q_Py_PCI_PMON_PKT_MASK0; 1201 reg2->config = event->attr.config2; 1202 } 1203 return 0; 1204} 1205 1206static void snbep_qpi_enable_event(struct intel_uncore_box *box, struct perf_event *event) 1207{ 1208 struct pci_dev *pdev = box->pci_dev; 1209 struct hw_perf_event *hwc = &event->hw; 1210 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 1211 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; 1212 1213 if (reg1->idx != EXTRA_REG_NONE) { 1214 int idx = box->pmu->pmu_idx + SNBEP_PCI_QPI_PORT0_FILTER; 1215 int die = box->dieid; 1216 struct pci_dev *filter_pdev = uncore_extra_pci_dev[die].dev[idx]; 1217 1218 if (filter_pdev) { 1219 pci_write_config_dword(filter_pdev, reg1->reg, 1220 (u32)reg1->config); 1221 pci_write_config_dword(filter_pdev, reg1->reg + 4, 1222 (u32)(reg1->config >> 32)); 1223 pci_write_config_dword(filter_pdev, reg2->reg, 1224 (u32)reg2->config); 1225 pci_write_config_dword(filter_pdev, reg2->reg + 4, 1226 (u32)(reg2->config >> 32)); 1227 } 1228 } 1229 1230 pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 1231} 1232 1233static struct intel_uncore_ops snbep_uncore_qpi_ops = { 1234 SNBEP_UNCORE_PCI_OPS_COMMON_INIT(), 1235 .enable_event = snbep_qpi_enable_event, 1236 .hw_config = snbep_qpi_hw_config, 1237 .get_constraint = uncore_get_constraint, 1238 .put_constraint = uncore_put_constraint, 1239}; 1240 1241#define SNBEP_UNCORE_PCI_COMMON_INIT() \ 1242 .perf_ctr = SNBEP_PCI_PMON_CTR0, \ 1243 .event_ctl = SNBEP_PCI_PMON_CTL0, \ 1244 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, \ 1245 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \ 1246 .ops = &snbep_uncore_pci_ops, \ 1247 .format_group = &snbep_uncore_format_group 1248 1249static struct intel_uncore_type snbep_uncore_ha = { 1250 .name = "ha", 1251 .num_counters = 4, 1252 .num_boxes = 1, 1253 .perf_ctr_bits = 48, 1254 SNBEP_UNCORE_PCI_COMMON_INIT(), 1255}; 1256 1257static struct intel_uncore_type snbep_uncore_imc = { 1258 .name = "imc", 1259 .num_counters = 4, 1260 .num_boxes = 4, 1261 .perf_ctr_bits = 48, 1262 .fixed_ctr_bits = 48, 1263 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR, 1264 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL, 1265 .event_descs = snbep_uncore_imc_events, 1266 SNBEP_UNCORE_PCI_COMMON_INIT(), 1267}; 1268 1269static struct intel_uncore_type snbep_uncore_qpi = { 1270 .name = "qpi", 1271 .num_counters = 4, 1272 .num_boxes = 2, 1273 .perf_ctr_bits = 48, 1274 .perf_ctr = SNBEP_PCI_PMON_CTR0, 1275 .event_ctl = SNBEP_PCI_PMON_CTL0, 1276 .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK, 1277 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 1278 .num_shared_regs = 1, 1279 .ops = &snbep_uncore_qpi_ops, 1280 .event_descs = snbep_uncore_qpi_events, 1281 .format_group = &snbep_uncore_qpi_format_group, 1282}; 1283 1284 1285static struct intel_uncore_type snbep_uncore_r2pcie = { 1286 .name = "r2pcie", 1287 .num_counters = 4, 1288 .num_boxes = 1, 1289 .perf_ctr_bits = 44, 1290 .constraints = snbep_uncore_r2pcie_constraints, 1291 SNBEP_UNCORE_PCI_COMMON_INIT(), 1292}; 1293 1294static struct intel_uncore_type snbep_uncore_r3qpi = { 1295 .name = "r3qpi", 1296 .num_counters = 3, 1297 .num_boxes = 2, 1298 .perf_ctr_bits = 44, 1299 .constraints = snbep_uncore_r3qpi_constraints, 1300 SNBEP_UNCORE_PCI_COMMON_INIT(), 1301}; 1302 1303enum { 1304 SNBEP_PCI_UNCORE_HA, 1305 SNBEP_PCI_UNCORE_IMC, 1306 SNBEP_PCI_UNCORE_QPI, 1307 SNBEP_PCI_UNCORE_R2PCIE, 1308 SNBEP_PCI_UNCORE_R3QPI, 1309}; 1310 1311static struct intel_uncore_type *snbep_pci_uncores[] = { 1312 [SNBEP_PCI_UNCORE_HA] = &snbep_uncore_ha, 1313 [SNBEP_PCI_UNCORE_IMC] = &snbep_uncore_imc, 1314 [SNBEP_PCI_UNCORE_QPI] = &snbep_uncore_qpi, 1315 [SNBEP_PCI_UNCORE_R2PCIE] = &snbep_uncore_r2pcie, 1316 [SNBEP_PCI_UNCORE_R3QPI] = &snbep_uncore_r3qpi, 1317 NULL, 1318}; 1319 1320static const struct pci_device_id snbep_uncore_pci_ids[] = { 1321 { /* Home Agent */ 1322 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA), 1323 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_HA, 0), 1324 }, 1325 { /* MC Channel 0 */ 1326 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0), 1327 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 0), 1328 }, 1329 { /* MC Channel 1 */ 1330 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1), 1331 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 1), 1332 }, 1333 { /* MC Channel 2 */ 1334 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2), 1335 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 2), 1336 }, 1337 { /* MC Channel 3 */ 1338 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3), 1339 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 3), 1340 }, 1341 { /* QPI Port 0 */ 1342 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0), 1343 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI, 0), 1344 }, 1345 { /* QPI Port 1 */ 1346 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1), 1347 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI, 1), 1348 }, 1349 { /* R2PCIe */ 1350 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE), 1351 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R2PCIE, 0), 1352 }, 1353 { /* R3QPI Link 0 */ 1354 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0), 1355 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI, 0), 1356 }, 1357 { /* R3QPI Link 1 */ 1358 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1), 1359 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI, 1), 1360 }, 1361 { /* QPI Port 0 filter */ 1362 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3c86), 1363 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 1364 SNBEP_PCI_QPI_PORT0_FILTER), 1365 }, 1366 { /* QPI Port 0 filter */ 1367 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3c96), 1368 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 1369 SNBEP_PCI_QPI_PORT1_FILTER), 1370 }, 1371 { /* end: all zeroes */ } 1372}; 1373 1374static struct pci_driver snbep_uncore_pci_driver = { 1375 .name = "snbep_uncore", 1376 .id_table = snbep_uncore_pci_ids, 1377}; 1378 1379#define NODE_ID_MASK 0x7 1380 1381/* Each three bits from 0 to 23 of GIDNIDMAP register correspond Node ID. */ 1382#define GIDNIDMAP(config, id) (((config) >> (3 * (id))) & 0x7) 1383 1384static int upi_nodeid_groupid(struct pci_dev *ubox_dev, int nodeid_loc, int idmap_loc, 1385 int *nodeid, int *groupid) 1386{ 1387 int ret; 1388 1389 /* get the Node ID of the local register */ 1390 ret = pci_read_config_dword(ubox_dev, nodeid_loc, nodeid); 1391 if (ret) 1392 goto err; 1393 1394 *nodeid = *nodeid & NODE_ID_MASK; 1395 /* get the Node ID mapping */ 1396 ret = pci_read_config_dword(ubox_dev, idmap_loc, groupid); 1397 if (ret) 1398 goto err; 1399err: 1400 return ret; 1401} 1402 1403static int topology_gidnid_map(int nodeid, u32 gidnid) 1404{ 1405 int i, die_id = -1; 1406 1407 /* 1408 * every three bits in the Node ID mapping register maps 1409 * to a particular node. 1410 */ 1411 for (i = 0; i < 8; i++) { 1412 if (nodeid == GIDNIDMAP(gidnid, i)) { 1413 if (topology_max_dies_per_package() > 1) 1414 die_id = i; 1415 else 1416 die_id = topology_phys_to_logical_pkg(i); 1417 if (die_id < 0) 1418 die_id = -ENODEV; 1419 break; 1420 } 1421 } 1422 1423 return die_id; 1424} 1425 1426/* 1427 * build pci bus to socket mapping 1428 */ 1429static int snbep_pci2phy_map_init(int devid, int nodeid_loc, int idmap_loc, bool reverse) 1430{ 1431 struct pci_dev *ubox_dev = NULL; 1432 int i, bus, nodeid, segment, die_id; 1433 struct pci2phy_map *map; 1434 int err = 0; 1435 u32 config = 0; 1436 1437 while (1) { 1438 /* find the UBOX device */ 1439 ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, ubox_dev); 1440 if (!ubox_dev) 1441 break; 1442 bus = ubox_dev->bus->number; 1443 /* 1444 * The nodeid and idmap registers only contain enough 1445 * information to handle 8 nodes. On systems with more 1446 * than 8 nodes, we need to rely on NUMA information, 1447 * filled in from BIOS supplied information, to determine 1448 * the topology. 1449 */ 1450 if (nr_node_ids <= 8) { 1451 err = upi_nodeid_groupid(ubox_dev, nodeid_loc, idmap_loc, 1452 &nodeid, &config); 1453 if (err) 1454 break; 1455 1456 segment = pci_domain_nr(ubox_dev->bus); 1457 raw_spin_lock(&pci2phy_map_lock); 1458 map = __find_pci2phy_map(segment); 1459 if (!map) { 1460 raw_spin_unlock(&pci2phy_map_lock); 1461 err = -ENOMEM; 1462 break; 1463 } 1464 1465 map->pbus_to_dieid[bus] = topology_gidnid_map(nodeid, config); 1466 raw_spin_unlock(&pci2phy_map_lock); 1467 } else { 1468 segment = pci_domain_nr(ubox_dev->bus); 1469 raw_spin_lock(&pci2phy_map_lock); 1470 map = __find_pci2phy_map(segment); 1471 if (!map) { 1472 raw_spin_unlock(&pci2phy_map_lock); 1473 err = -ENOMEM; 1474 break; 1475 } 1476 1477 map->pbus_to_dieid[bus] = die_id = uncore_device_to_die(ubox_dev); 1478 raw_spin_unlock(&pci2phy_map_lock); 1479 } 1480 } 1481 1482 if (!err) { 1483 /* 1484 * For PCI bus with no UBOX device, find the next bus 1485 * that has UBOX device and use its mapping. 1486 */ 1487 raw_spin_lock(&pci2phy_map_lock); 1488 list_for_each_entry(map, &pci2phy_map_head, list) { 1489 i = -1; 1490 if (reverse) { 1491 for (bus = 255; bus >= 0; bus--) { 1492 if (map->pbus_to_dieid[bus] != -1) 1493 i = map->pbus_to_dieid[bus]; 1494 else 1495 map->pbus_to_dieid[bus] = i; 1496 } 1497 } else { 1498 for (bus = 0; bus <= 255; bus++) { 1499 if (map->pbus_to_dieid[bus] != -1) 1500 i = map->pbus_to_dieid[bus]; 1501 else 1502 map->pbus_to_dieid[bus] = i; 1503 } 1504 } 1505 } 1506 raw_spin_unlock(&pci2phy_map_lock); 1507 } 1508 1509 pci_dev_put(ubox_dev); 1510 1511 return pcibios_err_to_errno(err); 1512} 1513 1514int snbep_uncore_pci_init(void) 1515{ 1516 int ret = snbep_pci2phy_map_init(0x3ce0, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true); 1517 if (ret) 1518 return ret; 1519 uncore_pci_uncores = snbep_pci_uncores; 1520 uncore_pci_driver = &snbep_uncore_pci_driver; 1521 return 0; 1522} 1523/* end of Sandy Bridge-EP uncore support */ 1524 1525/* IvyTown uncore support */ 1526static void ivbep_uncore_msr_init_box(struct intel_uncore_box *box) 1527{ 1528 unsigned msr = uncore_msr_box_ctl(box); 1529 if (msr) 1530 wrmsrq(msr, IVBEP_PMON_BOX_CTL_INT); 1531} 1532 1533static void ivbep_uncore_pci_init_box(struct intel_uncore_box *box) 1534{ 1535 struct pci_dev *pdev = box->pci_dev; 1536 1537 pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, IVBEP_PMON_BOX_CTL_INT); 1538} 1539 1540#define IVBEP_UNCORE_MSR_OPS_COMMON_INIT() \ 1541 .init_box = ivbep_uncore_msr_init_box, \ 1542 .disable_box = snbep_uncore_msr_disable_box, \ 1543 .enable_box = snbep_uncore_msr_enable_box, \ 1544 .disable_event = snbep_uncore_msr_disable_event, \ 1545 .enable_event = snbep_uncore_msr_enable_event, \ 1546 .read_counter = uncore_msr_read_counter 1547 1548static struct intel_uncore_ops ivbep_uncore_msr_ops = { 1549 IVBEP_UNCORE_MSR_OPS_COMMON_INIT(), 1550}; 1551 1552static struct intel_uncore_ops ivbep_uncore_pci_ops = { 1553 .init_box = ivbep_uncore_pci_init_box, 1554 .disable_box = snbep_uncore_pci_disable_box, 1555 .enable_box = snbep_uncore_pci_enable_box, 1556 .disable_event = snbep_uncore_pci_disable_event, 1557 .enable_event = snbep_uncore_pci_enable_event, 1558 .read_counter = snbep_uncore_pci_read_counter, 1559}; 1560 1561#define IVBEP_UNCORE_PCI_COMMON_INIT() \ 1562 .perf_ctr = SNBEP_PCI_PMON_CTR0, \ 1563 .event_ctl = SNBEP_PCI_PMON_CTL0, \ 1564 .event_mask = IVBEP_PMON_RAW_EVENT_MASK, \ 1565 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \ 1566 .ops = &ivbep_uncore_pci_ops, \ 1567 .format_group = &ivbep_uncore_format_group 1568 1569static struct attribute *ivbep_uncore_formats_attr[] = { 1570 &format_attr_event.attr, 1571 &format_attr_umask.attr, 1572 &format_attr_edge.attr, 1573 &format_attr_inv.attr, 1574 &format_attr_thresh8.attr, 1575 NULL, 1576}; 1577 1578static struct attribute *ivbep_uncore_ubox_formats_attr[] = { 1579 &format_attr_event.attr, 1580 &format_attr_umask.attr, 1581 &format_attr_edge.attr, 1582 &format_attr_inv.attr, 1583 &format_attr_thresh5.attr, 1584 NULL, 1585}; 1586 1587static struct attribute *ivbep_uncore_cbox_formats_attr[] = { 1588 &format_attr_event.attr, 1589 &format_attr_umask.attr, 1590 &format_attr_edge.attr, 1591 &format_attr_tid_en.attr, 1592 &format_attr_thresh8.attr, 1593 &format_attr_filter_tid.attr, 1594 &format_attr_filter_link.attr, 1595 &format_attr_filter_state2.attr, 1596 &format_attr_filter_nid2.attr, 1597 &format_attr_filter_opc2.attr, 1598 &format_attr_filter_nc.attr, 1599 &format_attr_filter_c6.attr, 1600 &format_attr_filter_isoc.attr, 1601 NULL, 1602}; 1603 1604static struct attribute *ivbep_uncore_pcu_formats_attr[] = { 1605 &format_attr_event.attr, 1606 &format_attr_occ_sel.attr, 1607 &format_attr_edge.attr, 1608 &format_attr_thresh5.attr, 1609 &format_attr_occ_invert.attr, 1610 &format_attr_occ_edge.attr, 1611 &format_attr_filter_band0.attr, 1612 &format_attr_filter_band1.attr, 1613 &format_attr_filter_band2.attr, 1614 &format_attr_filter_band3.attr, 1615 NULL, 1616}; 1617 1618static struct attribute *ivbep_uncore_qpi_formats_attr[] = { 1619 &format_attr_event_ext.attr, 1620 &format_attr_umask.attr, 1621 &format_attr_edge.attr, 1622 &format_attr_thresh8.attr, 1623 &format_attr_match_rds.attr, 1624 &format_attr_match_rnid30.attr, 1625 &format_attr_match_rnid4.attr, 1626 &format_attr_match_dnid.attr, 1627 &format_attr_match_mc.attr, 1628 &format_attr_match_opc.attr, 1629 &format_attr_match_vnw.attr, 1630 &format_attr_match0.attr, 1631 &format_attr_match1.attr, 1632 &format_attr_mask_rds.attr, 1633 &format_attr_mask_rnid30.attr, 1634 &format_attr_mask_rnid4.attr, 1635 &format_attr_mask_dnid.attr, 1636 &format_attr_mask_mc.attr, 1637 &format_attr_mask_opc.attr, 1638 &format_attr_mask_vnw.attr, 1639 &format_attr_mask0.attr, 1640 &format_attr_mask1.attr, 1641 NULL, 1642}; 1643 1644static const struct attribute_group ivbep_uncore_format_group = { 1645 .name = "format", 1646 .attrs = ivbep_uncore_formats_attr, 1647}; 1648 1649static const struct attribute_group ivbep_uncore_ubox_format_group = { 1650 .name = "format", 1651 .attrs = ivbep_uncore_ubox_formats_attr, 1652}; 1653 1654static const struct attribute_group ivbep_uncore_cbox_format_group = { 1655 .name = "format", 1656 .attrs = ivbep_uncore_cbox_formats_attr, 1657}; 1658 1659static const struct attribute_group ivbep_uncore_pcu_format_group = { 1660 .name = "format", 1661 .attrs = ivbep_uncore_pcu_formats_attr, 1662}; 1663 1664static const struct attribute_group ivbep_uncore_qpi_format_group = { 1665 .name = "format", 1666 .attrs = ivbep_uncore_qpi_formats_attr, 1667}; 1668 1669static struct intel_uncore_type ivbep_uncore_ubox = { 1670 .name = "ubox", 1671 .num_counters = 2, 1672 .num_boxes = 1, 1673 .perf_ctr_bits = 44, 1674 .fixed_ctr_bits = 48, 1675 .perf_ctr = SNBEP_U_MSR_PMON_CTR0, 1676 .event_ctl = SNBEP_U_MSR_PMON_CTL0, 1677 .event_mask = IVBEP_U_MSR_PMON_RAW_EVENT_MASK, 1678 .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR, 1679 .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL, 1680 .ops = &ivbep_uncore_msr_ops, 1681 .format_group = &ivbep_uncore_ubox_format_group, 1682}; 1683 1684static struct extra_reg ivbep_uncore_cbox_extra_regs[] = { 1685 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN, 1686 SNBEP_CBO_PMON_CTL_TID_EN, 0x1), 1687 SNBEP_CBO_EVENT_EXTRA_REG(0x1031, 0x10ff, 0x2), 1688 SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4), 1689 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0xc), 1690 SNBEP_CBO_EVENT_EXTRA_REG(0x5134, 0xffff, 0xc), 1691 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4), 1692 SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0xc), 1693 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4), 1694 SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0xc), 1695 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4), 1696 SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0xc), 1697 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x10), 1698 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10), 1699 SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10), 1700 SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10), 1701 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18), 1702 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18), 1703 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8), 1704 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8), 1705 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8), 1706 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8), 1707 SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10), 1708 SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10), 1709 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10), 1710 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10), 1711 SNBEP_CBO_EVENT_EXTRA_REG(0x2136, 0xffff, 0x10), 1712 SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10), 1713 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18), 1714 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18), 1715 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8), 1716 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8), 1717 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8), 1718 SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8), 1719 SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10), 1720 SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10), 1721 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8), 1722 EVENT_EXTRA_END 1723}; 1724 1725static u64 ivbep_cbox_filter_mask(int fields) 1726{ 1727 u64 mask = 0; 1728 1729 if (fields & 0x1) 1730 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_TID; 1731 if (fields & 0x2) 1732 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_LINK; 1733 if (fields & 0x4) 1734 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_STATE; 1735 if (fields & 0x8) 1736 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_NID; 1737 if (fields & 0x10) { 1738 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_OPC; 1739 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_NC; 1740 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_C6; 1741 mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_ISOC; 1742 } 1743 1744 return mask; 1745} 1746 1747static struct event_constraint * 1748ivbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 1749{ 1750 return __snbep_cbox_get_constraint(box, event, ivbep_cbox_filter_mask); 1751} 1752 1753static int ivbep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event) 1754{ 1755 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 1756 struct extra_reg *er; 1757 int idx = 0; 1758 1759 for (er = ivbep_uncore_cbox_extra_regs; er->msr; er++) { 1760 if (er->event != (event->hw.config & er->config_mask)) 1761 continue; 1762 idx |= er->idx; 1763 } 1764 1765 if (idx) { 1766 reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER + 1767 SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx; 1768 reg1->config = event->attr.config1 & ivbep_cbox_filter_mask(idx); 1769 reg1->idx = idx; 1770 } 1771 return 0; 1772} 1773 1774static void ivbep_cbox_enable_event(struct intel_uncore_box *box, struct perf_event *event) 1775{ 1776 struct hw_perf_event *hwc = &event->hw; 1777 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 1778 1779 if (reg1->idx != EXTRA_REG_NONE) { 1780 u64 filter = uncore_shared_reg_config(box, 0); 1781 wrmsrq(reg1->reg, filter & 0xffffffff); 1782 wrmsrq(reg1->reg + 6, filter >> 32); 1783 } 1784 1785 wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 1786} 1787 1788static struct intel_uncore_ops ivbep_uncore_cbox_ops = { 1789 .init_box = ivbep_uncore_msr_init_box, 1790 .disable_box = snbep_uncore_msr_disable_box, 1791 .enable_box = snbep_uncore_msr_enable_box, 1792 .disable_event = snbep_uncore_msr_disable_event, 1793 .enable_event = ivbep_cbox_enable_event, 1794 .read_counter = uncore_msr_read_counter, 1795 .hw_config = ivbep_cbox_hw_config, 1796 .get_constraint = ivbep_cbox_get_constraint, 1797 .put_constraint = snbep_cbox_put_constraint, 1798}; 1799 1800static struct intel_uncore_type ivbep_uncore_cbox = { 1801 .name = "cbox", 1802 .num_counters = 4, 1803 .num_boxes = 15, 1804 .perf_ctr_bits = 44, 1805 .event_ctl = SNBEP_C0_MSR_PMON_CTL0, 1806 .perf_ctr = SNBEP_C0_MSR_PMON_CTR0, 1807 .event_mask = IVBEP_CBO_MSR_PMON_RAW_EVENT_MASK, 1808 .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL, 1809 .msr_offset = SNBEP_CBO_MSR_OFFSET, 1810 .num_shared_regs = 1, 1811 .constraints = snbep_uncore_cbox_constraints, 1812 .ops = &ivbep_uncore_cbox_ops, 1813 .format_group = &ivbep_uncore_cbox_format_group, 1814}; 1815 1816static struct intel_uncore_ops ivbep_uncore_pcu_ops = { 1817 IVBEP_UNCORE_MSR_OPS_COMMON_INIT(), 1818 .hw_config = snbep_pcu_hw_config, 1819 .get_constraint = snbep_pcu_get_constraint, 1820 .put_constraint = snbep_pcu_put_constraint, 1821}; 1822 1823static struct intel_uncore_type ivbep_uncore_pcu = { 1824 .name = "pcu", 1825 .num_counters = 4, 1826 .num_boxes = 1, 1827 .perf_ctr_bits = 48, 1828 .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0, 1829 .event_ctl = SNBEP_PCU_MSR_PMON_CTL0, 1830 .event_mask = IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK, 1831 .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL, 1832 .num_shared_regs = 1, 1833 .ops = &ivbep_uncore_pcu_ops, 1834 .format_group = &ivbep_uncore_pcu_format_group, 1835}; 1836 1837static struct intel_uncore_type *ivbep_msr_uncores[] = { 1838 &ivbep_uncore_ubox, 1839 &ivbep_uncore_cbox, 1840 &ivbep_uncore_pcu, 1841 NULL, 1842}; 1843 1844void ivbep_uncore_cpu_init(void) 1845{ 1846 if (ivbep_uncore_cbox.num_boxes > topology_num_cores_per_package()) 1847 ivbep_uncore_cbox.num_boxes = topology_num_cores_per_package(); 1848 uncore_msr_uncores = ivbep_msr_uncores; 1849} 1850 1851static struct intel_uncore_type ivbep_uncore_ha = { 1852 .name = "ha", 1853 .num_counters = 4, 1854 .num_boxes = 2, 1855 .perf_ctr_bits = 48, 1856 IVBEP_UNCORE_PCI_COMMON_INIT(), 1857}; 1858 1859static struct intel_uncore_type ivbep_uncore_imc = { 1860 .name = "imc", 1861 .num_counters = 4, 1862 .num_boxes = 8, 1863 .perf_ctr_bits = 48, 1864 .fixed_ctr_bits = 48, 1865 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR, 1866 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL, 1867 .event_descs = snbep_uncore_imc_events, 1868 IVBEP_UNCORE_PCI_COMMON_INIT(), 1869}; 1870 1871/* registers in IRP boxes are not properly aligned */ 1872static unsigned ivbep_uncore_irp_ctls[] = {0xd8, 0xdc, 0xe0, 0xe4}; 1873static unsigned ivbep_uncore_irp_ctrs[] = {0xa0, 0xb0, 0xb8, 0xc0}; 1874 1875static void ivbep_uncore_irp_enable_event(struct intel_uncore_box *box, struct perf_event *event) 1876{ 1877 struct pci_dev *pdev = box->pci_dev; 1878 struct hw_perf_event *hwc = &event->hw; 1879 1880 pci_write_config_dword(pdev, ivbep_uncore_irp_ctls[hwc->idx], 1881 hwc->config | SNBEP_PMON_CTL_EN); 1882} 1883 1884static void ivbep_uncore_irp_disable_event(struct intel_uncore_box *box, struct perf_event *event) 1885{ 1886 struct pci_dev *pdev = box->pci_dev; 1887 struct hw_perf_event *hwc = &event->hw; 1888 1889 pci_write_config_dword(pdev, ivbep_uncore_irp_ctls[hwc->idx], hwc->config); 1890} 1891 1892static u64 ivbep_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event) 1893{ 1894 struct pci_dev *pdev = box->pci_dev; 1895 struct hw_perf_event *hwc = &event->hw; 1896 u64 count = 0; 1897 1898 pci_read_config_dword(pdev, ivbep_uncore_irp_ctrs[hwc->idx], (u32 *)&count); 1899 pci_read_config_dword(pdev, ivbep_uncore_irp_ctrs[hwc->idx] + 4, (u32 *)&count + 1); 1900 1901 return count; 1902} 1903 1904static struct intel_uncore_ops ivbep_uncore_irp_ops = { 1905 .init_box = ivbep_uncore_pci_init_box, 1906 .disable_box = snbep_uncore_pci_disable_box, 1907 .enable_box = snbep_uncore_pci_enable_box, 1908 .disable_event = ivbep_uncore_irp_disable_event, 1909 .enable_event = ivbep_uncore_irp_enable_event, 1910 .read_counter = ivbep_uncore_irp_read_counter, 1911}; 1912 1913static struct intel_uncore_type ivbep_uncore_irp = { 1914 .name = "irp", 1915 .num_counters = 4, 1916 .num_boxes = 1, 1917 .perf_ctr_bits = 48, 1918 .event_mask = IVBEP_PMON_RAW_EVENT_MASK, 1919 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 1920 .ops = &ivbep_uncore_irp_ops, 1921 .format_group = &ivbep_uncore_format_group, 1922}; 1923 1924static struct intel_uncore_ops ivbep_uncore_qpi_ops = { 1925 .init_box = ivbep_uncore_pci_init_box, 1926 .disable_box = snbep_uncore_pci_disable_box, 1927 .enable_box = snbep_uncore_pci_enable_box, 1928 .disable_event = snbep_uncore_pci_disable_event, 1929 .enable_event = snbep_qpi_enable_event, 1930 .read_counter = snbep_uncore_pci_read_counter, 1931 .hw_config = snbep_qpi_hw_config, 1932 .get_constraint = uncore_get_constraint, 1933 .put_constraint = uncore_put_constraint, 1934}; 1935 1936static struct intel_uncore_type ivbep_uncore_qpi = { 1937 .name = "qpi", 1938 .num_counters = 4, 1939 .num_boxes = 3, 1940 .perf_ctr_bits = 48, 1941 .perf_ctr = SNBEP_PCI_PMON_CTR0, 1942 .event_ctl = SNBEP_PCI_PMON_CTL0, 1943 .event_mask = IVBEP_QPI_PCI_PMON_RAW_EVENT_MASK, 1944 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 1945 .num_shared_regs = 1, 1946 .ops = &ivbep_uncore_qpi_ops, 1947 .format_group = &ivbep_uncore_qpi_format_group, 1948}; 1949 1950static struct intel_uncore_type ivbep_uncore_r2pcie = { 1951 .name = "r2pcie", 1952 .num_counters = 4, 1953 .num_boxes = 1, 1954 .perf_ctr_bits = 44, 1955 .constraints = snbep_uncore_r2pcie_constraints, 1956 IVBEP_UNCORE_PCI_COMMON_INIT(), 1957}; 1958 1959static struct intel_uncore_type ivbep_uncore_r3qpi = { 1960 .name = "r3qpi", 1961 .num_counters = 3, 1962 .num_boxes = 2, 1963 .perf_ctr_bits = 44, 1964 .constraints = snbep_uncore_r3qpi_constraints, 1965 IVBEP_UNCORE_PCI_COMMON_INIT(), 1966}; 1967 1968enum { 1969 IVBEP_PCI_UNCORE_HA, 1970 IVBEP_PCI_UNCORE_IMC, 1971 IVBEP_PCI_UNCORE_IRP, 1972 IVBEP_PCI_UNCORE_QPI, 1973 IVBEP_PCI_UNCORE_R2PCIE, 1974 IVBEP_PCI_UNCORE_R3QPI, 1975}; 1976 1977static struct intel_uncore_type *ivbep_pci_uncores[] = { 1978 [IVBEP_PCI_UNCORE_HA] = &ivbep_uncore_ha, 1979 [IVBEP_PCI_UNCORE_IMC] = &ivbep_uncore_imc, 1980 [IVBEP_PCI_UNCORE_IRP] = &ivbep_uncore_irp, 1981 [IVBEP_PCI_UNCORE_QPI] = &ivbep_uncore_qpi, 1982 [IVBEP_PCI_UNCORE_R2PCIE] = &ivbep_uncore_r2pcie, 1983 [IVBEP_PCI_UNCORE_R3QPI] = &ivbep_uncore_r3qpi, 1984 NULL, 1985}; 1986 1987static const struct pci_device_id ivbep_uncore_pci_ids[] = { 1988 { /* Home Agent 0 */ 1989 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe30), 1990 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_HA, 0), 1991 }, 1992 { /* Home Agent 1 */ 1993 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe38), 1994 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_HA, 1), 1995 }, 1996 { /* MC0 Channel 0 */ 1997 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb4), 1998 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 0), 1999 }, 2000 { /* MC0 Channel 1 */ 2001 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb5), 2002 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 1), 2003 }, 2004 { /* MC0 Channel 3 */ 2005 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb0), 2006 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 2), 2007 }, 2008 { /* MC0 Channel 4 */ 2009 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb1), 2010 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 3), 2011 }, 2012 { /* MC1 Channel 0 */ 2013 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef4), 2014 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 4), 2015 }, 2016 { /* MC1 Channel 1 */ 2017 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef5), 2018 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 5), 2019 }, 2020 { /* MC1 Channel 3 */ 2021 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef0), 2022 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 6), 2023 }, 2024 { /* MC1 Channel 4 */ 2025 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef1), 2026 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 7), 2027 }, 2028 { /* IRP */ 2029 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe39), 2030 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IRP, 0), 2031 }, 2032 { /* QPI0 Port 0 */ 2033 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe32), 2034 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_QPI, 0), 2035 }, 2036 { /* QPI0 Port 1 */ 2037 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe33), 2038 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_QPI, 1), 2039 }, 2040 { /* QPI1 Port 2 */ 2041 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3a), 2042 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_QPI, 2), 2043 }, 2044 { /* R2PCIe */ 2045 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe34), 2046 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R2PCIE, 0), 2047 }, 2048 { /* R3QPI0 Link 0 */ 2049 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe36), 2050 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R3QPI, 0), 2051 }, 2052 { /* R3QPI0 Link 1 */ 2053 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe37), 2054 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R3QPI, 1), 2055 }, 2056 { /* R3QPI1 Link 2 */ 2057 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3e), 2058 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R3QPI, 2), 2059 }, 2060 { /* QPI Port 0 filter */ 2061 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe86), 2062 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 2063 SNBEP_PCI_QPI_PORT0_FILTER), 2064 }, 2065 { /* QPI Port 0 filter */ 2066 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe96), 2067 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 2068 SNBEP_PCI_QPI_PORT1_FILTER), 2069 }, 2070 { /* end: all zeroes */ } 2071}; 2072 2073static struct pci_driver ivbep_uncore_pci_driver = { 2074 .name = "ivbep_uncore", 2075 .id_table = ivbep_uncore_pci_ids, 2076}; 2077 2078int ivbep_uncore_pci_init(void) 2079{ 2080 int ret = snbep_pci2phy_map_init(0x0e1e, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true); 2081 if (ret) 2082 return ret; 2083 uncore_pci_uncores = ivbep_pci_uncores; 2084 uncore_pci_driver = &ivbep_uncore_pci_driver; 2085 return 0; 2086} 2087/* end of IvyTown uncore support */ 2088 2089/* KNL uncore support */ 2090static struct attribute *knl_uncore_ubox_formats_attr[] = { 2091 &format_attr_event.attr, 2092 &format_attr_umask.attr, 2093 &format_attr_edge.attr, 2094 &format_attr_tid_en.attr, 2095 &format_attr_inv.attr, 2096 &format_attr_thresh5.attr, 2097 NULL, 2098}; 2099 2100static const struct attribute_group knl_uncore_ubox_format_group = { 2101 .name = "format", 2102 .attrs = knl_uncore_ubox_formats_attr, 2103}; 2104 2105static struct intel_uncore_type knl_uncore_ubox = { 2106 .name = "ubox", 2107 .num_counters = 2, 2108 .num_boxes = 1, 2109 .perf_ctr_bits = 48, 2110 .fixed_ctr_bits = 48, 2111 .perf_ctr = HSWEP_U_MSR_PMON_CTR0, 2112 .event_ctl = HSWEP_U_MSR_PMON_CTL0, 2113 .event_mask = KNL_U_MSR_PMON_RAW_EVENT_MASK, 2114 .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR, 2115 .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL, 2116 .ops = &snbep_uncore_msr_ops, 2117 .format_group = &knl_uncore_ubox_format_group, 2118}; 2119 2120static struct attribute *knl_uncore_cha_formats_attr[] = { 2121 &format_attr_event.attr, 2122 &format_attr_umask.attr, 2123 &format_attr_qor.attr, 2124 &format_attr_edge.attr, 2125 &format_attr_tid_en.attr, 2126 &format_attr_inv.attr, 2127 &format_attr_thresh8.attr, 2128 &format_attr_filter_tid4.attr, 2129 &format_attr_filter_link3.attr, 2130 &format_attr_filter_state4.attr, 2131 &format_attr_filter_local.attr, 2132 &format_attr_filter_all_op.attr, 2133 &format_attr_filter_nnm.attr, 2134 &format_attr_filter_opc3.attr, 2135 &format_attr_filter_nc.attr, 2136 &format_attr_filter_isoc.attr, 2137 NULL, 2138}; 2139 2140static const struct attribute_group knl_uncore_cha_format_group = { 2141 .name = "format", 2142 .attrs = knl_uncore_cha_formats_attr, 2143}; 2144 2145static struct event_constraint knl_uncore_cha_constraints[] = { 2146 UNCORE_EVENT_CONSTRAINT(0x11, 0x1), 2147 UNCORE_EVENT_CONSTRAINT(0x1f, 0x1), 2148 UNCORE_EVENT_CONSTRAINT(0x36, 0x1), 2149 EVENT_CONSTRAINT_END 2150}; 2151 2152static struct extra_reg knl_uncore_cha_extra_regs[] = { 2153 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN, 2154 SNBEP_CBO_PMON_CTL_TID_EN, 0x1), 2155 SNBEP_CBO_EVENT_EXTRA_REG(0x3d, 0xff, 0x2), 2156 SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x4), 2157 SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x4), 2158 EVENT_EXTRA_END 2159}; 2160 2161static u64 knl_cha_filter_mask(int fields) 2162{ 2163 u64 mask = 0; 2164 2165 if (fields & 0x1) 2166 mask |= KNL_CHA_MSR_PMON_BOX_FILTER_TID; 2167 if (fields & 0x2) 2168 mask |= KNL_CHA_MSR_PMON_BOX_FILTER_STATE; 2169 if (fields & 0x4) 2170 mask |= KNL_CHA_MSR_PMON_BOX_FILTER_OP; 2171 return mask; 2172} 2173 2174static struct event_constraint * 2175knl_cha_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 2176{ 2177 return __snbep_cbox_get_constraint(box, event, knl_cha_filter_mask); 2178} 2179 2180static int knl_cha_hw_config(struct intel_uncore_box *box, 2181 struct perf_event *event) 2182{ 2183 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 2184 struct extra_reg *er; 2185 int idx = 0; 2186 2187 for (er = knl_uncore_cha_extra_regs; er->msr; er++) { 2188 if (er->event != (event->hw.config & er->config_mask)) 2189 continue; 2190 idx |= er->idx; 2191 } 2192 2193 if (idx) { 2194 reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 + 2195 KNL_CHA_MSR_OFFSET * box->pmu->pmu_idx; 2196 reg1->config = event->attr.config1 & knl_cha_filter_mask(idx); 2197 2198 reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE; 2199 reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE; 2200 reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_NNC; 2201 reg1->idx = idx; 2202 } 2203 return 0; 2204} 2205 2206static void hswep_cbox_enable_event(struct intel_uncore_box *box, 2207 struct perf_event *event); 2208 2209static struct intel_uncore_ops knl_uncore_cha_ops = { 2210 .init_box = snbep_uncore_msr_init_box, 2211 .disable_box = snbep_uncore_msr_disable_box, 2212 .enable_box = snbep_uncore_msr_enable_box, 2213 .disable_event = snbep_uncore_msr_disable_event, 2214 .enable_event = hswep_cbox_enable_event, 2215 .read_counter = uncore_msr_read_counter, 2216 .hw_config = knl_cha_hw_config, 2217 .get_constraint = knl_cha_get_constraint, 2218 .put_constraint = snbep_cbox_put_constraint, 2219}; 2220 2221static struct intel_uncore_type knl_uncore_cha = { 2222 .name = "cha", 2223 .num_counters = 4, 2224 .num_boxes = 38, 2225 .perf_ctr_bits = 48, 2226 .event_ctl = HSWEP_C0_MSR_PMON_CTL0, 2227 .perf_ctr = HSWEP_C0_MSR_PMON_CTR0, 2228 .event_mask = KNL_CHA_MSR_PMON_RAW_EVENT_MASK, 2229 .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL, 2230 .msr_offset = KNL_CHA_MSR_OFFSET, 2231 .num_shared_regs = 1, 2232 .constraints = knl_uncore_cha_constraints, 2233 .ops = &knl_uncore_cha_ops, 2234 .format_group = &knl_uncore_cha_format_group, 2235}; 2236 2237static struct attribute *knl_uncore_pcu_formats_attr[] = { 2238 &format_attr_event2.attr, 2239 &format_attr_use_occ_ctr.attr, 2240 &format_attr_occ_sel.attr, 2241 &format_attr_edge.attr, 2242 &format_attr_tid_en.attr, 2243 &format_attr_inv.attr, 2244 &format_attr_thresh6.attr, 2245 &format_attr_occ_invert.attr, 2246 &format_attr_occ_edge_det.attr, 2247 NULL, 2248}; 2249 2250static const struct attribute_group knl_uncore_pcu_format_group = { 2251 .name = "format", 2252 .attrs = knl_uncore_pcu_formats_attr, 2253}; 2254 2255static struct intel_uncore_type knl_uncore_pcu = { 2256 .name = "pcu", 2257 .num_counters = 4, 2258 .num_boxes = 1, 2259 .perf_ctr_bits = 48, 2260 .perf_ctr = HSWEP_PCU_MSR_PMON_CTR0, 2261 .event_ctl = HSWEP_PCU_MSR_PMON_CTL0, 2262 .event_mask = KNL_PCU_MSR_PMON_RAW_EVENT_MASK, 2263 .box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL, 2264 .ops = &snbep_uncore_msr_ops, 2265 .format_group = &knl_uncore_pcu_format_group, 2266}; 2267 2268static struct intel_uncore_type *knl_msr_uncores[] = { 2269 &knl_uncore_ubox, 2270 &knl_uncore_cha, 2271 &knl_uncore_pcu, 2272 NULL, 2273}; 2274 2275void knl_uncore_cpu_init(void) 2276{ 2277 uncore_msr_uncores = knl_msr_uncores; 2278} 2279 2280static void knl_uncore_imc_enable_box(struct intel_uncore_box *box) 2281{ 2282 struct pci_dev *pdev = box->pci_dev; 2283 int box_ctl = uncore_pci_box_ctl(box); 2284 2285 pci_write_config_dword(pdev, box_ctl, 0); 2286} 2287 2288static void knl_uncore_imc_enable_event(struct intel_uncore_box *box, 2289 struct perf_event *event) 2290{ 2291 struct pci_dev *pdev = box->pci_dev; 2292 struct hw_perf_event *hwc = &event->hw; 2293 2294 if ((event->attr.config & SNBEP_PMON_CTL_EV_SEL_MASK) 2295 == UNCORE_FIXED_EVENT) 2296 pci_write_config_dword(pdev, hwc->config_base, 2297 hwc->config | KNL_PMON_FIXED_CTL_EN); 2298 else 2299 pci_write_config_dword(pdev, hwc->config_base, 2300 hwc->config | SNBEP_PMON_CTL_EN); 2301} 2302 2303static struct intel_uncore_ops knl_uncore_imc_ops = { 2304 .init_box = snbep_uncore_pci_init_box, 2305 .disable_box = snbep_uncore_pci_disable_box, 2306 .enable_box = knl_uncore_imc_enable_box, 2307 .read_counter = snbep_uncore_pci_read_counter, 2308 .enable_event = knl_uncore_imc_enable_event, 2309 .disable_event = snbep_uncore_pci_disable_event, 2310}; 2311 2312static struct intel_uncore_type knl_uncore_imc_uclk = { 2313 .name = "imc_uclk", 2314 .num_counters = 4, 2315 .num_boxes = 2, 2316 .perf_ctr_bits = 48, 2317 .fixed_ctr_bits = 48, 2318 .perf_ctr = KNL_UCLK_MSR_PMON_CTR0_LOW, 2319 .event_ctl = KNL_UCLK_MSR_PMON_CTL0, 2320 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 2321 .fixed_ctr = KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW, 2322 .fixed_ctl = KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL, 2323 .box_ctl = KNL_UCLK_MSR_PMON_BOX_CTL, 2324 .ops = &knl_uncore_imc_ops, 2325 .format_group = &snbep_uncore_format_group, 2326}; 2327 2328static struct intel_uncore_type knl_uncore_imc_dclk = { 2329 .name = "imc", 2330 .num_counters = 4, 2331 .num_boxes = 6, 2332 .perf_ctr_bits = 48, 2333 .fixed_ctr_bits = 48, 2334 .perf_ctr = KNL_MC0_CH0_MSR_PMON_CTR0_LOW, 2335 .event_ctl = KNL_MC0_CH0_MSR_PMON_CTL0, 2336 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 2337 .fixed_ctr = KNL_MC0_CH0_MSR_PMON_FIXED_LOW, 2338 .fixed_ctl = KNL_MC0_CH0_MSR_PMON_FIXED_CTL, 2339 .box_ctl = KNL_MC0_CH0_MSR_PMON_BOX_CTL, 2340 .ops = &knl_uncore_imc_ops, 2341 .format_group = &snbep_uncore_format_group, 2342}; 2343 2344static struct intel_uncore_type knl_uncore_edc_uclk = { 2345 .name = "edc_uclk", 2346 .num_counters = 4, 2347 .num_boxes = 8, 2348 .perf_ctr_bits = 48, 2349 .fixed_ctr_bits = 48, 2350 .perf_ctr = KNL_UCLK_MSR_PMON_CTR0_LOW, 2351 .event_ctl = KNL_UCLK_MSR_PMON_CTL0, 2352 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 2353 .fixed_ctr = KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW, 2354 .fixed_ctl = KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL, 2355 .box_ctl = KNL_UCLK_MSR_PMON_BOX_CTL, 2356 .ops = &knl_uncore_imc_ops, 2357 .format_group = &snbep_uncore_format_group, 2358}; 2359 2360static struct intel_uncore_type knl_uncore_edc_eclk = { 2361 .name = "edc_eclk", 2362 .num_counters = 4, 2363 .num_boxes = 8, 2364 .perf_ctr_bits = 48, 2365 .fixed_ctr_bits = 48, 2366 .perf_ctr = KNL_EDC0_ECLK_MSR_PMON_CTR0_LOW, 2367 .event_ctl = KNL_EDC0_ECLK_MSR_PMON_CTL0, 2368 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 2369 .fixed_ctr = KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_LOW, 2370 .fixed_ctl = KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_CTL, 2371 .box_ctl = KNL_EDC0_ECLK_MSR_PMON_BOX_CTL, 2372 .ops = &knl_uncore_imc_ops, 2373 .format_group = &snbep_uncore_format_group, 2374}; 2375 2376static struct event_constraint knl_uncore_m2pcie_constraints[] = { 2377 UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 2378 EVENT_CONSTRAINT_END 2379}; 2380 2381static struct intel_uncore_type knl_uncore_m2pcie = { 2382 .name = "m2pcie", 2383 .num_counters = 4, 2384 .num_boxes = 1, 2385 .perf_ctr_bits = 48, 2386 .constraints = knl_uncore_m2pcie_constraints, 2387 SNBEP_UNCORE_PCI_COMMON_INIT(), 2388}; 2389 2390static struct attribute *knl_uncore_irp_formats_attr[] = { 2391 &format_attr_event.attr, 2392 &format_attr_umask.attr, 2393 &format_attr_qor.attr, 2394 &format_attr_edge.attr, 2395 &format_attr_inv.attr, 2396 &format_attr_thresh8.attr, 2397 NULL, 2398}; 2399 2400static const struct attribute_group knl_uncore_irp_format_group = { 2401 .name = "format", 2402 .attrs = knl_uncore_irp_formats_attr, 2403}; 2404 2405static struct intel_uncore_type knl_uncore_irp = { 2406 .name = "irp", 2407 .num_counters = 2, 2408 .num_boxes = 1, 2409 .perf_ctr_bits = 48, 2410 .perf_ctr = SNBEP_PCI_PMON_CTR0, 2411 .event_ctl = SNBEP_PCI_PMON_CTL0, 2412 .event_mask = KNL_IRP_PCI_PMON_RAW_EVENT_MASK, 2413 .box_ctl = KNL_IRP_PCI_PMON_BOX_CTL, 2414 .ops = &snbep_uncore_pci_ops, 2415 .format_group = &knl_uncore_irp_format_group, 2416}; 2417 2418enum { 2419 KNL_PCI_UNCORE_MC_UCLK, 2420 KNL_PCI_UNCORE_MC_DCLK, 2421 KNL_PCI_UNCORE_EDC_UCLK, 2422 KNL_PCI_UNCORE_EDC_ECLK, 2423 KNL_PCI_UNCORE_M2PCIE, 2424 KNL_PCI_UNCORE_IRP, 2425}; 2426 2427static struct intel_uncore_type *knl_pci_uncores[] = { 2428 [KNL_PCI_UNCORE_MC_UCLK] = &knl_uncore_imc_uclk, 2429 [KNL_PCI_UNCORE_MC_DCLK] = &knl_uncore_imc_dclk, 2430 [KNL_PCI_UNCORE_EDC_UCLK] = &knl_uncore_edc_uclk, 2431 [KNL_PCI_UNCORE_EDC_ECLK] = &knl_uncore_edc_eclk, 2432 [KNL_PCI_UNCORE_M2PCIE] = &knl_uncore_m2pcie, 2433 [KNL_PCI_UNCORE_IRP] = &knl_uncore_irp, 2434 NULL, 2435}; 2436 2437/* 2438 * KNL uses a common PCI device ID for multiple instances of an Uncore PMU 2439 * device type. prior to KNL, each instance of a PMU device type had a unique 2440 * device ID. 2441 * 2442 * PCI Device ID Uncore PMU Devices 2443 * ---------------------------------- 2444 * 0x7841 MC0 UClk, MC1 UClk 2445 * 0x7843 MC0 DClk CH 0, MC0 DClk CH 1, MC0 DClk CH 2, 2446 * MC1 DClk CH 0, MC1 DClk CH 1, MC1 DClk CH 2 2447 * 0x7833 EDC0 UClk, EDC1 UClk, EDC2 UClk, EDC3 UClk, 2448 * EDC4 UClk, EDC5 UClk, EDC6 UClk, EDC7 UClk 2449 * 0x7835 EDC0 EClk, EDC1 EClk, EDC2 EClk, EDC3 EClk, 2450 * EDC4 EClk, EDC5 EClk, EDC6 EClk, EDC7 EClk 2451 * 0x7817 M2PCIe 2452 * 0x7814 IRP 2453*/ 2454 2455static const struct pci_device_id knl_uncore_pci_ids[] = { 2456 { /* MC0 UClk */ 2457 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7841), 2458 .driver_data = UNCORE_PCI_DEV_FULL_DATA(10, 0, KNL_PCI_UNCORE_MC_UCLK, 0), 2459 }, 2460 { /* MC1 UClk */ 2461 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7841), 2462 .driver_data = UNCORE_PCI_DEV_FULL_DATA(11, 0, KNL_PCI_UNCORE_MC_UCLK, 1), 2463 }, 2464 { /* MC0 DClk CH 0 */ 2465 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2466 .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 2, KNL_PCI_UNCORE_MC_DCLK, 0), 2467 }, 2468 { /* MC0 DClk CH 1 */ 2469 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2470 .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 3, KNL_PCI_UNCORE_MC_DCLK, 1), 2471 }, 2472 { /* MC0 DClk CH 2 */ 2473 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2474 .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 4, KNL_PCI_UNCORE_MC_DCLK, 2), 2475 }, 2476 { /* MC1 DClk CH 0 */ 2477 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2478 .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 2, KNL_PCI_UNCORE_MC_DCLK, 3), 2479 }, 2480 { /* MC1 DClk CH 1 */ 2481 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2482 .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 3, KNL_PCI_UNCORE_MC_DCLK, 4), 2483 }, 2484 { /* MC1 DClk CH 2 */ 2485 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843), 2486 .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 4, KNL_PCI_UNCORE_MC_DCLK, 5), 2487 }, 2488 { /* EDC0 UClk */ 2489 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2490 .driver_data = UNCORE_PCI_DEV_FULL_DATA(15, 0, KNL_PCI_UNCORE_EDC_UCLK, 0), 2491 }, 2492 { /* EDC1 UClk */ 2493 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2494 .driver_data = UNCORE_PCI_DEV_FULL_DATA(16, 0, KNL_PCI_UNCORE_EDC_UCLK, 1), 2495 }, 2496 { /* EDC2 UClk */ 2497 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2498 .driver_data = UNCORE_PCI_DEV_FULL_DATA(17, 0, KNL_PCI_UNCORE_EDC_UCLK, 2), 2499 }, 2500 { /* EDC3 UClk */ 2501 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2502 .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 0, KNL_PCI_UNCORE_EDC_UCLK, 3), 2503 }, 2504 { /* EDC4 UClk */ 2505 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2506 .driver_data = UNCORE_PCI_DEV_FULL_DATA(19, 0, KNL_PCI_UNCORE_EDC_UCLK, 4), 2507 }, 2508 { /* EDC5 UClk */ 2509 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2510 .driver_data = UNCORE_PCI_DEV_FULL_DATA(20, 0, KNL_PCI_UNCORE_EDC_UCLK, 5), 2511 }, 2512 { /* EDC6 UClk */ 2513 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2514 .driver_data = UNCORE_PCI_DEV_FULL_DATA(21, 0, KNL_PCI_UNCORE_EDC_UCLK, 6), 2515 }, 2516 { /* EDC7 UClk */ 2517 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833), 2518 .driver_data = UNCORE_PCI_DEV_FULL_DATA(22, 0, KNL_PCI_UNCORE_EDC_UCLK, 7), 2519 }, 2520 { /* EDC0 EClk */ 2521 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2522 .driver_data = UNCORE_PCI_DEV_FULL_DATA(24, 2, KNL_PCI_UNCORE_EDC_ECLK, 0), 2523 }, 2524 { /* EDC1 EClk */ 2525 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2526 .driver_data = UNCORE_PCI_DEV_FULL_DATA(25, 2, KNL_PCI_UNCORE_EDC_ECLK, 1), 2527 }, 2528 { /* EDC2 EClk */ 2529 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2530 .driver_data = UNCORE_PCI_DEV_FULL_DATA(26, 2, KNL_PCI_UNCORE_EDC_ECLK, 2), 2531 }, 2532 { /* EDC3 EClk */ 2533 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2534 .driver_data = UNCORE_PCI_DEV_FULL_DATA(27, 2, KNL_PCI_UNCORE_EDC_ECLK, 3), 2535 }, 2536 { /* EDC4 EClk */ 2537 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2538 .driver_data = UNCORE_PCI_DEV_FULL_DATA(28, 2, KNL_PCI_UNCORE_EDC_ECLK, 4), 2539 }, 2540 { /* EDC5 EClk */ 2541 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2542 .driver_data = UNCORE_PCI_DEV_FULL_DATA(29, 2, KNL_PCI_UNCORE_EDC_ECLK, 5), 2543 }, 2544 { /* EDC6 EClk */ 2545 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2546 .driver_data = UNCORE_PCI_DEV_FULL_DATA(30, 2, KNL_PCI_UNCORE_EDC_ECLK, 6), 2547 }, 2548 { /* EDC7 EClk */ 2549 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835), 2550 .driver_data = UNCORE_PCI_DEV_FULL_DATA(31, 2, KNL_PCI_UNCORE_EDC_ECLK, 7), 2551 }, 2552 { /* M2PCIe */ 2553 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7817), 2554 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_M2PCIE, 0), 2555 }, 2556 { /* IRP */ 2557 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7814), 2558 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_IRP, 0), 2559 }, 2560 { /* end: all zeroes */ } 2561}; 2562 2563static struct pci_driver knl_uncore_pci_driver = { 2564 .name = "knl_uncore", 2565 .id_table = knl_uncore_pci_ids, 2566}; 2567 2568int knl_uncore_pci_init(void) 2569{ 2570 int ret; 2571 2572 /* All KNL PCI based PMON units are on the same PCI bus except IRP */ 2573 ret = snb_pci2phy_map_init(0x7814); /* IRP */ 2574 if (ret) 2575 return ret; 2576 ret = snb_pci2phy_map_init(0x7817); /* M2PCIe */ 2577 if (ret) 2578 return ret; 2579 uncore_pci_uncores = knl_pci_uncores; 2580 uncore_pci_driver = &knl_uncore_pci_driver; 2581 return 0; 2582} 2583 2584/* end of KNL uncore support */ 2585 2586/* Haswell-EP uncore support */ 2587static struct attribute *hswep_uncore_ubox_formats_attr[] = { 2588 &format_attr_event.attr, 2589 &format_attr_umask.attr, 2590 &format_attr_edge.attr, 2591 &format_attr_inv.attr, 2592 &format_attr_thresh5.attr, 2593 &format_attr_filter_tid2.attr, 2594 &format_attr_filter_cid.attr, 2595 NULL, 2596}; 2597 2598static const struct attribute_group hswep_uncore_ubox_format_group = { 2599 .name = "format", 2600 .attrs = hswep_uncore_ubox_formats_attr, 2601}; 2602 2603static int hswep_ubox_hw_config(struct intel_uncore_box *box, struct perf_event *event) 2604{ 2605 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 2606 reg1->reg = HSWEP_U_MSR_PMON_FILTER; 2607 reg1->config = event->attr.config1 & HSWEP_U_MSR_PMON_BOX_FILTER_MASK; 2608 reg1->idx = 0; 2609 return 0; 2610} 2611 2612static struct intel_uncore_ops hswep_uncore_ubox_ops = { 2613 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 2614 .hw_config = hswep_ubox_hw_config, 2615 .get_constraint = uncore_get_constraint, 2616 .put_constraint = uncore_put_constraint, 2617}; 2618 2619static struct intel_uncore_type hswep_uncore_ubox = { 2620 .name = "ubox", 2621 .num_counters = 2, 2622 .num_boxes = 1, 2623 .perf_ctr_bits = 44, 2624 .fixed_ctr_bits = 48, 2625 .perf_ctr = HSWEP_U_MSR_PMON_CTR0, 2626 .event_ctl = HSWEP_U_MSR_PMON_CTL0, 2627 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK, 2628 .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR, 2629 .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL, 2630 .num_shared_regs = 1, 2631 .ops = &hswep_uncore_ubox_ops, 2632 .format_group = &hswep_uncore_ubox_format_group, 2633}; 2634 2635static struct attribute *hswep_uncore_cbox_formats_attr[] = { 2636 &format_attr_event.attr, 2637 &format_attr_umask.attr, 2638 &format_attr_edge.attr, 2639 &format_attr_tid_en.attr, 2640 &format_attr_thresh8.attr, 2641 &format_attr_filter_tid3.attr, 2642 &format_attr_filter_link2.attr, 2643 &format_attr_filter_state3.attr, 2644 &format_attr_filter_nid2.attr, 2645 &format_attr_filter_opc2.attr, 2646 &format_attr_filter_nc.attr, 2647 &format_attr_filter_c6.attr, 2648 &format_attr_filter_isoc.attr, 2649 NULL, 2650}; 2651 2652static const struct attribute_group hswep_uncore_cbox_format_group = { 2653 .name = "format", 2654 .attrs = hswep_uncore_cbox_formats_attr, 2655}; 2656 2657static struct event_constraint hswep_uncore_cbox_constraints[] = { 2658 UNCORE_EVENT_CONSTRAINT(0x01, 0x1), 2659 UNCORE_EVENT_CONSTRAINT(0x09, 0x1), 2660 UNCORE_EVENT_CONSTRAINT(0x11, 0x1), 2661 UNCORE_EVENT_CONSTRAINT(0x36, 0x1), 2662 UNCORE_EVENT_CONSTRAINT(0x38, 0x3), 2663 UNCORE_EVENT_CONSTRAINT(0x3b, 0x1), 2664 UNCORE_EVENT_CONSTRAINT(0x3e, 0x1), 2665 EVENT_CONSTRAINT_END 2666}; 2667 2668static struct extra_reg hswep_uncore_cbox_extra_regs[] = { 2669 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN, 2670 SNBEP_CBO_PMON_CTL_TID_EN, 0x1), 2671 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4), 2672 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4), 2673 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4), 2674 SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4), 2675 SNBEP_CBO_EVENT_EXTRA_REG(0x2134, 0xffff, 0x4), 2676 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x4), 2677 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8), 2678 SNBEP_CBO_EVENT_EXTRA_REG(0x4028, 0x40ff, 0x8), 2679 SNBEP_CBO_EVENT_EXTRA_REG(0x4032, 0x40ff, 0x8), 2680 SNBEP_CBO_EVENT_EXTRA_REG(0x4029, 0x40ff, 0x8), 2681 SNBEP_CBO_EVENT_EXTRA_REG(0x4033, 0x40ff, 0x8), 2682 SNBEP_CBO_EVENT_EXTRA_REG(0x402A, 0x40ff, 0x8), 2683 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x12), 2684 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10), 2685 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18), 2686 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8), 2687 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8), 2688 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8), 2689 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18), 2690 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8), 2691 SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10), 2692 SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10), 2693 SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10), 2694 SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10), 2695 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10), 2696 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10), 2697 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18), 2698 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8), 2699 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8), 2700 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18), 2701 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8), 2702 SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10), 2703 SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10), 2704 SNBEP_CBO_EVENT_EXTRA_REG(0x2136, 0xffff, 0x10), 2705 SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10), 2706 SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8), 2707 EVENT_EXTRA_END 2708}; 2709 2710static u64 hswep_cbox_filter_mask(int fields) 2711{ 2712 u64 mask = 0; 2713 if (fields & 0x1) 2714 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_TID; 2715 if (fields & 0x2) 2716 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_LINK; 2717 if (fields & 0x4) 2718 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_STATE; 2719 if (fields & 0x8) 2720 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_NID; 2721 if (fields & 0x10) { 2722 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_OPC; 2723 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_NC; 2724 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_C6; 2725 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_ISOC; 2726 } 2727 return mask; 2728} 2729 2730static struct event_constraint * 2731hswep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 2732{ 2733 return __snbep_cbox_get_constraint(box, event, hswep_cbox_filter_mask); 2734} 2735 2736static int hswep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event) 2737{ 2738 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 2739 struct extra_reg *er; 2740 int idx = 0; 2741 2742 for (er = hswep_uncore_cbox_extra_regs; er->msr; er++) { 2743 if (er->event != (event->hw.config & er->config_mask)) 2744 continue; 2745 idx |= er->idx; 2746 } 2747 2748 if (idx) { 2749 reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 + 2750 HSWEP_CBO_MSR_OFFSET * box->pmu->pmu_idx; 2751 reg1->config = event->attr.config1 & hswep_cbox_filter_mask(idx); 2752 reg1->idx = idx; 2753 } 2754 return 0; 2755} 2756 2757static void hswep_cbox_enable_event(struct intel_uncore_box *box, 2758 struct perf_event *event) 2759{ 2760 struct hw_perf_event *hwc = &event->hw; 2761 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 2762 2763 if (reg1->idx != EXTRA_REG_NONE) { 2764 u64 filter = uncore_shared_reg_config(box, 0); 2765 wrmsrq(reg1->reg, filter & 0xffffffff); 2766 wrmsrq(reg1->reg + 1, filter >> 32); 2767 } 2768 2769 wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 2770} 2771 2772static struct intel_uncore_ops hswep_uncore_cbox_ops = { 2773 .init_box = snbep_uncore_msr_init_box, 2774 .disable_box = snbep_uncore_msr_disable_box, 2775 .enable_box = snbep_uncore_msr_enable_box, 2776 .disable_event = snbep_uncore_msr_disable_event, 2777 .enable_event = hswep_cbox_enable_event, 2778 .read_counter = uncore_msr_read_counter, 2779 .hw_config = hswep_cbox_hw_config, 2780 .get_constraint = hswep_cbox_get_constraint, 2781 .put_constraint = snbep_cbox_put_constraint, 2782}; 2783 2784static struct intel_uncore_type hswep_uncore_cbox = { 2785 .name = "cbox", 2786 .num_counters = 4, 2787 .num_boxes = 18, 2788 .perf_ctr_bits = 48, 2789 .event_ctl = HSWEP_C0_MSR_PMON_CTL0, 2790 .perf_ctr = HSWEP_C0_MSR_PMON_CTR0, 2791 .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK, 2792 .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL, 2793 .msr_offset = HSWEP_CBO_MSR_OFFSET, 2794 .num_shared_regs = 1, 2795 .constraints = hswep_uncore_cbox_constraints, 2796 .ops = &hswep_uncore_cbox_ops, 2797 .format_group = &hswep_uncore_cbox_format_group, 2798}; 2799 2800/* 2801 * Write SBOX Initialization register bit by bit to avoid spurious #GPs 2802 */ 2803static void hswep_uncore_sbox_msr_init_box(struct intel_uncore_box *box) 2804{ 2805 unsigned msr = uncore_msr_box_ctl(box); 2806 2807 if (msr) { 2808 u64 init = SNBEP_PMON_BOX_CTL_INT; 2809 u64 flags = 0; 2810 int i; 2811 2812 for_each_set_bit(i, (unsigned long *)&init, 64) { 2813 flags |= (1ULL << i); 2814 wrmsrq(msr, flags); 2815 } 2816 } 2817} 2818 2819static struct intel_uncore_ops hswep_uncore_sbox_msr_ops = { 2820 __SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 2821 .init_box = hswep_uncore_sbox_msr_init_box 2822}; 2823 2824static struct attribute *hswep_uncore_sbox_formats_attr[] = { 2825 &format_attr_event.attr, 2826 &format_attr_umask.attr, 2827 &format_attr_edge.attr, 2828 &format_attr_tid_en.attr, 2829 &format_attr_inv.attr, 2830 &format_attr_thresh8.attr, 2831 NULL, 2832}; 2833 2834static const struct attribute_group hswep_uncore_sbox_format_group = { 2835 .name = "format", 2836 .attrs = hswep_uncore_sbox_formats_attr, 2837}; 2838 2839static struct intel_uncore_type hswep_uncore_sbox = { 2840 .name = "sbox", 2841 .num_counters = 4, 2842 .num_boxes = 4, 2843 .perf_ctr_bits = 44, 2844 .event_ctl = HSWEP_S0_MSR_PMON_CTL0, 2845 .perf_ctr = HSWEP_S0_MSR_PMON_CTR0, 2846 .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK, 2847 .box_ctl = HSWEP_S0_MSR_PMON_BOX_CTL, 2848 .msr_offset = HSWEP_SBOX_MSR_OFFSET, 2849 .ops = &hswep_uncore_sbox_msr_ops, 2850 .format_group = &hswep_uncore_sbox_format_group, 2851}; 2852 2853static int hswep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event) 2854{ 2855 struct hw_perf_event *hwc = &event->hw; 2856 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 2857 int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK; 2858 2859 if (ev_sel >= 0xb && ev_sel <= 0xe) { 2860 reg1->reg = HSWEP_PCU_MSR_PMON_BOX_FILTER; 2861 reg1->idx = ev_sel - 0xb; 2862 reg1->config = event->attr.config1 & (0xff << reg1->idx); 2863 } 2864 return 0; 2865} 2866 2867static struct intel_uncore_ops hswep_uncore_pcu_ops = { 2868 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(), 2869 .hw_config = hswep_pcu_hw_config, 2870 .get_constraint = snbep_pcu_get_constraint, 2871 .put_constraint = snbep_pcu_put_constraint, 2872}; 2873 2874static struct intel_uncore_type hswep_uncore_pcu = { 2875 .name = "pcu", 2876 .num_counters = 4, 2877 .num_boxes = 1, 2878 .perf_ctr_bits = 48, 2879 .perf_ctr = HSWEP_PCU_MSR_PMON_CTR0, 2880 .event_ctl = HSWEP_PCU_MSR_PMON_CTL0, 2881 .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK, 2882 .box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL, 2883 .num_shared_regs = 1, 2884 .ops = &hswep_uncore_pcu_ops, 2885 .format_group = &snbep_uncore_pcu_format_group, 2886}; 2887 2888static struct intel_uncore_type *hswep_msr_uncores[] = { 2889 &hswep_uncore_ubox, 2890 &hswep_uncore_cbox, 2891 &hswep_uncore_sbox, 2892 &hswep_uncore_pcu, 2893 NULL, 2894}; 2895 2896#define HSWEP_PCU_DID 0x2fc0 2897#define HSWEP_PCU_CAPID4_OFFET 0x94 2898#define hswep_get_chop(_cap) (((_cap) >> 6) & 0x3) 2899 2900static bool hswep_has_limit_sbox(unsigned int device) 2901{ 2902 struct pci_dev *dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 2903 u32 capid4; 2904 2905 if (!dev) 2906 return false; 2907 2908 pci_read_config_dword(dev, HSWEP_PCU_CAPID4_OFFET, &capid4); 2909 pci_dev_put(dev); 2910 if (!hswep_get_chop(capid4)) 2911 return true; 2912 2913 return false; 2914} 2915 2916void hswep_uncore_cpu_init(void) 2917{ 2918 if (hswep_uncore_cbox.num_boxes > topology_num_cores_per_package()) 2919 hswep_uncore_cbox.num_boxes = topology_num_cores_per_package(); 2920 2921 /* Detect 6-8 core systems with only two SBOXes */ 2922 if (hswep_has_limit_sbox(HSWEP_PCU_DID)) 2923 hswep_uncore_sbox.num_boxes = 2; 2924 2925 uncore_msr_uncores = hswep_msr_uncores; 2926} 2927 2928static struct intel_uncore_type hswep_uncore_ha = { 2929 .name = "ha", 2930 .num_counters = 4, 2931 .num_boxes = 2, 2932 .perf_ctr_bits = 48, 2933 SNBEP_UNCORE_PCI_COMMON_INIT(), 2934}; 2935 2936static struct uncore_event_desc hswep_uncore_imc_events[] = { 2937 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x00,umask=0x00"), 2938 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"), 2939 INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"), 2940 INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"), 2941 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"), 2942 INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"), 2943 INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"), 2944 { /* end: all zeroes */ }, 2945}; 2946 2947static struct intel_uncore_type hswep_uncore_imc = { 2948 .name = "imc", 2949 .num_counters = 4, 2950 .num_boxes = 8, 2951 .perf_ctr_bits = 48, 2952 .fixed_ctr_bits = 48, 2953 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR, 2954 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL, 2955 .event_descs = hswep_uncore_imc_events, 2956 SNBEP_UNCORE_PCI_COMMON_INIT(), 2957}; 2958 2959static unsigned hswep_uncore_irp_ctrs[] = {0xa0, 0xa8, 0xb0, 0xb8}; 2960 2961static u64 hswep_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event) 2962{ 2963 struct pci_dev *pdev = box->pci_dev; 2964 struct hw_perf_event *hwc = &event->hw; 2965 u64 count = 0; 2966 2967 pci_read_config_dword(pdev, hswep_uncore_irp_ctrs[hwc->idx], (u32 *)&count); 2968 pci_read_config_dword(pdev, hswep_uncore_irp_ctrs[hwc->idx] + 4, (u32 *)&count + 1); 2969 2970 return count; 2971} 2972 2973static struct intel_uncore_ops hswep_uncore_irp_ops = { 2974 .init_box = snbep_uncore_pci_init_box, 2975 .disable_box = snbep_uncore_pci_disable_box, 2976 .enable_box = snbep_uncore_pci_enable_box, 2977 .disable_event = ivbep_uncore_irp_disable_event, 2978 .enable_event = ivbep_uncore_irp_enable_event, 2979 .read_counter = hswep_uncore_irp_read_counter, 2980}; 2981 2982static struct intel_uncore_type hswep_uncore_irp = { 2983 .name = "irp", 2984 .num_counters = 4, 2985 .num_boxes = 1, 2986 .perf_ctr_bits = 48, 2987 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 2988 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 2989 .ops = &hswep_uncore_irp_ops, 2990 .format_group = &snbep_uncore_format_group, 2991}; 2992 2993static struct intel_uncore_type hswep_uncore_qpi = { 2994 .name = "qpi", 2995 .num_counters = 4, 2996 .num_boxes = 3, 2997 .perf_ctr_bits = 48, 2998 .perf_ctr = SNBEP_PCI_PMON_CTR0, 2999 .event_ctl = SNBEP_PCI_PMON_CTL0, 3000 .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK, 3001 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 3002 .num_shared_regs = 1, 3003 .ops = &snbep_uncore_qpi_ops, 3004 .format_group = &snbep_uncore_qpi_format_group, 3005}; 3006 3007static struct event_constraint hswep_uncore_r2pcie_constraints[] = { 3008 UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 3009 UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 3010 UNCORE_EVENT_CONSTRAINT(0x13, 0x1), 3011 UNCORE_EVENT_CONSTRAINT(0x23, 0x1), 3012 UNCORE_EVENT_CONSTRAINT(0x24, 0x1), 3013 UNCORE_EVENT_CONSTRAINT(0x25, 0x1), 3014 UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 3015 UNCORE_EVENT_CONSTRAINT(0x27, 0x1), 3016 UNCORE_EVENT_CONSTRAINT(0x28, 0x3), 3017 UNCORE_EVENT_CONSTRAINT(0x29, 0x3), 3018 UNCORE_EVENT_CONSTRAINT(0x2a, 0x1), 3019 UNCORE_EVENT_CONSTRAINT(0x2b, 0x3), 3020 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), 3021 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 3022 UNCORE_EVENT_CONSTRAINT(0x32, 0x3), 3023 UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 3024 UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 3025 UNCORE_EVENT_CONSTRAINT(0x35, 0x3), 3026 EVENT_CONSTRAINT_END 3027}; 3028 3029static struct intel_uncore_type hswep_uncore_r2pcie = { 3030 .name = "r2pcie", 3031 .num_counters = 4, 3032 .num_boxes = 1, 3033 .perf_ctr_bits = 48, 3034 .constraints = hswep_uncore_r2pcie_constraints, 3035 SNBEP_UNCORE_PCI_COMMON_INIT(), 3036}; 3037 3038static struct event_constraint hswep_uncore_r3qpi_constraints[] = { 3039 UNCORE_EVENT_CONSTRAINT(0x01, 0x3), 3040 UNCORE_EVENT_CONSTRAINT(0x07, 0x7), 3041 UNCORE_EVENT_CONSTRAINT(0x08, 0x7), 3042 UNCORE_EVENT_CONSTRAINT(0x09, 0x7), 3043 UNCORE_EVENT_CONSTRAINT(0x0a, 0x7), 3044 UNCORE_EVENT_CONSTRAINT(0x0e, 0x7), 3045 UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 3046 UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 3047 UNCORE_EVENT_CONSTRAINT(0x12, 0x3), 3048 UNCORE_EVENT_CONSTRAINT(0x13, 0x1), 3049 UNCORE_EVENT_CONSTRAINT(0x14, 0x3), 3050 UNCORE_EVENT_CONSTRAINT(0x15, 0x3), 3051 UNCORE_EVENT_CONSTRAINT(0x1f, 0x3), 3052 UNCORE_EVENT_CONSTRAINT(0x20, 0x3), 3053 UNCORE_EVENT_CONSTRAINT(0x21, 0x3), 3054 UNCORE_EVENT_CONSTRAINT(0x22, 0x3), 3055 UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 3056 UNCORE_EVENT_CONSTRAINT(0x25, 0x3), 3057 UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 3058 UNCORE_EVENT_CONSTRAINT(0x28, 0x3), 3059 UNCORE_EVENT_CONSTRAINT(0x29, 0x3), 3060 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), 3061 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 3062 UNCORE_EVENT_CONSTRAINT(0x2e, 0x3), 3063 UNCORE_EVENT_CONSTRAINT(0x2f, 0x3), 3064 UNCORE_EVENT_CONSTRAINT(0x31, 0x3), 3065 UNCORE_EVENT_CONSTRAINT(0x32, 0x3), 3066 UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 3067 UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 3068 UNCORE_EVENT_CONSTRAINT(0x36, 0x3), 3069 UNCORE_EVENT_CONSTRAINT(0x37, 0x3), 3070 UNCORE_EVENT_CONSTRAINT(0x38, 0x3), 3071 UNCORE_EVENT_CONSTRAINT(0x39, 0x3), 3072 EVENT_CONSTRAINT_END 3073}; 3074 3075static struct intel_uncore_type hswep_uncore_r3qpi = { 3076 .name = "r3qpi", 3077 .num_counters = 3, 3078 .num_boxes = 3, 3079 .perf_ctr_bits = 44, 3080 .constraints = hswep_uncore_r3qpi_constraints, 3081 SNBEP_UNCORE_PCI_COMMON_INIT(), 3082}; 3083 3084enum { 3085 HSWEP_PCI_UNCORE_HA, 3086 HSWEP_PCI_UNCORE_IMC, 3087 HSWEP_PCI_UNCORE_IRP, 3088 HSWEP_PCI_UNCORE_QPI, 3089 HSWEP_PCI_UNCORE_R2PCIE, 3090 HSWEP_PCI_UNCORE_R3QPI, 3091}; 3092 3093static struct intel_uncore_type *hswep_pci_uncores[] = { 3094 [HSWEP_PCI_UNCORE_HA] = &hswep_uncore_ha, 3095 [HSWEP_PCI_UNCORE_IMC] = &hswep_uncore_imc, 3096 [HSWEP_PCI_UNCORE_IRP] = &hswep_uncore_irp, 3097 [HSWEP_PCI_UNCORE_QPI] = &hswep_uncore_qpi, 3098 [HSWEP_PCI_UNCORE_R2PCIE] = &hswep_uncore_r2pcie, 3099 [HSWEP_PCI_UNCORE_R3QPI] = &hswep_uncore_r3qpi, 3100 NULL, 3101}; 3102 3103static const struct pci_device_id hswep_uncore_pci_ids[] = { 3104 { /* Home Agent 0 */ 3105 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f30), 3106 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_HA, 0), 3107 }, 3108 { /* Home Agent 1 */ 3109 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f38), 3110 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_HA, 1), 3111 }, 3112 { /* MC0 Channel 0 */ 3113 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb0), 3114 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 0), 3115 }, 3116 { /* MC0 Channel 1 */ 3117 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb1), 3118 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 1), 3119 }, 3120 { /* MC0 Channel 2 */ 3121 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb4), 3122 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 2), 3123 }, 3124 { /* MC0 Channel 3 */ 3125 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb5), 3126 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 3), 3127 }, 3128 { /* MC1 Channel 0 */ 3129 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd0), 3130 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 4), 3131 }, 3132 { /* MC1 Channel 1 */ 3133 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd1), 3134 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 5), 3135 }, 3136 { /* MC1 Channel 2 */ 3137 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd4), 3138 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 6), 3139 }, 3140 { /* MC1 Channel 3 */ 3141 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd5), 3142 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 7), 3143 }, 3144 { /* IRP */ 3145 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f39), 3146 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IRP, 0), 3147 }, 3148 { /* QPI0 Port 0 */ 3149 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f32), 3150 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 0), 3151 }, 3152 { /* QPI0 Port 1 */ 3153 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f33), 3154 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 1), 3155 }, 3156 { /* QPI1 Port 2 */ 3157 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f3a), 3158 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 2), 3159 }, 3160 { /* R2PCIe */ 3161 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f34), 3162 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R2PCIE, 0), 3163 }, 3164 { /* R3QPI0 Link 0 */ 3165 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f36), 3166 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 0), 3167 }, 3168 { /* R3QPI0 Link 1 */ 3169 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f37), 3170 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 1), 3171 }, 3172 { /* R3QPI1 Link 2 */ 3173 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f3e), 3174 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 2), 3175 }, 3176 { /* QPI Port 0 filter */ 3177 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f86), 3178 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 3179 SNBEP_PCI_QPI_PORT0_FILTER), 3180 }, 3181 { /* QPI Port 1 filter */ 3182 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f96), 3183 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 3184 SNBEP_PCI_QPI_PORT1_FILTER), 3185 }, 3186 { /* end: all zeroes */ } 3187}; 3188 3189static struct pci_driver hswep_uncore_pci_driver = { 3190 .name = "hswep_uncore", 3191 .id_table = hswep_uncore_pci_ids, 3192}; 3193 3194int hswep_uncore_pci_init(void) 3195{ 3196 int ret = snbep_pci2phy_map_init(0x2f1e, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true); 3197 if (ret) 3198 return ret; 3199 uncore_pci_uncores = hswep_pci_uncores; 3200 uncore_pci_driver = &hswep_uncore_pci_driver; 3201 return 0; 3202} 3203/* end of Haswell-EP uncore support */ 3204 3205/* BDX uncore support */ 3206 3207static struct intel_uncore_type bdx_uncore_ubox = { 3208 .name = "ubox", 3209 .num_counters = 2, 3210 .num_boxes = 1, 3211 .perf_ctr_bits = 48, 3212 .fixed_ctr_bits = 48, 3213 .perf_ctr = HSWEP_U_MSR_PMON_CTR0, 3214 .event_ctl = HSWEP_U_MSR_PMON_CTL0, 3215 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK, 3216 .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR, 3217 .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL, 3218 .num_shared_regs = 1, 3219 .ops = &ivbep_uncore_msr_ops, 3220 .format_group = &ivbep_uncore_ubox_format_group, 3221}; 3222 3223static struct event_constraint bdx_uncore_cbox_constraints[] = { 3224 UNCORE_EVENT_CONSTRAINT(0x09, 0x3), 3225 UNCORE_EVENT_CONSTRAINT(0x11, 0x1), 3226 UNCORE_EVENT_CONSTRAINT(0x36, 0x1), 3227 UNCORE_EVENT_CONSTRAINT(0x3e, 0x1), 3228 EVENT_CONSTRAINT_END 3229}; 3230 3231static struct intel_uncore_type bdx_uncore_cbox = { 3232 .name = "cbox", 3233 .num_counters = 4, 3234 .num_boxes = 24, 3235 .perf_ctr_bits = 48, 3236 .event_ctl = HSWEP_C0_MSR_PMON_CTL0, 3237 .perf_ctr = HSWEP_C0_MSR_PMON_CTR0, 3238 .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK, 3239 .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL, 3240 .msr_offset = HSWEP_CBO_MSR_OFFSET, 3241 .num_shared_regs = 1, 3242 .constraints = bdx_uncore_cbox_constraints, 3243 .ops = &hswep_uncore_cbox_ops, 3244 .format_group = &hswep_uncore_cbox_format_group, 3245}; 3246 3247static struct intel_uncore_type bdx_uncore_sbox = { 3248 .name = "sbox", 3249 .num_counters = 4, 3250 .num_boxes = 4, 3251 .perf_ctr_bits = 48, 3252 .event_ctl = HSWEP_S0_MSR_PMON_CTL0, 3253 .perf_ctr = HSWEP_S0_MSR_PMON_CTR0, 3254 .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK, 3255 .box_ctl = HSWEP_S0_MSR_PMON_BOX_CTL, 3256 .msr_offset = HSWEP_SBOX_MSR_OFFSET, 3257 .ops = &hswep_uncore_sbox_msr_ops, 3258 .format_group = &hswep_uncore_sbox_format_group, 3259}; 3260 3261#define BDX_MSR_UNCORE_SBOX 3 3262 3263static struct intel_uncore_type *bdx_msr_uncores[] = { 3264 &bdx_uncore_ubox, 3265 &bdx_uncore_cbox, 3266 &hswep_uncore_pcu, 3267 &bdx_uncore_sbox, 3268 NULL, 3269}; 3270 3271/* Bit 7 'Use Occupancy' is not available for counter 0 on BDX */ 3272static struct event_constraint bdx_uncore_pcu_constraints[] = { 3273 EVENT_CONSTRAINT(0x80, 0xe, 0x80), 3274 EVENT_CONSTRAINT_END 3275}; 3276 3277#define BDX_PCU_DID 0x6fc0 3278 3279void bdx_uncore_cpu_init(void) 3280{ 3281 if (bdx_uncore_cbox.num_boxes > topology_num_cores_per_package()) 3282 bdx_uncore_cbox.num_boxes = topology_num_cores_per_package(); 3283 uncore_msr_uncores = bdx_msr_uncores; 3284 3285 /* Detect systems with no SBOXes */ 3286 if (boot_cpu_data.x86_vfm == INTEL_BROADWELL_D || hswep_has_limit_sbox(BDX_PCU_DID)) 3287 uncore_msr_uncores[BDX_MSR_UNCORE_SBOX] = NULL; 3288 3289 hswep_uncore_pcu.constraints = bdx_uncore_pcu_constraints; 3290} 3291 3292static struct intel_uncore_type bdx_uncore_ha = { 3293 .name = "ha", 3294 .num_counters = 4, 3295 .num_boxes = 2, 3296 .perf_ctr_bits = 48, 3297 SNBEP_UNCORE_PCI_COMMON_INIT(), 3298}; 3299 3300static struct intel_uncore_type bdx_uncore_imc = { 3301 .name = "imc", 3302 .num_counters = 4, 3303 .num_boxes = 8, 3304 .perf_ctr_bits = 48, 3305 .fixed_ctr_bits = 48, 3306 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR, 3307 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL, 3308 .event_descs = hswep_uncore_imc_events, 3309 SNBEP_UNCORE_PCI_COMMON_INIT(), 3310}; 3311 3312static struct intel_uncore_type bdx_uncore_irp = { 3313 .name = "irp", 3314 .num_counters = 4, 3315 .num_boxes = 1, 3316 .perf_ctr_bits = 48, 3317 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 3318 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 3319 .ops = &hswep_uncore_irp_ops, 3320 .format_group = &snbep_uncore_format_group, 3321}; 3322 3323static struct intel_uncore_type bdx_uncore_qpi = { 3324 .name = "qpi", 3325 .num_counters = 4, 3326 .num_boxes = 3, 3327 .perf_ctr_bits = 48, 3328 .perf_ctr = SNBEP_PCI_PMON_CTR0, 3329 .event_ctl = SNBEP_PCI_PMON_CTL0, 3330 .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK, 3331 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 3332 .num_shared_regs = 1, 3333 .ops = &snbep_uncore_qpi_ops, 3334 .format_group = &snbep_uncore_qpi_format_group, 3335}; 3336 3337static struct event_constraint bdx_uncore_r2pcie_constraints[] = { 3338 UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 3339 UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 3340 UNCORE_EVENT_CONSTRAINT(0x13, 0x1), 3341 UNCORE_EVENT_CONSTRAINT(0x23, 0x1), 3342 UNCORE_EVENT_CONSTRAINT(0x25, 0x1), 3343 UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 3344 UNCORE_EVENT_CONSTRAINT(0x28, 0x3), 3345 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), 3346 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 3347 EVENT_CONSTRAINT_END 3348}; 3349 3350static struct intel_uncore_type bdx_uncore_r2pcie = { 3351 .name = "r2pcie", 3352 .num_counters = 4, 3353 .num_boxes = 1, 3354 .perf_ctr_bits = 48, 3355 .constraints = bdx_uncore_r2pcie_constraints, 3356 SNBEP_UNCORE_PCI_COMMON_INIT(), 3357}; 3358 3359static struct event_constraint bdx_uncore_r3qpi_constraints[] = { 3360 UNCORE_EVENT_CONSTRAINT(0x01, 0x7), 3361 UNCORE_EVENT_CONSTRAINT(0x07, 0x7), 3362 UNCORE_EVENT_CONSTRAINT(0x08, 0x7), 3363 UNCORE_EVENT_CONSTRAINT(0x09, 0x7), 3364 UNCORE_EVENT_CONSTRAINT(0x0a, 0x7), 3365 UNCORE_EVENT_CONSTRAINT(0x0e, 0x7), 3366 UNCORE_EVENT_CONSTRAINT(0x10, 0x3), 3367 UNCORE_EVENT_CONSTRAINT(0x11, 0x3), 3368 UNCORE_EVENT_CONSTRAINT(0x13, 0x1), 3369 UNCORE_EVENT_CONSTRAINT(0x14, 0x3), 3370 UNCORE_EVENT_CONSTRAINT(0x15, 0x3), 3371 UNCORE_EVENT_CONSTRAINT(0x1f, 0x3), 3372 UNCORE_EVENT_CONSTRAINT(0x20, 0x3), 3373 UNCORE_EVENT_CONSTRAINT(0x21, 0x3), 3374 UNCORE_EVENT_CONSTRAINT(0x22, 0x3), 3375 UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 3376 UNCORE_EVENT_CONSTRAINT(0x25, 0x3), 3377 UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 3378 UNCORE_EVENT_CONSTRAINT(0x28, 0x3), 3379 UNCORE_EVENT_CONSTRAINT(0x29, 0x3), 3380 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), 3381 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 3382 UNCORE_EVENT_CONSTRAINT(0x2e, 0x3), 3383 UNCORE_EVENT_CONSTRAINT(0x2f, 0x3), 3384 UNCORE_EVENT_CONSTRAINT(0x33, 0x3), 3385 UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 3386 UNCORE_EVENT_CONSTRAINT(0x36, 0x3), 3387 UNCORE_EVENT_CONSTRAINT(0x37, 0x3), 3388 UNCORE_EVENT_CONSTRAINT(0x38, 0x3), 3389 UNCORE_EVENT_CONSTRAINT(0x39, 0x3), 3390 EVENT_CONSTRAINT_END 3391}; 3392 3393static struct intel_uncore_type bdx_uncore_r3qpi = { 3394 .name = "r3qpi", 3395 .num_counters = 3, 3396 .num_boxes = 3, 3397 .perf_ctr_bits = 48, 3398 .constraints = bdx_uncore_r3qpi_constraints, 3399 SNBEP_UNCORE_PCI_COMMON_INIT(), 3400}; 3401 3402enum { 3403 BDX_PCI_UNCORE_HA, 3404 BDX_PCI_UNCORE_IMC, 3405 BDX_PCI_UNCORE_IRP, 3406 BDX_PCI_UNCORE_QPI, 3407 BDX_PCI_UNCORE_R2PCIE, 3408 BDX_PCI_UNCORE_R3QPI, 3409}; 3410 3411static struct intel_uncore_type *bdx_pci_uncores[] = { 3412 [BDX_PCI_UNCORE_HA] = &bdx_uncore_ha, 3413 [BDX_PCI_UNCORE_IMC] = &bdx_uncore_imc, 3414 [BDX_PCI_UNCORE_IRP] = &bdx_uncore_irp, 3415 [BDX_PCI_UNCORE_QPI] = &bdx_uncore_qpi, 3416 [BDX_PCI_UNCORE_R2PCIE] = &bdx_uncore_r2pcie, 3417 [BDX_PCI_UNCORE_R3QPI] = &bdx_uncore_r3qpi, 3418 NULL, 3419}; 3420 3421static const struct pci_device_id bdx_uncore_pci_ids[] = { 3422 { /* Home Agent 0 */ 3423 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f30), 3424 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 0), 3425 }, 3426 { /* Home Agent 1 */ 3427 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f38), 3428 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 1), 3429 }, 3430 { /* MC0 Channel 0 */ 3431 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb0), 3432 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 0), 3433 }, 3434 { /* MC0 Channel 1 */ 3435 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb1), 3436 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 1), 3437 }, 3438 { /* MC0 Channel 2 */ 3439 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb4), 3440 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 2), 3441 }, 3442 { /* MC0 Channel 3 */ 3443 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb5), 3444 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 3), 3445 }, 3446 { /* MC1 Channel 0 */ 3447 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd0), 3448 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 4), 3449 }, 3450 { /* MC1 Channel 1 */ 3451 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd1), 3452 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 5), 3453 }, 3454 { /* MC1 Channel 2 */ 3455 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd4), 3456 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 6), 3457 }, 3458 { /* MC1 Channel 3 */ 3459 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd5), 3460 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 7), 3461 }, 3462 { /* IRP */ 3463 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f39), 3464 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IRP, 0), 3465 }, 3466 { /* QPI0 Port 0 */ 3467 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f32), 3468 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 0), 3469 }, 3470 { /* QPI0 Port 1 */ 3471 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f33), 3472 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 1), 3473 }, 3474 { /* QPI1 Port 2 */ 3475 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f3a), 3476 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 2), 3477 }, 3478 { /* R2PCIe */ 3479 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f34), 3480 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R2PCIE, 0), 3481 }, 3482 { /* R3QPI0 Link 0 */ 3483 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f36), 3484 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 0), 3485 }, 3486 { /* R3QPI0 Link 1 */ 3487 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f37), 3488 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 1), 3489 }, 3490 { /* R3QPI1 Link 2 */ 3491 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f3e), 3492 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 2), 3493 }, 3494 { /* QPI Port 0 filter */ 3495 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f86), 3496 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 3497 SNBEP_PCI_QPI_PORT0_FILTER), 3498 }, 3499 { /* QPI Port 1 filter */ 3500 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f96), 3501 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 3502 SNBEP_PCI_QPI_PORT1_FILTER), 3503 }, 3504 { /* QPI Port 2 filter */ 3505 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f46), 3506 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 3507 BDX_PCI_QPI_PORT2_FILTER), 3508 }, 3509 { /* end: all zeroes */ } 3510}; 3511 3512static struct pci_driver bdx_uncore_pci_driver = { 3513 .name = "bdx_uncore", 3514 .id_table = bdx_uncore_pci_ids, 3515}; 3516 3517int bdx_uncore_pci_init(void) 3518{ 3519 int ret = snbep_pci2phy_map_init(0x6f1e, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true); 3520 3521 if (ret) 3522 return ret; 3523 uncore_pci_uncores = bdx_pci_uncores; 3524 uncore_pci_driver = &bdx_uncore_pci_driver; 3525 return 0; 3526} 3527 3528/* end of BDX uncore support */ 3529 3530/* SKX uncore support */ 3531 3532static struct intel_uncore_type skx_uncore_ubox = { 3533 .name = "ubox", 3534 .num_counters = 2, 3535 .num_boxes = 1, 3536 .perf_ctr_bits = 48, 3537 .fixed_ctr_bits = 48, 3538 .perf_ctr = HSWEP_U_MSR_PMON_CTR0, 3539 .event_ctl = HSWEP_U_MSR_PMON_CTL0, 3540 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK, 3541 .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR, 3542 .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL, 3543 .ops = &ivbep_uncore_msr_ops, 3544 .format_group = &ivbep_uncore_ubox_format_group, 3545}; 3546 3547static struct attribute *skx_uncore_cha_formats_attr[] = { 3548 &format_attr_event.attr, 3549 &format_attr_umask.attr, 3550 &format_attr_edge.attr, 3551 &format_attr_tid_en.attr, 3552 &format_attr_inv.attr, 3553 &format_attr_thresh8.attr, 3554 &format_attr_filter_tid4.attr, 3555 &format_attr_filter_state5.attr, 3556 &format_attr_filter_rem.attr, 3557 &format_attr_filter_loc.attr, 3558 &format_attr_filter_nm.attr, 3559 &format_attr_filter_all_op.attr, 3560 &format_attr_filter_not_nm.attr, 3561 &format_attr_filter_opc_0.attr, 3562 &format_attr_filter_opc_1.attr, 3563 &format_attr_filter_nc.attr, 3564 &format_attr_filter_isoc.attr, 3565 NULL, 3566}; 3567 3568static const struct attribute_group skx_uncore_chabox_format_group = { 3569 .name = "format", 3570 .attrs = skx_uncore_cha_formats_attr, 3571}; 3572 3573static struct event_constraint skx_uncore_chabox_constraints[] = { 3574 UNCORE_EVENT_CONSTRAINT(0x11, 0x1), 3575 UNCORE_EVENT_CONSTRAINT(0x36, 0x1), 3576 EVENT_CONSTRAINT_END 3577}; 3578 3579static struct extra_reg skx_uncore_cha_extra_regs[] = { 3580 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4), 3581 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4), 3582 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4), 3583 SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4), 3584 SNBEP_CBO_EVENT_EXTRA_REG(0x3134, 0xffff, 0x4), 3585 SNBEP_CBO_EVENT_EXTRA_REG(0x9134, 0xffff, 0x4), 3586 SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x8), 3587 SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x8), 3588 SNBEP_CBO_EVENT_EXTRA_REG(0x38, 0xff, 0x3), 3589 EVENT_EXTRA_END 3590}; 3591 3592static u64 skx_cha_filter_mask(int fields) 3593{ 3594 u64 mask = 0; 3595 3596 if (fields & 0x1) 3597 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_TID; 3598 if (fields & 0x2) 3599 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_LINK; 3600 if (fields & 0x4) 3601 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_STATE; 3602 if (fields & 0x8) { 3603 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_REM; 3604 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_LOC; 3605 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_ALL_OPC; 3606 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NM; 3607 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NOT_NM; 3608 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_OPC0; 3609 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_OPC1; 3610 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NC; 3611 mask |= SKX_CHA_MSR_PMON_BOX_FILTER_ISOC; 3612 } 3613 return mask; 3614} 3615 3616static struct event_constraint * 3617skx_cha_get_constraint(struct intel_uncore_box *box, struct perf_event *event) 3618{ 3619 return __snbep_cbox_get_constraint(box, event, skx_cha_filter_mask); 3620} 3621 3622static int skx_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event) 3623{ 3624 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 3625 struct extra_reg *er; 3626 int idx = 0; 3627 /* Any of the CHA events may be filtered by Thread/Core-ID.*/ 3628 if (event->hw.config & SNBEP_CBO_PMON_CTL_TID_EN) 3629 idx = SKX_CHA_MSR_PMON_BOX_FILTER_TID; 3630 3631 for (er = skx_uncore_cha_extra_regs; er->msr; er++) { 3632 if (er->event != (event->hw.config & er->config_mask)) 3633 continue; 3634 idx |= er->idx; 3635 } 3636 3637 if (idx) { 3638 reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 + 3639 HSWEP_CBO_MSR_OFFSET * box->pmu->pmu_idx; 3640 reg1->config = event->attr.config1 & skx_cha_filter_mask(idx); 3641 reg1->idx = idx; 3642 } 3643 return 0; 3644} 3645 3646static struct intel_uncore_ops skx_uncore_chabox_ops = { 3647 /* There is no frz_en for chabox ctl */ 3648 .init_box = ivbep_uncore_msr_init_box, 3649 .disable_box = snbep_uncore_msr_disable_box, 3650 .enable_box = snbep_uncore_msr_enable_box, 3651 .disable_event = snbep_uncore_msr_disable_event, 3652 .enable_event = hswep_cbox_enable_event, 3653 .read_counter = uncore_msr_read_counter, 3654 .hw_config = skx_cha_hw_config, 3655 .get_constraint = skx_cha_get_constraint, 3656 .put_constraint = snbep_cbox_put_constraint, 3657}; 3658 3659static struct intel_uncore_type skx_uncore_chabox = { 3660 .name = "cha", 3661 .num_counters = 4, 3662 .perf_ctr_bits = 48, 3663 .event_ctl = HSWEP_C0_MSR_PMON_CTL0, 3664 .perf_ctr = HSWEP_C0_MSR_PMON_CTR0, 3665 .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK, 3666 .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL, 3667 .msr_offset = HSWEP_CBO_MSR_OFFSET, 3668 .num_shared_regs = 1, 3669 .constraints = skx_uncore_chabox_constraints, 3670 .ops = &skx_uncore_chabox_ops, 3671 .format_group = &skx_uncore_chabox_format_group, 3672}; 3673 3674static struct attribute *skx_uncore_iio_formats_attr[] = { 3675 &format_attr_event.attr, 3676 &format_attr_umask.attr, 3677 &format_attr_edge.attr, 3678 &format_attr_inv.attr, 3679 &format_attr_thresh9.attr, 3680 &format_attr_ch_mask.attr, 3681 &format_attr_fc_mask.attr, 3682 NULL, 3683}; 3684 3685static const struct attribute_group skx_uncore_iio_format_group = { 3686 .name = "format", 3687 .attrs = skx_uncore_iio_formats_attr, 3688}; 3689 3690static struct event_constraint skx_uncore_iio_constraints[] = { 3691 UNCORE_EVENT_CONSTRAINT(0x83, 0x3), 3692 UNCORE_EVENT_CONSTRAINT(0x88, 0xc), 3693 UNCORE_EVENT_CONSTRAINT(0x95, 0xc), 3694 UNCORE_EVENT_CONSTRAINT(0xc0, 0xc), 3695 UNCORE_EVENT_CONSTRAINT(0xc5, 0xc), 3696 UNCORE_EVENT_CONSTRAINT(0xd4, 0xc), 3697 UNCORE_EVENT_CONSTRAINT(0xd5, 0xc), 3698 EVENT_CONSTRAINT_END 3699}; 3700 3701static void skx_iio_enable_event(struct intel_uncore_box *box, 3702 struct perf_event *event) 3703{ 3704 struct hw_perf_event *hwc = &event->hw; 3705 3706 wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 3707} 3708 3709static struct intel_uncore_ops skx_uncore_iio_ops = { 3710 .init_box = ivbep_uncore_msr_init_box, 3711 .disable_box = snbep_uncore_msr_disable_box, 3712 .enable_box = snbep_uncore_msr_enable_box, 3713 .disable_event = snbep_uncore_msr_disable_event, 3714 .enable_event = skx_iio_enable_event, 3715 .read_counter = uncore_msr_read_counter, 3716}; 3717 3718static struct intel_uncore_topology *pmu_topology(struct intel_uncore_pmu *pmu, int die) 3719{ 3720 int idx; 3721 3722 for (idx = 0; idx < pmu->type->num_boxes; idx++) { 3723 if (pmu->type->topology[die][idx].pmu_idx == pmu->pmu_idx) 3724 return &pmu->type->topology[die][idx]; 3725 } 3726 3727 return NULL; 3728} 3729 3730static umode_t 3731pmu_iio_mapping_visible(struct kobject *kobj, struct attribute *attr, 3732 int die, int zero_bus_pmu) 3733{ 3734 struct intel_uncore_pmu *pmu = dev_to_uncore_pmu(kobj_to_dev(kobj)); 3735 struct intel_uncore_topology *pmut = pmu_topology(pmu, die); 3736 3737 return (pmut && !pmut->iio->pci_bus_no && pmu->pmu_idx != zero_bus_pmu) ? 0 : attr->mode; 3738} 3739 3740static umode_t 3741skx_iio_mapping_visible(struct kobject *kobj, struct attribute *attr, int die) 3742{ 3743 /* Root bus 0x00 is valid only for pmu_idx = 0. */ 3744 return pmu_iio_mapping_visible(kobj, attr, die, 0); 3745} 3746 3747static ssize_t skx_iio_mapping_show(struct device *dev, 3748 struct device_attribute *attr, char *buf) 3749{ 3750 struct intel_uncore_pmu *pmu = dev_to_uncore_pmu(dev); 3751 struct dev_ext_attribute *ea = to_dev_ext_attribute(attr); 3752 long die = (long)ea->var; 3753 struct intel_uncore_topology *pmut = pmu_topology(pmu, die); 3754 3755 return sprintf(buf, "%04x:%02x\n", pmut ? pmut->iio->segment : 0, 3756 pmut ? pmut->iio->pci_bus_no : 0); 3757} 3758 3759static int skx_msr_cpu_bus_read(int cpu, u64 *topology) 3760{ 3761 u64 msr_value; 3762 3763 if (rdmsrq_on_cpu(cpu, SKX_MSR_CPU_BUS_NUMBER, &msr_value) || 3764 !(msr_value & SKX_MSR_CPU_BUS_VALID_BIT)) 3765 return -ENXIO; 3766 3767 *topology = msr_value; 3768 3769 return 0; 3770} 3771 3772static int die_to_cpu(int die) 3773{ 3774 int res = 0, cpu, current_die; 3775 /* 3776 * Using cpus_read_lock() to ensure cpu is not going down between 3777 * looking at cpu_online_mask. 3778 */ 3779 cpus_read_lock(); 3780 for_each_online_cpu(cpu) { 3781 current_die = topology_logical_die_id(cpu); 3782 if (current_die == die) { 3783 res = cpu; 3784 break; 3785 } 3786 } 3787 cpus_read_unlock(); 3788 return res; 3789} 3790 3791enum { 3792 IIO_TOPOLOGY_TYPE, 3793 UPI_TOPOLOGY_TYPE, 3794 TOPOLOGY_MAX 3795}; 3796 3797static const size_t topology_size[TOPOLOGY_MAX] = { 3798 sizeof(*((struct intel_uncore_topology *)NULL)->iio), 3799 sizeof(*((struct intel_uncore_topology *)NULL)->upi) 3800}; 3801 3802static int pmu_alloc_topology(struct intel_uncore_type *type, int topology_type) 3803{ 3804 int die, idx; 3805 struct intel_uncore_topology **topology; 3806 3807 if (!type->num_boxes) 3808 return -EPERM; 3809 3810 topology = kcalloc(uncore_max_dies(), sizeof(*topology), GFP_KERNEL); 3811 if (!topology) 3812 goto err; 3813 3814 for (die = 0; die < uncore_max_dies(); die++) { 3815 topology[die] = kcalloc(type->num_boxes, sizeof(**topology), GFP_KERNEL); 3816 if (!topology[die]) 3817 goto clear; 3818 for (idx = 0; idx < type->num_boxes; idx++) { 3819 topology[die][idx].untyped = kcalloc(type->num_boxes, 3820 topology_size[topology_type], 3821 GFP_KERNEL); 3822 if (!topology[die][idx].untyped) 3823 goto clear; 3824 } 3825 } 3826 3827 type->topology = topology; 3828 3829 return 0; 3830clear: 3831 for (; die >= 0; die--) { 3832 for (idx = 0; idx < type->num_boxes; idx++) 3833 kfree(topology[die][idx].untyped); 3834 kfree(topology[die]); 3835 } 3836 kfree(topology); 3837err: 3838 return -ENOMEM; 3839} 3840 3841static void pmu_free_topology(struct intel_uncore_type *type) 3842{ 3843 int die, idx; 3844 3845 if (type->topology) { 3846 for (die = 0; die < uncore_max_dies(); die++) { 3847 for (idx = 0; idx < type->num_boxes; idx++) 3848 kfree(type->topology[die][idx].untyped); 3849 kfree(type->topology[die]); 3850 } 3851 kfree(type->topology); 3852 type->topology = NULL; 3853 } 3854} 3855 3856static int skx_pmu_get_topology(struct intel_uncore_type *type, 3857 int (*topology_cb)(struct intel_uncore_type*, int, int, u64)) 3858{ 3859 int die, ret = -EPERM; 3860 u64 cpu_bus_msr; 3861 3862 for (die = 0; die < uncore_max_dies(); die++) { 3863 ret = skx_msr_cpu_bus_read(die_to_cpu(die), &cpu_bus_msr); 3864 if (ret) 3865 break; 3866 3867 ret = uncore_die_to_segment(die); 3868 if (ret < 0) 3869 break; 3870 3871 ret = topology_cb(type, ret, die, cpu_bus_msr); 3872 if (ret) 3873 break; 3874 } 3875 3876 return ret; 3877} 3878 3879static int skx_iio_topology_cb(struct intel_uncore_type *type, int segment, 3880 int die, u64 cpu_bus_msr) 3881{ 3882 int idx; 3883 struct intel_uncore_topology *t; 3884 3885 for (idx = 0; idx < type->num_boxes; idx++) { 3886 t = &type->topology[die][idx]; 3887 t->pmu_idx = idx; 3888 t->iio->segment = segment; 3889 t->iio->pci_bus_no = (cpu_bus_msr >> (idx * BUS_NUM_STRIDE)) & 0xff; 3890 } 3891 3892 return 0; 3893} 3894 3895static int skx_iio_get_topology(struct intel_uncore_type *type) 3896{ 3897 return skx_pmu_get_topology(type, skx_iio_topology_cb); 3898} 3899 3900static struct attribute_group skx_iio_mapping_group = { 3901 .is_visible = skx_iio_mapping_visible, 3902}; 3903 3904static const struct attribute_group *skx_iio_attr_update[] = { 3905 &skx_iio_mapping_group, 3906 NULL, 3907}; 3908 3909static void pmu_clear_mapping_attr(const struct attribute_group **groups, 3910 struct attribute_group *ag) 3911{ 3912 int i; 3913 3914 for (i = 0; groups[i]; i++) { 3915 if (groups[i] == ag) { 3916 for (i++; groups[i]; i++) 3917 groups[i - 1] = groups[i]; 3918 groups[i - 1] = NULL; 3919 break; 3920 } 3921 } 3922} 3923 3924static void 3925pmu_set_mapping(struct intel_uncore_type *type, struct attribute_group *ag, 3926 ssize_t (*show)(struct device*, struct device_attribute*, char*), 3927 int topology_type) 3928{ 3929 char buf[64]; 3930 int ret; 3931 long die = -1; 3932 struct attribute **attrs = NULL; 3933 struct dev_ext_attribute *eas = NULL; 3934 3935 ret = pmu_alloc_topology(type, topology_type); 3936 if (ret < 0) 3937 goto clear_attr_update; 3938 3939 ret = type->get_topology(type); 3940 if (ret < 0) 3941 goto clear_topology; 3942 3943 /* One more for NULL. */ 3944 attrs = kcalloc((uncore_max_dies() + 1), sizeof(*attrs), GFP_KERNEL); 3945 if (!attrs) 3946 goto clear_topology; 3947 3948 eas = kcalloc(uncore_max_dies(), sizeof(*eas), GFP_KERNEL); 3949 if (!eas) 3950 goto clear_attrs; 3951 3952 for (die = 0; die < uncore_max_dies(); die++) { 3953 snprintf(buf, sizeof(buf), "die%ld", die); 3954 sysfs_attr_init(&eas[die].attr.attr); 3955 eas[die].attr.attr.name = kstrdup(buf, GFP_KERNEL); 3956 if (!eas[die].attr.attr.name) 3957 goto err; 3958 eas[die].attr.attr.mode = 0444; 3959 eas[die].attr.show = show; 3960 eas[die].attr.store = NULL; 3961 eas[die].var = (void *)die; 3962 attrs[die] = &eas[die].attr.attr; 3963 } 3964 ag->attrs = attrs; 3965 3966 return; 3967err: 3968 for (; die >= 0; die--) 3969 kfree(eas[die].attr.attr.name); 3970 kfree(eas); 3971clear_attrs: 3972 kfree(attrs); 3973clear_topology: 3974 pmu_free_topology(type); 3975clear_attr_update: 3976 pmu_clear_mapping_attr(type->attr_update, ag); 3977} 3978 3979static void 3980pmu_cleanup_mapping(struct intel_uncore_type *type, struct attribute_group *ag) 3981{ 3982 struct attribute **attr = ag->attrs; 3983 3984 if (!attr) 3985 return; 3986 3987 for (; *attr; attr++) 3988 kfree((*attr)->name); 3989 kfree(attr_to_ext_attr(*ag->attrs)); 3990 kfree(ag->attrs); 3991 ag->attrs = NULL; 3992 pmu_free_topology(type); 3993} 3994 3995static void 3996pmu_iio_set_mapping(struct intel_uncore_type *type, struct attribute_group *ag) 3997{ 3998 pmu_set_mapping(type, ag, skx_iio_mapping_show, IIO_TOPOLOGY_TYPE); 3999} 4000 4001static void skx_iio_set_mapping(struct intel_uncore_type *type) 4002{ 4003 pmu_iio_set_mapping(type, &skx_iio_mapping_group); 4004} 4005 4006static void skx_iio_cleanup_mapping(struct intel_uncore_type *type) 4007{ 4008 pmu_cleanup_mapping(type, &skx_iio_mapping_group); 4009} 4010 4011static struct intel_uncore_type skx_uncore_iio = { 4012 .name = "iio", 4013 .num_counters = 4, 4014 .num_boxes = 6, 4015 .perf_ctr_bits = 48, 4016 .event_ctl = SKX_IIO0_MSR_PMON_CTL0, 4017 .perf_ctr = SKX_IIO0_MSR_PMON_CTR0, 4018 .event_mask = SKX_IIO_PMON_RAW_EVENT_MASK, 4019 .event_mask_ext = SKX_IIO_PMON_RAW_EVENT_MASK_EXT, 4020 .box_ctl = SKX_IIO0_MSR_PMON_BOX_CTL, 4021 .msr_offset = SKX_IIO_MSR_OFFSET, 4022 .constraints = skx_uncore_iio_constraints, 4023 .ops = &skx_uncore_iio_ops, 4024 .format_group = &skx_uncore_iio_format_group, 4025 .attr_update = skx_iio_attr_update, 4026 .get_topology = skx_iio_get_topology, 4027 .set_mapping = skx_iio_set_mapping, 4028 .cleanup_mapping = skx_iio_cleanup_mapping, 4029}; 4030 4031enum perf_uncore_iio_freerunning_type_id { 4032 SKX_IIO_MSR_IOCLK = 0, 4033 SKX_IIO_MSR_BW = 1, 4034 SKX_IIO_MSR_UTIL = 2, 4035 4036 SKX_IIO_FREERUNNING_TYPE_MAX, 4037}; 4038 4039 4040static struct freerunning_counters skx_iio_freerunning[] = { 4041 [SKX_IIO_MSR_IOCLK] = { 0xa45, 0x1, 0x20, 1, 36 }, 4042 [SKX_IIO_MSR_BW] = { 0xb00, 0x1, 0x10, 8, 36 }, 4043 [SKX_IIO_MSR_UTIL] = { 0xb08, 0x1, 0x10, 8, 36 }, 4044}; 4045 4046static struct uncore_event_desc skx_uncore_iio_freerunning_events[] = { 4047 /* Free-Running IO CLOCKS Counter */ 4048 INTEL_UNCORE_EVENT_DESC(ioclk, "event=0xff,umask=0x10"), 4049 /* Free-Running IIO BANDWIDTH Counters */ 4050 INTEL_UNCORE_EVENT_DESC(bw_in_port0, "event=0xff,umask=0x20"), 4051 INTEL_UNCORE_EVENT_DESC(bw_in_port0.scale, "3.814697266e-6"), 4052 INTEL_UNCORE_EVENT_DESC(bw_in_port0.unit, "MiB"), 4053 INTEL_UNCORE_EVENT_DESC(bw_in_port1, "event=0xff,umask=0x21"), 4054 INTEL_UNCORE_EVENT_DESC(bw_in_port1.scale, "3.814697266e-6"), 4055 INTEL_UNCORE_EVENT_DESC(bw_in_port1.unit, "MiB"), 4056 INTEL_UNCORE_EVENT_DESC(bw_in_port2, "event=0xff,umask=0x22"), 4057 INTEL_UNCORE_EVENT_DESC(bw_in_port2.scale, "3.814697266e-6"), 4058 INTEL_UNCORE_EVENT_DESC(bw_in_port2.unit, "MiB"), 4059 INTEL_UNCORE_EVENT_DESC(bw_in_port3, "event=0xff,umask=0x23"), 4060 INTEL_UNCORE_EVENT_DESC(bw_in_port3.scale, "3.814697266e-6"), 4061 INTEL_UNCORE_EVENT_DESC(bw_in_port3.unit, "MiB"), 4062 INTEL_UNCORE_EVENT_DESC(bw_out_port0, "event=0xff,umask=0x24"), 4063 INTEL_UNCORE_EVENT_DESC(bw_out_port0.scale, "3.814697266e-6"), 4064 INTEL_UNCORE_EVENT_DESC(bw_out_port0.unit, "MiB"), 4065 INTEL_UNCORE_EVENT_DESC(bw_out_port1, "event=0xff,umask=0x25"), 4066 INTEL_UNCORE_EVENT_DESC(bw_out_port1.scale, "3.814697266e-6"), 4067 INTEL_UNCORE_EVENT_DESC(bw_out_port1.unit, "MiB"), 4068 INTEL_UNCORE_EVENT_DESC(bw_out_port2, "event=0xff,umask=0x26"), 4069 INTEL_UNCORE_EVENT_DESC(bw_out_port2.scale, "3.814697266e-6"), 4070 INTEL_UNCORE_EVENT_DESC(bw_out_port2.unit, "MiB"), 4071 INTEL_UNCORE_EVENT_DESC(bw_out_port3, "event=0xff,umask=0x27"), 4072 INTEL_UNCORE_EVENT_DESC(bw_out_port3.scale, "3.814697266e-6"), 4073 INTEL_UNCORE_EVENT_DESC(bw_out_port3.unit, "MiB"), 4074 /* Free-running IIO UTILIZATION Counters */ 4075 INTEL_UNCORE_EVENT_DESC(util_in_port0, "event=0xff,umask=0x30"), 4076 INTEL_UNCORE_EVENT_DESC(util_out_port0, "event=0xff,umask=0x31"), 4077 INTEL_UNCORE_EVENT_DESC(util_in_port1, "event=0xff,umask=0x32"), 4078 INTEL_UNCORE_EVENT_DESC(util_out_port1, "event=0xff,umask=0x33"), 4079 INTEL_UNCORE_EVENT_DESC(util_in_port2, "event=0xff,umask=0x34"), 4080 INTEL_UNCORE_EVENT_DESC(util_out_port2, "event=0xff,umask=0x35"), 4081 INTEL_UNCORE_EVENT_DESC(util_in_port3, "event=0xff,umask=0x36"), 4082 INTEL_UNCORE_EVENT_DESC(util_out_port3, "event=0xff,umask=0x37"), 4083 { /* end: all zeroes */ }, 4084}; 4085 4086static struct intel_uncore_ops skx_uncore_iio_freerunning_ops = { 4087 .read_counter = uncore_msr_read_counter, 4088 .hw_config = uncore_freerunning_hw_config, 4089}; 4090 4091static struct attribute *skx_uncore_iio_freerunning_formats_attr[] = { 4092 &format_attr_event.attr, 4093 &format_attr_umask.attr, 4094 NULL, 4095}; 4096 4097static const struct attribute_group skx_uncore_iio_freerunning_format_group = { 4098 .name = "format", 4099 .attrs = skx_uncore_iio_freerunning_formats_attr, 4100}; 4101 4102static struct intel_uncore_type skx_uncore_iio_free_running = { 4103 .name = "iio_free_running", 4104 .num_counters = 17, 4105 .num_boxes = 6, 4106 .num_freerunning_types = SKX_IIO_FREERUNNING_TYPE_MAX, 4107 .freerunning = skx_iio_freerunning, 4108 .ops = &skx_uncore_iio_freerunning_ops, 4109 .event_descs = skx_uncore_iio_freerunning_events, 4110 .format_group = &skx_uncore_iio_freerunning_format_group, 4111}; 4112 4113static struct attribute *skx_uncore_formats_attr[] = { 4114 &format_attr_event.attr, 4115 &format_attr_umask.attr, 4116 &format_attr_edge.attr, 4117 &format_attr_inv.attr, 4118 &format_attr_thresh8.attr, 4119 NULL, 4120}; 4121 4122static const struct attribute_group skx_uncore_format_group = { 4123 .name = "format", 4124 .attrs = skx_uncore_formats_attr, 4125}; 4126 4127static struct intel_uncore_type skx_uncore_irp = { 4128 .name = "irp", 4129 .num_counters = 2, 4130 .num_boxes = 6, 4131 .perf_ctr_bits = 48, 4132 .event_ctl = SKX_IRP0_MSR_PMON_CTL0, 4133 .perf_ctr = SKX_IRP0_MSR_PMON_CTR0, 4134 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4135 .box_ctl = SKX_IRP0_MSR_PMON_BOX_CTL, 4136 .msr_offset = SKX_IRP_MSR_OFFSET, 4137 .ops = &skx_uncore_iio_ops, 4138 .format_group = &skx_uncore_format_group, 4139}; 4140 4141static struct attribute *skx_uncore_pcu_formats_attr[] = { 4142 &format_attr_event.attr, 4143 &format_attr_umask.attr, 4144 &format_attr_edge.attr, 4145 &format_attr_inv.attr, 4146 &format_attr_thresh8.attr, 4147 &format_attr_occ_invert.attr, 4148 &format_attr_occ_edge_det.attr, 4149 &format_attr_filter_band0.attr, 4150 &format_attr_filter_band1.attr, 4151 &format_attr_filter_band2.attr, 4152 &format_attr_filter_band3.attr, 4153 NULL, 4154}; 4155 4156static struct attribute_group skx_uncore_pcu_format_group = { 4157 .name = "format", 4158 .attrs = skx_uncore_pcu_formats_attr, 4159}; 4160 4161static struct intel_uncore_ops skx_uncore_pcu_ops = { 4162 IVBEP_UNCORE_MSR_OPS_COMMON_INIT(), 4163 .hw_config = hswep_pcu_hw_config, 4164 .get_constraint = snbep_pcu_get_constraint, 4165 .put_constraint = snbep_pcu_put_constraint, 4166}; 4167 4168static struct intel_uncore_type skx_uncore_pcu = { 4169 .name = "pcu", 4170 .num_counters = 4, 4171 .num_boxes = 1, 4172 .perf_ctr_bits = 48, 4173 .perf_ctr = HSWEP_PCU_MSR_PMON_CTR0, 4174 .event_ctl = HSWEP_PCU_MSR_PMON_CTL0, 4175 .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK, 4176 .box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL, 4177 .num_shared_regs = 1, 4178 .ops = &skx_uncore_pcu_ops, 4179 .format_group = &skx_uncore_pcu_format_group, 4180}; 4181 4182static struct intel_uncore_type *skx_msr_uncores[] = { 4183 &skx_uncore_ubox, 4184 &skx_uncore_chabox, 4185 &skx_uncore_iio, 4186 &skx_uncore_iio_free_running, 4187 &skx_uncore_irp, 4188 &skx_uncore_pcu, 4189 NULL, 4190}; 4191 4192/* 4193 * To determine the number of CHAs, it should read bits 27:0 in the CAPID6 4194 * register which located at Device 30, Function 3, Offset 0x9C. PCI ID 0x2083. 4195 */ 4196#define SKX_CAPID6 0x9c 4197#define SKX_CHA_BIT_MASK GENMASK(27, 0) 4198 4199static int skx_count_chabox(void) 4200{ 4201 struct pci_dev *dev = NULL; 4202 u32 val = 0; 4203 4204 dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2083, dev); 4205 if (!dev) 4206 goto out; 4207 4208 pci_read_config_dword(dev, SKX_CAPID6, &val); 4209 val &= SKX_CHA_BIT_MASK; 4210out: 4211 pci_dev_put(dev); 4212 return hweight32(val); 4213} 4214 4215void skx_uncore_cpu_init(void) 4216{ 4217 skx_uncore_chabox.num_boxes = skx_count_chabox(); 4218 uncore_msr_uncores = skx_msr_uncores; 4219} 4220 4221static struct intel_uncore_type skx_uncore_imc = { 4222 .name = "imc", 4223 .num_counters = 4, 4224 .num_boxes = 6, 4225 .perf_ctr_bits = 48, 4226 .fixed_ctr_bits = 48, 4227 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR, 4228 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL, 4229 .event_descs = hswep_uncore_imc_events, 4230 .perf_ctr = SNBEP_PCI_PMON_CTR0, 4231 .event_ctl = SNBEP_PCI_PMON_CTL0, 4232 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4233 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 4234 .ops = &ivbep_uncore_pci_ops, 4235 .format_group = &skx_uncore_format_group, 4236}; 4237 4238static struct attribute *skx_upi_uncore_formats_attr[] = { 4239 &format_attr_event.attr, 4240 &format_attr_umask_ext.attr, 4241 &format_attr_edge.attr, 4242 &format_attr_inv.attr, 4243 &format_attr_thresh8.attr, 4244 NULL, 4245}; 4246 4247static const struct attribute_group skx_upi_uncore_format_group = { 4248 .name = "format", 4249 .attrs = skx_upi_uncore_formats_attr, 4250}; 4251 4252static void skx_upi_uncore_pci_init_box(struct intel_uncore_box *box) 4253{ 4254 struct pci_dev *pdev = box->pci_dev; 4255 4256 __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); 4257 pci_write_config_dword(pdev, SKX_UPI_PCI_PMON_BOX_CTL, IVBEP_PMON_BOX_CTL_INT); 4258} 4259 4260static struct intel_uncore_ops skx_upi_uncore_pci_ops = { 4261 .init_box = skx_upi_uncore_pci_init_box, 4262 .disable_box = snbep_uncore_pci_disable_box, 4263 .enable_box = snbep_uncore_pci_enable_box, 4264 .disable_event = snbep_uncore_pci_disable_event, 4265 .enable_event = snbep_uncore_pci_enable_event, 4266 .read_counter = snbep_uncore_pci_read_counter, 4267}; 4268 4269static umode_t 4270skx_upi_mapping_visible(struct kobject *kobj, struct attribute *attr, int die) 4271{ 4272 struct intel_uncore_pmu *pmu = dev_to_uncore_pmu(kobj_to_dev(kobj)); 4273 4274 return pmu->type->topology[die][pmu->pmu_idx].upi->enabled ? attr->mode : 0; 4275} 4276 4277static ssize_t skx_upi_mapping_show(struct device *dev, 4278 struct device_attribute *attr, char *buf) 4279{ 4280 struct intel_uncore_pmu *pmu = dev_to_uncore_pmu(dev); 4281 struct dev_ext_attribute *ea = to_dev_ext_attribute(attr); 4282 long die = (long)ea->var; 4283 struct uncore_upi_topology *upi = pmu->type->topology[die][pmu->pmu_idx].upi; 4284 4285 return sysfs_emit(buf, "upi_%d,die_%d\n", upi->pmu_idx_to, upi->die_to); 4286} 4287 4288#define SKX_UPI_REG_DID 0x2058 4289#define SKX_UPI_REGS_ADDR_DEVICE_LINK0 0x0e 4290#define SKX_UPI_REGS_ADDR_FUNCTION 0x00 4291 4292/* 4293 * UPI Link Parameter 0 4294 * | Bit | Default | Description 4295 * | 19:16 | 0h | base_nodeid - The NodeID of the sending socket. 4296 * | 12:8 | 00h | sending_port - The processor die port number of the sending port. 4297 */ 4298#define SKX_KTILP0_OFFSET 0x94 4299 4300/* 4301 * UPI Pcode Status. This register is used by PCode to store the link training status. 4302 * | Bit | Default | Description 4303 * | 4 | 0h | ll_status_valid — Bit indicates the valid training status 4304 * logged from PCode to the BIOS. 4305 */ 4306#define SKX_KTIPCSTS_OFFSET 0x120 4307 4308static int upi_fill_topology(struct pci_dev *dev, struct intel_uncore_topology *tp, 4309 int pmu_idx) 4310{ 4311 int ret; 4312 u32 upi_conf; 4313 struct uncore_upi_topology *upi = tp->upi; 4314 4315 tp->pmu_idx = pmu_idx; 4316 ret = pci_read_config_dword(dev, SKX_KTIPCSTS_OFFSET, &upi_conf); 4317 if (ret) { 4318 ret = pcibios_err_to_errno(ret); 4319 goto err; 4320 } 4321 upi->enabled = (upi_conf >> 4) & 1; 4322 if (upi->enabled) { 4323 ret = pci_read_config_dword(dev, SKX_KTILP0_OFFSET, 4324 &upi_conf); 4325 if (ret) { 4326 ret = pcibios_err_to_errno(ret); 4327 goto err; 4328 } 4329 upi->die_to = (upi_conf >> 16) & 0xf; 4330 upi->pmu_idx_to = (upi_conf >> 8) & 0x1f; 4331 } 4332err: 4333 return ret; 4334} 4335 4336static int skx_upi_topology_cb(struct intel_uncore_type *type, int segment, 4337 int die, u64 cpu_bus_msr) 4338{ 4339 int idx, ret; 4340 struct intel_uncore_topology *upi; 4341 unsigned int devfn; 4342 struct pci_dev *dev = NULL; 4343 u8 bus = cpu_bus_msr >> (3 * BUS_NUM_STRIDE); 4344 4345 for (idx = 0; idx < type->num_boxes; idx++) { 4346 upi = &type->topology[die][idx]; 4347 devfn = PCI_DEVFN(SKX_UPI_REGS_ADDR_DEVICE_LINK0 + idx, 4348 SKX_UPI_REGS_ADDR_FUNCTION); 4349 dev = pci_get_domain_bus_and_slot(segment, bus, devfn); 4350 if (dev) { 4351 ret = upi_fill_topology(dev, upi, idx); 4352 if (ret) 4353 break; 4354 } 4355 } 4356 4357 pci_dev_put(dev); 4358 return ret; 4359} 4360 4361static int skx_upi_get_topology(struct intel_uncore_type *type) 4362{ 4363 /* CPX case is not supported */ 4364 if (boot_cpu_data.x86_stepping == 11) 4365 return -EPERM; 4366 4367 return skx_pmu_get_topology(type, skx_upi_topology_cb); 4368} 4369 4370static struct attribute_group skx_upi_mapping_group = { 4371 .is_visible = skx_upi_mapping_visible, 4372}; 4373 4374static const struct attribute_group *skx_upi_attr_update[] = { 4375 &skx_upi_mapping_group, 4376 NULL 4377}; 4378 4379static void 4380pmu_upi_set_mapping(struct intel_uncore_type *type, struct attribute_group *ag) 4381{ 4382 pmu_set_mapping(type, ag, skx_upi_mapping_show, UPI_TOPOLOGY_TYPE); 4383} 4384 4385static void skx_upi_set_mapping(struct intel_uncore_type *type) 4386{ 4387 pmu_upi_set_mapping(type, &skx_upi_mapping_group); 4388} 4389 4390static void skx_upi_cleanup_mapping(struct intel_uncore_type *type) 4391{ 4392 pmu_cleanup_mapping(type, &skx_upi_mapping_group); 4393} 4394 4395static struct intel_uncore_type skx_uncore_upi = { 4396 .name = "upi", 4397 .num_counters = 4, 4398 .num_boxes = 3, 4399 .perf_ctr_bits = 48, 4400 .perf_ctr = SKX_UPI_PCI_PMON_CTR0, 4401 .event_ctl = SKX_UPI_PCI_PMON_CTL0, 4402 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4403 .event_mask_ext = SKX_UPI_CTL_UMASK_EXT, 4404 .box_ctl = SKX_UPI_PCI_PMON_BOX_CTL, 4405 .ops = &skx_upi_uncore_pci_ops, 4406 .format_group = &skx_upi_uncore_format_group, 4407 .attr_update = skx_upi_attr_update, 4408 .get_topology = skx_upi_get_topology, 4409 .set_mapping = skx_upi_set_mapping, 4410 .cleanup_mapping = skx_upi_cleanup_mapping, 4411}; 4412 4413static void skx_m2m_uncore_pci_init_box(struct intel_uncore_box *box) 4414{ 4415 struct pci_dev *pdev = box->pci_dev; 4416 4417 __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); 4418 pci_write_config_dword(pdev, SKX_M2M_PCI_PMON_BOX_CTL, IVBEP_PMON_BOX_CTL_INT); 4419} 4420 4421static struct intel_uncore_ops skx_m2m_uncore_pci_ops = { 4422 .init_box = skx_m2m_uncore_pci_init_box, 4423 .disable_box = snbep_uncore_pci_disable_box, 4424 .enable_box = snbep_uncore_pci_enable_box, 4425 .disable_event = snbep_uncore_pci_disable_event, 4426 .enable_event = snbep_uncore_pci_enable_event, 4427 .read_counter = snbep_uncore_pci_read_counter, 4428}; 4429 4430static struct intel_uncore_type skx_uncore_m2m = { 4431 .name = "m2m", 4432 .num_counters = 4, 4433 .num_boxes = 2, 4434 .perf_ctr_bits = 48, 4435 .perf_ctr = SKX_M2M_PCI_PMON_CTR0, 4436 .event_ctl = SKX_M2M_PCI_PMON_CTL0, 4437 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4438 .box_ctl = SKX_M2M_PCI_PMON_BOX_CTL, 4439 .ops = &skx_m2m_uncore_pci_ops, 4440 .format_group = &skx_uncore_format_group, 4441}; 4442 4443static struct event_constraint skx_uncore_m2pcie_constraints[] = { 4444 UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 4445 EVENT_CONSTRAINT_END 4446}; 4447 4448static struct intel_uncore_type skx_uncore_m2pcie = { 4449 .name = "m2pcie", 4450 .num_counters = 4, 4451 .num_boxes = 4, 4452 .perf_ctr_bits = 48, 4453 .constraints = skx_uncore_m2pcie_constraints, 4454 .perf_ctr = SNBEP_PCI_PMON_CTR0, 4455 .event_ctl = SNBEP_PCI_PMON_CTL0, 4456 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4457 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 4458 .ops = &ivbep_uncore_pci_ops, 4459 .format_group = &skx_uncore_format_group, 4460}; 4461 4462static struct event_constraint skx_uncore_m3upi_constraints[] = { 4463 UNCORE_EVENT_CONSTRAINT(0x1d, 0x1), 4464 UNCORE_EVENT_CONSTRAINT(0x1e, 0x1), 4465 UNCORE_EVENT_CONSTRAINT(0x40, 0x7), 4466 UNCORE_EVENT_CONSTRAINT(0x4e, 0x7), 4467 UNCORE_EVENT_CONSTRAINT(0x4f, 0x7), 4468 UNCORE_EVENT_CONSTRAINT(0x50, 0x7), 4469 UNCORE_EVENT_CONSTRAINT(0x51, 0x7), 4470 UNCORE_EVENT_CONSTRAINT(0x52, 0x7), 4471 EVENT_CONSTRAINT_END 4472}; 4473 4474static struct intel_uncore_type skx_uncore_m3upi = { 4475 .name = "m3upi", 4476 .num_counters = 3, 4477 .num_boxes = 3, 4478 .perf_ctr_bits = 48, 4479 .constraints = skx_uncore_m3upi_constraints, 4480 .perf_ctr = SNBEP_PCI_PMON_CTR0, 4481 .event_ctl = SNBEP_PCI_PMON_CTL0, 4482 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4483 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, 4484 .ops = &ivbep_uncore_pci_ops, 4485 .format_group = &skx_uncore_format_group, 4486}; 4487 4488enum { 4489 SKX_PCI_UNCORE_IMC, 4490 SKX_PCI_UNCORE_M2M, 4491 SKX_PCI_UNCORE_UPI, 4492 SKX_PCI_UNCORE_M2PCIE, 4493 SKX_PCI_UNCORE_M3UPI, 4494}; 4495 4496static struct intel_uncore_type *skx_pci_uncores[] = { 4497 [SKX_PCI_UNCORE_IMC] = &skx_uncore_imc, 4498 [SKX_PCI_UNCORE_M2M] = &skx_uncore_m2m, 4499 [SKX_PCI_UNCORE_UPI] = &skx_uncore_upi, 4500 [SKX_PCI_UNCORE_M2PCIE] = &skx_uncore_m2pcie, 4501 [SKX_PCI_UNCORE_M3UPI] = &skx_uncore_m3upi, 4502 NULL, 4503}; 4504 4505static const struct pci_device_id skx_uncore_pci_ids[] = { 4506 { /* MC0 Channel 0 */ 4507 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2042), 4508 .driver_data = UNCORE_PCI_DEV_FULL_DATA(10, 2, SKX_PCI_UNCORE_IMC, 0), 4509 }, 4510 { /* MC0 Channel 1 */ 4511 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2046), 4512 .driver_data = UNCORE_PCI_DEV_FULL_DATA(10, 6, SKX_PCI_UNCORE_IMC, 1), 4513 }, 4514 { /* MC0 Channel 2 */ 4515 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204a), 4516 .driver_data = UNCORE_PCI_DEV_FULL_DATA(11, 2, SKX_PCI_UNCORE_IMC, 2), 4517 }, 4518 { /* MC1 Channel 0 */ 4519 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2042), 4520 .driver_data = UNCORE_PCI_DEV_FULL_DATA(12, 2, SKX_PCI_UNCORE_IMC, 3), 4521 }, 4522 { /* MC1 Channel 1 */ 4523 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2046), 4524 .driver_data = UNCORE_PCI_DEV_FULL_DATA(12, 6, SKX_PCI_UNCORE_IMC, 4), 4525 }, 4526 { /* MC1 Channel 2 */ 4527 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204a), 4528 .driver_data = UNCORE_PCI_DEV_FULL_DATA(13, 2, SKX_PCI_UNCORE_IMC, 5), 4529 }, 4530 { /* M2M0 */ 4531 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2066), 4532 .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 0, SKX_PCI_UNCORE_M2M, 0), 4533 }, 4534 { /* M2M1 */ 4535 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2066), 4536 .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 0, SKX_PCI_UNCORE_M2M, 1), 4537 }, 4538 { /* UPI0 Link 0 */ 4539 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2058), 4540 .driver_data = UNCORE_PCI_DEV_FULL_DATA(14, 0, SKX_PCI_UNCORE_UPI, 0), 4541 }, 4542 { /* UPI0 Link 1 */ 4543 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2058), 4544 .driver_data = UNCORE_PCI_DEV_FULL_DATA(15, 0, SKX_PCI_UNCORE_UPI, 1), 4545 }, 4546 { /* UPI1 Link 2 */ 4547 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2058), 4548 .driver_data = UNCORE_PCI_DEV_FULL_DATA(16, 0, SKX_PCI_UNCORE_UPI, 2), 4549 }, 4550 { /* M2PCIe 0 */ 4551 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088), 4552 .driver_data = UNCORE_PCI_DEV_FULL_DATA(21, 1, SKX_PCI_UNCORE_M2PCIE, 0), 4553 }, 4554 { /* M2PCIe 1 */ 4555 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088), 4556 .driver_data = UNCORE_PCI_DEV_FULL_DATA(22, 1, SKX_PCI_UNCORE_M2PCIE, 1), 4557 }, 4558 { /* M2PCIe 2 */ 4559 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088), 4560 .driver_data = UNCORE_PCI_DEV_FULL_DATA(23, 1, SKX_PCI_UNCORE_M2PCIE, 2), 4561 }, 4562 { /* M2PCIe 3 */ 4563 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088), 4564 .driver_data = UNCORE_PCI_DEV_FULL_DATA(21, 5, SKX_PCI_UNCORE_M2PCIE, 3), 4565 }, 4566 { /* M3UPI0 Link 0 */ 4567 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204D), 4568 .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 1, SKX_PCI_UNCORE_M3UPI, 0), 4569 }, 4570 { /* M3UPI0 Link 1 */ 4571 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204E), 4572 .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 2, SKX_PCI_UNCORE_M3UPI, 1), 4573 }, 4574 { /* M3UPI1 Link 2 */ 4575 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204D), 4576 .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 5, SKX_PCI_UNCORE_M3UPI, 2), 4577 }, 4578 { /* end: all zeroes */ } 4579}; 4580 4581 4582static struct pci_driver skx_uncore_pci_driver = { 4583 .name = "skx_uncore", 4584 .id_table = skx_uncore_pci_ids, 4585}; 4586 4587int skx_uncore_pci_init(void) 4588{ 4589 /* need to double check pci address */ 4590 int ret = snbep_pci2phy_map_init(0x2014, SKX_CPUNODEID, SKX_GIDNIDMAP, false); 4591 4592 if (ret) 4593 return ret; 4594 4595 uncore_pci_uncores = skx_pci_uncores; 4596 uncore_pci_driver = &skx_uncore_pci_driver; 4597 return 0; 4598} 4599 4600/* end of SKX uncore support */ 4601 4602/* SNR uncore support */ 4603 4604static struct intel_uncore_type snr_uncore_ubox = { 4605 .name = "ubox", 4606 .num_counters = 2, 4607 .num_boxes = 1, 4608 .perf_ctr_bits = 48, 4609 .fixed_ctr_bits = 48, 4610 .perf_ctr = SNR_U_MSR_PMON_CTR0, 4611 .event_ctl = SNR_U_MSR_PMON_CTL0, 4612 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4613 .fixed_ctr = SNR_U_MSR_PMON_UCLK_FIXED_CTR, 4614 .fixed_ctl = SNR_U_MSR_PMON_UCLK_FIXED_CTL, 4615 .ops = &ivbep_uncore_msr_ops, 4616 .format_group = &ivbep_uncore_format_group, 4617}; 4618 4619static struct attribute *snr_uncore_cha_formats_attr[] = { 4620 &format_attr_event.attr, 4621 &format_attr_umask_ext2.attr, 4622 &format_attr_edge.attr, 4623 &format_attr_tid_en.attr, 4624 &format_attr_inv.attr, 4625 &format_attr_thresh8.attr, 4626 &format_attr_filter_tid5.attr, 4627 NULL, 4628}; 4629static const struct attribute_group snr_uncore_chabox_format_group = { 4630 .name = "format", 4631 .attrs = snr_uncore_cha_formats_attr, 4632}; 4633 4634static int snr_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event) 4635{ 4636 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 4637 4638 reg1->reg = SNR_C0_MSR_PMON_BOX_FILTER0 + 4639 box->pmu->type->msr_offset * box->pmu->pmu_idx; 4640 reg1->config = event->attr.config1 & SKX_CHA_MSR_PMON_BOX_FILTER_TID; 4641 reg1->idx = 0; 4642 4643 return 0; 4644} 4645 4646static void snr_cha_enable_event(struct intel_uncore_box *box, 4647 struct perf_event *event) 4648{ 4649 struct hw_perf_event *hwc = &event->hw; 4650 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 4651 4652 if (reg1->idx != EXTRA_REG_NONE) 4653 wrmsrq(reg1->reg, reg1->config); 4654 4655 wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 4656} 4657 4658static struct intel_uncore_ops snr_uncore_chabox_ops = { 4659 .init_box = ivbep_uncore_msr_init_box, 4660 .disable_box = snbep_uncore_msr_disable_box, 4661 .enable_box = snbep_uncore_msr_enable_box, 4662 .disable_event = snbep_uncore_msr_disable_event, 4663 .enable_event = snr_cha_enable_event, 4664 .read_counter = uncore_msr_read_counter, 4665 .hw_config = snr_cha_hw_config, 4666}; 4667 4668static struct intel_uncore_type snr_uncore_chabox = { 4669 .name = "cha", 4670 .num_counters = 4, 4671 .num_boxes = 6, 4672 .perf_ctr_bits = 48, 4673 .event_ctl = SNR_CHA_MSR_PMON_CTL0, 4674 .perf_ctr = SNR_CHA_MSR_PMON_CTR0, 4675 .box_ctl = SNR_CHA_MSR_PMON_BOX_CTL, 4676 .msr_offset = HSWEP_CBO_MSR_OFFSET, 4677 .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK, 4678 .event_mask_ext = SNR_CHA_RAW_EVENT_MASK_EXT, 4679 .ops = &snr_uncore_chabox_ops, 4680 .format_group = &snr_uncore_chabox_format_group, 4681}; 4682 4683static struct attribute *snr_uncore_iio_formats_attr[] = { 4684 &format_attr_event.attr, 4685 &format_attr_umask.attr, 4686 &format_attr_edge.attr, 4687 &format_attr_inv.attr, 4688 &format_attr_thresh9.attr, 4689 &format_attr_ch_mask2.attr, 4690 &format_attr_fc_mask2.attr, 4691 NULL, 4692}; 4693 4694static const struct attribute_group snr_uncore_iio_format_group = { 4695 .name = "format", 4696 .attrs = snr_uncore_iio_formats_attr, 4697}; 4698 4699static umode_t 4700snr_iio_mapping_visible(struct kobject *kobj, struct attribute *attr, int die) 4701{ 4702 /* Root bus 0x00 is valid only for pmu_idx = 1. */ 4703 return pmu_iio_mapping_visible(kobj, attr, die, 1); 4704} 4705 4706static struct attribute_group snr_iio_mapping_group = { 4707 .is_visible = snr_iio_mapping_visible, 4708}; 4709 4710static const struct attribute_group *snr_iio_attr_update[] = { 4711 &snr_iio_mapping_group, 4712 NULL, 4713}; 4714 4715static int sad_cfg_iio_topology(struct intel_uncore_type *type, u8 *sad_pmon_mapping) 4716{ 4717 u32 sad_cfg; 4718 int die, stack_id, ret = -EPERM; 4719 struct pci_dev *dev = NULL; 4720 4721 while ((dev = pci_get_device(PCI_VENDOR_ID_INTEL, SNR_ICX_MESH2IIO_MMAP_DID, dev))) { 4722 ret = pci_read_config_dword(dev, SNR_ICX_SAD_CONTROL_CFG, &sad_cfg); 4723 if (ret) { 4724 ret = pcibios_err_to_errno(ret); 4725 break; 4726 } 4727 4728 die = uncore_pcibus_to_dieid(dev->bus); 4729 stack_id = SAD_CONTROL_STACK_ID(sad_cfg); 4730 if (die < 0 || stack_id >= type->num_boxes) { 4731 ret = -EPERM; 4732 break; 4733 } 4734 4735 /* Convert stack id from SAD_CONTROL to PMON notation. */ 4736 stack_id = sad_pmon_mapping[stack_id]; 4737 4738 type->topology[die][stack_id].iio->segment = pci_domain_nr(dev->bus); 4739 type->topology[die][stack_id].pmu_idx = stack_id; 4740 type->topology[die][stack_id].iio->pci_bus_no = dev->bus->number; 4741 } 4742 4743 pci_dev_put(dev); 4744 4745 return ret; 4746} 4747 4748/* 4749 * SNR has a static mapping of stack IDs from SAD_CONTROL_CFG notation to PMON 4750 */ 4751enum { 4752 SNR_QAT_PMON_ID, 4753 SNR_CBDMA_DMI_PMON_ID, 4754 SNR_NIS_PMON_ID, 4755 SNR_DLB_PMON_ID, 4756 SNR_PCIE_GEN3_PMON_ID 4757}; 4758 4759static u8 snr_sad_pmon_mapping[] = { 4760 SNR_CBDMA_DMI_PMON_ID, 4761 SNR_PCIE_GEN3_PMON_ID, 4762 SNR_DLB_PMON_ID, 4763 SNR_NIS_PMON_ID, 4764 SNR_QAT_PMON_ID 4765}; 4766 4767static int snr_iio_get_topology(struct intel_uncore_type *type) 4768{ 4769 return sad_cfg_iio_topology(type, snr_sad_pmon_mapping); 4770} 4771 4772static void snr_iio_set_mapping(struct intel_uncore_type *type) 4773{ 4774 pmu_iio_set_mapping(type, &snr_iio_mapping_group); 4775} 4776 4777static void snr_iio_cleanup_mapping(struct intel_uncore_type *type) 4778{ 4779 pmu_cleanup_mapping(type, &snr_iio_mapping_group); 4780} 4781 4782static struct event_constraint snr_uncore_iio_constraints[] = { 4783 UNCORE_EVENT_CONSTRAINT(0x83, 0x3), 4784 UNCORE_EVENT_CONSTRAINT(0xc0, 0xc), 4785 UNCORE_EVENT_CONSTRAINT(0xd5, 0xc), 4786 EVENT_CONSTRAINT_END 4787}; 4788 4789static struct intel_uncore_type snr_uncore_iio = { 4790 .name = "iio", 4791 .num_counters = 4, 4792 .num_boxes = 5, 4793 .perf_ctr_bits = 48, 4794 .event_ctl = SNR_IIO_MSR_PMON_CTL0, 4795 .perf_ctr = SNR_IIO_MSR_PMON_CTR0, 4796 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4797 .event_mask_ext = SNR_IIO_PMON_RAW_EVENT_MASK_EXT, 4798 .box_ctl = SNR_IIO_MSR_PMON_BOX_CTL, 4799 .msr_offset = SNR_IIO_MSR_OFFSET, 4800 .constraints = snr_uncore_iio_constraints, 4801 .ops = &ivbep_uncore_msr_ops, 4802 .format_group = &snr_uncore_iio_format_group, 4803 .attr_update = snr_iio_attr_update, 4804 .get_topology = snr_iio_get_topology, 4805 .set_mapping = snr_iio_set_mapping, 4806 .cleanup_mapping = snr_iio_cleanup_mapping, 4807}; 4808 4809static struct intel_uncore_type snr_uncore_irp = { 4810 .name = "irp", 4811 .num_counters = 2, 4812 .num_boxes = 5, 4813 .perf_ctr_bits = 48, 4814 .event_ctl = SNR_IRP0_MSR_PMON_CTL0, 4815 .perf_ctr = SNR_IRP0_MSR_PMON_CTR0, 4816 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4817 .box_ctl = SNR_IRP0_MSR_PMON_BOX_CTL, 4818 .msr_offset = SNR_IRP_MSR_OFFSET, 4819 .ops = &ivbep_uncore_msr_ops, 4820 .format_group = &ivbep_uncore_format_group, 4821}; 4822 4823static struct intel_uncore_type snr_uncore_m2pcie = { 4824 .name = "m2pcie", 4825 .num_counters = 4, 4826 .num_boxes = 5, 4827 .perf_ctr_bits = 48, 4828 .event_ctl = SNR_M2PCIE_MSR_PMON_CTL0, 4829 .perf_ctr = SNR_M2PCIE_MSR_PMON_CTR0, 4830 .box_ctl = SNR_M2PCIE_MSR_PMON_BOX_CTL, 4831 .msr_offset = SNR_M2PCIE_MSR_OFFSET, 4832 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4833 .ops = &ivbep_uncore_msr_ops, 4834 .format_group = &ivbep_uncore_format_group, 4835}; 4836 4837static int snr_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event) 4838{ 4839 struct hw_perf_event *hwc = &event->hw; 4840 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 4841 int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK; 4842 4843 if (ev_sel >= 0xb && ev_sel <= 0xe) { 4844 reg1->reg = SNR_PCU_MSR_PMON_BOX_FILTER; 4845 reg1->idx = ev_sel - 0xb; 4846 reg1->config = event->attr.config1 & (0xff << reg1->idx); 4847 } 4848 return 0; 4849} 4850 4851static struct intel_uncore_ops snr_uncore_pcu_ops = { 4852 IVBEP_UNCORE_MSR_OPS_COMMON_INIT(), 4853 .hw_config = snr_pcu_hw_config, 4854 .get_constraint = snbep_pcu_get_constraint, 4855 .put_constraint = snbep_pcu_put_constraint, 4856}; 4857 4858static struct intel_uncore_type snr_uncore_pcu = { 4859 .name = "pcu", 4860 .num_counters = 4, 4861 .num_boxes = 1, 4862 .perf_ctr_bits = 48, 4863 .perf_ctr = SNR_PCU_MSR_PMON_CTR0, 4864 .event_ctl = SNR_PCU_MSR_PMON_CTL0, 4865 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4866 .box_ctl = SNR_PCU_MSR_PMON_BOX_CTL, 4867 .num_shared_regs = 1, 4868 .ops = &snr_uncore_pcu_ops, 4869 .format_group = &skx_uncore_pcu_format_group, 4870}; 4871 4872enum perf_uncore_snr_iio_freerunning_type_id { 4873 SNR_IIO_MSR_IOCLK, 4874 SNR_IIO_MSR_BW_IN, 4875 4876 SNR_IIO_FREERUNNING_TYPE_MAX, 4877}; 4878 4879static struct freerunning_counters snr_iio_freerunning[] = { 4880 [SNR_IIO_MSR_IOCLK] = { 0x1eac, 0x1, 0x10, 1, 48 }, 4881 [SNR_IIO_MSR_BW_IN] = { 0x1f00, 0x1, 0x10, 8, 48 }, 4882}; 4883 4884static struct uncore_event_desc snr_uncore_iio_freerunning_events[] = { 4885 /* Free-Running IIO CLOCKS Counter */ 4886 INTEL_UNCORE_EVENT_DESC(ioclk, "event=0xff,umask=0x10"), 4887 /* Free-Running IIO BANDWIDTH IN Counters */ 4888 INTEL_UNCORE_EVENT_DESC(bw_in_port0, "event=0xff,umask=0x20"), 4889 INTEL_UNCORE_EVENT_DESC(bw_in_port0.scale, "3.0517578125e-5"), 4890 INTEL_UNCORE_EVENT_DESC(bw_in_port0.unit, "MiB"), 4891 INTEL_UNCORE_EVENT_DESC(bw_in_port1, "event=0xff,umask=0x21"), 4892 INTEL_UNCORE_EVENT_DESC(bw_in_port1.scale, "3.0517578125e-5"), 4893 INTEL_UNCORE_EVENT_DESC(bw_in_port1.unit, "MiB"), 4894 INTEL_UNCORE_EVENT_DESC(bw_in_port2, "event=0xff,umask=0x22"), 4895 INTEL_UNCORE_EVENT_DESC(bw_in_port2.scale, "3.0517578125e-5"), 4896 INTEL_UNCORE_EVENT_DESC(bw_in_port2.unit, "MiB"), 4897 INTEL_UNCORE_EVENT_DESC(bw_in_port3, "event=0xff,umask=0x23"), 4898 INTEL_UNCORE_EVENT_DESC(bw_in_port3.scale, "3.0517578125e-5"), 4899 INTEL_UNCORE_EVENT_DESC(bw_in_port3.unit, "MiB"), 4900 INTEL_UNCORE_EVENT_DESC(bw_in_port4, "event=0xff,umask=0x24"), 4901 INTEL_UNCORE_EVENT_DESC(bw_in_port4.scale, "3.0517578125e-5"), 4902 INTEL_UNCORE_EVENT_DESC(bw_in_port4.unit, "MiB"), 4903 INTEL_UNCORE_EVENT_DESC(bw_in_port5, "event=0xff,umask=0x25"), 4904 INTEL_UNCORE_EVENT_DESC(bw_in_port5.scale, "3.0517578125e-5"), 4905 INTEL_UNCORE_EVENT_DESC(bw_in_port5.unit, "MiB"), 4906 INTEL_UNCORE_EVENT_DESC(bw_in_port6, "event=0xff,umask=0x26"), 4907 INTEL_UNCORE_EVENT_DESC(bw_in_port6.scale, "3.0517578125e-5"), 4908 INTEL_UNCORE_EVENT_DESC(bw_in_port6.unit, "MiB"), 4909 INTEL_UNCORE_EVENT_DESC(bw_in_port7, "event=0xff,umask=0x27"), 4910 INTEL_UNCORE_EVENT_DESC(bw_in_port7.scale, "3.0517578125e-5"), 4911 INTEL_UNCORE_EVENT_DESC(bw_in_port7.unit, "MiB"), 4912 { /* end: all zeroes */ }, 4913}; 4914 4915static struct intel_uncore_type snr_uncore_iio_free_running = { 4916 .name = "iio_free_running", 4917 .num_counters = 9, 4918 .num_boxes = 5, 4919 .num_freerunning_types = SNR_IIO_FREERUNNING_TYPE_MAX, 4920 .freerunning = snr_iio_freerunning, 4921 .ops = &skx_uncore_iio_freerunning_ops, 4922 .event_descs = snr_uncore_iio_freerunning_events, 4923 .format_group = &skx_uncore_iio_freerunning_format_group, 4924}; 4925 4926static struct intel_uncore_type *snr_msr_uncores[] = { 4927 &snr_uncore_ubox, 4928 &snr_uncore_chabox, 4929 &snr_uncore_iio, 4930 &snr_uncore_irp, 4931 &snr_uncore_m2pcie, 4932 &snr_uncore_pcu, 4933 &snr_uncore_iio_free_running, 4934 NULL, 4935}; 4936 4937void snr_uncore_cpu_init(void) 4938{ 4939 uncore_msr_uncores = snr_msr_uncores; 4940} 4941 4942static void snr_m2m_uncore_pci_init_box(struct intel_uncore_box *box) 4943{ 4944 struct pci_dev *pdev = box->pci_dev; 4945 int box_ctl = uncore_pci_box_ctl(box); 4946 4947 __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); 4948 pci_write_config_dword(pdev, box_ctl, IVBEP_PMON_BOX_CTL_INT); 4949} 4950 4951static struct intel_uncore_ops snr_m2m_uncore_pci_ops = { 4952 .init_box = snr_m2m_uncore_pci_init_box, 4953 .disable_box = snbep_uncore_pci_disable_box, 4954 .enable_box = snbep_uncore_pci_enable_box, 4955 .disable_event = snbep_uncore_pci_disable_event, 4956 .enable_event = snbep_uncore_pci_enable_event, 4957 .read_counter = snbep_uncore_pci_read_counter, 4958}; 4959 4960static struct attribute *snr_m2m_uncore_formats_attr[] = { 4961 &format_attr_event.attr, 4962 &format_attr_umask_ext3.attr, 4963 &format_attr_edge.attr, 4964 &format_attr_inv.attr, 4965 &format_attr_thresh8.attr, 4966 NULL, 4967}; 4968 4969static const struct attribute_group snr_m2m_uncore_format_group = { 4970 .name = "format", 4971 .attrs = snr_m2m_uncore_formats_attr, 4972}; 4973 4974static struct intel_uncore_type snr_uncore_m2m = { 4975 .name = "m2m", 4976 .num_counters = 4, 4977 .num_boxes = 1, 4978 .perf_ctr_bits = 48, 4979 .perf_ctr = SNR_M2M_PCI_PMON_CTR0, 4980 .event_ctl = SNR_M2M_PCI_PMON_CTL0, 4981 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 4982 .event_mask_ext = SNR_M2M_PCI_PMON_UMASK_EXT, 4983 .box_ctl = SNR_M2M_PCI_PMON_BOX_CTL, 4984 .ops = &snr_m2m_uncore_pci_ops, 4985 .format_group = &snr_m2m_uncore_format_group, 4986}; 4987 4988static void snr_uncore_pci_enable_event(struct intel_uncore_box *box, struct perf_event *event) 4989{ 4990 struct pci_dev *pdev = box->pci_dev; 4991 struct hw_perf_event *hwc = &event->hw; 4992 4993 pci_write_config_dword(pdev, hwc->config_base, (u32)(hwc->config | SNBEP_PMON_CTL_EN)); 4994 pci_write_config_dword(pdev, hwc->config_base + 4, (u32)(hwc->config >> 32)); 4995} 4996 4997static struct intel_uncore_ops snr_pcie3_uncore_pci_ops = { 4998 .init_box = snr_m2m_uncore_pci_init_box, 4999 .disable_box = snbep_uncore_pci_disable_box, 5000 .enable_box = snbep_uncore_pci_enable_box, 5001 .disable_event = snbep_uncore_pci_disable_event, 5002 .enable_event = snr_uncore_pci_enable_event, 5003 .read_counter = snbep_uncore_pci_read_counter, 5004}; 5005 5006static struct intel_uncore_type snr_uncore_pcie3 = { 5007 .name = "pcie3", 5008 .num_counters = 4, 5009 .num_boxes = 1, 5010 .perf_ctr_bits = 48, 5011 .perf_ctr = SNR_PCIE3_PCI_PMON_CTR0, 5012 .event_ctl = SNR_PCIE3_PCI_PMON_CTL0, 5013 .event_mask = SKX_IIO_PMON_RAW_EVENT_MASK, 5014 .event_mask_ext = SKX_IIO_PMON_RAW_EVENT_MASK_EXT, 5015 .box_ctl = SNR_PCIE3_PCI_PMON_BOX_CTL, 5016 .ops = &snr_pcie3_uncore_pci_ops, 5017 .format_group = &skx_uncore_iio_format_group, 5018}; 5019 5020enum { 5021 SNR_PCI_UNCORE_M2M, 5022 SNR_PCI_UNCORE_PCIE3, 5023}; 5024 5025static struct intel_uncore_type *snr_pci_uncores[] = { 5026 [SNR_PCI_UNCORE_M2M] = &snr_uncore_m2m, 5027 [SNR_PCI_UNCORE_PCIE3] = &snr_uncore_pcie3, 5028 NULL, 5029}; 5030 5031static const struct pci_device_id snr_uncore_pci_ids[] = { 5032 { /* M2M */ 5033 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a), 5034 .driver_data = UNCORE_PCI_DEV_FULL_DATA(12, 0, SNR_PCI_UNCORE_M2M, 0), 5035 }, 5036 { /* end: all zeroes */ } 5037}; 5038 5039static struct pci_driver snr_uncore_pci_driver = { 5040 .name = "snr_uncore", 5041 .id_table = snr_uncore_pci_ids, 5042}; 5043 5044static const struct pci_device_id snr_uncore_pci_sub_ids[] = { 5045 { /* PCIe3 RP */ 5046 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x334a), 5047 .driver_data = UNCORE_PCI_DEV_FULL_DATA(4, 0, SNR_PCI_UNCORE_PCIE3, 0), 5048 }, 5049 { /* end: all zeroes */ } 5050}; 5051 5052static struct pci_driver snr_uncore_pci_sub_driver = { 5053 .name = "snr_uncore_sub", 5054 .id_table = snr_uncore_pci_sub_ids, 5055}; 5056 5057int snr_uncore_pci_init(void) 5058{ 5059 /* SNR UBOX DID */ 5060 int ret = snbep_pci2phy_map_init(0x3460, SKX_CPUNODEID, 5061 SKX_GIDNIDMAP, true); 5062 5063 if (ret) 5064 return ret; 5065 5066 uncore_pci_uncores = snr_pci_uncores; 5067 uncore_pci_driver = &snr_uncore_pci_driver; 5068 uncore_pci_sub_driver = &snr_uncore_pci_sub_driver; 5069 return 0; 5070} 5071 5072#define SNR_MC_DEVICE_ID 0x3451 5073 5074static struct pci_dev *snr_uncore_get_mc_dev(unsigned int device, int id) 5075{ 5076 struct pci_dev *mc_dev = NULL; 5077 int pkg; 5078 5079 while (1) { 5080 mc_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, mc_dev); 5081 if (!mc_dev) 5082 break; 5083 pkg = uncore_pcibus_to_dieid(mc_dev->bus); 5084 if (pkg == id) 5085 break; 5086 } 5087 return mc_dev; 5088} 5089 5090static int snr_uncore_mmio_map(struct intel_uncore_box *box, 5091 unsigned int box_ctl, int mem_offset, 5092 unsigned int device) 5093{ 5094 struct pci_dev *pdev = snr_uncore_get_mc_dev(device, box->dieid); 5095 struct intel_uncore_type *type = box->pmu->type; 5096 resource_size_t addr; 5097 u32 pci_dword; 5098 5099 if (!pdev) 5100 return -ENODEV; 5101 5102 pci_read_config_dword(pdev, SNR_IMC_MMIO_BASE_OFFSET, &pci_dword); 5103 addr = ((resource_size_t)pci_dword & SNR_IMC_MMIO_BASE_MASK) << 23; 5104 5105 pci_read_config_dword(pdev, mem_offset, &pci_dword); 5106 addr |= (pci_dword & SNR_IMC_MMIO_MEM0_MASK) << 12; 5107 5108 addr += box_ctl; 5109 5110 pci_dev_put(pdev); 5111 5112 box->io_addr = ioremap(addr, type->mmio_map_size); 5113 if (!box->io_addr) { 5114 pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name); 5115 return -EINVAL; 5116 } 5117 5118 return 0; 5119} 5120 5121static void __snr_uncore_mmio_init_box(struct intel_uncore_box *box, 5122 unsigned int box_ctl, int mem_offset, 5123 unsigned int device) 5124{ 5125 if (!snr_uncore_mmio_map(box, box_ctl, mem_offset, device)) 5126 writel(IVBEP_PMON_BOX_CTL_INT, box->io_addr); 5127} 5128 5129static void snr_uncore_mmio_init_box(struct intel_uncore_box *box) 5130{ 5131 __snr_uncore_mmio_init_box(box, uncore_mmio_box_ctl(box), 5132 SNR_IMC_MMIO_MEM0_OFFSET, 5133 SNR_MC_DEVICE_ID); 5134} 5135 5136static void snr_uncore_mmio_disable_box(struct intel_uncore_box *box) 5137{ 5138 u32 config; 5139 5140 if (!box->io_addr) 5141 return; 5142 5143 config = readl(box->io_addr); 5144 config |= SNBEP_PMON_BOX_CTL_FRZ; 5145 writel(config, box->io_addr); 5146} 5147 5148static void snr_uncore_mmio_enable_box(struct intel_uncore_box *box) 5149{ 5150 u32 config; 5151 5152 if (!box->io_addr) 5153 return; 5154 5155 config = readl(box->io_addr); 5156 config &= ~SNBEP_PMON_BOX_CTL_FRZ; 5157 writel(config, box->io_addr); 5158} 5159 5160static void snr_uncore_mmio_enable_event(struct intel_uncore_box *box, 5161 struct perf_event *event) 5162{ 5163 struct hw_perf_event *hwc = &event->hw; 5164 5165 if (!box->io_addr) 5166 return; 5167 5168 if (!uncore_mmio_is_valid_offset(box, hwc->config_base)) 5169 return; 5170 5171 writel(hwc->config | SNBEP_PMON_CTL_EN, 5172 box->io_addr + hwc->config_base); 5173} 5174 5175static void snr_uncore_mmio_disable_event(struct intel_uncore_box *box, 5176 struct perf_event *event) 5177{ 5178 struct hw_perf_event *hwc = &event->hw; 5179 5180 if (!box->io_addr) 5181 return; 5182 5183 if (!uncore_mmio_is_valid_offset(box, hwc->config_base)) 5184 return; 5185 5186 writel(hwc->config, box->io_addr + hwc->config_base); 5187} 5188 5189static struct intel_uncore_ops snr_uncore_mmio_ops = { 5190 .init_box = snr_uncore_mmio_init_box, 5191 .exit_box = uncore_mmio_exit_box, 5192 .disable_box = snr_uncore_mmio_disable_box, 5193 .enable_box = snr_uncore_mmio_enable_box, 5194 .disable_event = snr_uncore_mmio_disable_event, 5195 .enable_event = snr_uncore_mmio_enable_event, 5196 .read_counter = uncore_mmio_read_counter, 5197}; 5198 5199static struct uncore_event_desc snr_uncore_imc_events[] = { 5200 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x00,umask=0x00"), 5201 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x0f"), 5202 INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"), 5203 INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"), 5204 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x30"), 5205 INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"), 5206 INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"), 5207 { /* end: all zeroes */ }, 5208}; 5209 5210static struct intel_uncore_type snr_uncore_imc = { 5211 .name = "imc", 5212 .num_counters = 4, 5213 .num_boxes = 2, 5214 .perf_ctr_bits = 48, 5215 .fixed_ctr_bits = 48, 5216 .fixed_ctr = SNR_IMC_MMIO_PMON_FIXED_CTR, 5217 .fixed_ctl = SNR_IMC_MMIO_PMON_FIXED_CTL, 5218 .event_descs = snr_uncore_imc_events, 5219 .perf_ctr = SNR_IMC_MMIO_PMON_CTR0, 5220 .event_ctl = SNR_IMC_MMIO_PMON_CTL0, 5221 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 5222 .box_ctl = SNR_IMC_MMIO_PMON_BOX_CTL, 5223 .mmio_offset = SNR_IMC_MMIO_OFFSET, 5224 .mmio_map_size = SNR_IMC_MMIO_SIZE, 5225 .ops = &snr_uncore_mmio_ops, 5226 .format_group = &skx_uncore_format_group, 5227}; 5228 5229enum perf_uncore_snr_imc_freerunning_type_id { 5230 SNR_IMC_DCLK, 5231 SNR_IMC_DDR, 5232 5233 SNR_IMC_FREERUNNING_TYPE_MAX, 5234}; 5235 5236static struct freerunning_counters snr_imc_freerunning[] = { 5237 [SNR_IMC_DCLK] = { 0x22b0, 0x0, 0, 1, 48 }, 5238 [SNR_IMC_DDR] = { 0x2290, 0x8, 0, 2, 48 }, 5239}; 5240 5241static struct uncore_event_desc snr_uncore_imc_freerunning_events[] = { 5242 INTEL_UNCORE_EVENT_DESC(dclk, "event=0xff,umask=0x10"), 5243 5244 INTEL_UNCORE_EVENT_DESC(read, "event=0xff,umask=0x20"), 5245 INTEL_UNCORE_EVENT_DESC(read.scale, "6.103515625e-5"), 5246 INTEL_UNCORE_EVENT_DESC(read.unit, "MiB"), 5247 INTEL_UNCORE_EVENT_DESC(write, "event=0xff,umask=0x21"), 5248 INTEL_UNCORE_EVENT_DESC(write.scale, "6.103515625e-5"), 5249 INTEL_UNCORE_EVENT_DESC(write.unit, "MiB"), 5250 { /* end: all zeroes */ }, 5251}; 5252 5253static struct intel_uncore_ops snr_uncore_imc_freerunning_ops = { 5254 .init_box = snr_uncore_mmio_init_box, 5255 .exit_box = uncore_mmio_exit_box, 5256 .read_counter = uncore_mmio_read_counter, 5257 .hw_config = uncore_freerunning_hw_config, 5258}; 5259 5260static struct intel_uncore_type snr_uncore_imc_free_running = { 5261 .name = "imc_free_running", 5262 .num_counters = 3, 5263 .num_boxes = 1, 5264 .num_freerunning_types = SNR_IMC_FREERUNNING_TYPE_MAX, 5265 .mmio_map_size = SNR_IMC_MMIO_SIZE, 5266 .freerunning = snr_imc_freerunning, 5267 .ops = &snr_uncore_imc_freerunning_ops, 5268 .event_descs = snr_uncore_imc_freerunning_events, 5269 .format_group = &skx_uncore_iio_freerunning_format_group, 5270}; 5271 5272static struct intel_uncore_type *snr_mmio_uncores[] = { 5273 &snr_uncore_imc, 5274 &snr_uncore_imc_free_running, 5275 NULL, 5276}; 5277 5278void snr_uncore_mmio_init(void) 5279{ 5280 uncore_mmio_uncores = snr_mmio_uncores; 5281} 5282 5283/* end of SNR uncore support */ 5284 5285/* ICX uncore support */ 5286 5287static u64 icx_cha_msr_offsets[] = { 5288 0x2a0, 0x2ae, 0x2bc, 0x2ca, 0x2d8, 0x2e6, 0x2f4, 0x302, 0x310, 5289 0x31e, 0x32c, 0x33a, 0x348, 0x356, 0x364, 0x372, 0x380, 0x38e, 5290 0x3aa, 0x3b8, 0x3c6, 0x3d4, 0x3e2, 0x3f0, 0x3fe, 0x40c, 0x41a, 5291 0x428, 0x436, 0x444, 0x452, 0x460, 0x46e, 0x47c, 0x0, 0xe, 5292 0x1c, 0x2a, 0x38, 0x46, 5293}; 5294 5295static int icx_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event) 5296{ 5297 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 5298 bool tie_en = !!(event->hw.config & SNBEP_CBO_PMON_CTL_TID_EN); 5299 5300 if (tie_en) { 5301 reg1->reg = ICX_C34_MSR_PMON_BOX_FILTER0 + 5302 icx_cha_msr_offsets[box->pmu->pmu_idx]; 5303 reg1->config = event->attr.config1 & SKX_CHA_MSR_PMON_BOX_FILTER_TID; 5304 reg1->idx = 0; 5305 } 5306 5307 return 0; 5308} 5309 5310static struct intel_uncore_ops icx_uncore_chabox_ops = { 5311 .init_box = ivbep_uncore_msr_init_box, 5312 .disable_box = snbep_uncore_msr_disable_box, 5313 .enable_box = snbep_uncore_msr_enable_box, 5314 .disable_event = snbep_uncore_msr_disable_event, 5315 .enable_event = snr_cha_enable_event, 5316 .read_counter = uncore_msr_read_counter, 5317 .hw_config = icx_cha_hw_config, 5318}; 5319 5320static struct intel_uncore_type icx_uncore_chabox = { 5321 .name = "cha", 5322 .num_counters = 4, 5323 .perf_ctr_bits = 48, 5324 .event_ctl = ICX_C34_MSR_PMON_CTL0, 5325 .perf_ctr = ICX_C34_MSR_PMON_CTR0, 5326 .box_ctl = ICX_C34_MSR_PMON_BOX_CTL, 5327 .msr_offsets = icx_cha_msr_offsets, 5328 .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK, 5329 .event_mask_ext = SNR_CHA_RAW_EVENT_MASK_EXT, 5330 .constraints = skx_uncore_chabox_constraints, 5331 .ops = &icx_uncore_chabox_ops, 5332 .format_group = &snr_uncore_chabox_format_group, 5333}; 5334 5335static u64 icx_msr_offsets[] = { 5336 0x0, 0x20, 0x40, 0x90, 0xb0, 0xd0, 5337}; 5338 5339static struct event_constraint icx_uncore_iio_constraints[] = { 5340 UNCORE_EVENT_CONSTRAINT(0x02, 0x3), 5341 UNCORE_EVENT_CONSTRAINT(0x03, 0x3), 5342 UNCORE_EVENT_CONSTRAINT(0x83, 0x3), 5343 UNCORE_EVENT_CONSTRAINT(0x88, 0xc), 5344 UNCORE_EVENT_CONSTRAINT(0xc0, 0xc), 5345 UNCORE_EVENT_CONSTRAINT(0xc5, 0xc), 5346 UNCORE_EVENT_CONSTRAINT(0xd5, 0xc), 5347 EVENT_CONSTRAINT_END 5348}; 5349 5350static umode_t 5351icx_iio_mapping_visible(struct kobject *kobj, struct attribute *attr, int die) 5352{ 5353 /* Root bus 0x00 is valid only for pmu_idx = 5. */ 5354 return pmu_iio_mapping_visible(kobj, attr, die, 5); 5355} 5356 5357static struct attribute_group icx_iio_mapping_group = { 5358 .is_visible = icx_iio_mapping_visible, 5359}; 5360 5361static const struct attribute_group *icx_iio_attr_update[] = { 5362 &icx_iio_mapping_group, 5363 NULL, 5364}; 5365 5366/* 5367 * ICX has a static mapping of stack IDs from SAD_CONTROL_CFG notation to PMON 5368 */ 5369enum { 5370 ICX_PCIE1_PMON_ID, 5371 ICX_PCIE2_PMON_ID, 5372 ICX_PCIE3_PMON_ID, 5373 ICX_PCIE4_PMON_ID, 5374 ICX_PCIE5_PMON_ID, 5375 ICX_CBDMA_DMI_PMON_ID 5376}; 5377 5378static u8 icx_sad_pmon_mapping[] = { 5379 ICX_CBDMA_DMI_PMON_ID, 5380 ICX_PCIE1_PMON_ID, 5381 ICX_PCIE2_PMON_ID, 5382 ICX_PCIE3_PMON_ID, 5383 ICX_PCIE4_PMON_ID, 5384 ICX_PCIE5_PMON_ID, 5385}; 5386 5387static int icx_iio_get_topology(struct intel_uncore_type *type) 5388{ 5389 return sad_cfg_iio_topology(type, icx_sad_pmon_mapping); 5390} 5391 5392static void icx_iio_set_mapping(struct intel_uncore_type *type) 5393{ 5394 /* Detect ICX-D system. This case is not supported */ 5395 if (boot_cpu_data.x86_vfm == INTEL_ICELAKE_D) { 5396 pmu_clear_mapping_attr(type->attr_update, &icx_iio_mapping_group); 5397 return; 5398 } 5399 pmu_iio_set_mapping(type, &icx_iio_mapping_group); 5400} 5401 5402static void icx_iio_cleanup_mapping(struct intel_uncore_type *type) 5403{ 5404 pmu_cleanup_mapping(type, &icx_iio_mapping_group); 5405} 5406 5407static struct intel_uncore_type icx_uncore_iio = { 5408 .name = "iio", 5409 .num_counters = 4, 5410 .num_boxes = 6, 5411 .perf_ctr_bits = 48, 5412 .event_ctl = ICX_IIO_MSR_PMON_CTL0, 5413 .perf_ctr = ICX_IIO_MSR_PMON_CTR0, 5414 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 5415 .event_mask_ext = SNR_IIO_PMON_RAW_EVENT_MASK_EXT, 5416 .box_ctl = ICX_IIO_MSR_PMON_BOX_CTL, 5417 .msr_offsets = icx_msr_offsets, 5418 .constraints = icx_uncore_iio_constraints, 5419 .ops = &skx_uncore_iio_ops, 5420 .format_group = &snr_uncore_iio_format_group, 5421 .attr_update = icx_iio_attr_update, 5422 .get_topology = icx_iio_get_topology, 5423 .set_mapping = icx_iio_set_mapping, 5424 .cleanup_mapping = icx_iio_cleanup_mapping, 5425}; 5426 5427static struct intel_uncore_type icx_uncore_irp = { 5428 .name = "irp", 5429 .num_counters = 2, 5430 .num_boxes = 6, 5431 .perf_ctr_bits = 48, 5432 .event_ctl = ICX_IRP0_MSR_PMON_CTL0, 5433 .perf_ctr = ICX_IRP0_MSR_PMON_CTR0, 5434 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 5435 .box_ctl = ICX_IRP0_MSR_PMON_BOX_CTL, 5436 .msr_offsets = icx_msr_offsets, 5437 .ops = &ivbep_uncore_msr_ops, 5438 .format_group = &ivbep_uncore_format_group, 5439}; 5440 5441static struct event_constraint icx_uncore_m2pcie_constraints[] = { 5442 UNCORE_EVENT_CONSTRAINT(0x14, 0x3), 5443 UNCORE_EVENT_CONSTRAINT(0x23, 0x3), 5444 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 5445 EVENT_CONSTRAINT_END 5446}; 5447 5448static struct intel_uncore_type icx_uncore_m2pcie = { 5449 .name = "m2pcie", 5450 .num_counters = 4, 5451 .num_boxes = 6, 5452 .perf_ctr_bits = 48, 5453 .event_ctl = ICX_M2PCIE_MSR_PMON_CTL0, 5454 .perf_ctr = ICX_M2PCIE_MSR_PMON_CTR0, 5455 .box_ctl = ICX_M2PCIE_MSR_PMON_BOX_CTL, 5456 .msr_offsets = icx_msr_offsets, 5457 .constraints = icx_uncore_m2pcie_constraints, 5458 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 5459 .ops = &ivbep_uncore_msr_ops, 5460 .format_group = &ivbep_uncore_format_group, 5461}; 5462 5463enum perf_uncore_icx_iio_freerunning_type_id { 5464 ICX_IIO_MSR_IOCLK, 5465 ICX_IIO_MSR_BW_IN, 5466 5467 ICX_IIO_FREERUNNING_TYPE_MAX, 5468}; 5469 5470static unsigned icx_iio_clk_freerunning_box_offsets[] = { 5471 0x0, 0x20, 0x40, 0x90, 0xb0, 0xd0, 5472}; 5473 5474static unsigned icx_iio_bw_freerunning_box_offsets[] = { 5475 0x0, 0x10, 0x20, 0x90, 0xa0, 0xb0, 5476}; 5477 5478static struct freerunning_counters icx_iio_freerunning[] = { 5479 [ICX_IIO_MSR_IOCLK] = { 0xa55, 0x1, 0x20, 1, 48, icx_iio_clk_freerunning_box_offsets }, 5480 [ICX_IIO_MSR_BW_IN] = { 0xaa0, 0x1, 0x10, 8, 48, icx_iio_bw_freerunning_box_offsets }, 5481}; 5482 5483static struct intel_uncore_type icx_uncore_iio_free_running = { 5484 .name = "iio_free_running", 5485 .num_counters = 9, 5486 .num_boxes = 6, 5487 .num_freerunning_types = ICX_IIO_FREERUNNING_TYPE_MAX, 5488 .freerunning = icx_iio_freerunning, 5489 .ops = &skx_uncore_iio_freerunning_ops, 5490 .event_descs = snr_uncore_iio_freerunning_events, 5491 .format_group = &skx_uncore_iio_freerunning_format_group, 5492}; 5493 5494static struct intel_uncore_type *icx_msr_uncores[] = { 5495 &skx_uncore_ubox, 5496 &icx_uncore_chabox, 5497 &icx_uncore_iio, 5498 &icx_uncore_irp, 5499 &icx_uncore_m2pcie, 5500 &skx_uncore_pcu, 5501 &icx_uncore_iio_free_running, 5502 NULL, 5503}; 5504 5505/* 5506 * To determine the number of CHAs, it should read CAPID6(Low) and CAPID7 (High) 5507 * registers which located at Device 30, Function 3 5508 */ 5509#define ICX_CAPID6 0x9c 5510#define ICX_CAPID7 0xa0 5511 5512static u64 icx_count_chabox(void) 5513{ 5514 struct pci_dev *dev = NULL; 5515 u64 caps = 0; 5516 5517 dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x345b, dev); 5518 if (!dev) 5519 goto out; 5520 5521 pci_read_config_dword(dev, ICX_CAPID6, (u32 *)&caps); 5522 pci_read_config_dword(dev, ICX_CAPID7, (u32 *)&caps + 1); 5523out: 5524 pci_dev_put(dev); 5525 return hweight64(caps); 5526} 5527 5528void icx_uncore_cpu_init(void) 5529{ 5530 u64 num_boxes = icx_count_chabox(); 5531 5532 if (WARN_ON(num_boxes > ARRAY_SIZE(icx_cha_msr_offsets))) 5533 return; 5534 icx_uncore_chabox.num_boxes = num_boxes; 5535 uncore_msr_uncores = icx_msr_uncores; 5536} 5537 5538static struct intel_uncore_type icx_uncore_m2m = { 5539 .name = "m2m", 5540 .num_counters = 4, 5541 .num_boxes = 4, 5542 .perf_ctr_bits = 48, 5543 .perf_ctr = SNR_M2M_PCI_PMON_CTR0, 5544 .event_ctl = SNR_M2M_PCI_PMON_CTL0, 5545 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 5546 .event_mask_ext = SNR_M2M_PCI_PMON_UMASK_EXT, 5547 .box_ctl = SNR_M2M_PCI_PMON_BOX_CTL, 5548 .ops = &snr_m2m_uncore_pci_ops, 5549 .format_group = &snr_m2m_uncore_format_group, 5550}; 5551 5552static struct attribute *icx_upi_uncore_formats_attr[] = { 5553 &format_attr_event.attr, 5554 &format_attr_umask_ext4.attr, 5555 &format_attr_edge.attr, 5556 &format_attr_inv.attr, 5557 &format_attr_thresh8.attr, 5558 NULL, 5559}; 5560 5561static const struct attribute_group icx_upi_uncore_format_group = { 5562 .name = "format", 5563 .attrs = icx_upi_uncore_formats_attr, 5564}; 5565 5566#define ICX_UPI_REGS_ADDR_DEVICE_LINK0 0x02 5567#define ICX_UPI_REGS_ADDR_FUNCTION 0x01 5568 5569static int discover_upi_topology(struct intel_uncore_type *type, int ubox_did, int dev_link0) 5570{ 5571 struct pci_dev *ubox = NULL; 5572 struct pci_dev *dev = NULL; 5573 u32 nid, gid; 5574 int idx, lgc_pkg, ret = -EPERM; 5575 struct intel_uncore_topology *upi; 5576 unsigned int devfn; 5577 5578 /* GIDNIDMAP method supports machines which have less than 8 sockets. */ 5579 if (uncore_max_dies() > 8) 5580 goto err; 5581 5582 while ((ubox = pci_get_device(PCI_VENDOR_ID_INTEL, ubox_did, ubox))) { 5583 ret = upi_nodeid_groupid(ubox, SKX_CPUNODEID, SKX_GIDNIDMAP, &nid, &gid); 5584 if (ret) { 5585 ret = pcibios_err_to_errno(ret); 5586 break; 5587 } 5588 5589 lgc_pkg = topology_gidnid_map(nid, gid); 5590 if (lgc_pkg < 0) { 5591 ret = -EPERM; 5592 goto err; 5593 } 5594 for (idx = 0; idx < type->num_boxes; idx++) { 5595 upi = &type->topology[lgc_pkg][idx]; 5596 devfn = PCI_DEVFN(dev_link0 + idx, ICX_UPI_REGS_ADDR_FUNCTION); 5597 dev = pci_get_domain_bus_and_slot(pci_domain_nr(ubox->bus), 5598 ubox->bus->number, 5599 devfn); 5600 if (dev) { 5601 ret = upi_fill_topology(dev, upi, idx); 5602 if (ret) 5603 goto err; 5604 } 5605 } 5606 } 5607err: 5608 pci_dev_put(ubox); 5609 pci_dev_put(dev); 5610 return ret; 5611} 5612 5613static int icx_upi_get_topology(struct intel_uncore_type *type) 5614{ 5615 return discover_upi_topology(type, ICX_UBOX_DID, ICX_UPI_REGS_ADDR_DEVICE_LINK0); 5616} 5617 5618static struct attribute_group icx_upi_mapping_group = { 5619 .is_visible = skx_upi_mapping_visible, 5620}; 5621 5622static const struct attribute_group *icx_upi_attr_update[] = { 5623 &icx_upi_mapping_group, 5624 NULL 5625}; 5626 5627static void icx_upi_set_mapping(struct intel_uncore_type *type) 5628{ 5629 pmu_upi_set_mapping(type, &icx_upi_mapping_group); 5630} 5631 5632static void icx_upi_cleanup_mapping(struct intel_uncore_type *type) 5633{ 5634 pmu_cleanup_mapping(type, &icx_upi_mapping_group); 5635} 5636 5637static struct intel_uncore_type icx_uncore_upi = { 5638 .name = "upi", 5639 .num_counters = 4, 5640 .num_boxes = 3, 5641 .perf_ctr_bits = 48, 5642 .perf_ctr = ICX_UPI_PCI_PMON_CTR0, 5643 .event_ctl = ICX_UPI_PCI_PMON_CTL0, 5644 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 5645 .event_mask_ext = ICX_UPI_CTL_UMASK_EXT, 5646 .box_ctl = ICX_UPI_PCI_PMON_BOX_CTL, 5647 .ops = &skx_upi_uncore_pci_ops, 5648 .format_group = &icx_upi_uncore_format_group, 5649 .attr_update = icx_upi_attr_update, 5650 .get_topology = icx_upi_get_topology, 5651 .set_mapping = icx_upi_set_mapping, 5652 .cleanup_mapping = icx_upi_cleanup_mapping, 5653}; 5654 5655static struct event_constraint icx_uncore_m3upi_constraints[] = { 5656 UNCORE_EVENT_CONSTRAINT(0x1c, 0x1), 5657 UNCORE_EVENT_CONSTRAINT(0x1d, 0x1), 5658 UNCORE_EVENT_CONSTRAINT(0x1e, 0x1), 5659 UNCORE_EVENT_CONSTRAINT(0x1f, 0x1), 5660 UNCORE_EVENT_CONSTRAINT(0x40, 0x7), 5661 UNCORE_EVENT_CONSTRAINT(0x4e, 0x7), 5662 UNCORE_EVENT_CONSTRAINT(0x4f, 0x7), 5663 UNCORE_EVENT_CONSTRAINT(0x50, 0x7), 5664 EVENT_CONSTRAINT_END 5665}; 5666 5667static struct intel_uncore_type icx_uncore_m3upi = { 5668 .name = "m3upi", 5669 .num_counters = 4, 5670 .num_boxes = 3, 5671 .perf_ctr_bits = 48, 5672 .perf_ctr = ICX_M3UPI_PCI_PMON_CTR0, 5673 .event_ctl = ICX_M3UPI_PCI_PMON_CTL0, 5674 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 5675 .box_ctl = ICX_M3UPI_PCI_PMON_BOX_CTL, 5676 .constraints = icx_uncore_m3upi_constraints, 5677 .ops = &ivbep_uncore_pci_ops, 5678 .format_group = &skx_uncore_format_group, 5679}; 5680 5681enum { 5682 ICX_PCI_UNCORE_M2M, 5683 ICX_PCI_UNCORE_UPI, 5684 ICX_PCI_UNCORE_M3UPI, 5685}; 5686 5687static struct intel_uncore_type *icx_pci_uncores[] = { 5688 [ICX_PCI_UNCORE_M2M] = &icx_uncore_m2m, 5689 [ICX_PCI_UNCORE_UPI] = &icx_uncore_upi, 5690 [ICX_PCI_UNCORE_M3UPI] = &icx_uncore_m3upi, 5691 NULL, 5692}; 5693 5694static const struct pci_device_id icx_uncore_pci_ids[] = { 5695 { /* M2M 0 */ 5696 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a), 5697 .driver_data = UNCORE_PCI_DEV_FULL_DATA(12, 0, ICX_PCI_UNCORE_M2M, 0), 5698 }, 5699 { /* M2M 1 */ 5700 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a), 5701 .driver_data = UNCORE_PCI_DEV_FULL_DATA(13, 0, ICX_PCI_UNCORE_M2M, 1), 5702 }, 5703 { /* M2M 2 */ 5704 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a), 5705 .driver_data = UNCORE_PCI_DEV_FULL_DATA(14, 0, ICX_PCI_UNCORE_M2M, 2), 5706 }, 5707 { /* M2M 3 */ 5708 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a), 5709 .driver_data = UNCORE_PCI_DEV_FULL_DATA(15, 0, ICX_PCI_UNCORE_M2M, 3), 5710 }, 5711 { /* UPI Link 0 */ 5712 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3441), 5713 .driver_data = UNCORE_PCI_DEV_FULL_DATA(2, 1, ICX_PCI_UNCORE_UPI, 0), 5714 }, 5715 { /* UPI Link 1 */ 5716 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3441), 5717 .driver_data = UNCORE_PCI_DEV_FULL_DATA(3, 1, ICX_PCI_UNCORE_UPI, 1), 5718 }, 5719 { /* UPI Link 2 */ 5720 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3441), 5721 .driver_data = UNCORE_PCI_DEV_FULL_DATA(4, 1, ICX_PCI_UNCORE_UPI, 2), 5722 }, 5723 { /* M3UPI Link 0 */ 5724 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3446), 5725 .driver_data = UNCORE_PCI_DEV_FULL_DATA(5, 1, ICX_PCI_UNCORE_M3UPI, 0), 5726 }, 5727 { /* M3UPI Link 1 */ 5728 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3446), 5729 .driver_data = UNCORE_PCI_DEV_FULL_DATA(6, 1, ICX_PCI_UNCORE_M3UPI, 1), 5730 }, 5731 { /* M3UPI Link 2 */ 5732 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3446), 5733 .driver_data = UNCORE_PCI_DEV_FULL_DATA(7, 1, ICX_PCI_UNCORE_M3UPI, 2), 5734 }, 5735 { /* end: all zeroes */ } 5736}; 5737 5738static struct pci_driver icx_uncore_pci_driver = { 5739 .name = "icx_uncore", 5740 .id_table = icx_uncore_pci_ids, 5741}; 5742 5743int icx_uncore_pci_init(void) 5744{ 5745 /* ICX UBOX DID */ 5746 int ret = snbep_pci2phy_map_init(0x3450, SKX_CPUNODEID, 5747 SKX_GIDNIDMAP, true); 5748 5749 if (ret) 5750 return ret; 5751 5752 uncore_pci_uncores = icx_pci_uncores; 5753 uncore_pci_driver = &icx_uncore_pci_driver; 5754 return 0; 5755} 5756 5757static void icx_uncore_imc_init_box(struct intel_uncore_box *box) 5758{ 5759 unsigned int box_ctl = box->pmu->type->box_ctl + 5760 box->pmu->type->mmio_offset * (box->pmu->pmu_idx % ICX_NUMBER_IMC_CHN); 5761 int mem_offset = (box->pmu->pmu_idx / ICX_NUMBER_IMC_CHN) * ICX_IMC_MEM_STRIDE + 5762 SNR_IMC_MMIO_MEM0_OFFSET; 5763 5764 __snr_uncore_mmio_init_box(box, box_ctl, mem_offset, 5765 SNR_MC_DEVICE_ID); 5766} 5767 5768static struct intel_uncore_ops icx_uncore_mmio_ops = { 5769 .init_box = icx_uncore_imc_init_box, 5770 .exit_box = uncore_mmio_exit_box, 5771 .disable_box = snr_uncore_mmio_disable_box, 5772 .enable_box = snr_uncore_mmio_enable_box, 5773 .disable_event = snr_uncore_mmio_disable_event, 5774 .enable_event = snr_uncore_mmio_enable_event, 5775 .read_counter = uncore_mmio_read_counter, 5776}; 5777 5778static struct intel_uncore_type icx_uncore_imc = { 5779 .name = "imc", 5780 .num_counters = 4, 5781 .num_boxes = 12, 5782 .perf_ctr_bits = 48, 5783 .fixed_ctr_bits = 48, 5784 .fixed_ctr = SNR_IMC_MMIO_PMON_FIXED_CTR, 5785 .fixed_ctl = SNR_IMC_MMIO_PMON_FIXED_CTL, 5786 .event_descs = snr_uncore_imc_events, 5787 .perf_ctr = SNR_IMC_MMIO_PMON_CTR0, 5788 .event_ctl = SNR_IMC_MMIO_PMON_CTL0, 5789 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 5790 .box_ctl = SNR_IMC_MMIO_PMON_BOX_CTL, 5791 .mmio_offset = SNR_IMC_MMIO_OFFSET, 5792 .mmio_map_size = SNR_IMC_MMIO_SIZE, 5793 .ops = &icx_uncore_mmio_ops, 5794 .format_group = &skx_uncore_format_group, 5795}; 5796 5797enum perf_uncore_icx_imc_freerunning_type_id { 5798 ICX_IMC_DCLK, 5799 ICX_IMC_DDR, 5800 ICX_IMC_DDRT, 5801 5802 ICX_IMC_FREERUNNING_TYPE_MAX, 5803}; 5804 5805static struct freerunning_counters icx_imc_freerunning[] = { 5806 [ICX_IMC_DCLK] = { 0x22b0, 0x0, 0, 1, 48 }, 5807 [ICX_IMC_DDR] = { 0x2290, 0x8, 0, 2, 48 }, 5808 [ICX_IMC_DDRT] = { 0x22a0, 0x8, 0, 2, 48 }, 5809}; 5810 5811static struct uncore_event_desc icx_uncore_imc_freerunning_events[] = { 5812 INTEL_UNCORE_EVENT_DESC(dclk, "event=0xff,umask=0x10"), 5813 5814 INTEL_UNCORE_EVENT_DESC(read, "event=0xff,umask=0x20"), 5815 INTEL_UNCORE_EVENT_DESC(read.scale, "6.103515625e-5"), 5816 INTEL_UNCORE_EVENT_DESC(read.unit, "MiB"), 5817 INTEL_UNCORE_EVENT_DESC(write, "event=0xff,umask=0x21"), 5818 INTEL_UNCORE_EVENT_DESC(write.scale, "6.103515625e-5"), 5819 INTEL_UNCORE_EVENT_DESC(write.unit, "MiB"), 5820 5821 INTEL_UNCORE_EVENT_DESC(ddrt_read, "event=0xff,umask=0x30"), 5822 INTEL_UNCORE_EVENT_DESC(ddrt_read.scale, "6.103515625e-5"), 5823 INTEL_UNCORE_EVENT_DESC(ddrt_read.unit, "MiB"), 5824 INTEL_UNCORE_EVENT_DESC(ddrt_write, "event=0xff,umask=0x31"), 5825 INTEL_UNCORE_EVENT_DESC(ddrt_write.scale, "6.103515625e-5"), 5826 INTEL_UNCORE_EVENT_DESC(ddrt_write.unit, "MiB"), 5827 { /* end: all zeroes */ }, 5828}; 5829 5830static void icx_uncore_imc_freerunning_init_box(struct intel_uncore_box *box) 5831{ 5832 int mem_offset = box->pmu->pmu_idx * ICX_IMC_MEM_STRIDE + 5833 SNR_IMC_MMIO_MEM0_OFFSET; 5834 5835 snr_uncore_mmio_map(box, uncore_mmio_box_ctl(box), 5836 mem_offset, SNR_MC_DEVICE_ID); 5837} 5838 5839static struct intel_uncore_ops icx_uncore_imc_freerunning_ops = { 5840 .init_box = icx_uncore_imc_freerunning_init_box, 5841 .exit_box = uncore_mmio_exit_box, 5842 .read_counter = uncore_mmio_read_counter, 5843 .hw_config = uncore_freerunning_hw_config, 5844}; 5845 5846static struct intel_uncore_type icx_uncore_imc_free_running = { 5847 .name = "imc_free_running", 5848 .num_counters = 5, 5849 .num_boxes = 4, 5850 .num_freerunning_types = ICX_IMC_FREERUNNING_TYPE_MAX, 5851 .mmio_map_size = SNR_IMC_MMIO_SIZE, 5852 .freerunning = icx_imc_freerunning, 5853 .ops = &icx_uncore_imc_freerunning_ops, 5854 .event_descs = icx_uncore_imc_freerunning_events, 5855 .format_group = &skx_uncore_iio_freerunning_format_group, 5856}; 5857 5858static struct intel_uncore_type *icx_mmio_uncores[] = { 5859 &icx_uncore_imc, 5860 &icx_uncore_imc_free_running, 5861 NULL, 5862}; 5863 5864void icx_uncore_mmio_init(void) 5865{ 5866 uncore_mmio_uncores = icx_mmio_uncores; 5867} 5868 5869/* end of ICX uncore support */ 5870 5871/* SPR uncore support */ 5872 5873static void spr_uncore_msr_enable_event(struct intel_uncore_box *box, 5874 struct perf_event *event) 5875{ 5876 struct hw_perf_event *hwc = &event->hw; 5877 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 5878 5879 if (reg1->idx != EXTRA_REG_NONE) 5880 wrmsrq(reg1->reg, reg1->config); 5881 5882 wrmsrq(hwc->config_base, hwc->config); 5883} 5884 5885static void spr_uncore_msr_disable_event(struct intel_uncore_box *box, 5886 struct perf_event *event) 5887{ 5888 struct hw_perf_event *hwc = &event->hw; 5889 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 5890 5891 if (reg1->idx != EXTRA_REG_NONE) 5892 wrmsrq(reg1->reg, 0); 5893 5894 wrmsrq(hwc->config_base, 0); 5895} 5896 5897static int spr_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event) 5898{ 5899 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; 5900 bool tie_en = !!(event->hw.config & SPR_CHA_PMON_CTL_TID_EN); 5901 struct intel_uncore_type *type = box->pmu->type; 5902 int id = intel_uncore_find_discovery_unit_id(type->boxes, -1, box->pmu->pmu_idx); 5903 5904 if (tie_en) { 5905 reg1->reg = SPR_C0_MSR_PMON_BOX_FILTER0 + 5906 HSWEP_CBO_MSR_OFFSET * id; 5907 reg1->config = event->attr.config1 & SPR_CHA_PMON_BOX_FILTER_TID; 5908 reg1->idx = 0; 5909 } 5910 5911 return 0; 5912} 5913 5914static struct intel_uncore_ops spr_uncore_chabox_ops = { 5915 .init_box = intel_generic_uncore_msr_init_box, 5916 .disable_box = intel_generic_uncore_msr_disable_box, 5917 .enable_box = intel_generic_uncore_msr_enable_box, 5918 .disable_event = spr_uncore_msr_disable_event, 5919 .enable_event = spr_uncore_msr_enable_event, 5920 .read_counter = uncore_msr_read_counter, 5921 .hw_config = spr_cha_hw_config, 5922 .get_constraint = uncore_get_constraint, 5923 .put_constraint = uncore_put_constraint, 5924}; 5925 5926static struct attribute *spr_uncore_cha_formats_attr[] = { 5927 &format_attr_event.attr, 5928 &format_attr_umask_ext5.attr, 5929 &format_attr_tid_en2.attr, 5930 &format_attr_edge.attr, 5931 &format_attr_inv.attr, 5932 &format_attr_thresh8.attr, 5933 &format_attr_filter_tid5.attr, 5934 NULL, 5935}; 5936static const struct attribute_group spr_uncore_chabox_format_group = { 5937 .name = "format", 5938 .attrs = spr_uncore_cha_formats_attr, 5939}; 5940 5941static ssize_t alias_show(struct device *dev, 5942 struct device_attribute *attr, 5943 char *buf) 5944{ 5945 struct intel_uncore_pmu *pmu = dev_to_uncore_pmu(dev); 5946 char pmu_name[UNCORE_PMU_NAME_LEN]; 5947 5948 uncore_get_alias_name(pmu_name, pmu); 5949 return sysfs_emit(buf, "%s\n", pmu_name); 5950} 5951 5952static DEVICE_ATTR_RO(alias); 5953 5954static struct attribute *uncore_alias_attrs[] = { 5955 &dev_attr_alias.attr, 5956 NULL 5957}; 5958 5959ATTRIBUTE_GROUPS(uncore_alias); 5960 5961static struct intel_uncore_type spr_uncore_chabox = { 5962 .name = "cha", 5963 .event_mask = SPR_CHA_PMON_EVENT_MASK, 5964 .event_mask_ext = SPR_CHA_EVENT_MASK_EXT, 5965 .num_shared_regs = 1, 5966 .constraints = skx_uncore_chabox_constraints, 5967 .ops = &spr_uncore_chabox_ops, 5968 .format_group = &spr_uncore_chabox_format_group, 5969 .attr_update = uncore_alias_groups, 5970}; 5971 5972static struct intel_uncore_type spr_uncore_iio = { 5973 .name = "iio", 5974 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 5975 .event_mask_ext = SNR_IIO_PMON_RAW_EVENT_MASK_EXT, 5976 .format_group = &snr_uncore_iio_format_group, 5977 .attr_update = uncore_alias_groups, 5978 .constraints = icx_uncore_iio_constraints, 5979}; 5980 5981static struct attribute *spr_uncore_raw_formats_attr[] = { 5982 &format_attr_event.attr, 5983 &format_attr_umask_ext4.attr, 5984 &format_attr_edge.attr, 5985 &format_attr_inv.attr, 5986 &format_attr_thresh8.attr, 5987 NULL, 5988}; 5989 5990static const struct attribute_group spr_uncore_raw_format_group = { 5991 .name = "format", 5992 .attrs = spr_uncore_raw_formats_attr, 5993}; 5994 5995#define SPR_UNCORE_COMMON_FORMAT() \ 5996 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, \ 5997 .event_mask_ext = SPR_RAW_EVENT_MASK_EXT, \ 5998 .format_group = &spr_uncore_raw_format_group, \ 5999 .attr_update = uncore_alias_groups 6000 6001static struct intel_uncore_type spr_uncore_irp = { 6002 SPR_UNCORE_COMMON_FORMAT(), 6003 .name = "irp", 6004 6005}; 6006 6007static struct event_constraint spr_uncore_m2pcie_constraints[] = { 6008 UNCORE_EVENT_CONSTRAINT(0x14, 0x3), 6009 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), 6010 EVENT_CONSTRAINT_END 6011}; 6012 6013static struct intel_uncore_type spr_uncore_m2pcie = { 6014 SPR_UNCORE_COMMON_FORMAT(), 6015 .name = "m2pcie", 6016 .constraints = spr_uncore_m2pcie_constraints, 6017}; 6018 6019static struct intel_uncore_type spr_uncore_pcu = { 6020 .name = "pcu", 6021 .attr_update = uncore_alias_groups, 6022}; 6023 6024static void spr_uncore_mmio_enable_event(struct intel_uncore_box *box, 6025 struct perf_event *event) 6026{ 6027 struct hw_perf_event *hwc = &event->hw; 6028 6029 if (!box->io_addr) 6030 return; 6031 6032 if (uncore_pmc_fixed(hwc->idx)) 6033 writel(SNBEP_PMON_CTL_EN, box->io_addr + hwc->config_base); 6034 else 6035 writel(hwc->config, box->io_addr + hwc->config_base); 6036} 6037 6038static struct intel_uncore_ops spr_uncore_mmio_ops = { 6039 .init_box = intel_generic_uncore_mmio_init_box, 6040 .exit_box = uncore_mmio_exit_box, 6041 .disable_box = intel_generic_uncore_mmio_disable_box, 6042 .enable_box = intel_generic_uncore_mmio_enable_box, 6043 .disable_event = intel_generic_uncore_mmio_disable_event, 6044 .enable_event = spr_uncore_mmio_enable_event, 6045 .read_counter = uncore_mmio_read_counter, 6046}; 6047 6048static struct uncore_event_desc spr_uncore_imc_events[] = { 6049 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x01,umask=0x00"), 6050 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x05,umask=0xcf"), 6051 INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"), 6052 INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"), 6053 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x05,umask=0xf0"), 6054 INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"), 6055 INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"), 6056 { /* end: all zeroes */ }, 6057}; 6058 6059#define SPR_UNCORE_MMIO_COMMON_FORMAT() \ 6060 SPR_UNCORE_COMMON_FORMAT(), \ 6061 .ops = &spr_uncore_mmio_ops 6062 6063static struct intel_uncore_type spr_uncore_imc = { 6064 SPR_UNCORE_MMIO_COMMON_FORMAT(), 6065 .name = "imc", 6066 .fixed_ctr_bits = 48, 6067 .fixed_ctr = SNR_IMC_MMIO_PMON_FIXED_CTR, 6068 .fixed_ctl = SNR_IMC_MMIO_PMON_FIXED_CTL, 6069 .event_descs = spr_uncore_imc_events, 6070}; 6071 6072static void spr_uncore_pci_enable_event(struct intel_uncore_box *box, 6073 struct perf_event *event) 6074{ 6075 struct pci_dev *pdev = box->pci_dev; 6076 struct hw_perf_event *hwc = &event->hw; 6077 6078 pci_write_config_dword(pdev, hwc->config_base + 4, (u32)(hwc->config >> 32)); 6079 pci_write_config_dword(pdev, hwc->config_base, (u32)hwc->config); 6080} 6081 6082static struct intel_uncore_ops spr_uncore_pci_ops = { 6083 .init_box = intel_generic_uncore_pci_init_box, 6084 .disable_box = intel_generic_uncore_pci_disable_box, 6085 .enable_box = intel_generic_uncore_pci_enable_box, 6086 .disable_event = intel_generic_uncore_pci_disable_event, 6087 .enable_event = spr_uncore_pci_enable_event, 6088 .read_counter = intel_generic_uncore_pci_read_counter, 6089}; 6090 6091#define SPR_UNCORE_PCI_COMMON_FORMAT() \ 6092 SPR_UNCORE_COMMON_FORMAT(), \ 6093 .ops = &spr_uncore_pci_ops 6094 6095static struct intel_uncore_type spr_uncore_m2m = { 6096 SPR_UNCORE_PCI_COMMON_FORMAT(), 6097 .name = "m2m", 6098}; 6099 6100static struct attribute_group spr_upi_mapping_group = { 6101 .is_visible = skx_upi_mapping_visible, 6102}; 6103 6104static const struct attribute_group *spr_upi_attr_update[] = { 6105 &uncore_alias_group, 6106 &spr_upi_mapping_group, 6107 NULL 6108}; 6109 6110#define SPR_UPI_REGS_ADDR_DEVICE_LINK0 0x01 6111 6112static void spr_upi_set_mapping(struct intel_uncore_type *type) 6113{ 6114 pmu_upi_set_mapping(type, &spr_upi_mapping_group); 6115} 6116 6117static void spr_upi_cleanup_mapping(struct intel_uncore_type *type) 6118{ 6119 pmu_cleanup_mapping(type, &spr_upi_mapping_group); 6120} 6121 6122static int spr_upi_get_topology(struct intel_uncore_type *type) 6123{ 6124 return discover_upi_topology(type, SPR_UBOX_DID, SPR_UPI_REGS_ADDR_DEVICE_LINK0); 6125} 6126 6127static struct intel_uncore_type spr_uncore_mdf = { 6128 SPR_UNCORE_COMMON_FORMAT(), 6129 .name = "mdf", 6130}; 6131 6132static void spr_uncore_mmio_offs8_init_box(struct intel_uncore_box *box) 6133{ 6134 __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); 6135 intel_generic_uncore_mmio_init_box(box); 6136} 6137 6138static struct intel_uncore_ops spr_uncore_mmio_offs8_ops = { 6139 .init_box = spr_uncore_mmio_offs8_init_box, 6140 .exit_box = uncore_mmio_exit_box, 6141 .disable_box = intel_generic_uncore_mmio_disable_box, 6142 .enable_box = intel_generic_uncore_mmio_enable_box, 6143 .disable_event = intel_generic_uncore_mmio_disable_event, 6144 .enable_event = spr_uncore_mmio_enable_event, 6145 .read_counter = uncore_mmio_read_counter, 6146}; 6147 6148#define SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT() \ 6149 SPR_UNCORE_COMMON_FORMAT(), \ 6150 .ops = &spr_uncore_mmio_offs8_ops 6151 6152static struct event_constraint spr_uncore_cxlcm_constraints[] = { 6153 UNCORE_EVENT_CONSTRAINT(0x02, 0x0f), 6154 UNCORE_EVENT_CONSTRAINT(0x05, 0x0f), 6155 UNCORE_EVENT_CONSTRAINT(0x40, 0xf0), 6156 UNCORE_EVENT_CONSTRAINT(0x41, 0xf0), 6157 UNCORE_EVENT_CONSTRAINT(0x42, 0xf0), 6158 UNCORE_EVENT_CONSTRAINT(0x43, 0xf0), 6159 UNCORE_EVENT_CONSTRAINT(0x4b, 0xf0), 6160 UNCORE_EVENT_CONSTRAINT(0x52, 0xf0), 6161 EVENT_CONSTRAINT_END 6162}; 6163 6164static struct intel_uncore_type spr_uncore_cxlcm = { 6165 SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT(), 6166 .name = "cxlcm", 6167 .constraints = spr_uncore_cxlcm_constraints, 6168}; 6169 6170static struct intel_uncore_type spr_uncore_cxldp = { 6171 SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT(), 6172 .name = "cxldp", 6173}; 6174 6175static struct intel_uncore_type spr_uncore_hbm = { 6176 SPR_UNCORE_COMMON_FORMAT(), 6177 .name = "hbm", 6178}; 6179 6180#define UNCORE_SPR_NUM_UNCORE_TYPES 15 6181#define UNCORE_SPR_CHA 0 6182#define UNCORE_SPR_IIO 1 6183#define UNCORE_SPR_IMC 6 6184#define UNCORE_SPR_UPI 8 6185#define UNCORE_SPR_M3UPI 9 6186 6187/* 6188 * The uncore units, which are supported by the discovery table, 6189 * are defined here. 6190 */ 6191static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = { 6192 &spr_uncore_chabox, 6193 &spr_uncore_iio, 6194 &spr_uncore_irp, 6195 &spr_uncore_m2pcie, 6196 &spr_uncore_pcu, 6197 NULL, 6198 &spr_uncore_imc, 6199 &spr_uncore_m2m, 6200 NULL, 6201 NULL, 6202 NULL, 6203 &spr_uncore_mdf, 6204 &spr_uncore_cxlcm, 6205 &spr_uncore_cxldp, 6206 &spr_uncore_hbm, 6207}; 6208 6209/* 6210 * The uncore units, which are not supported by the discovery table, 6211 * are implemented from here. 6212 */ 6213#define SPR_UNCORE_UPI_NUM_BOXES 4 6214 6215static u64 spr_upi_pci_offsets[SPR_UNCORE_UPI_NUM_BOXES] = { 6216 0, 0x8000, 0x10000, 0x18000 6217}; 6218 6219static void spr_extra_boxes_cleanup(struct intel_uncore_type *type) 6220{ 6221 struct intel_uncore_discovery_unit *pos; 6222 struct rb_node *node; 6223 6224 if (!type->boxes) 6225 return; 6226 6227 while (!RB_EMPTY_ROOT(type->boxes)) { 6228 node = rb_first(type->boxes); 6229 pos = rb_entry(node, struct intel_uncore_discovery_unit, node); 6230 rb_erase(node, type->boxes); 6231 kfree(pos); 6232 } 6233 kfree(type->boxes); 6234 type->boxes = NULL; 6235} 6236 6237static struct intel_uncore_type spr_uncore_upi = { 6238 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, 6239 .event_mask_ext = SPR_RAW_EVENT_MASK_EXT, 6240 .format_group = &spr_uncore_raw_format_group, 6241 .ops = &spr_uncore_pci_ops, 6242 .name = "upi", 6243 .attr_update = spr_upi_attr_update, 6244 .get_topology = spr_upi_get_topology, 6245 .set_mapping = spr_upi_set_mapping, 6246 .cleanup_mapping = spr_upi_cleanup_mapping, 6247 .type_id = UNCORE_SPR_UPI, 6248 .num_counters = 4, 6249 .num_boxes = SPR_UNCORE_UPI_NUM_BOXES, 6250 .perf_ctr_bits = 48, 6251 .perf_ctr = ICX_UPI_PCI_PMON_CTR0 - ICX_UPI_PCI_PMON_BOX_CTL, 6252 .event_ctl = ICX_UPI_PCI_PMON_CTL0 - ICX_UPI_PCI_PMON_BOX_CTL, 6253 .box_ctl = ICX_UPI_PCI_PMON_BOX_CTL, 6254 .pci_offsets = spr_upi_pci_offsets, 6255 .cleanup_extra_boxes = spr_extra_boxes_cleanup, 6256}; 6257 6258static struct intel_uncore_type spr_uncore_m3upi = { 6259 SPR_UNCORE_PCI_COMMON_FORMAT(), 6260 .name = "m3upi", 6261 .type_id = UNCORE_SPR_M3UPI, 6262 .num_counters = 4, 6263 .num_boxes = SPR_UNCORE_UPI_NUM_BOXES, 6264 .perf_ctr_bits = 48, 6265 .perf_ctr = ICX_M3UPI_PCI_PMON_CTR0 - ICX_M3UPI_PCI_PMON_BOX_CTL, 6266 .event_ctl = ICX_M3UPI_PCI_PMON_CTL0 - ICX_M3UPI_PCI_PMON_BOX_CTL, 6267 .box_ctl = ICX_M3UPI_PCI_PMON_BOX_CTL, 6268 .pci_offsets = spr_upi_pci_offsets, 6269 .constraints = icx_uncore_m3upi_constraints, 6270 .cleanup_extra_boxes = spr_extra_boxes_cleanup, 6271}; 6272 6273enum perf_uncore_spr_iio_freerunning_type_id { 6274 SPR_IIO_MSR_IOCLK, 6275 SPR_IIO_MSR_BW_IN, 6276 SPR_IIO_MSR_BW_OUT, 6277 6278 SPR_IIO_FREERUNNING_TYPE_MAX, 6279}; 6280 6281static struct freerunning_counters spr_iio_freerunning[] = { 6282 [SPR_IIO_MSR_IOCLK] = { 0x340e, 0x1, 0x10, 1, 48 }, 6283 [SPR_IIO_MSR_BW_IN] = { 0x3800, 0x1, 0x10, 8, 48 }, 6284 [SPR_IIO_MSR_BW_OUT] = { 0x3808, 0x1, 0x10, 8, 48 }, 6285}; 6286 6287static struct intel_uncore_type spr_uncore_iio_free_running = { 6288 .name = "iio_free_running", 6289 .num_counters = 17, 6290 .num_freerunning_types = SPR_IIO_FREERUNNING_TYPE_MAX, 6291 .freerunning = spr_iio_freerunning, 6292 .ops = &skx_uncore_iio_freerunning_ops, 6293 .event_descs = snr_uncore_iio_freerunning_events, 6294 .format_group = &skx_uncore_iio_freerunning_format_group, 6295}; 6296 6297enum perf_uncore_spr_imc_freerunning_type_id { 6298 SPR_IMC_DCLK, 6299 SPR_IMC_PQ_CYCLES, 6300 6301 SPR_IMC_FREERUNNING_TYPE_MAX, 6302}; 6303 6304static struct freerunning_counters spr_imc_freerunning[] = { 6305 [SPR_IMC_DCLK] = { 0x22b0, 0x0, 0, 1, 48 }, 6306 [SPR_IMC_PQ_CYCLES] = { 0x2318, 0x8, 0, 2, 48 }, 6307}; 6308 6309static struct uncore_event_desc spr_uncore_imc_freerunning_events[] = { 6310 INTEL_UNCORE_EVENT_DESC(dclk, "event=0xff,umask=0x10"), 6311 6312 INTEL_UNCORE_EVENT_DESC(rpq_cycles, "event=0xff,umask=0x20"), 6313 INTEL_UNCORE_EVENT_DESC(wpq_cycles, "event=0xff,umask=0x21"), 6314 { /* end: all zeroes */ }, 6315}; 6316 6317#define SPR_MC_DEVICE_ID 0x3251 6318 6319static void spr_uncore_imc_freerunning_init_box(struct intel_uncore_box *box) 6320{ 6321 int mem_offset = box->pmu->pmu_idx * ICX_IMC_MEM_STRIDE + SNR_IMC_MMIO_MEM0_OFFSET; 6322 6323 snr_uncore_mmio_map(box, uncore_mmio_box_ctl(box), 6324 mem_offset, SPR_MC_DEVICE_ID); 6325} 6326 6327static struct intel_uncore_ops spr_uncore_imc_freerunning_ops = { 6328 .init_box = spr_uncore_imc_freerunning_init_box, 6329 .exit_box = uncore_mmio_exit_box, 6330 .read_counter = uncore_mmio_read_counter, 6331 .hw_config = uncore_freerunning_hw_config, 6332}; 6333 6334static struct intel_uncore_type spr_uncore_imc_free_running = { 6335 .name = "imc_free_running", 6336 .num_counters = 3, 6337 .mmio_map_size = SNR_IMC_MMIO_SIZE, 6338 .num_freerunning_types = SPR_IMC_FREERUNNING_TYPE_MAX, 6339 .freerunning = spr_imc_freerunning, 6340 .ops = &spr_uncore_imc_freerunning_ops, 6341 .event_descs = spr_uncore_imc_freerunning_events, 6342 .format_group = &skx_uncore_iio_freerunning_format_group, 6343}; 6344 6345#define UNCORE_SPR_MSR_EXTRA_UNCORES 1 6346#define UNCORE_SPR_MMIO_EXTRA_UNCORES 1 6347#define UNCORE_SPR_PCI_EXTRA_UNCORES 2 6348 6349static struct intel_uncore_type *spr_msr_uncores[UNCORE_SPR_MSR_EXTRA_UNCORES] = { 6350 &spr_uncore_iio_free_running, 6351}; 6352 6353static struct intel_uncore_type *spr_mmio_uncores[UNCORE_SPR_MMIO_EXTRA_UNCORES] = { 6354 &spr_uncore_imc_free_running, 6355}; 6356 6357static struct intel_uncore_type *spr_pci_uncores[UNCORE_SPR_PCI_EXTRA_UNCORES] = { 6358 &spr_uncore_upi, 6359 &spr_uncore_m3upi 6360}; 6361 6362int spr_uncore_units_ignore[] = { 6363 UNCORE_SPR_UPI, 6364 UNCORE_SPR_M3UPI, 6365 UNCORE_IGNORE_END 6366}; 6367 6368static void uncore_type_customized_copy(struct intel_uncore_type *to_type, 6369 struct intel_uncore_type *from_type) 6370{ 6371 if (!to_type || !from_type) 6372 return; 6373 6374 if (from_type->name) 6375 to_type->name = from_type->name; 6376 if (from_type->fixed_ctr_bits) 6377 to_type->fixed_ctr_bits = from_type->fixed_ctr_bits; 6378 if (from_type->event_mask) 6379 to_type->event_mask = from_type->event_mask; 6380 if (from_type->event_mask_ext) 6381 to_type->event_mask_ext = from_type->event_mask_ext; 6382 if (from_type->fixed_ctr) 6383 to_type->fixed_ctr = from_type->fixed_ctr; 6384 if (from_type->fixed_ctl) 6385 to_type->fixed_ctl = from_type->fixed_ctl; 6386 if (from_type->fixed_ctr_bits) 6387 to_type->fixed_ctr_bits = from_type->fixed_ctr_bits; 6388 if (from_type->num_shared_regs) 6389 to_type->num_shared_regs = from_type->num_shared_regs; 6390 if (from_type->constraints) 6391 to_type->constraints = from_type->constraints; 6392 if (from_type->ops) 6393 to_type->ops = from_type->ops; 6394 if (from_type->event_descs) 6395 to_type->event_descs = from_type->event_descs; 6396 if (from_type->format_group) 6397 to_type->format_group = from_type->format_group; 6398 if (from_type->attr_update) 6399 to_type->attr_update = from_type->attr_update; 6400 if (from_type->set_mapping) 6401 to_type->set_mapping = from_type->set_mapping; 6402 if (from_type->get_topology) 6403 to_type->get_topology = from_type->get_topology; 6404 if (from_type->cleanup_mapping) 6405 to_type->cleanup_mapping = from_type->cleanup_mapping; 6406 if (from_type->mmio_map_size) 6407 to_type->mmio_map_size = from_type->mmio_map_size; 6408} 6409 6410struct intel_uncore_type ** 6411uncore_get_uncores(enum uncore_access_type type_id, int num_extra, 6412 struct intel_uncore_type **extra, int max_num_types, 6413 struct intel_uncore_type **uncores) 6414{ 6415 struct intel_uncore_type **types, **start_types; 6416 int i; 6417 6418 start_types = types = intel_uncore_generic_init_uncores(type_id, num_extra); 6419 6420 /* Only copy the customized features */ 6421 for (; *types; types++) { 6422 if ((*types)->type_id >= max_num_types) 6423 continue; 6424 uncore_type_customized_copy(*types, uncores[(*types)->type_id]); 6425 } 6426 6427 for (i = 0; i < num_extra; i++, types++) 6428 *types = extra[i]; 6429 6430 return start_types; 6431} 6432 6433static struct intel_uncore_type * 6434uncore_find_type_by_id(struct intel_uncore_type **types, int type_id) 6435{ 6436 for (; *types; types++) { 6437 if (type_id == (*types)->type_id) 6438 return *types; 6439 } 6440 6441 return NULL; 6442} 6443 6444static int uncore_type_max_boxes(struct intel_uncore_type **types, 6445 int type_id) 6446{ 6447 struct intel_uncore_discovery_unit *unit; 6448 struct intel_uncore_type *type; 6449 struct rb_node *node; 6450 int max = 0; 6451 6452 type = uncore_find_type_by_id(types, type_id); 6453 if (!type) 6454 return 0; 6455 6456 for (node = rb_first(type->boxes); node; node = rb_next(node)) { 6457 unit = rb_entry(node, struct intel_uncore_discovery_unit, node); 6458 6459 if (unit->id > max) 6460 max = unit->id; 6461 } 6462 return max + 1; 6463} 6464 6465#define SPR_MSR_UNC_CBO_CONFIG 0x2FFE 6466 6467void spr_uncore_cpu_init(void) 6468{ 6469 struct intel_uncore_type *type; 6470 u64 num_cbo; 6471 6472 uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR, 6473 UNCORE_SPR_MSR_EXTRA_UNCORES, 6474 spr_msr_uncores, 6475 UNCORE_SPR_NUM_UNCORE_TYPES, 6476 spr_uncores); 6477 6478 type = uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA); 6479 if (type) { 6480 /* 6481 * The value from the discovery table (stored in the type->num_boxes 6482 * of UNCORE_SPR_CHA) is incorrect on some SPR variants because of a 6483 * firmware bug. Using the value from SPR_MSR_UNC_CBO_CONFIG to replace it. 6484 */ 6485 rdmsrq(SPR_MSR_UNC_CBO_CONFIG, num_cbo); 6486 /* 6487 * The MSR doesn't work on the EMR XCC, but the firmware bug doesn't impact 6488 * the EMR XCC. Don't let the value from the MSR replace the existing value. 6489 */ 6490 if (num_cbo) 6491 type->num_boxes = num_cbo; 6492 } 6493 spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO); 6494} 6495 6496#define SPR_UNCORE_UPI_PCIID 0x3241 6497#define SPR_UNCORE_UPI0_DEVFN 0x9 6498#define SPR_UNCORE_M3UPI_PCIID 0x3246 6499#define SPR_UNCORE_M3UPI0_DEVFN 0x29 6500 6501static void spr_update_device_location(int type_id) 6502{ 6503 struct intel_uncore_discovery_unit *unit; 6504 struct intel_uncore_type *type; 6505 struct pci_dev *dev = NULL; 6506 struct rb_root *root; 6507 u32 device, devfn; 6508 int die; 6509 6510 if (type_id == UNCORE_SPR_UPI) { 6511 type = &spr_uncore_upi; 6512 device = SPR_UNCORE_UPI_PCIID; 6513 devfn = SPR_UNCORE_UPI0_DEVFN; 6514 } else if (type_id == UNCORE_SPR_M3UPI) { 6515 type = &spr_uncore_m3upi; 6516 device = SPR_UNCORE_M3UPI_PCIID; 6517 devfn = SPR_UNCORE_M3UPI0_DEVFN; 6518 } else 6519 return; 6520 6521 root = kzalloc(sizeof(struct rb_root), GFP_KERNEL); 6522 if (!root) { 6523 type->num_boxes = 0; 6524 return; 6525 } 6526 *root = RB_ROOT; 6527 6528 while ((dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, dev)) != NULL) { 6529 6530 die = uncore_pcibus_to_dieid(dev->bus); 6531 if (die < 0) 6532 continue; 6533 6534 unit = kzalloc(sizeof(*unit), GFP_KERNEL); 6535 if (!unit) 6536 continue; 6537 unit->die = die; 6538 unit->id = PCI_SLOT(dev->devfn) - PCI_SLOT(devfn); 6539 unit->addr = pci_domain_nr(dev->bus) << UNCORE_DISCOVERY_PCI_DOMAIN_OFFSET | 6540 dev->bus->number << UNCORE_DISCOVERY_PCI_BUS_OFFSET | 6541 devfn << UNCORE_DISCOVERY_PCI_DEVFN_OFFSET | 6542 type->box_ctl; 6543 6544 unit->pmu_idx = unit->id; 6545 6546 uncore_find_add_unit(unit, root, NULL); 6547 } 6548 6549 type->boxes = root; 6550} 6551 6552int spr_uncore_pci_init(void) 6553{ 6554 int ret = snbep_pci2phy_map_init(0x3250, SKX_CPUNODEID, SKX_GIDNIDMAP, true); 6555 6556 if (ret) 6557 return ret; 6558 6559 /* 6560 * The discovery table of UPI on some SPR variant is broken, 6561 * which impacts the detection of both UPI and M3UPI uncore PMON. 6562 * Use the pre-defined UPI and M3UPI table to replace. 6563 * 6564 * The accurate location, e.g., domain and BUS number, 6565 * can only be retrieved at load time. 6566 * Update the location of UPI and M3UPI. 6567 */ 6568 spr_update_device_location(UNCORE_SPR_UPI); 6569 spr_update_device_location(UNCORE_SPR_M3UPI); 6570 uncore_pci_uncores = uncore_get_uncores(UNCORE_ACCESS_PCI, 6571 UNCORE_SPR_PCI_EXTRA_UNCORES, 6572 spr_pci_uncores, 6573 UNCORE_SPR_NUM_UNCORE_TYPES, 6574 spr_uncores); 6575 return 0; 6576} 6577 6578void spr_uncore_mmio_init(void) 6579{ 6580 int ret = snbep_pci2phy_map_init(0x3250, SKX_CPUNODEID, SKX_GIDNIDMAP, true); 6581 6582 if (ret) { 6583 uncore_mmio_uncores = uncore_get_uncores(UNCORE_ACCESS_MMIO, 0, NULL, 6584 UNCORE_SPR_NUM_UNCORE_TYPES, 6585 spr_uncores); 6586 } else { 6587 uncore_mmio_uncores = uncore_get_uncores(UNCORE_ACCESS_MMIO, 6588 UNCORE_SPR_MMIO_EXTRA_UNCORES, 6589 spr_mmio_uncores, 6590 UNCORE_SPR_NUM_UNCORE_TYPES, 6591 spr_uncores); 6592 6593 spr_uncore_imc_free_running.num_boxes = uncore_type_max_boxes(uncore_mmio_uncores, UNCORE_SPR_IMC) / 2; 6594 } 6595} 6596 6597/* end of SPR uncore support */ 6598 6599/* GNR uncore support */ 6600 6601#define UNCORE_GNR_NUM_UNCORE_TYPES 23 6602 6603int gnr_uncore_units_ignore[] = { 6604 UNCORE_IGNORE_END 6605}; 6606 6607static struct intel_uncore_type gnr_uncore_ubox = { 6608 .name = "ubox", 6609 .attr_update = uncore_alias_groups, 6610}; 6611 6612static struct uncore_event_desc gnr_uncore_imc_events[] = { 6613 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x01,umask=0x00"), 6614 INTEL_UNCORE_EVENT_DESC(cas_count_read_sch0, "event=0x05,umask=0xcf"), 6615 INTEL_UNCORE_EVENT_DESC(cas_count_read_sch0.scale, "6.103515625e-5"), 6616 INTEL_UNCORE_EVENT_DESC(cas_count_read_sch0.unit, "MiB"), 6617 INTEL_UNCORE_EVENT_DESC(cas_count_read_sch1, "event=0x06,umask=0xcf"), 6618 INTEL_UNCORE_EVENT_DESC(cas_count_read_sch1.scale, "6.103515625e-5"), 6619 INTEL_UNCORE_EVENT_DESC(cas_count_read_sch1.unit, "MiB"), 6620 INTEL_UNCORE_EVENT_DESC(cas_count_write_sch0, "event=0x05,umask=0xf0"), 6621 INTEL_UNCORE_EVENT_DESC(cas_count_write_sch0.scale, "6.103515625e-5"), 6622 INTEL_UNCORE_EVENT_DESC(cas_count_write_sch0.unit, "MiB"), 6623 INTEL_UNCORE_EVENT_DESC(cas_count_write_sch1, "event=0x06,umask=0xf0"), 6624 INTEL_UNCORE_EVENT_DESC(cas_count_write_sch1.scale, "6.103515625e-5"), 6625 INTEL_UNCORE_EVENT_DESC(cas_count_write_sch1.unit, "MiB"), 6626 { /* end: all zeroes */ }, 6627}; 6628 6629static struct intel_uncore_type gnr_uncore_imc = { 6630 SPR_UNCORE_MMIO_COMMON_FORMAT(), 6631 .name = "imc", 6632 .fixed_ctr_bits = 48, 6633 .fixed_ctr = SNR_IMC_MMIO_PMON_FIXED_CTR, 6634 .fixed_ctl = SNR_IMC_MMIO_PMON_FIXED_CTL, 6635 .event_descs = gnr_uncore_imc_events, 6636}; 6637 6638static struct intel_uncore_type gnr_uncore_pciex8 = { 6639 SPR_UNCORE_PCI_COMMON_FORMAT(), 6640 .name = "pciex8", 6641}; 6642 6643static struct intel_uncore_type gnr_uncore_pciex16 = { 6644 SPR_UNCORE_PCI_COMMON_FORMAT(), 6645 .name = "pciex16", 6646}; 6647 6648static struct intel_uncore_type gnr_uncore_upi = { 6649 SPR_UNCORE_PCI_COMMON_FORMAT(), 6650 .name = "upi", 6651}; 6652 6653static struct intel_uncore_type gnr_uncore_b2upi = { 6654 SPR_UNCORE_PCI_COMMON_FORMAT(), 6655 .name = "b2upi", 6656}; 6657 6658static struct intel_uncore_type gnr_uncore_b2hot = { 6659 .name = "b2hot", 6660 .attr_update = uncore_alias_groups, 6661}; 6662 6663static struct intel_uncore_type gnr_uncore_b2cmi = { 6664 SPR_UNCORE_PCI_COMMON_FORMAT(), 6665 .name = "b2cmi", 6666}; 6667 6668static struct intel_uncore_type gnr_uncore_b2cxl = { 6669 SPR_UNCORE_MMIO_OFFS8_COMMON_FORMAT(), 6670 .name = "b2cxl", 6671}; 6672 6673static struct intel_uncore_type gnr_uncore_mdf_sbo = { 6674 .name = "mdf_sbo", 6675 .attr_update = uncore_alias_groups, 6676}; 6677 6678static struct intel_uncore_type *gnr_uncores[UNCORE_GNR_NUM_UNCORE_TYPES] = { 6679 &spr_uncore_chabox, 6680 &spr_uncore_iio, 6681 &spr_uncore_irp, 6682 NULL, 6683 &spr_uncore_pcu, 6684 &gnr_uncore_ubox, 6685 &gnr_uncore_imc, 6686 NULL, 6687 &gnr_uncore_upi, 6688 NULL, 6689 NULL, 6690 NULL, 6691 &spr_uncore_cxlcm, 6692 &spr_uncore_cxldp, 6693 NULL, 6694 &gnr_uncore_b2hot, 6695 &gnr_uncore_b2cmi, 6696 &gnr_uncore_b2cxl, 6697 &gnr_uncore_b2upi, 6698 NULL, 6699 &gnr_uncore_mdf_sbo, 6700 &gnr_uncore_pciex16, 6701 &gnr_uncore_pciex8, 6702}; 6703 6704static struct freerunning_counters gnr_iio_freerunning[] = { 6705 [SPR_IIO_MSR_IOCLK] = { 0x290e, 0x01, 0x10, 1, 48 }, 6706 [SPR_IIO_MSR_BW_IN] = { 0x360e, 0x10, 0x80, 8, 48 }, 6707 [SPR_IIO_MSR_BW_OUT] = { 0x2e0e, 0x10, 0x80, 8, 48 }, 6708}; 6709 6710void gnr_uncore_cpu_init(void) 6711{ 6712 uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR, 6713 UNCORE_SPR_MSR_EXTRA_UNCORES, 6714 spr_msr_uncores, 6715 UNCORE_GNR_NUM_UNCORE_TYPES, 6716 gnr_uncores); 6717 spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO); 6718 spr_uncore_iio_free_running.freerunning = gnr_iio_freerunning; 6719} 6720 6721int gnr_uncore_pci_init(void) 6722{ 6723 uncore_pci_uncores = uncore_get_uncores(UNCORE_ACCESS_PCI, 0, NULL, 6724 UNCORE_GNR_NUM_UNCORE_TYPES, 6725 gnr_uncores); 6726 return 0; 6727} 6728 6729void gnr_uncore_mmio_init(void) 6730{ 6731 uncore_mmio_uncores = uncore_get_uncores(UNCORE_ACCESS_MMIO, 0, NULL, 6732 UNCORE_GNR_NUM_UNCORE_TYPES, 6733 gnr_uncores); 6734} 6735 6736/* end of GNR uncore support */
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