FILE
core.c
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linux-6.19.14/arch/x86/events/intel/core.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Per core/cpu state 4 * 5 * Used to coordinate shared registers between HT threads or 6 * among events on a single PMU. 7 */ 8 9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11#include <linux/stddef.h> 12#include <linux/types.h> 13#include <linux/init.h> 14#include <linux/slab.h> 15#include <linux/export.h> 16#include <linux/nmi.h> 17#include <linux/kvm_host.h> 18 19#include <asm/cpufeature.h> 20#include <asm/debugreg.h> 21#include <asm/hardirq.h> 22#include <asm/intel-family.h> 23#include <asm/intel_pt.h> 24#include <asm/apic.h> 25#include <asm/cpu_device_id.h> 26#include <asm/msr.h> 27 28#include "../perf_event.h" 29 30/* 31 * Intel PerfMon, used on Core and later. 32 */ 33static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = 34{ 35 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, 36 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 37 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, 38 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, 39 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, 40 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, 41 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, 42 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ 43}; 44 45static struct event_constraint intel_core_event_constraints[] __read_mostly = 46{ 47 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 48 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 49 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 50 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 51 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 52 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ 53 EVENT_CONSTRAINT_END 54}; 55 56static struct event_constraint intel_core2_event_constraints[] __read_mostly = 57{ 58 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 59 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 60 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 61 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ 62 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ 63 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ 64 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ 65 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ 66 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ 67 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ 68 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ 69 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ 70 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ 71 EVENT_CONSTRAINT_END 72}; 73 74static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = 75{ 76 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 77 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 78 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 79 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ 80 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ 81 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ 82 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ 83 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ 84 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ 85 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 86 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 87 EVENT_CONSTRAINT_END 88}; 89 90static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = 91{ 92 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 93 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 94 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 95 EVENT_EXTRA_END 96}; 97 98static struct event_constraint intel_westmere_event_constraints[] __read_mostly = 99{ 100 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 101 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 102 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 103 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ 104 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ 105 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ 106 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ 107 EVENT_CONSTRAINT_END 108}; 109 110static struct event_constraint intel_snb_event_constraints[] __read_mostly = 111{ 112 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 113 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 114 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 115 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 116 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 117 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 118 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 119 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ 120 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 121 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 122 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 123 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 124 125 /* 126 * When HT is off these events can only run on the bottom 4 counters 127 * When HT is on, they are impacted by the HT bug and require EXCL access 128 */ 129 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 130 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 131 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 132 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 133 134 EVENT_CONSTRAINT_END 135}; 136 137static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 138{ 139 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 140 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 141 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 142 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */ 143 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */ 144 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */ 145 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ 146 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 147 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ 148 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ 149 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 150 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 151 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 152 153 /* 154 * When HT is off these events can only run on the bottom 4 counters 155 * When HT is on, they are impacted by the HT bug and require EXCL access 156 */ 157 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 158 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 159 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 160 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 161 162 EVENT_CONSTRAINT_END 163}; 164 165static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 166{ 167 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 168 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), 169 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), 170 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b), 171 EVENT_EXTRA_END 172}; 173 174static struct event_constraint intel_v1_event_constraints[] __read_mostly = 175{ 176 EVENT_CONSTRAINT_END 177}; 178 179static struct event_constraint intel_gen_event_constraints[] __read_mostly = 180{ 181 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 182 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 183 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 184 EVENT_CONSTRAINT_END 185}; 186 187static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly = 188{ 189 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 190 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 191 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 192 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 193 FIXED_EVENT_CONSTRAINT(0x0500, 4), 194 FIXED_EVENT_CONSTRAINT(0x0600, 5), 195 FIXED_EVENT_CONSTRAINT(0x0700, 6), 196 FIXED_EVENT_CONSTRAINT(0x0800, 7), 197 FIXED_EVENT_CONSTRAINT(0x0900, 8), 198 FIXED_EVENT_CONSTRAINT(0x0a00, 9), 199 FIXED_EVENT_CONSTRAINT(0x0b00, 10), 200 FIXED_EVENT_CONSTRAINT(0x0c00, 11), 201 FIXED_EVENT_CONSTRAINT(0x0d00, 12), 202 FIXED_EVENT_CONSTRAINT(0x0e00, 13), 203 FIXED_EVENT_CONSTRAINT(0x0f00, 14), 204 FIXED_EVENT_CONSTRAINT(0x1000, 15), 205 EVENT_CONSTRAINT_END 206}; 207 208static struct event_constraint intel_slm_event_constraints[] __read_mostly = 209{ 210 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 211 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 212 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 213 EVENT_CONSTRAINT_END 214}; 215 216static struct event_constraint intel_grt_event_constraints[] __read_mostly = { 217 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 218 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 219 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 220 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 221 EVENT_CONSTRAINT_END 222}; 223 224static struct event_constraint intel_skt_event_constraints[] __read_mostly = { 225 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 226 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 227 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ 228 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 229 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */ 230 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */ 231 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */ 232 EVENT_CONSTRAINT_END 233}; 234 235static struct event_constraint intel_skl_event_constraints[] = { 236 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 237 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 238 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 239 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 240 241 /* 242 * when HT is off, these can only run on the bottom 4 counters 243 */ 244 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 245 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 246 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 247 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 248 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 249 250 EVENT_CONSTRAINT_END 251}; 252 253static struct extra_reg intel_knl_extra_regs[] __read_mostly = { 254 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), 255 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), 256 EVENT_EXTRA_END 257}; 258 259static struct extra_reg intel_snb_extra_regs[] __read_mostly = { 260 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 261 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), 262 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), 263 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 264 EVENT_EXTRA_END 265}; 266 267static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { 268 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 269 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 270 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 271 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 272 EVENT_EXTRA_END 273}; 274 275static struct extra_reg intel_skl_extra_regs[] __read_mostly = { 276 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), 277 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), 278 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 279 /* 280 * Note the low 8 bits eventsel code is not a continuous field, containing 281 * some #GPing bits. These are masked out. 282 */ 283 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 284 EVENT_EXTRA_END 285}; 286 287static struct event_constraint intel_icl_event_constraints[] = { 288 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 289 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */ 290 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 291 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 292 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 293 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 294 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 295 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 296 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 297 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 298 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf), 299 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf), 300 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */ 301 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf), 302 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf), 303 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */ 304 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ 305 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ 306 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */ 307 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf), 308 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf), 309 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf), 310 INTEL_EVENT_CONSTRAINT(0xef, 0xf), 311 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf), 312 EVENT_CONSTRAINT_END 313}; 314 315static struct extra_reg intel_icl_extra_regs[] __read_mostly = { 316 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), 317 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), 318 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 319 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), 320 EVENT_EXTRA_END 321}; 322 323static struct extra_reg intel_glc_extra_regs[] __read_mostly = { 324 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 325 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 326 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 327 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 328 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 329 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 330 EVENT_EXTRA_END 331}; 332 333static struct event_constraint intel_glc_event_constraints[] = { 334 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 335 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 336 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 337 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 338 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 339 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 340 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 341 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 342 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 343 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 344 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 345 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 346 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 347 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 348 349 INTEL_EVENT_CONSTRAINT(0x2e, 0xff), 350 INTEL_EVENT_CONSTRAINT(0x3c, 0xff), 351 /* 352 * Generally event codes < 0x90 are restricted to counters 0-3. 353 * The 0x2E and 0x3C are exception, which has no restriction. 354 */ 355 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf), 356 357 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), 358 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), 359 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), 360 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 361 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 362 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), 363 INTEL_EVENT_CONSTRAINT(0xce, 0x1), 364 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 365 /* 366 * Generally event codes >= 0x90 are likely to have no restrictions. 367 * The exception are defined as above. 368 */ 369 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff), 370 371 EVENT_CONSTRAINT_END 372}; 373 374static struct extra_reg intel_rwc_extra_regs[] __read_mostly = { 375 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 376 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 377 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 378 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), 379 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 380 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), 381 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 382 EVENT_EXTRA_END 383}; 384 385static struct event_constraint intel_lnc_event_constraints[] = { 386 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 387 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ 388 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 389 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 390 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ 391 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ 392 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), 393 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), 394 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), 395 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3), 396 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4), 397 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5), 398 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6), 399 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7), 400 401 INTEL_EVENT_CONSTRAINT(0x20, 0xf), 402 403 INTEL_UEVENT_CONSTRAINT(0x012a, 0xf), 404 INTEL_UEVENT_CONSTRAINT(0x012b, 0xf), 405 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), 406 INTEL_UEVENT_CONSTRAINT(0x0175, 0x4), 407 408 INTEL_EVENT_CONSTRAINT(0x2e, 0x3ff), 409 INTEL_EVENT_CONSTRAINT(0x3c, 0x3ff), 410 411 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 412 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 413 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), 414 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), 415 INTEL_UEVENT_CONSTRAINT(0x10a4, 0x1), 416 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8), 417 INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc), 418 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3), 419 420 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), 421 422 INTEL_UEVENT_CONSTRAINT(0x00e0, 0xf), 423 424 EVENT_CONSTRAINT_END 425}; 426 427static struct extra_reg intel_lnc_extra_regs[] __read_mostly = { 428 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0xfffffffffffull, RSP_0), 429 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0xfffffffffffull, RSP_1), 430 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), 431 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), 432 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), 433 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE), 434 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), 435 EVENT_EXTRA_END 436}; 437 438EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); 439EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); 440EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2"); 441 442static struct attribute *nhm_mem_events_attrs[] = { 443 EVENT_PTR(mem_ld_nhm), 444 NULL, 445}; 446 447/* 448 * topdown events for Intel Core CPUs. 449 * 450 * The events are all in slots, which is a free slot in a 4 wide 451 * pipeline. Some events are already reported in slots, for cycle 452 * events we multiply by the pipeline width (4). 453 * 454 * With Hyper Threading on, topdown metrics are either summed or averaged 455 * between the threads of a core: (count_t0 + count_t1). 456 * 457 * For the average case the metric is always scaled to pipeline width, 458 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) 459 */ 460 461EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots, 462 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */ 463 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */ 464EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2"); 465EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued, 466 "event=0xe,umask=0x1"); /* uops_issued.any */ 467EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired, 468 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */ 469EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles, 470 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */ 471EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles, 472 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */ 473 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */ 474EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale, 475 "4", "2"); 476 477EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4"); 478EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80"); 479EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81"); 480EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82"); 481EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83"); 482EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84"); 483EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85"); 484EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86"); 485EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87"); 486 487static struct attribute *snb_events_attrs[] = { 488 EVENT_PTR(td_slots_issued), 489 EVENT_PTR(td_slots_retired), 490 EVENT_PTR(td_fetch_bubbles), 491 EVENT_PTR(td_total_slots), 492 EVENT_PTR(td_total_slots_scale), 493 EVENT_PTR(td_recovery_bubbles), 494 EVENT_PTR(td_recovery_bubbles_scale), 495 NULL, 496}; 497 498static struct attribute *snb_mem_events_attrs[] = { 499 EVENT_PTR(mem_ld_snb), 500 EVENT_PTR(mem_st_snb), 501 NULL, 502}; 503 504static struct event_constraint intel_hsw_event_constraints[] = { 505 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 506 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 507 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 508 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 509 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 510 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ 511 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 512 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), 513 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 514 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), 515 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 516 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 517 518 /* 519 * When HT is off these events can only run on the bottom 4 counters 520 * When HT is on, they are impacted by the HT bug and require EXCL access 521 */ 522 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 523 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 524 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 525 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 526 527 EVENT_CONSTRAINT_END 528}; 529 530static struct event_constraint intel_bdw_event_constraints[] = { 531 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ 532 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 533 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 534 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 535 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 536 /* 537 * when HT is off, these can only run on the bottom 4 counters 538 */ 539 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 540 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 541 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 542 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 543 EVENT_CONSTRAINT_END 544}; 545 546static u64 intel_pmu_event_map(int hw_event) 547{ 548 return intel_perfmon_event_map[hw_event]; 549} 550 551static __initconst const u64 glc_hw_cache_event_ids 552 [PERF_COUNT_HW_CACHE_MAX] 553 [PERF_COUNT_HW_CACHE_OP_MAX] 554 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 555{ 556 [ C(L1D ) ] = { 557 [ C(OP_READ) ] = { 558 [ C(RESULT_ACCESS) ] = 0x81d0, 559 [ C(RESULT_MISS) ] = 0xe124, 560 }, 561 [ C(OP_WRITE) ] = { 562 [ C(RESULT_ACCESS) ] = 0x82d0, 563 }, 564 }, 565 [ C(L1I ) ] = { 566 [ C(OP_READ) ] = { 567 [ C(RESULT_MISS) ] = 0xe424, 568 }, 569 [ C(OP_WRITE) ] = { 570 [ C(RESULT_ACCESS) ] = -1, 571 [ C(RESULT_MISS) ] = -1, 572 }, 573 }, 574 [ C(LL ) ] = { 575 [ C(OP_READ) ] = { 576 [ C(RESULT_ACCESS) ] = 0x12a, 577 [ C(RESULT_MISS) ] = 0x12a, 578 }, 579 [ C(OP_WRITE) ] = { 580 [ C(RESULT_ACCESS) ] = 0x12a, 581 [ C(RESULT_MISS) ] = 0x12a, 582 }, 583 }, 584 [ C(DTLB) ] = { 585 [ C(OP_READ) ] = { 586 [ C(RESULT_ACCESS) ] = 0x81d0, 587 [ C(RESULT_MISS) ] = 0xe12, 588 }, 589 [ C(OP_WRITE) ] = { 590 [ C(RESULT_ACCESS) ] = 0x82d0, 591 [ C(RESULT_MISS) ] = 0xe13, 592 }, 593 }, 594 [ C(ITLB) ] = { 595 [ C(OP_READ) ] = { 596 [ C(RESULT_ACCESS) ] = -1, 597 [ C(RESULT_MISS) ] = 0xe11, 598 }, 599 [ C(OP_WRITE) ] = { 600 [ C(RESULT_ACCESS) ] = -1, 601 [ C(RESULT_MISS) ] = -1, 602 }, 603 [ C(OP_PREFETCH) ] = { 604 [ C(RESULT_ACCESS) ] = -1, 605 [ C(RESULT_MISS) ] = -1, 606 }, 607 }, 608 [ C(BPU ) ] = { 609 [ C(OP_READ) ] = { 610 [ C(RESULT_ACCESS) ] = 0x4c4, 611 [ C(RESULT_MISS) ] = 0x4c5, 612 }, 613 [ C(OP_WRITE) ] = { 614 [ C(RESULT_ACCESS) ] = -1, 615 [ C(RESULT_MISS) ] = -1, 616 }, 617 [ C(OP_PREFETCH) ] = { 618 [ C(RESULT_ACCESS) ] = -1, 619 [ C(RESULT_MISS) ] = -1, 620 }, 621 }, 622 [ C(NODE) ] = { 623 [ C(OP_READ) ] = { 624 [ C(RESULT_ACCESS) ] = 0x12a, 625 [ C(RESULT_MISS) ] = 0x12a, 626 }, 627 }, 628}; 629 630static __initconst const u64 glc_hw_cache_extra_regs 631 [PERF_COUNT_HW_CACHE_MAX] 632 [PERF_COUNT_HW_CACHE_OP_MAX] 633 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 634{ 635 [ C(LL ) ] = { 636 [ C(OP_READ) ] = { 637 [ C(RESULT_ACCESS) ] = 0x10001, 638 [ C(RESULT_MISS) ] = 0x3fbfc00001, 639 }, 640 [ C(OP_WRITE) ] = { 641 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, 642 [ C(RESULT_MISS) ] = 0x3f3fc00002, 643 }, 644 }, 645 [ C(NODE) ] = { 646 [ C(OP_READ) ] = { 647 [ C(RESULT_ACCESS) ] = 0x10c000001, 648 [ C(RESULT_MISS) ] = 0x3fb3000001, 649 }, 650 }, 651}; 652 653/* 654 * Notes on the events: 655 * - data reads do not include code reads (comparable to earlier tables) 656 * - data counts include speculative execution (except L1 write, dtlb, bpu) 657 * - remote node access includes remote memory, remote cache, remote mmio. 658 * - prefetches are not included in the counts. 659 * - icache miss does not include decoded icache 660 */ 661 662#define SKL_DEMAND_DATA_RD BIT_ULL(0) 663#define SKL_DEMAND_RFO BIT_ULL(1) 664#define SKL_ANY_RESPONSE BIT_ULL(16) 665#define SKL_SUPPLIER_NONE BIT_ULL(17) 666#define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26) 667#define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27) 668#define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28) 669#define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29) 670#define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \ 671 SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 672 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 673 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 674#define SKL_SPL_HIT BIT_ULL(30) 675#define SKL_SNOOP_NONE BIT_ULL(31) 676#define SKL_SNOOP_NOT_NEEDED BIT_ULL(32) 677#define SKL_SNOOP_MISS BIT_ULL(33) 678#define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34) 679#define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35) 680#define SKL_SNOOP_HITM BIT_ULL(36) 681#define SKL_SNOOP_NON_DRAM BIT_ULL(37) 682#define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \ 683 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 684 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 685 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM) 686#define SKL_DEMAND_READ SKL_DEMAND_DATA_RD 687#define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \ 688 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \ 689 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \ 690 SKL_SNOOP_HITM|SKL_SPL_HIT) 691#define SKL_DEMAND_WRITE SKL_DEMAND_RFO 692#define SKL_LLC_ACCESS SKL_ANY_RESPONSE 693#define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \ 694 SKL_L3_MISS_REMOTE_HOP1_DRAM| \ 695 SKL_L3_MISS_REMOTE_HOP2P_DRAM) 696 697static __initconst const u64 skl_hw_cache_event_ids 698 [PERF_COUNT_HW_CACHE_MAX] 699 [PERF_COUNT_HW_CACHE_OP_MAX] 700 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 701{ 702 [ C(L1D ) ] = { 703 [ C(OP_READ) ] = { 704 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 705 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 706 }, 707 [ C(OP_WRITE) ] = { 708 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 709 [ C(RESULT_MISS) ] = 0x0, 710 }, 711 [ C(OP_PREFETCH) ] = { 712 [ C(RESULT_ACCESS) ] = 0x0, 713 [ C(RESULT_MISS) ] = 0x0, 714 }, 715 }, 716 [ C(L1I ) ] = { 717 [ C(OP_READ) ] = { 718 [ C(RESULT_ACCESS) ] = 0x0, 719 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */ 720 }, 721 [ C(OP_WRITE) ] = { 722 [ C(RESULT_ACCESS) ] = -1, 723 [ C(RESULT_MISS) ] = -1, 724 }, 725 [ C(OP_PREFETCH) ] = { 726 [ C(RESULT_ACCESS) ] = 0x0, 727 [ C(RESULT_MISS) ] = 0x0, 728 }, 729 }, 730 [ C(LL ) ] = { 731 [ C(OP_READ) ] = { 732 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 733 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 734 }, 735 [ C(OP_WRITE) ] = { 736 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 737 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 738 }, 739 [ C(OP_PREFETCH) ] = { 740 [ C(RESULT_ACCESS) ] = 0x0, 741 [ C(RESULT_MISS) ] = 0x0, 742 }, 743 }, 744 [ C(DTLB) ] = { 745 [ C(OP_READ) ] = { 746 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ 747 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 748 }, 749 [ C(OP_WRITE) ] = { 750 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ 751 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 752 }, 753 [ C(OP_PREFETCH) ] = { 754 [ C(RESULT_ACCESS) ] = 0x0, 755 [ C(RESULT_MISS) ] = 0x0, 756 }, 757 }, 758 [ C(ITLB) ] = { 759 [ C(OP_READ) ] = { 760 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */ 761 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */ 762 }, 763 [ C(OP_WRITE) ] = { 764 [ C(RESULT_ACCESS) ] = -1, 765 [ C(RESULT_MISS) ] = -1, 766 }, 767 [ C(OP_PREFETCH) ] = { 768 [ C(RESULT_ACCESS) ] = -1, 769 [ C(RESULT_MISS) ] = -1, 770 }, 771 }, 772 [ C(BPU ) ] = { 773 [ C(OP_READ) ] = { 774 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 775 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 776 }, 777 [ C(OP_WRITE) ] = { 778 [ C(RESULT_ACCESS) ] = -1, 779 [ C(RESULT_MISS) ] = -1, 780 }, 781 [ C(OP_PREFETCH) ] = { 782 [ C(RESULT_ACCESS) ] = -1, 783 [ C(RESULT_MISS) ] = -1, 784 }, 785 }, 786 [ C(NODE) ] = { 787 [ C(OP_READ) ] = { 788 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 789 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 790 }, 791 [ C(OP_WRITE) ] = { 792 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 793 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 794 }, 795 [ C(OP_PREFETCH) ] = { 796 [ C(RESULT_ACCESS) ] = 0x0, 797 [ C(RESULT_MISS) ] = 0x0, 798 }, 799 }, 800}; 801 802static __initconst const u64 skl_hw_cache_extra_regs 803 [PERF_COUNT_HW_CACHE_MAX] 804 [PERF_COUNT_HW_CACHE_OP_MAX] 805 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 806{ 807 [ C(LL ) ] = { 808 [ C(OP_READ) ] = { 809 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 810 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 811 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 812 SKL_L3_MISS|SKL_ANY_SNOOP| 813 SKL_SUPPLIER_NONE, 814 }, 815 [ C(OP_WRITE) ] = { 816 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 817 SKL_LLC_ACCESS|SKL_ANY_SNOOP, 818 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 819 SKL_L3_MISS|SKL_ANY_SNOOP| 820 SKL_SUPPLIER_NONE, 821 }, 822 [ C(OP_PREFETCH) ] = { 823 [ C(RESULT_ACCESS) ] = 0x0, 824 [ C(RESULT_MISS) ] = 0x0, 825 }, 826 }, 827 [ C(NODE) ] = { 828 [ C(OP_READ) ] = { 829 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ| 830 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 831 [ C(RESULT_MISS) ] = SKL_DEMAND_READ| 832 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 833 }, 834 [ C(OP_WRITE) ] = { 835 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE| 836 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM, 837 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE| 838 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM, 839 }, 840 [ C(OP_PREFETCH) ] = { 841 [ C(RESULT_ACCESS) ] = 0x0, 842 [ C(RESULT_MISS) ] = 0x0, 843 }, 844 }, 845}; 846 847#define SNB_DMND_DATA_RD (1ULL << 0) 848#define SNB_DMND_RFO (1ULL << 1) 849#define SNB_DMND_IFETCH (1ULL << 2) 850#define SNB_DMND_WB (1ULL << 3) 851#define SNB_PF_DATA_RD (1ULL << 4) 852#define SNB_PF_RFO (1ULL << 5) 853#define SNB_PF_IFETCH (1ULL << 6) 854#define SNB_LLC_DATA_RD (1ULL << 7) 855#define SNB_LLC_RFO (1ULL << 8) 856#define SNB_LLC_IFETCH (1ULL << 9) 857#define SNB_BUS_LOCKS (1ULL << 10) 858#define SNB_STRM_ST (1ULL << 11) 859#define SNB_OTHER (1ULL << 15) 860#define SNB_RESP_ANY (1ULL << 16) 861#define SNB_NO_SUPP (1ULL << 17) 862#define SNB_LLC_HITM (1ULL << 18) 863#define SNB_LLC_HITE (1ULL << 19) 864#define SNB_LLC_HITS (1ULL << 20) 865#define SNB_LLC_HITF (1ULL << 21) 866#define SNB_LOCAL (1ULL << 22) 867#define SNB_REMOTE (0xffULL << 23) 868#define SNB_SNP_NONE (1ULL << 31) 869#define SNB_SNP_NOT_NEEDED (1ULL << 32) 870#define SNB_SNP_MISS (1ULL << 33) 871#define SNB_NO_FWD (1ULL << 34) 872#define SNB_SNP_FWD (1ULL << 35) 873#define SNB_HITM (1ULL << 36) 874#define SNB_NON_DRAM (1ULL << 37) 875 876#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) 877#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) 878#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 879 880#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ 881 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ 882 SNB_HITM) 883 884#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) 885#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) 886 887#define SNB_L3_ACCESS SNB_RESP_ANY 888#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) 889 890static __initconst const u64 snb_hw_cache_extra_regs 891 [PERF_COUNT_HW_CACHE_MAX] 892 [PERF_COUNT_HW_CACHE_OP_MAX] 893 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 894{ 895 [ C(LL ) ] = { 896 [ C(OP_READ) ] = { 897 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS, 898 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS, 899 }, 900 [ C(OP_WRITE) ] = { 901 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS, 902 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS, 903 }, 904 [ C(OP_PREFETCH) ] = { 905 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS, 906 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS, 907 }, 908 }, 909 [ C(NODE) ] = { 910 [ C(OP_READ) ] = { 911 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY, 912 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE, 913 }, 914 [ C(OP_WRITE) ] = { 915 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY, 916 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE, 917 }, 918 [ C(OP_PREFETCH) ] = { 919 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY, 920 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE, 921 }, 922 }, 923}; 924 925static __initconst const u64 snb_hw_cache_event_ids 926 [PERF_COUNT_HW_CACHE_MAX] 927 [PERF_COUNT_HW_CACHE_OP_MAX] 928 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 929{ 930 [ C(L1D) ] = { 931 [ C(OP_READ) ] = { 932 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ 933 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ 934 }, 935 [ C(OP_WRITE) ] = { 936 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ 937 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ 938 }, 939 [ C(OP_PREFETCH) ] = { 940 [ C(RESULT_ACCESS) ] = 0x0, 941 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ 942 }, 943 }, 944 [ C(L1I ) ] = { 945 [ C(OP_READ) ] = { 946 [ C(RESULT_ACCESS) ] = 0x0, 947 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ 948 }, 949 [ C(OP_WRITE) ] = { 950 [ C(RESULT_ACCESS) ] = -1, 951 [ C(RESULT_MISS) ] = -1, 952 }, 953 [ C(OP_PREFETCH) ] = { 954 [ C(RESULT_ACCESS) ] = 0x0, 955 [ C(RESULT_MISS) ] = 0x0, 956 }, 957 }, 958 [ C(LL ) ] = { 959 [ C(OP_READ) ] = { 960 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 961 [ C(RESULT_ACCESS) ] = 0x01b7, 962 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 963 [ C(RESULT_MISS) ] = 0x01b7, 964 }, 965 [ C(OP_WRITE) ] = { 966 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 967 [ C(RESULT_ACCESS) ] = 0x01b7, 968 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 969 [ C(RESULT_MISS) ] = 0x01b7, 970 }, 971 [ C(OP_PREFETCH) ] = { 972 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 973 [ C(RESULT_ACCESS) ] = 0x01b7, 974 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 975 [ C(RESULT_MISS) ] = 0x01b7, 976 }, 977 }, 978 [ C(DTLB) ] = { 979 [ C(OP_READ) ] = { 980 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ 981 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ 982 }, 983 [ C(OP_WRITE) ] = { 984 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ 985 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 986 }, 987 [ C(OP_PREFETCH) ] = { 988 [ C(RESULT_ACCESS) ] = 0x0, 989 [ C(RESULT_MISS) ] = 0x0, 990 }, 991 }, 992 [ C(ITLB) ] = { 993 [ C(OP_READ) ] = { 994 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ 995 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ 996 }, 997 [ C(OP_WRITE) ] = { 998 [ C(RESULT_ACCESS) ] = -1, 999 [ C(RESULT_MISS) ] = -1, 1000 }, 1001 [ C(OP_PREFETCH) ] = { 1002 [ C(RESULT_ACCESS) ] = -1, 1003 [ C(RESULT_MISS) ] = -1, 1004 }, 1005 }, 1006 [ C(BPU ) ] = { 1007 [ C(OP_READ) ] = { 1008 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1009 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1010 }, 1011 [ C(OP_WRITE) ] = { 1012 [ C(RESULT_ACCESS) ] = -1, 1013 [ C(RESULT_MISS) ] = -1, 1014 }, 1015 [ C(OP_PREFETCH) ] = { 1016 [ C(RESULT_ACCESS) ] = -1, 1017 [ C(RESULT_MISS) ] = -1, 1018 }, 1019 }, 1020 [ C(NODE) ] = { 1021 [ C(OP_READ) ] = { 1022 [ C(RESULT_ACCESS) ] = 0x01b7, 1023 [ C(RESULT_MISS) ] = 0x01b7, 1024 }, 1025 [ C(OP_WRITE) ] = { 1026 [ C(RESULT_ACCESS) ] = 0x01b7, 1027 [ C(RESULT_MISS) ] = 0x01b7, 1028 }, 1029 [ C(OP_PREFETCH) ] = { 1030 [ C(RESULT_ACCESS) ] = 0x01b7, 1031 [ C(RESULT_MISS) ] = 0x01b7, 1032 }, 1033 }, 1034 1035}; 1036 1037/* 1038 * Notes on the events: 1039 * - data reads do not include code reads (comparable to earlier tables) 1040 * - data counts include speculative execution (except L1 write, dtlb, bpu) 1041 * - remote node access includes remote memory, remote cache, remote mmio. 1042 * - prefetches are not included in the counts because they are not 1043 * reliably counted. 1044 */ 1045 1046#define HSW_DEMAND_DATA_RD BIT_ULL(0) 1047#define HSW_DEMAND_RFO BIT_ULL(1) 1048#define HSW_ANY_RESPONSE BIT_ULL(16) 1049#define HSW_SUPPLIER_NONE BIT_ULL(17) 1050#define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22) 1051#define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27) 1052#define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28) 1053#define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29) 1054#define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \ 1055 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 1056 HSW_L3_MISS_REMOTE_HOP2P) 1057#define HSW_SNOOP_NONE BIT_ULL(31) 1058#define HSW_SNOOP_NOT_NEEDED BIT_ULL(32) 1059#define HSW_SNOOP_MISS BIT_ULL(33) 1060#define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34) 1061#define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35) 1062#define HSW_SNOOP_HITM BIT_ULL(36) 1063#define HSW_SNOOP_NON_DRAM BIT_ULL(37) 1064#define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \ 1065 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \ 1066 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \ 1067 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM) 1068#define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM) 1069#define HSW_DEMAND_READ HSW_DEMAND_DATA_RD 1070#define HSW_DEMAND_WRITE HSW_DEMAND_RFO 1071#define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\ 1072 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P) 1073#define HSW_LLC_ACCESS HSW_ANY_RESPONSE 1074 1075#define BDW_L3_MISS_LOCAL BIT(26) 1076#define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \ 1077 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \ 1078 HSW_L3_MISS_REMOTE_HOP2P) 1079 1080 1081static __initconst const u64 hsw_hw_cache_event_ids 1082 [PERF_COUNT_HW_CACHE_MAX] 1083 [PERF_COUNT_HW_CACHE_OP_MAX] 1084 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1085{ 1086 [ C(L1D ) ] = { 1087 [ C(OP_READ) ] = { 1088 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1089 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ 1090 }, 1091 [ C(OP_WRITE) ] = { 1092 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1093 [ C(RESULT_MISS) ] = 0x0, 1094 }, 1095 [ C(OP_PREFETCH) ] = { 1096 [ C(RESULT_ACCESS) ] = 0x0, 1097 [ C(RESULT_MISS) ] = 0x0, 1098 }, 1099 }, 1100 [ C(L1I ) ] = { 1101 [ C(OP_READ) ] = { 1102 [ C(RESULT_ACCESS) ] = 0x0, 1103 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ 1104 }, 1105 [ C(OP_WRITE) ] = { 1106 [ C(RESULT_ACCESS) ] = -1, 1107 [ C(RESULT_MISS) ] = -1, 1108 }, 1109 [ C(OP_PREFETCH) ] = { 1110 [ C(RESULT_ACCESS) ] = 0x0, 1111 [ C(RESULT_MISS) ] = 0x0, 1112 }, 1113 }, 1114 [ C(LL ) ] = { 1115 [ C(OP_READ) ] = { 1116 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1117 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1118 }, 1119 [ C(OP_WRITE) ] = { 1120 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1121 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1122 }, 1123 [ C(OP_PREFETCH) ] = { 1124 [ C(RESULT_ACCESS) ] = 0x0, 1125 [ C(RESULT_MISS) ] = 0x0, 1126 }, 1127 }, 1128 [ C(DTLB) ] = { 1129 [ C(OP_READ) ] = { 1130 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1131 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ 1132 }, 1133 [ C(OP_WRITE) ] = { 1134 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1135 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ 1136 }, 1137 [ C(OP_PREFETCH) ] = { 1138 [ C(RESULT_ACCESS) ] = 0x0, 1139 [ C(RESULT_MISS) ] = 0x0, 1140 }, 1141 }, 1142 [ C(ITLB) ] = { 1143 [ C(OP_READ) ] = { 1144 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ 1145 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ 1146 }, 1147 [ C(OP_WRITE) ] = { 1148 [ C(RESULT_ACCESS) ] = -1, 1149 [ C(RESULT_MISS) ] = -1, 1150 }, 1151 [ C(OP_PREFETCH) ] = { 1152 [ C(RESULT_ACCESS) ] = -1, 1153 [ C(RESULT_MISS) ] = -1, 1154 }, 1155 }, 1156 [ C(BPU ) ] = { 1157 [ C(OP_READ) ] = { 1158 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1159 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1160 }, 1161 [ C(OP_WRITE) ] = { 1162 [ C(RESULT_ACCESS) ] = -1, 1163 [ C(RESULT_MISS) ] = -1, 1164 }, 1165 [ C(OP_PREFETCH) ] = { 1166 [ C(RESULT_ACCESS) ] = -1, 1167 [ C(RESULT_MISS) ] = -1, 1168 }, 1169 }, 1170 [ C(NODE) ] = { 1171 [ C(OP_READ) ] = { 1172 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1173 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1174 }, 1175 [ C(OP_WRITE) ] = { 1176 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1177 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */ 1178 }, 1179 [ C(OP_PREFETCH) ] = { 1180 [ C(RESULT_ACCESS) ] = 0x0, 1181 [ C(RESULT_MISS) ] = 0x0, 1182 }, 1183 }, 1184}; 1185 1186static __initconst const u64 hsw_hw_cache_extra_regs 1187 [PERF_COUNT_HW_CACHE_MAX] 1188 [PERF_COUNT_HW_CACHE_OP_MAX] 1189 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1190{ 1191 [ C(LL ) ] = { 1192 [ C(OP_READ) ] = { 1193 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1194 HSW_LLC_ACCESS, 1195 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1196 HSW_L3_MISS|HSW_ANY_SNOOP, 1197 }, 1198 [ C(OP_WRITE) ] = { 1199 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1200 HSW_LLC_ACCESS, 1201 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1202 HSW_L3_MISS|HSW_ANY_SNOOP, 1203 }, 1204 [ C(OP_PREFETCH) ] = { 1205 [ C(RESULT_ACCESS) ] = 0x0, 1206 [ C(RESULT_MISS) ] = 0x0, 1207 }, 1208 }, 1209 [ C(NODE) ] = { 1210 [ C(OP_READ) ] = { 1211 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ| 1212 HSW_L3_MISS_LOCAL_DRAM| 1213 HSW_SNOOP_DRAM, 1214 [ C(RESULT_MISS) ] = HSW_DEMAND_READ| 1215 HSW_L3_MISS_REMOTE| 1216 HSW_SNOOP_DRAM, 1217 }, 1218 [ C(OP_WRITE) ] = { 1219 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE| 1220 HSW_L3_MISS_LOCAL_DRAM| 1221 HSW_SNOOP_DRAM, 1222 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE| 1223 HSW_L3_MISS_REMOTE| 1224 HSW_SNOOP_DRAM, 1225 }, 1226 [ C(OP_PREFETCH) ] = { 1227 [ C(RESULT_ACCESS) ] = 0x0, 1228 [ C(RESULT_MISS) ] = 0x0, 1229 }, 1230 }, 1231}; 1232 1233static __initconst const u64 westmere_hw_cache_event_ids 1234 [PERF_COUNT_HW_CACHE_MAX] 1235 [PERF_COUNT_HW_CACHE_OP_MAX] 1236 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1237{ 1238 [ C(L1D) ] = { 1239 [ C(OP_READ) ] = { 1240 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1241 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1242 }, 1243 [ C(OP_WRITE) ] = { 1244 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1245 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1246 }, 1247 [ C(OP_PREFETCH) ] = { 1248 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1249 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1250 }, 1251 }, 1252 [ C(L1I ) ] = { 1253 [ C(OP_READ) ] = { 1254 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1255 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1256 }, 1257 [ C(OP_WRITE) ] = { 1258 [ C(RESULT_ACCESS) ] = -1, 1259 [ C(RESULT_MISS) ] = -1, 1260 }, 1261 [ C(OP_PREFETCH) ] = { 1262 [ C(RESULT_ACCESS) ] = 0x0, 1263 [ C(RESULT_MISS) ] = 0x0, 1264 }, 1265 }, 1266 [ C(LL ) ] = { 1267 [ C(OP_READ) ] = { 1268 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1269 [ C(RESULT_ACCESS) ] = 0x01b7, 1270 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1271 [ C(RESULT_MISS) ] = 0x01b7, 1272 }, 1273 /* 1274 * Use RFO, not WRITEBACK, because a write miss would typically occur 1275 * on RFO. 1276 */ 1277 [ C(OP_WRITE) ] = { 1278 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1279 [ C(RESULT_ACCESS) ] = 0x01b7, 1280 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1281 [ C(RESULT_MISS) ] = 0x01b7, 1282 }, 1283 [ C(OP_PREFETCH) ] = { 1284 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1285 [ C(RESULT_ACCESS) ] = 0x01b7, 1286 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1287 [ C(RESULT_MISS) ] = 0x01b7, 1288 }, 1289 }, 1290 [ C(DTLB) ] = { 1291 [ C(OP_READ) ] = { 1292 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1293 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1294 }, 1295 [ C(OP_WRITE) ] = { 1296 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1297 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1298 }, 1299 [ C(OP_PREFETCH) ] = { 1300 [ C(RESULT_ACCESS) ] = 0x0, 1301 [ C(RESULT_MISS) ] = 0x0, 1302 }, 1303 }, 1304 [ C(ITLB) ] = { 1305 [ C(OP_READ) ] = { 1306 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1307 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ 1308 }, 1309 [ C(OP_WRITE) ] = { 1310 [ C(RESULT_ACCESS) ] = -1, 1311 [ C(RESULT_MISS) ] = -1, 1312 }, 1313 [ C(OP_PREFETCH) ] = { 1314 [ C(RESULT_ACCESS) ] = -1, 1315 [ C(RESULT_MISS) ] = -1, 1316 }, 1317 }, 1318 [ C(BPU ) ] = { 1319 [ C(OP_READ) ] = { 1320 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1321 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1322 }, 1323 [ C(OP_WRITE) ] = { 1324 [ C(RESULT_ACCESS) ] = -1, 1325 [ C(RESULT_MISS) ] = -1, 1326 }, 1327 [ C(OP_PREFETCH) ] = { 1328 [ C(RESULT_ACCESS) ] = -1, 1329 [ C(RESULT_MISS) ] = -1, 1330 }, 1331 }, 1332 [ C(NODE) ] = { 1333 [ C(OP_READ) ] = { 1334 [ C(RESULT_ACCESS) ] = 0x01b7, 1335 [ C(RESULT_MISS) ] = 0x01b7, 1336 }, 1337 [ C(OP_WRITE) ] = { 1338 [ C(RESULT_ACCESS) ] = 0x01b7, 1339 [ C(RESULT_MISS) ] = 0x01b7, 1340 }, 1341 [ C(OP_PREFETCH) ] = { 1342 [ C(RESULT_ACCESS) ] = 0x01b7, 1343 [ C(RESULT_MISS) ] = 0x01b7, 1344 }, 1345 }, 1346}; 1347 1348/* 1349 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; 1350 * See IA32 SDM Vol 3B 30.6.1.3 1351 */ 1352 1353#define NHM_DMND_DATA_RD (1 << 0) 1354#define NHM_DMND_RFO (1 << 1) 1355#define NHM_DMND_IFETCH (1 << 2) 1356#define NHM_DMND_WB (1 << 3) 1357#define NHM_PF_DATA_RD (1 << 4) 1358#define NHM_PF_DATA_RFO (1 << 5) 1359#define NHM_PF_IFETCH (1 << 6) 1360#define NHM_OFFCORE_OTHER (1 << 7) 1361#define NHM_UNCORE_HIT (1 << 8) 1362#define NHM_OTHER_CORE_HIT_SNP (1 << 9) 1363#define NHM_OTHER_CORE_HITM (1 << 10) 1364 /* reserved */ 1365#define NHM_REMOTE_CACHE_FWD (1 << 12) 1366#define NHM_REMOTE_DRAM (1 << 13) 1367#define NHM_LOCAL_DRAM (1 << 14) 1368#define NHM_NON_DRAM (1 << 15) 1369 1370#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) 1371#define NHM_REMOTE (NHM_REMOTE_DRAM) 1372 1373#define NHM_DMND_READ (NHM_DMND_DATA_RD) 1374#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) 1375#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) 1376 1377#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) 1378#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) 1379#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) 1380 1381static __initconst const u64 nehalem_hw_cache_extra_regs 1382 [PERF_COUNT_HW_CACHE_MAX] 1383 [PERF_COUNT_HW_CACHE_OP_MAX] 1384 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1385{ 1386 [ C(LL ) ] = { 1387 [ C(OP_READ) ] = { 1388 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, 1389 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, 1390 }, 1391 [ C(OP_WRITE) ] = { 1392 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, 1393 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, 1394 }, 1395 [ C(OP_PREFETCH) ] = { 1396 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, 1397 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, 1398 }, 1399 }, 1400 [ C(NODE) ] = { 1401 [ C(OP_READ) ] = { 1402 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, 1403 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, 1404 }, 1405 [ C(OP_WRITE) ] = { 1406 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, 1407 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, 1408 }, 1409 [ C(OP_PREFETCH) ] = { 1410 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, 1411 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, 1412 }, 1413 }, 1414}; 1415 1416static __initconst const u64 nehalem_hw_cache_event_ids 1417 [PERF_COUNT_HW_CACHE_MAX] 1418 [PERF_COUNT_HW_CACHE_OP_MAX] 1419 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1420{ 1421 [ C(L1D) ] = { 1422 [ C(OP_READ) ] = { 1423 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ 1424 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ 1425 }, 1426 [ C(OP_WRITE) ] = { 1427 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ 1428 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ 1429 }, 1430 [ C(OP_PREFETCH) ] = { 1431 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ 1432 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ 1433 }, 1434 }, 1435 [ C(L1I ) ] = { 1436 [ C(OP_READ) ] = { 1437 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1438 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1439 }, 1440 [ C(OP_WRITE) ] = { 1441 [ C(RESULT_ACCESS) ] = -1, 1442 [ C(RESULT_MISS) ] = -1, 1443 }, 1444 [ C(OP_PREFETCH) ] = { 1445 [ C(RESULT_ACCESS) ] = 0x0, 1446 [ C(RESULT_MISS) ] = 0x0, 1447 }, 1448 }, 1449 [ C(LL ) ] = { 1450 [ C(OP_READ) ] = { 1451 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1452 [ C(RESULT_ACCESS) ] = 0x01b7, 1453 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ 1454 [ C(RESULT_MISS) ] = 0x01b7, 1455 }, 1456 /* 1457 * Use RFO, not WRITEBACK, because a write miss would typically occur 1458 * on RFO. 1459 */ 1460 [ C(OP_WRITE) ] = { 1461 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1462 [ C(RESULT_ACCESS) ] = 0x01b7, 1463 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1464 [ C(RESULT_MISS) ] = 0x01b7, 1465 }, 1466 [ C(OP_PREFETCH) ] = { 1467 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1468 [ C(RESULT_ACCESS) ] = 0x01b7, 1469 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1470 [ C(RESULT_MISS) ] = 0x01b7, 1471 }, 1472 }, 1473 [ C(DTLB) ] = { 1474 [ C(OP_READ) ] = { 1475 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1476 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ 1477 }, 1478 [ C(OP_WRITE) ] = { 1479 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1480 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ 1481 }, 1482 [ C(OP_PREFETCH) ] = { 1483 [ C(RESULT_ACCESS) ] = 0x0, 1484 [ C(RESULT_MISS) ] = 0x0, 1485 }, 1486 }, 1487 [ C(ITLB) ] = { 1488 [ C(OP_READ) ] = { 1489 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ 1490 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ 1491 }, 1492 [ C(OP_WRITE) ] = { 1493 [ C(RESULT_ACCESS) ] = -1, 1494 [ C(RESULT_MISS) ] = -1, 1495 }, 1496 [ C(OP_PREFETCH) ] = { 1497 [ C(RESULT_ACCESS) ] = -1, 1498 [ C(RESULT_MISS) ] = -1, 1499 }, 1500 }, 1501 [ C(BPU ) ] = { 1502 [ C(OP_READ) ] = { 1503 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1504 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ 1505 }, 1506 [ C(OP_WRITE) ] = { 1507 [ C(RESULT_ACCESS) ] = -1, 1508 [ C(RESULT_MISS) ] = -1, 1509 }, 1510 [ C(OP_PREFETCH) ] = { 1511 [ C(RESULT_ACCESS) ] = -1, 1512 [ C(RESULT_MISS) ] = -1, 1513 }, 1514 }, 1515 [ C(NODE) ] = { 1516 [ C(OP_READ) ] = { 1517 [ C(RESULT_ACCESS) ] = 0x01b7, 1518 [ C(RESULT_MISS) ] = 0x01b7, 1519 }, 1520 [ C(OP_WRITE) ] = { 1521 [ C(RESULT_ACCESS) ] = 0x01b7, 1522 [ C(RESULT_MISS) ] = 0x01b7, 1523 }, 1524 [ C(OP_PREFETCH) ] = { 1525 [ C(RESULT_ACCESS) ] = 0x01b7, 1526 [ C(RESULT_MISS) ] = 0x01b7, 1527 }, 1528 }, 1529}; 1530 1531static __initconst const u64 core2_hw_cache_event_ids 1532 [PERF_COUNT_HW_CACHE_MAX] 1533 [PERF_COUNT_HW_CACHE_OP_MAX] 1534 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1535{ 1536 [ C(L1D) ] = { 1537 [ C(OP_READ) ] = { 1538 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ 1539 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ 1540 }, 1541 [ C(OP_WRITE) ] = { 1542 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ 1543 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ 1544 }, 1545 [ C(OP_PREFETCH) ] = { 1546 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ 1547 [ C(RESULT_MISS) ] = 0, 1548 }, 1549 }, 1550 [ C(L1I ) ] = { 1551 [ C(OP_READ) ] = { 1552 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ 1553 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ 1554 }, 1555 [ C(OP_WRITE) ] = { 1556 [ C(RESULT_ACCESS) ] = -1, 1557 [ C(RESULT_MISS) ] = -1, 1558 }, 1559 [ C(OP_PREFETCH) ] = { 1560 [ C(RESULT_ACCESS) ] = 0, 1561 [ C(RESULT_MISS) ] = 0, 1562 }, 1563 }, 1564 [ C(LL ) ] = { 1565 [ C(OP_READ) ] = { 1566 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1567 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1568 }, 1569 [ C(OP_WRITE) ] = { 1570 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1571 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1572 }, 1573 [ C(OP_PREFETCH) ] = { 1574 [ C(RESULT_ACCESS) ] = 0, 1575 [ C(RESULT_MISS) ] = 0, 1576 }, 1577 }, 1578 [ C(DTLB) ] = { 1579 [ C(OP_READ) ] = { 1580 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ 1581 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ 1582 }, 1583 [ C(OP_WRITE) ] = { 1584 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ 1585 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ 1586 }, 1587 [ C(OP_PREFETCH) ] = { 1588 [ C(RESULT_ACCESS) ] = 0, 1589 [ C(RESULT_MISS) ] = 0, 1590 }, 1591 }, 1592 [ C(ITLB) ] = { 1593 [ C(OP_READ) ] = { 1594 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1595 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ 1596 }, 1597 [ C(OP_WRITE) ] = { 1598 [ C(RESULT_ACCESS) ] = -1, 1599 [ C(RESULT_MISS) ] = -1, 1600 }, 1601 [ C(OP_PREFETCH) ] = { 1602 [ C(RESULT_ACCESS) ] = -1, 1603 [ C(RESULT_MISS) ] = -1, 1604 }, 1605 }, 1606 [ C(BPU ) ] = { 1607 [ C(OP_READ) ] = { 1608 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1609 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1610 }, 1611 [ C(OP_WRITE) ] = { 1612 [ C(RESULT_ACCESS) ] = -1, 1613 [ C(RESULT_MISS) ] = -1, 1614 }, 1615 [ C(OP_PREFETCH) ] = { 1616 [ C(RESULT_ACCESS) ] = -1, 1617 [ C(RESULT_MISS) ] = -1, 1618 }, 1619 }, 1620}; 1621 1622static __initconst const u64 atom_hw_cache_event_ids 1623 [PERF_COUNT_HW_CACHE_MAX] 1624 [PERF_COUNT_HW_CACHE_OP_MAX] 1625 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1626{ 1627 [ C(L1D) ] = { 1628 [ C(OP_READ) ] = { 1629 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ 1630 [ C(RESULT_MISS) ] = 0, 1631 }, 1632 [ C(OP_WRITE) ] = { 1633 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ 1634 [ C(RESULT_MISS) ] = 0, 1635 }, 1636 [ C(OP_PREFETCH) ] = { 1637 [ C(RESULT_ACCESS) ] = 0x0, 1638 [ C(RESULT_MISS) ] = 0, 1639 }, 1640 }, 1641 [ C(L1I ) ] = { 1642 [ C(OP_READ) ] = { 1643 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ 1644 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ 1645 }, 1646 [ C(OP_WRITE) ] = { 1647 [ C(RESULT_ACCESS) ] = -1, 1648 [ C(RESULT_MISS) ] = -1, 1649 }, 1650 [ C(OP_PREFETCH) ] = { 1651 [ C(RESULT_ACCESS) ] = 0, 1652 [ C(RESULT_MISS) ] = 0, 1653 }, 1654 }, 1655 [ C(LL ) ] = { 1656 [ C(OP_READ) ] = { 1657 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ 1658 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ 1659 }, 1660 [ C(OP_WRITE) ] = { 1661 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ 1662 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ 1663 }, 1664 [ C(OP_PREFETCH) ] = { 1665 [ C(RESULT_ACCESS) ] = 0, 1666 [ C(RESULT_MISS) ] = 0, 1667 }, 1668 }, 1669 [ C(DTLB) ] = { 1670 [ C(OP_READ) ] = { 1671 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ 1672 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ 1673 }, 1674 [ C(OP_WRITE) ] = { 1675 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ 1676 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ 1677 }, 1678 [ C(OP_PREFETCH) ] = { 1679 [ C(RESULT_ACCESS) ] = 0, 1680 [ C(RESULT_MISS) ] = 0, 1681 }, 1682 }, 1683 [ C(ITLB) ] = { 1684 [ C(OP_READ) ] = { 1685 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1686 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ 1687 }, 1688 [ C(OP_WRITE) ] = { 1689 [ C(RESULT_ACCESS) ] = -1, 1690 [ C(RESULT_MISS) ] = -1, 1691 }, 1692 [ C(OP_PREFETCH) ] = { 1693 [ C(RESULT_ACCESS) ] = -1, 1694 [ C(RESULT_MISS) ] = -1, 1695 }, 1696 }, 1697 [ C(BPU ) ] = { 1698 [ C(OP_READ) ] = { 1699 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1700 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1701 }, 1702 [ C(OP_WRITE) ] = { 1703 [ C(RESULT_ACCESS) ] = -1, 1704 [ C(RESULT_MISS) ] = -1, 1705 }, 1706 [ C(OP_PREFETCH) ] = { 1707 [ C(RESULT_ACCESS) ] = -1, 1708 [ C(RESULT_MISS) ] = -1, 1709 }, 1710 }, 1711}; 1712 1713EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c"); 1714EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2"); 1715/* no_alloc_cycles.not_delivered */ 1716EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm, 1717 "event=0xca,umask=0x50"); 1718EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2"); 1719/* uops_retired.all */ 1720EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm, 1721 "event=0xc2,umask=0x10"); 1722/* uops_retired.all */ 1723EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm, 1724 "event=0xc2,umask=0x10"); 1725 1726static struct attribute *slm_events_attrs[] = { 1727 EVENT_PTR(td_total_slots_slm), 1728 EVENT_PTR(td_total_slots_scale_slm), 1729 EVENT_PTR(td_fetch_bubbles_slm), 1730 EVENT_PTR(td_fetch_bubbles_scale_slm), 1731 EVENT_PTR(td_slots_issued_slm), 1732 EVENT_PTR(td_slots_retired_slm), 1733 NULL 1734}; 1735 1736static struct extra_reg intel_slm_extra_regs[] __read_mostly = 1737{ 1738 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1739 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0), 1740 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1), 1741 EVENT_EXTRA_END 1742}; 1743 1744#define SLM_DMND_READ SNB_DMND_DATA_RD 1745#define SLM_DMND_WRITE SNB_DMND_RFO 1746#define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1747 1748#define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM) 1749#define SLM_LLC_ACCESS SNB_RESP_ANY 1750#define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM) 1751 1752static __initconst const u64 slm_hw_cache_extra_regs 1753 [PERF_COUNT_HW_CACHE_MAX] 1754 [PERF_COUNT_HW_CACHE_OP_MAX] 1755 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1756{ 1757 [ C(LL ) ] = { 1758 [ C(OP_READ) ] = { 1759 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS, 1760 [ C(RESULT_MISS) ] = 0, 1761 }, 1762 [ C(OP_WRITE) ] = { 1763 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS, 1764 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS, 1765 }, 1766 [ C(OP_PREFETCH) ] = { 1767 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS, 1768 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS, 1769 }, 1770 }, 1771}; 1772 1773static __initconst const u64 slm_hw_cache_event_ids 1774 [PERF_COUNT_HW_CACHE_MAX] 1775 [PERF_COUNT_HW_CACHE_OP_MAX] 1776 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 1777{ 1778 [ C(L1D) ] = { 1779 [ C(OP_READ) ] = { 1780 [ C(RESULT_ACCESS) ] = 0, 1781 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */ 1782 }, 1783 [ C(OP_WRITE) ] = { 1784 [ C(RESULT_ACCESS) ] = 0, 1785 [ C(RESULT_MISS) ] = 0, 1786 }, 1787 [ C(OP_PREFETCH) ] = { 1788 [ C(RESULT_ACCESS) ] = 0, 1789 [ C(RESULT_MISS) ] = 0, 1790 }, 1791 }, 1792 [ C(L1I ) ] = { 1793 [ C(OP_READ) ] = { 1794 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */ 1795 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */ 1796 }, 1797 [ C(OP_WRITE) ] = { 1798 [ C(RESULT_ACCESS) ] = -1, 1799 [ C(RESULT_MISS) ] = -1, 1800 }, 1801 [ C(OP_PREFETCH) ] = { 1802 [ C(RESULT_ACCESS) ] = 0, 1803 [ C(RESULT_MISS) ] = 0, 1804 }, 1805 }, 1806 [ C(LL ) ] = { 1807 [ C(OP_READ) ] = { 1808 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ 1809 [ C(RESULT_ACCESS) ] = 0x01b7, 1810 [ C(RESULT_MISS) ] = 0, 1811 }, 1812 [ C(OP_WRITE) ] = { 1813 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ 1814 [ C(RESULT_ACCESS) ] = 0x01b7, 1815 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ 1816 [ C(RESULT_MISS) ] = 0x01b7, 1817 }, 1818 [ C(OP_PREFETCH) ] = { 1819 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ 1820 [ C(RESULT_ACCESS) ] = 0x01b7, 1821 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ 1822 [ C(RESULT_MISS) ] = 0x01b7, 1823 }, 1824 }, 1825 [ C(DTLB) ] = { 1826 [ C(OP_READ) ] = { 1827 [ C(RESULT_ACCESS) ] = 0, 1828 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */ 1829 }, 1830 [ C(OP_WRITE) ] = { 1831 [ C(RESULT_ACCESS) ] = 0, 1832 [ C(RESULT_MISS) ] = 0, 1833 }, 1834 [ C(OP_PREFETCH) ] = { 1835 [ C(RESULT_ACCESS) ] = 0, 1836 [ C(RESULT_MISS) ] = 0, 1837 }, 1838 }, 1839 [ C(ITLB) ] = { 1840 [ C(OP_READ) ] = { 1841 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ 1842 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */ 1843 }, 1844 [ C(OP_WRITE) ] = { 1845 [ C(RESULT_ACCESS) ] = -1, 1846 [ C(RESULT_MISS) ] = -1, 1847 }, 1848 [ C(OP_PREFETCH) ] = { 1849 [ C(RESULT_ACCESS) ] = -1, 1850 [ C(RESULT_MISS) ] = -1, 1851 }, 1852 }, 1853 [ C(BPU ) ] = { 1854 [ C(OP_READ) ] = { 1855 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ 1856 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ 1857 }, 1858 [ C(OP_WRITE) ] = { 1859 [ C(RESULT_ACCESS) ] = -1, 1860 [ C(RESULT_MISS) ] = -1, 1861 }, 1862 [ C(OP_PREFETCH) ] = { 1863 [ C(RESULT_ACCESS) ] = -1, 1864 [ C(RESULT_MISS) ] = -1, 1865 }, 1866 }, 1867}; 1868 1869EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); 1870EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); 1871/* UOPS_NOT_DELIVERED.ANY */ 1872EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); 1873/* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ 1874EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); 1875/* UOPS_RETIRED.ANY */ 1876EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); 1877/* UOPS_ISSUED.ANY */ 1878EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); 1879 1880static struct attribute *glm_events_attrs[] = { 1881 EVENT_PTR(td_total_slots_glm), 1882 EVENT_PTR(td_total_slots_scale_glm), 1883 EVENT_PTR(td_fetch_bubbles_glm), 1884 EVENT_PTR(td_recovery_bubbles_glm), 1885 EVENT_PTR(td_slots_issued_glm), 1886 EVENT_PTR(td_slots_retired_glm), 1887 NULL 1888}; 1889 1890static struct extra_reg intel_glm_extra_regs[] __read_mostly = { 1891 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 1892 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), 1893 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1), 1894 EVENT_EXTRA_END 1895}; 1896 1897#define GLM_DEMAND_DATA_RD BIT_ULL(0) 1898#define GLM_DEMAND_RFO BIT_ULL(1) 1899#define GLM_ANY_RESPONSE BIT_ULL(16) 1900#define GLM_SNP_NONE_OR_MISS BIT_ULL(33) 1901#define GLM_DEMAND_READ GLM_DEMAND_DATA_RD 1902#define GLM_DEMAND_WRITE GLM_DEMAND_RFO 1903#define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) 1904#define GLM_LLC_ACCESS GLM_ANY_RESPONSE 1905#define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM) 1906#define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM) 1907 1908static __initconst const u64 glm_hw_cache_event_ids 1909 [PERF_COUNT_HW_CACHE_MAX] 1910 [PERF_COUNT_HW_CACHE_OP_MAX] 1911 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1912 [C(L1D)] = { 1913 [C(OP_READ)] = { 1914 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1915 [C(RESULT_MISS)] = 0x0, 1916 }, 1917 [C(OP_WRITE)] = { 1918 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1919 [C(RESULT_MISS)] = 0x0, 1920 }, 1921 [C(OP_PREFETCH)] = { 1922 [C(RESULT_ACCESS)] = 0x0, 1923 [C(RESULT_MISS)] = 0x0, 1924 }, 1925 }, 1926 [C(L1I)] = { 1927 [C(OP_READ)] = { 1928 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1929 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1930 }, 1931 [C(OP_WRITE)] = { 1932 [C(RESULT_ACCESS)] = -1, 1933 [C(RESULT_MISS)] = -1, 1934 }, 1935 [C(OP_PREFETCH)] = { 1936 [C(RESULT_ACCESS)] = 0x0, 1937 [C(RESULT_MISS)] = 0x0, 1938 }, 1939 }, 1940 [C(LL)] = { 1941 [C(OP_READ)] = { 1942 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1943 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1944 }, 1945 [C(OP_WRITE)] = { 1946 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1947 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1948 }, 1949 [C(OP_PREFETCH)] = { 1950 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1951 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1952 }, 1953 }, 1954 [C(DTLB)] = { 1955 [C(OP_READ)] = { 1956 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1957 [C(RESULT_MISS)] = 0x0, 1958 }, 1959 [C(OP_WRITE)] = { 1960 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1961 [C(RESULT_MISS)] = 0x0, 1962 }, 1963 [C(OP_PREFETCH)] = { 1964 [C(RESULT_ACCESS)] = 0x0, 1965 [C(RESULT_MISS)] = 0x0, 1966 }, 1967 }, 1968 [C(ITLB)] = { 1969 [C(OP_READ)] = { 1970 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1971 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1972 }, 1973 [C(OP_WRITE)] = { 1974 [C(RESULT_ACCESS)] = -1, 1975 [C(RESULT_MISS)] = -1, 1976 }, 1977 [C(OP_PREFETCH)] = { 1978 [C(RESULT_ACCESS)] = -1, 1979 [C(RESULT_MISS)] = -1, 1980 }, 1981 }, 1982 [C(BPU)] = { 1983 [C(OP_READ)] = { 1984 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1985 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1986 }, 1987 [C(OP_WRITE)] = { 1988 [C(RESULT_ACCESS)] = -1, 1989 [C(RESULT_MISS)] = -1, 1990 }, 1991 [C(OP_PREFETCH)] = { 1992 [C(RESULT_ACCESS)] = -1, 1993 [C(RESULT_MISS)] = -1, 1994 }, 1995 }, 1996}; 1997 1998static __initconst const u64 glm_hw_cache_extra_regs 1999 [PERF_COUNT_HW_CACHE_MAX] 2000 [PERF_COUNT_HW_CACHE_OP_MAX] 2001 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2002 [C(LL)] = { 2003 [C(OP_READ)] = { 2004 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2005 GLM_LLC_ACCESS, 2006 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2007 GLM_LLC_MISS, 2008 }, 2009 [C(OP_WRITE)] = { 2010 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2011 GLM_LLC_ACCESS, 2012 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2013 GLM_LLC_MISS, 2014 }, 2015 [C(OP_PREFETCH)] = { 2016 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH| 2017 GLM_LLC_ACCESS, 2018 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH| 2019 GLM_LLC_MISS, 2020 }, 2021 }, 2022}; 2023 2024static __initconst const u64 glp_hw_cache_event_ids 2025 [PERF_COUNT_HW_CACHE_MAX] 2026 [PERF_COUNT_HW_CACHE_OP_MAX] 2027 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2028 [C(L1D)] = { 2029 [C(OP_READ)] = { 2030 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2031 [C(RESULT_MISS)] = 0x0, 2032 }, 2033 [C(OP_WRITE)] = { 2034 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2035 [C(RESULT_MISS)] = 0x0, 2036 }, 2037 [C(OP_PREFETCH)] = { 2038 [C(RESULT_ACCESS)] = 0x0, 2039 [C(RESULT_MISS)] = 0x0, 2040 }, 2041 }, 2042 [C(L1I)] = { 2043 [C(OP_READ)] = { 2044 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 2045 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 2046 }, 2047 [C(OP_WRITE)] = { 2048 [C(RESULT_ACCESS)] = -1, 2049 [C(RESULT_MISS)] = -1, 2050 }, 2051 [C(OP_PREFETCH)] = { 2052 [C(RESULT_ACCESS)] = 0x0, 2053 [C(RESULT_MISS)] = 0x0, 2054 }, 2055 }, 2056 [C(LL)] = { 2057 [C(OP_READ)] = { 2058 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2059 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2060 }, 2061 [C(OP_WRITE)] = { 2062 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2063 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 2064 }, 2065 [C(OP_PREFETCH)] = { 2066 [C(RESULT_ACCESS)] = 0x0, 2067 [C(RESULT_MISS)] = 0x0, 2068 }, 2069 }, 2070 [C(DTLB)] = { 2071 [C(OP_READ)] = { 2072 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 2073 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 2074 }, 2075 [C(OP_WRITE)] = { 2076 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 2077 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 2078 }, 2079 [C(OP_PREFETCH)] = { 2080 [C(RESULT_ACCESS)] = 0x0, 2081 [C(RESULT_MISS)] = 0x0, 2082 }, 2083 }, 2084 [C(ITLB)] = { 2085 [C(OP_READ)] = { 2086 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 2087 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 2088 }, 2089 [C(OP_WRITE)] = { 2090 [C(RESULT_ACCESS)] = -1, 2091 [C(RESULT_MISS)] = -1, 2092 }, 2093 [C(OP_PREFETCH)] = { 2094 [C(RESULT_ACCESS)] = -1, 2095 [C(RESULT_MISS)] = -1, 2096 }, 2097 }, 2098 [C(BPU)] = { 2099 [C(OP_READ)] = { 2100 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 2101 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 2102 }, 2103 [C(OP_WRITE)] = { 2104 [C(RESULT_ACCESS)] = -1, 2105 [C(RESULT_MISS)] = -1, 2106 }, 2107 [C(OP_PREFETCH)] = { 2108 [C(RESULT_ACCESS)] = -1, 2109 [C(RESULT_MISS)] = -1, 2110 }, 2111 }, 2112}; 2113 2114static __initconst const u64 glp_hw_cache_extra_regs 2115 [PERF_COUNT_HW_CACHE_MAX] 2116 [PERF_COUNT_HW_CACHE_OP_MAX] 2117 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2118 [C(LL)] = { 2119 [C(OP_READ)] = { 2120 [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 2121 GLM_LLC_ACCESS, 2122 [C(RESULT_MISS)] = GLM_DEMAND_READ| 2123 GLM_LLC_MISS, 2124 }, 2125 [C(OP_WRITE)] = { 2126 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 2127 GLM_LLC_ACCESS, 2128 [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 2129 GLM_LLC_MISS, 2130 }, 2131 [C(OP_PREFETCH)] = { 2132 [C(RESULT_ACCESS)] = 0x0, 2133 [C(RESULT_MISS)] = 0x0, 2134 }, 2135 }, 2136}; 2137 2138#define TNT_LOCAL_DRAM BIT_ULL(26) 2139#define TNT_DEMAND_READ GLM_DEMAND_DATA_RD 2140#define TNT_DEMAND_WRITE GLM_DEMAND_RFO 2141#define TNT_LLC_ACCESS GLM_ANY_RESPONSE 2142#define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ 2143 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) 2144#define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) 2145 2146static __initconst const u64 tnt_hw_cache_extra_regs 2147 [PERF_COUNT_HW_CACHE_MAX] 2148 [PERF_COUNT_HW_CACHE_OP_MAX] 2149 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2150 [C(LL)] = { 2151 [C(OP_READ)] = { 2152 [C(RESULT_ACCESS)] = TNT_DEMAND_READ| 2153 TNT_LLC_ACCESS, 2154 [C(RESULT_MISS)] = TNT_DEMAND_READ| 2155 TNT_LLC_MISS, 2156 }, 2157 [C(OP_WRITE)] = { 2158 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| 2159 TNT_LLC_ACCESS, 2160 [C(RESULT_MISS)] = TNT_DEMAND_WRITE| 2161 TNT_LLC_MISS, 2162 }, 2163 [C(OP_PREFETCH)] = { 2164 [C(RESULT_ACCESS)] = 0x0, 2165 [C(RESULT_MISS)] = 0x0, 2166 }, 2167 }, 2168}; 2169 2170EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0"); 2171EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0"); 2172EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6"); 2173EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0"); 2174 2175static struct attribute *tnt_events_attrs[] = { 2176 EVENT_PTR(td_fe_bound_tnt), 2177 EVENT_PTR(td_retiring_tnt), 2178 EVENT_PTR(td_bad_spec_tnt), 2179 EVENT_PTR(td_be_bound_tnt), 2180 NULL, 2181}; 2182 2183static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { 2184 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2185 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), 2186 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), 2187 EVENT_EXTRA_END 2188}; 2189 2190EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3"); 2191EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6"); 2192 2193static struct attribute *grt_mem_attrs[] = { 2194 EVENT_PTR(mem_ld_grt), 2195 EVENT_PTR(mem_st_grt), 2196 NULL 2197}; 2198 2199static struct extra_reg intel_grt_extra_regs[] __read_mostly = { 2200 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2201 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), 2202 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), 2203 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2204 EVENT_EXTRA_END 2205}; 2206 2207EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0"); 2208EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0"); 2209 2210static struct attribute *cmt_events_attrs[] = { 2211 EVENT_PTR(td_fe_bound_tnt), 2212 EVENT_PTR(td_retiring_cmt), 2213 EVENT_PTR(td_bad_spec_cmt), 2214 EVENT_PTR(td_be_bound_tnt), 2215 NULL 2216}; 2217 2218static struct extra_reg intel_cmt_extra_regs[] __read_mostly = { 2219 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ 2220 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0), 2221 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1), 2222 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), 2223 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0), 2224 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1), 2225 EVENT_EXTRA_END 2226}; 2227 2228EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_skt, "event=0x9c,umask=0x01"); 2229EVENT_ATTR_STR(topdown-retiring, td_retiring_skt, "event=0xc2,umask=0x02"); 2230EVENT_ATTR_STR(topdown-be-bound, td_be_bound_skt, "event=0xa4,umask=0x02"); 2231 2232static struct attribute *skt_events_attrs[] = { 2233 EVENT_PTR(td_fe_bound_skt), 2234 EVENT_PTR(td_retiring_skt), 2235 EVENT_PTR(td_bad_spec_cmt), 2236 EVENT_PTR(td_be_bound_skt), 2237 NULL, 2238}; 2239 2240#define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 2241#define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 2242#define KNL_MCDRAM_LOCAL BIT_ULL(21) 2243#define KNL_MCDRAM_FAR BIT_ULL(22) 2244#define KNL_DDR_LOCAL BIT_ULL(23) 2245#define KNL_DDR_FAR BIT_ULL(24) 2246#define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \ 2247 KNL_DDR_LOCAL | KNL_DDR_FAR) 2248#define KNL_L2_READ SLM_DMND_READ 2249#define KNL_L2_WRITE SLM_DMND_WRITE 2250#define KNL_L2_PREFETCH SLM_DMND_PREFETCH 2251#define KNL_L2_ACCESS SLM_LLC_ACCESS 2252#define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \ 2253 KNL_DRAM_ANY | SNB_SNP_ANY | \ 2254 SNB_NON_DRAM) 2255 2256static __initconst const u64 knl_hw_cache_extra_regs 2257 [PERF_COUNT_HW_CACHE_MAX] 2258 [PERF_COUNT_HW_CACHE_OP_MAX] 2259 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 2260 [C(LL)] = { 2261 [C(OP_READ)] = { 2262 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS, 2263 [C(RESULT_MISS)] = 0, 2264 }, 2265 [C(OP_WRITE)] = { 2266 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS, 2267 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS, 2268 }, 2269 [C(OP_PREFETCH)] = { 2270 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS, 2271 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS, 2272 }, 2273 }, 2274}; 2275 2276/* 2277 * Used from PMIs where the LBRs are already disabled. 2278 * 2279 * This function could be called consecutively. It is required to remain in 2280 * disabled state if called consecutively. 2281 * 2282 * During consecutive calls, the same disable value will be written to related 2283 * registers, so the PMU state remains unchanged. 2284 * 2285 * intel_bts events don't coexist with intel PMU's BTS events because of 2286 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them 2287 * disabled around intel PMU's event batching etc, only inside the PMI handler. 2288 * 2289 * Avoid PEBS_ENABLE MSR access in PMIs. 2290 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore. 2291 * It doesn't matter if the PEBS is enabled or not. 2292 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to 2293 * access PEBS_ENABLE MSR in disable_all()/enable_all(). 2294 * However, there are some cases which may change PEBS status, e.g. PMI 2295 * throttle. The PEBS_ENABLE should be updated where the status changes. 2296 */ 2297static __always_inline void __intel_pmu_disable_all(bool bts) 2298{ 2299 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2300 2301 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2302 2303 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2304 intel_pmu_disable_bts(); 2305} 2306 2307static __always_inline void intel_pmu_disable_all(void) 2308{ 2309 __intel_pmu_disable_all(true); 2310 static_call_cond(x86_pmu_pebs_disable_all)(); 2311 intel_pmu_lbr_disable_all(); 2312} 2313 2314static void __intel_pmu_enable_all(int added, bool pmi) 2315{ 2316 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2317 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 2318 2319 intel_pmu_lbr_enable_all(pmi); 2320 2321 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) { 2322 wrmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val); 2323 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val; 2324 } 2325 2326 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 2327 intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2328 2329 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { 2330 struct perf_event *event = 2331 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 2332 2333 if (WARN_ON_ONCE(!event)) 2334 return; 2335 2336 intel_pmu_enable_bts(event->hw.config); 2337 } 2338} 2339 2340static void intel_pmu_enable_all(int added) 2341{ 2342 static_call_cond(x86_pmu_pebs_enable_all)(); 2343 __intel_pmu_enable_all(added, false); 2344} 2345 2346static noinline int 2347__intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, 2348 unsigned int cnt, unsigned long flags) 2349{ 2350 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2351 2352 intel_pmu_lbr_read(); 2353 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr); 2354 2355 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt); 2356 intel_pmu_enable_all(0); 2357 local_irq_restore(flags); 2358 return cnt; 2359} 2360 2361static int 2362intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2363{ 2364 unsigned long flags; 2365 2366 /* must not have branches... */ 2367 local_irq_save(flags); 2368 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2369 __intel_pmu_lbr_disable(); 2370 /* ... until here */ 2371 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2372} 2373 2374static int 2375intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt) 2376{ 2377 unsigned long flags; 2378 2379 /* must not have branches... */ 2380 local_irq_save(flags); 2381 __intel_pmu_disable_all(false); /* we don't care about BTS */ 2382 __intel_pmu_arch_lbr_disable(); 2383 /* ... until here */ 2384 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags); 2385} 2386 2387/* 2388 * Workaround for: 2389 * Intel Errata AAK100 (model 26) 2390 * Intel Errata AAP53 (model 30) 2391 * Intel Errata BD53 (model 44) 2392 * 2393 * The official story: 2394 * These chips need to be 'reset' when adding counters by programming the 2395 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either 2396 * in sequence on the same PMC or on different PMCs. 2397 * 2398 * In practice it appears some of these events do in fact count, and 2399 * we need to program all 4 events. 2400 */ 2401static void intel_pmu_nhm_workaround(void) 2402{ 2403 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2404 static const unsigned long nhm_magic[4] = { 2405 0x4300B5, 2406 0x4300D2, 2407 0x4300B1, 2408 0x4300B1 2409 }; 2410 struct perf_event *event; 2411 int i; 2412 2413 /* 2414 * The Errata requires below steps: 2415 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; 2416 * 2) Configure 4 PERFEVTSELx with the magic events and clear 2417 * the corresponding PMCx; 2418 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; 2419 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; 2420 * 5) Clear 4 pairs of ERFEVTSELx and PMCx; 2421 */ 2422 2423 /* 2424 * The real steps we choose are a little different from above. 2425 * A) To reduce MSR operations, we don't run step 1) as they 2426 * are already cleared before this function is called; 2427 * B) Call x86_perf_event_update to save PMCx before configuring 2428 * PERFEVTSELx with magic number; 2429 * C) With step 5), we do clear only when the PERFEVTSELx is 2430 * not used currently. 2431 * D) Call x86_perf_event_set_period to restore PMCx; 2432 */ 2433 2434 /* We always operate 4 pairs of PERF Counters */ 2435 for (i = 0; i < 4; i++) { 2436 event = cpuc->events[i]; 2437 if (event) 2438 static_call(x86_pmu_update)(event); 2439 } 2440 2441 for (i = 0; i < 4; i++) { 2442 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2443 wrmsrq(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2444 } 2445 2446 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2447 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2448 2449 for (i = 0; i < 4; i++) { 2450 event = cpuc->events[i]; 2451 2452 if (event) { 2453 static_call(x86_pmu_set_period)(event); 2454 __x86_pmu_enable_event(&event->hw, 2455 ARCH_PERFMON_EVENTSEL_ENABLE); 2456 } else 2457 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2458 } 2459} 2460 2461static void intel_pmu_nhm_enable_all(int added) 2462{ 2463 if (added) 2464 intel_pmu_nhm_workaround(); 2465 intel_pmu_enable_all(added); 2466} 2467 2468static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on) 2469{ 2470 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0; 2471 2472 if (cpuc->tfa_shadow != val) { 2473 cpuc->tfa_shadow = val; 2474 wrmsrq(MSR_TSX_FORCE_ABORT, val); 2475 } 2476} 2477 2478static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 2479{ 2480 /* 2481 * We're going to use PMC3, make sure TFA is set before we touch it. 2482 */ 2483 if (cntr == 3) 2484 intel_set_tfa(cpuc, true); 2485} 2486 2487static void intel_tfa_pmu_enable_all(int added) 2488{ 2489 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2490 2491 /* 2492 * If we find PMC3 is no longer used when we enable the PMU, we can 2493 * clear TFA. 2494 */ 2495 if (!test_bit(3, cpuc->active_mask)) 2496 intel_set_tfa(cpuc, false); 2497 2498 intel_pmu_enable_all(added); 2499} 2500 2501static inline u64 intel_pmu_get_status(void) 2502{ 2503 u64 status; 2504 2505 rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status); 2506 2507 return status; 2508} 2509 2510static inline void intel_pmu_ack_status(u64 ack) 2511{ 2512 wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2513} 2514 2515static inline bool event_is_checkpointed(struct perf_event *event) 2516{ 2517 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0; 2518} 2519 2520static inline void intel_set_masks(struct perf_event *event, int idx) 2521{ 2522 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2523 2524 if (event->attr.exclude_host) 2525 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2526 if (event->attr.exclude_guest) 2527 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2528 if (event_is_checkpointed(event)) 2529 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2530} 2531 2532static inline void intel_clear_masks(struct perf_event *event, int idx) 2533{ 2534 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2535 2536 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask); 2537 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask); 2538 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status); 2539} 2540 2541static void intel_pmu_disable_fixed(struct perf_event *event) 2542{ 2543 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2544 struct hw_perf_event *hwc = &event->hw; 2545 int idx = hwc->idx; 2546 u64 mask; 2547 2548 if (is_topdown_idx(idx)) { 2549 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2550 2551 /* 2552 * When there are other active TopDown events, 2553 * don't disable the fixed counter 3. 2554 */ 2555 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2556 return; 2557 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2558 } 2559 2560 intel_clear_masks(event, idx); 2561 2562 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK); 2563 cpuc->fixed_ctrl_val &= ~mask; 2564} 2565 2566static inline void __intel_pmu_update_event_ext(int idx, u64 ext) 2567{ 2568 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2569 u32 msr; 2570 2571 if (idx < INTEL_PMC_IDX_FIXED) { 2572 msr = MSR_IA32_PMC_V6_GP0_CFG_C + 2573 x86_pmu.addr_offset(idx, false); 2574 } else { 2575 msr = MSR_IA32_PMC_V6_FX0_CFG_C + 2576 x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false); 2577 } 2578 2579 cpuc->cfg_c_val[idx] = ext; 2580 wrmsrq(msr, ext); 2581} 2582 2583static void intel_pmu_disable_event_ext(struct perf_event *event) 2584{ 2585 /* 2586 * Only clear CFG_C MSR for PEBS counter group events, 2587 * it avoids the HW counter's value to be added into 2588 * other PEBS records incorrectly after PEBS counter 2589 * group events are disabled. 2590 * 2591 * For other events, it's unnecessary to clear CFG_C MSRs 2592 * since CFG_C doesn't take effect if counter is in 2593 * disabled state. That helps to reduce the WRMSR overhead 2594 * in context switches. 2595 */ 2596 if (!is_pebs_counter_event_group(event)) 2597 return; 2598 2599 __intel_pmu_update_event_ext(event->hw.idx, 0); 2600} 2601 2602DEFINE_STATIC_CALL_NULL(intel_pmu_disable_event_ext, intel_pmu_disable_event_ext); 2603 2604static void intel_pmu_disable_event(struct perf_event *event) 2605{ 2606 struct hw_perf_event *hwc = &event->hw; 2607 int idx = hwc->idx; 2608 2609 switch (idx) { 2610 case 0 ... INTEL_PMC_IDX_FIXED - 1: 2611 intel_clear_masks(event, idx); 2612 static_call_cond(intel_pmu_disable_event_ext)(event); 2613 x86_pmu_disable_event(event); 2614 break; 2615 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 2616 static_call_cond(intel_pmu_disable_event_ext)(event); 2617 fallthrough; 2618 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 2619 intel_pmu_disable_fixed(event); 2620 break; 2621 case INTEL_PMC_IDX_FIXED_BTS: 2622 intel_pmu_disable_bts(); 2623 intel_pmu_drain_bts_buffer(); 2624 return; 2625 case INTEL_PMC_IDX_FIXED_VLBR: 2626 intel_clear_masks(event, idx); 2627 break; 2628 default: 2629 intel_clear_masks(event, idx); 2630 pr_warn("Failed to disable the event with invalid index %d\n", 2631 idx); 2632 return; 2633 } 2634 2635 /* 2636 * Needs to be called after x86_pmu_disable_event, 2637 * so we don't trigger the event without PEBS bit set. 2638 */ 2639 if (unlikely(event->attr.precise_ip)) 2640 static_call(x86_pmu_pebs_disable)(event); 2641} 2642 2643static void intel_pmu_assign_event(struct perf_event *event, int idx) 2644{ 2645 if (is_pebs_pt(event)) 2646 perf_report_aux_output_id(event, idx); 2647} 2648 2649static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event) 2650{ 2651 return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK; 2652} 2653 2654static void intel_pmu_del_event(struct perf_event *event) 2655{ 2656 if (intel_pmu_needs_branch_stack(event)) 2657 intel_pmu_lbr_del(event); 2658 if (event->attr.precise_ip) 2659 intel_pmu_pebs_del(event); 2660 if (is_pebs_counter_event_group(event) || 2661 is_acr_event_group(event)) 2662 this_cpu_ptr(&cpu_hw_events)->n_late_setup--; 2663} 2664 2665static int icl_set_topdown_event_period(struct perf_event *event) 2666{ 2667 struct hw_perf_event *hwc = &event->hw; 2668 s64 left = local64_read(&hwc->period_left); 2669 2670 /* 2671 * The values in PERF_METRICS MSR are derived from fixed counter 3. 2672 * Software should start both registers, PERF_METRICS and fixed 2673 * counter 3, from zero. 2674 * Clear PERF_METRICS and Fixed counter 3 in initialization. 2675 * After that, both MSRs will be cleared for each read. 2676 * Don't need to clear them again. 2677 */ 2678 if (left == x86_pmu.max_period) { 2679 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0); 2680 wrmsrq(MSR_PERF_METRICS, 0); 2681 hwc->saved_slots = 0; 2682 hwc->saved_metric = 0; 2683 } 2684 2685 if ((hwc->saved_slots) && is_slots_event(event)) { 2686 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 2687 wrmsrq(MSR_PERF_METRICS, hwc->saved_metric); 2688 } 2689 2690 perf_event_update_userpage(event); 2691 2692 return 0; 2693} 2694 2695DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period); 2696 2697static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx) 2698{ 2699 u32 val; 2700 2701 /* 2702 * The metric is reported as an 8bit integer fraction 2703 * summing up to 0xff. 2704 * slots-in-metric = (Metric / 0xff) * slots 2705 */ 2706 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff; 2707 return mul_u64_u32_div(slots, val, 0xff); 2708} 2709 2710static u64 icl_get_topdown_value(struct perf_event *event, 2711 u64 slots, u64 metrics) 2712{ 2713 int idx = event->hw.idx; 2714 u64 delta; 2715 2716 if (is_metric_idx(idx)) 2717 delta = icl_get_metrics_event_value(metrics, slots, idx); 2718 else 2719 delta = slots; 2720 2721 return delta; 2722} 2723 2724static void __icl_update_topdown_event(struct perf_event *event, 2725 u64 slots, u64 metrics, 2726 u64 last_slots, u64 last_metrics) 2727{ 2728 u64 delta, last = 0; 2729 2730 delta = icl_get_topdown_value(event, slots, metrics); 2731 if (last_slots) 2732 last = icl_get_topdown_value(event, last_slots, last_metrics); 2733 2734 /* 2735 * The 8bit integer fraction of metric may be not accurate, 2736 * especially when the changes is very small. 2737 * For example, if only a few bad_spec happens, the fraction 2738 * may be reduced from 1 to 0. If so, the bad_spec event value 2739 * will be 0 which is definitely less than the last value. 2740 * Avoid update event->count for this case. 2741 */ 2742 if (delta > last) { 2743 delta -= last; 2744 local64_add(delta, &event->count); 2745 } 2746} 2747 2748static void update_saved_topdown_regs(struct perf_event *event, u64 slots, 2749 u64 metrics, int metric_end) 2750{ 2751 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2752 struct perf_event *other; 2753 int idx; 2754 2755 event->hw.saved_slots = slots; 2756 event->hw.saved_metric = metrics; 2757 2758 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2759 if (!is_topdown_idx(idx)) 2760 continue; 2761 other = cpuc->events[idx]; 2762 other->hw.saved_slots = slots; 2763 other->hw.saved_metric = metrics; 2764 } 2765} 2766 2767/* 2768 * Update all active Topdown events. 2769 * 2770 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be 2771 * modify by a NMI. PMU has to be disabled before calling this function. 2772 */ 2773 2774static u64 intel_update_topdown_event(struct perf_event *event, int metric_end, u64 *val) 2775{ 2776 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2777 struct perf_event *other; 2778 u64 slots, metrics; 2779 bool reset = true; 2780 int idx; 2781 2782 if (!val) { 2783 /* read Fixed counter 3 */ 2784 slots = rdpmc(3 | INTEL_PMC_FIXED_RDPMC_BASE); 2785 if (!slots) 2786 return 0; 2787 2788 /* read PERF_METRICS */ 2789 metrics = rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS); 2790 } else { 2791 slots = val[0]; 2792 metrics = val[1]; 2793 /* 2794 * Don't reset the PERF_METRICS and Fixed counter 3 2795 * for each PEBS record read. Utilize the RDPMC metrics 2796 * clear mode. 2797 */ 2798 reset = false; 2799 } 2800 2801 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) { 2802 if (!is_topdown_idx(idx)) 2803 continue; 2804 other = cpuc->events[idx]; 2805 __icl_update_topdown_event(other, slots, metrics, 2806 event ? event->hw.saved_slots : 0, 2807 event ? event->hw.saved_metric : 0); 2808 } 2809 2810 /* 2811 * Check and update this event, which may have been cleared 2812 * in active_mask e.g. x86_pmu_stop() 2813 */ 2814 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) { 2815 __icl_update_topdown_event(event, slots, metrics, 2816 event->hw.saved_slots, 2817 event->hw.saved_metric); 2818 2819 /* 2820 * In x86_pmu_stop(), the event is cleared in active_mask first, 2821 * then drain the delta, which indicates context switch for 2822 * counting. 2823 * Save metric and slots for context switch. 2824 * Don't need to reset the PERF_METRICS and Fixed counter 3. 2825 * Because the values will be restored in next schedule in. 2826 */ 2827 update_saved_topdown_regs(event, slots, metrics, metric_end); 2828 reset = false; 2829 } 2830 2831 if (reset) { 2832 /* The fixed counter 3 has to be written before the PERF_METRICS. */ 2833 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0); 2834 wrmsrq(MSR_PERF_METRICS, 0); 2835 if (event) 2836 update_saved_topdown_regs(event, 0, 0, metric_end); 2837 } 2838 2839 return slots; 2840} 2841 2842static u64 icl_update_topdown_event(struct perf_event *event, u64 *val) 2843{ 2844 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE + 2845 x86_pmu.num_topdown_events - 1, 2846 val); 2847} 2848 2849DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, intel_pmu_topdown_event_update); 2850 2851static void intel_pmu_read_event(struct perf_event *event) 2852{ 2853 if (event->hw.flags & (PERF_X86_EVENT_AUTO_RELOAD | PERF_X86_EVENT_TOPDOWN) || 2854 is_pebs_counter_event_group(event)) { 2855 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2856 bool pmu_enabled = cpuc->enabled; 2857 2858 /* Only need to call update_topdown_event() once for group read. */ 2859 if (is_metric_event(event) && (cpuc->txn_flags & PERF_PMU_TXN_READ)) 2860 return; 2861 2862 cpuc->enabled = 0; 2863 if (pmu_enabled) 2864 intel_pmu_disable_all(); 2865 2866 /* 2867 * If the PEBS counters snapshotting is enabled, 2868 * the topdown event is available in PEBS records. 2869 */ 2870 if (is_topdown_count(event) && !is_pebs_counter_event_group(event)) 2871 static_call(intel_pmu_update_topdown_event)(event, NULL); 2872 else 2873 intel_pmu_drain_pebs_buffer(); 2874 2875 cpuc->enabled = pmu_enabled; 2876 if (pmu_enabled) 2877 intel_pmu_enable_all(0); 2878 2879 return; 2880 } 2881 2882 x86_perf_event_update(event); 2883} 2884 2885static void intel_pmu_enable_fixed(struct perf_event *event) 2886{ 2887 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2888 struct hw_perf_event *hwc = &event->hw; 2889 int idx = hwc->idx; 2890 u64 bits = 0; 2891 2892 if (is_topdown_idx(idx)) { 2893 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2894 /* 2895 * When there are other active TopDown events, 2896 * don't enable the fixed counter 3 again. 2897 */ 2898 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx)) 2899 return; 2900 2901 idx = INTEL_PMC_IDX_FIXED_SLOTS; 2902 2903 if (event->attr.config1 & INTEL_TD_CFG_METRIC_CLEAR) 2904 bits |= INTEL_FIXED_3_METRICS_CLEAR; 2905 } 2906 2907 intel_set_masks(event, idx); 2908 2909 /* 2910 * Enable IRQ generation (0x8), if not PEBS, 2911 * and enable ring-3 counting (0x2) and ring-0 counting (0x1) 2912 * if requested: 2913 */ 2914 if (!event->attr.precise_ip) 2915 bits |= INTEL_FIXED_0_ENABLE_PMI; 2916 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) 2917 bits |= INTEL_FIXED_0_USER; 2918 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) 2919 bits |= INTEL_FIXED_0_KERNEL; 2920 2921 /* 2922 * ANY bit is supported in v3 and up 2923 */ 2924 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) 2925 bits |= INTEL_FIXED_0_ANYTHREAD; 2926 2927 idx -= INTEL_PMC_IDX_FIXED; 2928 bits = intel_fixed_bits_by_idx(idx, bits); 2929 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) 2930 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); 2931 2932 cpuc->fixed_ctrl_val &= ~intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK); 2933 cpuc->fixed_ctrl_val |= bits; 2934} 2935 2936static void intel_pmu_config_acr(int idx, u64 mask, u32 reload) 2937{ 2938 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2939 int msr_b, msr_c; 2940 int msr_offset; 2941 2942 if (!mask && !cpuc->acr_cfg_b[idx]) 2943 return; 2944 2945 if (idx < INTEL_PMC_IDX_FIXED) { 2946 msr_b = MSR_IA32_PMC_V6_GP0_CFG_B; 2947 msr_c = MSR_IA32_PMC_V6_GP0_CFG_C; 2948 msr_offset = x86_pmu.addr_offset(idx, false); 2949 } else { 2950 msr_b = MSR_IA32_PMC_V6_FX0_CFG_B; 2951 msr_c = MSR_IA32_PMC_V6_FX0_CFG_C; 2952 msr_offset = x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false); 2953 } 2954 2955 if (cpuc->acr_cfg_b[idx] != mask) { 2956 wrmsrl(msr_b + msr_offset, mask); 2957 cpuc->acr_cfg_b[idx] = mask; 2958 } 2959 /* Only need to update the reload value when there is a valid config value. */ 2960 if (mask && cpuc->acr_cfg_c[idx] != reload) { 2961 wrmsrl(msr_c + msr_offset, reload); 2962 cpuc->acr_cfg_c[idx] = reload; 2963 } 2964} 2965 2966static void intel_pmu_enable_acr(struct perf_event *event) 2967{ 2968 struct hw_perf_event *hwc = &event->hw; 2969 2970 if (!is_acr_event_group(event) || !event->attr.config2) { 2971 /* 2972 * The disable doesn't clear the ACR CFG register. 2973 * Check and clear the ACR CFG register. 2974 */ 2975 intel_pmu_config_acr(hwc->idx, 0, 0); 2976 return; 2977 } 2978 2979 intel_pmu_config_acr(hwc->idx, hwc->config1, -hwc->sample_period); 2980} 2981 2982DEFINE_STATIC_CALL_NULL(intel_pmu_enable_acr_event, intel_pmu_enable_acr); 2983 2984static void intel_pmu_enable_event_ext(struct perf_event *event) 2985{ 2986 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2987 struct hw_perf_event *hwc = &event->hw; 2988 union arch_pebs_index old, new; 2989 struct arch_pebs_cap cap; 2990 u64 ext = 0; 2991 2992 cap = hybrid(cpuc->pmu, arch_pebs_cap); 2993 2994 if (event->attr.precise_ip) { 2995 u64 pebs_data_cfg = intel_get_arch_pebs_data_config(event); 2996 2997 ext |= ARCH_PEBS_EN; 2998 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) 2999 ext |= (-hwc->sample_period) & ARCH_PEBS_RELOAD; 3000 3001 if (pebs_data_cfg && cap.caps) { 3002 if (pebs_data_cfg & PEBS_DATACFG_MEMINFO) 3003 ext |= ARCH_PEBS_AUX & cap.caps; 3004 3005 if (pebs_data_cfg & PEBS_DATACFG_GP) 3006 ext |= ARCH_PEBS_GPR & cap.caps; 3007 3008 if (pebs_data_cfg & PEBS_DATACFG_XMMS) 3009 ext |= ARCH_PEBS_VECR_XMM & cap.caps; 3010 3011 if (pebs_data_cfg & PEBS_DATACFG_LBRS) 3012 ext |= ARCH_PEBS_LBR & cap.caps; 3013 3014 if (pebs_data_cfg & 3015 (PEBS_DATACFG_CNTR_MASK << PEBS_DATACFG_CNTR_SHIFT)) 3016 ext |= ARCH_PEBS_CNTR_GP & cap.caps; 3017 3018 if (pebs_data_cfg & 3019 (PEBS_DATACFG_FIX_MASK << PEBS_DATACFG_FIX_SHIFT)) 3020 ext |= ARCH_PEBS_CNTR_FIXED & cap.caps; 3021 3022 if (pebs_data_cfg & PEBS_DATACFG_METRICS) 3023 ext |= ARCH_PEBS_CNTR_METRICS & cap.caps; 3024 } 3025 3026 if (cpuc->n_pebs == cpuc->n_large_pebs) 3027 new.thresh = ARCH_PEBS_THRESH_MULTI; 3028 else 3029 new.thresh = ARCH_PEBS_THRESH_SINGLE; 3030 3031 rdmsrq(MSR_IA32_PEBS_INDEX, old.whole); 3032 if (new.thresh != old.thresh || !old.en) { 3033 if (old.thresh == ARCH_PEBS_THRESH_MULTI && old.wr > 0) { 3034 /* 3035 * Large PEBS was enabled. 3036 * Drain PEBS buffer before applying the single PEBS. 3037 */ 3038 intel_pmu_drain_pebs_buffer(); 3039 } else { 3040 new.wr = 0; 3041 new.full = 0; 3042 new.en = 1; 3043 wrmsrq(MSR_IA32_PEBS_INDEX, new.whole); 3044 } 3045 } 3046 } 3047 3048 if (is_pebs_counter_event_group(event)) 3049 ext |= ARCH_PEBS_CNTR_ALLOW; 3050 3051 if (cpuc->cfg_c_val[hwc->idx] != ext) 3052 __intel_pmu_update_event_ext(hwc->idx, ext); 3053} 3054 3055DEFINE_STATIC_CALL_NULL(intel_pmu_enable_event_ext, intel_pmu_enable_event_ext); 3056 3057static void intel_pmu_enable_event(struct perf_event *event) 3058{ 3059 u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE; 3060 struct hw_perf_event *hwc = &event->hw; 3061 int idx = hwc->idx; 3062 3063 if (unlikely(event->attr.precise_ip)) 3064 static_call(x86_pmu_pebs_enable)(event); 3065 3066 switch (idx) { 3067 case 0 ... INTEL_PMC_IDX_FIXED - 1: 3068 if (branch_sample_counters(event)) 3069 enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR; 3070 intel_set_masks(event, idx); 3071 static_call_cond(intel_pmu_enable_acr_event)(event); 3072 static_call_cond(intel_pmu_enable_event_ext)(event); 3073 __x86_pmu_enable_event(hwc, enable_mask); 3074 break; 3075 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: 3076 static_call_cond(intel_pmu_enable_acr_event)(event); 3077 static_call_cond(intel_pmu_enable_event_ext)(event); 3078 fallthrough; 3079 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: 3080 intel_pmu_enable_fixed(event); 3081 break; 3082 case INTEL_PMC_IDX_FIXED_BTS: 3083 if (!__this_cpu_read(cpu_hw_events.enabled)) 3084 return; 3085 intel_pmu_enable_bts(hwc->config); 3086 break; 3087 case INTEL_PMC_IDX_FIXED_VLBR: 3088 intel_set_masks(event, idx); 3089 break; 3090 default: 3091 pr_warn("Failed to enable the event with invalid index %d\n", 3092 idx); 3093 } 3094} 3095 3096static void intel_pmu_acr_late_setup(struct cpu_hw_events *cpuc) 3097{ 3098 struct perf_event *event, *leader; 3099 int i, j, idx; 3100 3101 for (i = 0; i < cpuc->n_events; i++) { 3102 leader = cpuc->event_list[i]; 3103 if (!is_acr_event_group(leader)) 3104 continue; 3105 3106 /* The ACR events must be contiguous. */ 3107 for (j = i; j < cpuc->n_events; j++) { 3108 event = cpuc->event_list[j]; 3109 if (event->group_leader != leader->group_leader) 3110 break; 3111 for_each_set_bit(idx, (unsigned long *)&event->attr.config2, X86_PMC_IDX_MAX) { 3112 if (i + idx >= cpuc->n_events || 3113 !is_acr_event_group(cpuc->event_list[i + idx])) 3114 return; 3115 __set_bit(cpuc->assign[i + idx], (unsigned long *)&event->hw.config1); 3116 } 3117 } 3118 i = j - 1; 3119 } 3120} 3121 3122void intel_pmu_late_setup(void) 3123{ 3124 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3125 3126 if (!cpuc->n_late_setup) 3127 return; 3128 3129 intel_pmu_pebs_late_setup(cpuc); 3130 intel_pmu_acr_late_setup(cpuc); 3131} 3132 3133static void intel_pmu_add_event(struct perf_event *event) 3134{ 3135 if (event->attr.precise_ip) 3136 intel_pmu_pebs_add(event); 3137 if (intel_pmu_needs_branch_stack(event)) 3138 intel_pmu_lbr_add(event); 3139 if (is_pebs_counter_event_group(event) || 3140 is_acr_event_group(event)) 3141 this_cpu_ptr(&cpu_hw_events)->n_late_setup++; 3142} 3143 3144/* 3145 * Save and restart an expired event. Called by NMI contexts, 3146 * so it has to be careful about preempting normal event ops: 3147 */ 3148int intel_pmu_save_and_restart(struct perf_event *event) 3149{ 3150 static_call(x86_pmu_update)(event); 3151 /* 3152 * For a checkpointed counter always reset back to 0. This 3153 * avoids a situation where the counter overflows, aborts the 3154 * transaction and is then set back to shortly before the 3155 * overflow, and overflows and aborts again. 3156 */ 3157 if (unlikely(event_is_checkpointed(event))) { 3158 /* No race with NMIs because the counter should not be armed */ 3159 wrmsrq(event->hw.event_base, 0); 3160 local64_set(&event->hw.prev_count, 0); 3161 } 3162 return static_call(x86_pmu_set_period)(event); 3163} 3164 3165static int intel_pmu_set_period(struct perf_event *event) 3166{ 3167 if (unlikely(is_topdown_count(event))) 3168 return static_call(intel_pmu_set_topdown_event_period)(event); 3169 3170 return x86_perf_event_set_period(event); 3171} 3172 3173static u64 intel_pmu_update(struct perf_event *event) 3174{ 3175 if (unlikely(is_topdown_count(event))) 3176 return static_call(intel_pmu_update_topdown_event)(event, NULL); 3177 3178 return x86_perf_event_update(event); 3179} 3180 3181static void intel_pmu_reset(void) 3182{ 3183 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 3184 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3185 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask); 3186 unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask); 3187 unsigned long flags; 3188 int idx; 3189 3190 if (!*(u64 *)cntr_mask) 3191 return; 3192 3193 local_irq_save(flags); 3194 3195 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 3196 3197 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) { 3198 wrmsrq_safe(x86_pmu_config_addr(idx), 0ull); 3199 wrmsrq_safe(x86_pmu_event_addr(idx), 0ull); 3200 } 3201 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) { 3202 if (fixed_counter_disabled(idx, cpuc->pmu)) 3203 continue; 3204 wrmsrq_safe(x86_pmu_fixed_ctr_addr(idx), 0ull); 3205 } 3206 3207 if (ds) 3208 ds->bts_index = ds->bts_buffer_base; 3209 3210 /* Ack all overflows and disable fixed counters */ 3211 if (x86_pmu.version >= 2) { 3212 intel_pmu_ack_status(intel_pmu_get_status()); 3213 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0); 3214 } 3215 3216 /* Reset LBRs and LBR freezing */ 3217 if (x86_pmu.lbr_nr) { 3218 update_debugctlmsr(get_debugctlmsr() & 3219 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); 3220 } 3221 3222 local_irq_restore(flags); 3223} 3224 3225/* 3226 * We may be running with guest PEBS events created by KVM, and the 3227 * PEBS records are logged into the guest's DS and invisible to host. 3228 * 3229 * In the case of guest PEBS overflow, we only trigger a fake event 3230 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM. 3231 * The guest will then vm-entry and check the guest DS area to read 3232 * the guest PEBS records. 3233 * 3234 * The contents and other behavior of the guest event do not matter. 3235 */ 3236static void x86_pmu_handle_guest_pebs(struct pt_regs *regs, 3237 struct perf_sample_data *data) 3238{ 3239 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3240 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask; 3241 struct perf_event *event = NULL; 3242 int bit; 3243 3244 if (!unlikely(perf_guest_state())) 3245 return; 3246 3247 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active || 3248 !guest_pebs_idxs) 3249 return; 3250 3251 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) { 3252 event = cpuc->events[bit]; 3253 if (!event->attr.precise_ip) 3254 continue; 3255 3256 perf_sample_data_init(data, 0, event->hw.last_period); 3257 perf_event_overflow(event, data, regs); 3258 3259 /* Inject one fake event is enough. */ 3260 break; 3261 } 3262} 3263 3264static int handle_pmi_common(struct pt_regs *regs, u64 status) 3265{ 3266 struct perf_sample_data data; 3267 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3268 int bit; 3269 int handled = 0; 3270 3271 inc_irq_stat(apic_perf_irqs); 3272 3273 /* 3274 * Ignore a range of extra bits in status that do not indicate 3275 * overflow by themselves. 3276 */ 3277 status &= ~(GLOBAL_STATUS_COND_CHG | 3278 GLOBAL_STATUS_ASIF | 3279 GLOBAL_STATUS_LBRS_FROZEN); 3280 if (!status) 3281 return 0; 3282 /* 3283 * In case multiple PEBS events are sampled at the same time, 3284 * it is possible to have GLOBAL_STATUS bit 62 set indicating 3285 * PEBS buffer overflow and also seeing at most 3 PEBS counters 3286 * having their bits set in the status register. This is a sign 3287 * that there was at least one PEBS record pending at the time 3288 * of the PMU interrupt. PEBS counters must only be processed 3289 * via the drain_pebs() calls and not via the regular sample 3290 * processing loop coming after that the function, otherwise 3291 * phony regular samples may be generated in the sampling buffer 3292 * not marked with the EXACT tag. Another possibility is to have 3293 * one PEBS event and at least one non-PEBS event which overflows 3294 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will 3295 * not be set, yet the overflow status bit for the PEBS counter will 3296 * be on Skylake. 3297 * 3298 * To avoid this problem, we systematically ignore the PEBS-enabled 3299 * counters from the GLOBAL_STATUS mask and we always process PEBS 3300 * events via drain_pebs(). 3301 */ 3302 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable); 3303 3304 /* 3305 * PEBS overflow sets bit 62 in the global status register 3306 */ 3307 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) { 3308 u64 pebs_enabled = cpuc->pebs_enabled; 3309 3310 handled++; 3311 x86_pmu_handle_guest_pebs(regs, &data); 3312 static_call(x86_pmu_drain_pebs)(regs, &data); 3313 3314 /* 3315 * PMI throttle may be triggered, which stops the PEBS event. 3316 * Although cpuc->pebs_enabled is updated accordingly, the 3317 * MSR_IA32_PEBS_ENABLE is not updated. Because the 3318 * cpuc->enabled has been forced to 0 in PMI. 3319 * Update the MSR if pebs_enabled is changed. 3320 */ 3321 if (pebs_enabled != cpuc->pebs_enabled) 3322 wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 3323 3324 /* 3325 * Above PEBS handler (PEBS counters snapshotting) has updated fixed 3326 * counter 3 and perf metrics counts if they are in counter group, 3327 * unnecessary to update again. 3328 */ 3329 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] && 3330 is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS])) 3331 status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT; 3332 } 3333 3334 /* 3335 * Arch PEBS sets bit 54 in the global status register 3336 */ 3337 if (__test_and_clear_bit(GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT, 3338 (unsigned long *)&status)) { 3339 handled++; 3340 static_call(x86_pmu_drain_pebs)(regs, &data); 3341 3342 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] && 3343 is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS])) 3344 status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT; 3345 } 3346 3347 /* 3348 * Intel PT 3349 */ 3350 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) { 3351 handled++; 3352 if (!perf_guest_handle_intel_pt_intr()) 3353 intel_pt_interrupt(); 3354 } 3355 3356 /* 3357 * Intel Perf metrics 3358 */ 3359 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) { 3360 handled++; 3361 static_call(intel_pmu_update_topdown_event)(NULL, NULL); 3362 } 3363 3364 status &= hybrid(cpuc->pmu, intel_ctrl); 3365 3366 /* 3367 * Checkpointed counters can lead to 'spurious' PMIs because the 3368 * rollback caused by the PMI will have cleared the overflow status 3369 * bit. Therefore always force probe these counters. 3370 */ 3371 status |= cpuc->intel_cp_status; 3372 3373 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { 3374 struct perf_event *event = cpuc->events[bit]; 3375 u64 last_period; 3376 3377 handled++; 3378 3379 if (!test_bit(bit, cpuc->active_mask)) 3380 continue; 3381 /* Event may have already been cleared: */ 3382 if (!event) 3383 continue; 3384 3385 /* 3386 * There may be unprocessed PEBS records in the PEBS buffer, 3387 * which still stores the previous values. 3388 * Process those records first before handling the latest value. 3389 * For example, 3390 * A is a regular counter 3391 * B is a PEBS event which reads A 3392 * C is a PEBS event 3393 * 3394 * The following can happen: 3395 * B-assist A=1 3396 * C A=2 3397 * B-assist A=3 3398 * A-overflow-PMI A=4 3399 * C-assist-PMI (PEBS buffer) A=5 3400 * 3401 * The PEBS buffer has to be drained before handling the A-PMI 3402 */ 3403 if (is_pebs_counter_event_group(event)) 3404 static_call(x86_pmu_drain_pebs)(regs, &data); 3405 3406 last_period = event->hw.last_period; 3407 3408 if (!intel_pmu_save_and_restart(event)) 3409 continue; 3410 3411 perf_sample_data_init(&data, 0, last_period); 3412 3413 if (has_branch_stack(event)) 3414 intel_pmu_lbr_save_brstack(&data, cpuc, event); 3415 3416 perf_event_overflow(event, &data, regs); 3417 } 3418 3419 return handled; 3420} 3421 3422/* 3423 * This handler is triggered by the local APIC, so the APIC IRQ handling 3424 * rules apply: 3425 */ 3426static int intel_pmu_handle_irq(struct pt_regs *regs) 3427{ 3428 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 3429 bool late_ack = hybrid_bit(cpuc->pmu, late_ack); 3430 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack); 3431 int loops; 3432 u64 status; 3433 int handled; 3434 int pmu_enabled; 3435 3436 /* 3437 * Save the PMU state. 3438 * It needs to be restored when leaving the handler. 3439 */ 3440 pmu_enabled = cpuc->enabled; 3441 /* 3442 * In general, the early ACK is only applied for old platforms. 3443 * For the big core starts from Haswell, the late ACK should be 3444 * applied. 3445 * For the small core after Tremont, we have to do the ACK right 3446 * before re-enabling counters, which is in the middle of the 3447 * NMI handler. 3448 */ 3449 if (!late_ack && !mid_ack) 3450 apic_write(APIC_LVTPC, APIC_DM_NMI); 3451 intel_bts_disable_local(); 3452 cpuc->enabled = 0; 3453 __intel_pmu_disable_all(true); 3454 handled = intel_pmu_drain_bts_buffer(); 3455 handled += intel_bts_interrupt(); 3456 status = intel_pmu_get_status(); 3457 if (!status) 3458 goto done; 3459 3460 loops = 0; 3461again: 3462 intel_pmu_lbr_read(); 3463 intel_pmu_ack_status(status); 3464 if (++loops > 100) { 3465 static bool warned; 3466 3467 if (!warned) { 3468 WARN(1, "perfevents: irq loop stuck!\n"); 3469 perf_event_print_debug(); 3470 warned = true; 3471 } 3472 intel_pmu_reset(); 3473 goto done; 3474 } 3475 3476 handled += handle_pmi_common(regs, status); 3477 3478 /* 3479 * Repeat if there is more work to be done: 3480 */ 3481 status = intel_pmu_get_status(); 3482 if (status) 3483 goto again; 3484 3485done: 3486 if (mid_ack) 3487 apic_write(APIC_LVTPC, APIC_DM_NMI); 3488 /* Only restore PMU state when it's active. See x86_pmu_disable(). */ 3489 cpuc->enabled = pmu_enabled; 3490 if (pmu_enabled) 3491 __intel_pmu_enable_all(0, true); 3492 intel_bts_enable_local(); 3493 3494 /* 3495 * Only unmask the NMI after the overflow counters 3496 * have been reset. This avoids spurious NMIs on 3497 * Haswell CPUs. 3498 */ 3499 if (late_ack) 3500 apic_write(APIC_LVTPC, APIC_DM_NMI); 3501 return handled; 3502} 3503 3504static struct event_constraint * 3505intel_bts_constraints(struct perf_event *event) 3506{ 3507 if (unlikely(intel_pmu_has_bts(event))) 3508 return &bts_constraint; 3509 3510 return NULL; 3511} 3512 3513/* 3514 * Note: matches a fake event, like Fixed2. 3515 */ 3516static struct event_constraint * 3517intel_vlbr_constraints(struct perf_event *event) 3518{ 3519 struct event_constraint *c = &vlbr_constraint; 3520 3521 if (unlikely(constraint_match(c, event->hw.config))) { 3522 event->hw.flags |= c->flags; 3523 return c; 3524 } 3525 3526 return NULL; 3527} 3528 3529static int intel_alt_er(struct cpu_hw_events *cpuc, 3530 int idx, u64 config) 3531{ 3532 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); 3533 int alt_idx = idx; 3534 3535 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) 3536 return idx; 3537 3538 if (idx == EXTRA_REG_RSP_0) 3539 alt_idx = EXTRA_REG_RSP_1; 3540 3541 if (idx == EXTRA_REG_RSP_1) 3542 alt_idx = EXTRA_REG_RSP_0; 3543 3544 if (config & ~extra_regs[alt_idx].valid_mask) 3545 return idx; 3546 3547 return alt_idx; 3548} 3549 3550static void intel_fixup_er(struct perf_event *event, int idx) 3551{ 3552 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); 3553 event->hw.extra_reg.idx = idx; 3554 3555 if (idx == EXTRA_REG_RSP_0) { 3556 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3557 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event; 3558 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; 3559 } else if (idx == EXTRA_REG_RSP_1) { 3560 event->hw.config &= ~INTEL_ARCH_EVENT_MASK; 3561 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event; 3562 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; 3563 } 3564} 3565 3566/* 3567 * manage allocation of shared extra msr for certain events 3568 * 3569 * sharing can be: 3570 * per-cpu: to be shared between the various events on a single PMU 3571 * per-core: per-cpu + shared by HT threads 3572 */ 3573static struct event_constraint * 3574__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, 3575 struct perf_event *event, 3576 struct hw_perf_event_extra *reg) 3577{ 3578 struct event_constraint *c = &emptyconstraint; 3579 struct er_account *era; 3580 unsigned long flags; 3581 int idx = reg->idx; 3582 3583 /* 3584 * reg->alloc can be set due to existing state, so for fake cpuc we 3585 * need to ignore this, otherwise we might fail to allocate proper fake 3586 * state for this extra reg constraint. Also see the comment below. 3587 */ 3588 if (reg->alloc && !cpuc->is_fake) 3589 return NULL; /* call x86_get_event_constraint() */ 3590 3591again: 3592 era = &cpuc->shared_regs->regs[idx]; 3593 /* 3594 * we use spin_lock_irqsave() to avoid lockdep issues when 3595 * passing a fake cpuc 3596 */ 3597 raw_spin_lock_irqsave(&era->lock, flags); 3598 3599 if (!atomic_read(&era->ref) || era->config == reg->config) { 3600 3601 /* 3602 * If its a fake cpuc -- as per validate_{group,event}() we 3603 * shouldn't touch event state and we can avoid doing so 3604 * since both will only call get_event_constraints() once 3605 * on each event, this avoids the need for reg->alloc. 3606 * 3607 * Not doing the ER fixup will only result in era->reg being 3608 * wrong, but since we won't actually try and program hardware 3609 * this isn't a problem either. 3610 */ 3611 if (!cpuc->is_fake) { 3612 if (idx != reg->idx) 3613 intel_fixup_er(event, idx); 3614 3615 /* 3616 * x86_schedule_events() can call get_event_constraints() 3617 * multiple times on events in the case of incremental 3618 * scheduling(). reg->alloc ensures we only do the ER 3619 * allocation once. 3620 */ 3621 reg->alloc = 1; 3622 } 3623 3624 /* lock in msr value */ 3625 era->config = reg->config; 3626 era->reg = reg->reg; 3627 3628 /* one more user */ 3629 atomic_inc(&era->ref); 3630 3631 /* 3632 * need to call x86_get_event_constraint() 3633 * to check if associated event has constraints 3634 */ 3635 c = NULL; 3636 } else { 3637 idx = intel_alt_er(cpuc, idx, reg->config); 3638 if (idx != reg->idx) { 3639 raw_spin_unlock_irqrestore(&era->lock, flags); 3640 goto again; 3641 } 3642 } 3643 raw_spin_unlock_irqrestore(&era->lock, flags); 3644 3645 return c; 3646} 3647 3648static void 3649__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, 3650 struct hw_perf_event_extra *reg) 3651{ 3652 struct er_account *era; 3653 3654 /* 3655 * Only put constraint if extra reg was actually allocated. Also takes 3656 * care of event which do not use an extra shared reg. 3657 * 3658 * Also, if this is a fake cpuc we shouldn't touch any event state 3659 * (reg->alloc) and we don't care about leaving inconsistent cpuc state 3660 * either since it'll be thrown out. 3661 */ 3662 if (!reg->alloc || cpuc->is_fake) 3663 return; 3664 3665 era = &cpuc->shared_regs->regs[reg->idx]; 3666 3667 /* one fewer user */ 3668 atomic_dec(&era->ref); 3669 3670 /* allocate again next time */ 3671 reg->alloc = 0; 3672} 3673 3674static struct event_constraint * 3675intel_shared_regs_constraints(struct cpu_hw_events *cpuc, 3676 struct perf_event *event) 3677{ 3678 struct event_constraint *c = NULL, *d; 3679 struct hw_perf_event_extra *xreg, *breg; 3680 3681 xreg = &event->hw.extra_reg; 3682 if (xreg->idx != EXTRA_REG_NONE) { 3683 c = __intel_shared_reg_get_constraints(cpuc, event, xreg); 3684 if (c == &emptyconstraint) 3685 return c; 3686 } 3687 breg = &event->hw.branch_reg; 3688 if (breg->idx != EXTRA_REG_NONE) { 3689 d = __intel_shared_reg_get_constraints(cpuc, event, breg); 3690 if (d == &emptyconstraint) { 3691 __intel_shared_reg_put_constraints(cpuc, xreg); 3692 c = d; 3693 } 3694 } 3695 return c; 3696} 3697 3698struct event_constraint * 3699x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3700 struct perf_event *event) 3701{ 3702 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints); 3703 struct event_constraint *c; 3704 3705 if (event_constraints) { 3706 for_each_event_constraint(c, event_constraints) { 3707 if (constraint_match(c, event->hw.config)) { 3708 event->hw.flags |= c->flags; 3709 return c; 3710 } 3711 } 3712 } 3713 3714 return &hybrid_var(cpuc->pmu, unconstrained); 3715} 3716 3717static struct event_constraint * 3718__intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3719 struct perf_event *event) 3720{ 3721 struct event_constraint *c; 3722 3723 c = intel_vlbr_constraints(event); 3724 if (c) 3725 return c; 3726 3727 c = intel_bts_constraints(event); 3728 if (c) 3729 return c; 3730 3731 c = intel_shared_regs_constraints(cpuc, event); 3732 if (c) 3733 return c; 3734 3735 c = intel_pebs_constraints(event); 3736 if (c) 3737 return c; 3738 3739 return x86_get_event_constraints(cpuc, idx, event); 3740} 3741 3742static void 3743intel_start_scheduling(struct cpu_hw_events *cpuc) 3744{ 3745 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3746 struct intel_excl_states *xl; 3747 int tid = cpuc->excl_thread_id; 3748 3749 /* 3750 * nothing needed if in group validation mode 3751 */ 3752 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3753 return; 3754 3755 /* 3756 * no exclusion needed 3757 */ 3758 if (WARN_ON_ONCE(!excl_cntrs)) 3759 return; 3760 3761 xl = &excl_cntrs->states[tid]; 3762 3763 xl->sched_started = true; 3764 /* 3765 * lock shared state until we are done scheduling 3766 * in stop_event_scheduling() 3767 * makes scheduling appear as a transaction 3768 */ 3769 raw_spin_lock(&excl_cntrs->lock); 3770} 3771 3772static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr) 3773{ 3774 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3775 struct event_constraint *c = cpuc->event_constraint[idx]; 3776 struct intel_excl_states *xl; 3777 int tid = cpuc->excl_thread_id; 3778 3779 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3780 return; 3781 3782 if (WARN_ON_ONCE(!excl_cntrs)) 3783 return; 3784 3785 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) 3786 return; 3787 3788 xl = &excl_cntrs->states[tid]; 3789 3790 lockdep_assert_held(&excl_cntrs->lock); 3791 3792 if (c->flags & PERF_X86_EVENT_EXCL) 3793 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE; 3794 else 3795 xl->state[cntr] = INTEL_EXCL_SHARED; 3796} 3797 3798static void 3799intel_stop_scheduling(struct cpu_hw_events *cpuc) 3800{ 3801 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3802 struct intel_excl_states *xl; 3803 int tid = cpuc->excl_thread_id; 3804 3805 /* 3806 * nothing needed if in group validation mode 3807 */ 3808 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3809 return; 3810 /* 3811 * no exclusion needed 3812 */ 3813 if (WARN_ON_ONCE(!excl_cntrs)) 3814 return; 3815 3816 xl = &excl_cntrs->states[tid]; 3817 3818 xl->sched_started = false; 3819 /* 3820 * release shared state lock (acquired in intel_start_scheduling()) 3821 */ 3822 raw_spin_unlock(&excl_cntrs->lock); 3823} 3824 3825static struct event_constraint * 3826dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx) 3827{ 3828 WARN_ON_ONCE(!cpuc->constraint_list); 3829 3830 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) { 3831 struct event_constraint *cx; 3832 3833 /* 3834 * grab pre-allocated constraint entry 3835 */ 3836 cx = &cpuc->constraint_list[idx]; 3837 3838 /* 3839 * initialize dynamic constraint 3840 * with static constraint 3841 */ 3842 *cx = *c; 3843 3844 /* 3845 * mark constraint as dynamic 3846 */ 3847 cx->flags |= PERF_X86_EVENT_DYNAMIC; 3848 c = cx; 3849 } 3850 3851 return c; 3852} 3853 3854static struct event_constraint * 3855intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 3856 int idx, struct event_constraint *c) 3857{ 3858 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3859 struct intel_excl_states *xlo; 3860 int tid = cpuc->excl_thread_id; 3861 int is_excl, i, w; 3862 3863 /* 3864 * validating a group does not require 3865 * enforcing cross-thread exclusion 3866 */ 3867 if (cpuc->is_fake || !is_ht_workaround_enabled()) 3868 return c; 3869 3870 /* 3871 * no exclusion needed 3872 */ 3873 if (WARN_ON_ONCE(!excl_cntrs)) 3874 return c; 3875 3876 /* 3877 * because we modify the constraint, we need 3878 * to make a copy. Static constraints come 3879 * from static const tables. 3880 * 3881 * only needed when constraint has not yet 3882 * been cloned (marked dynamic) 3883 */ 3884 c = dyn_constraint(cpuc, c, idx); 3885 3886 /* 3887 * From here on, the constraint is dynamic. 3888 * Either it was just allocated above, or it 3889 * was allocated during a earlier invocation 3890 * of this function 3891 */ 3892 3893 /* 3894 * state of sibling HT 3895 */ 3896 xlo = &excl_cntrs->states[tid ^ 1]; 3897 3898 /* 3899 * event requires exclusive counter access 3900 * across HT threads 3901 */ 3902 is_excl = c->flags & PERF_X86_EVENT_EXCL; 3903 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) { 3904 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT; 3905 if (!cpuc->n_excl++) 3906 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1); 3907 } 3908 3909 /* 3910 * Modify static constraint with current dynamic 3911 * state of thread 3912 * 3913 * EXCLUSIVE: sibling counter measuring exclusive event 3914 * SHARED : sibling counter measuring non-exclusive event 3915 * UNUSED : sibling counter unused 3916 */ 3917 w = c->weight; 3918 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) { 3919 /* 3920 * exclusive event in sibling counter 3921 * our corresponding counter cannot be used 3922 * regardless of our event 3923 */ 3924 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) { 3925 __clear_bit(i, c->idxmsk); 3926 w--; 3927 continue; 3928 } 3929 /* 3930 * if measuring an exclusive event, sibling 3931 * measuring non-exclusive, then counter cannot 3932 * be used 3933 */ 3934 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) { 3935 __clear_bit(i, c->idxmsk); 3936 w--; 3937 continue; 3938 } 3939 } 3940 3941 /* 3942 * if we return an empty mask, then switch 3943 * back to static empty constraint to avoid 3944 * the cost of freeing later on 3945 */ 3946 if (!w) 3947 c = &emptyconstraint; 3948 3949 c->weight = w; 3950 3951 return c; 3952} 3953 3954static struct event_constraint * 3955intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3956 struct perf_event *event) 3957{ 3958 struct event_constraint *c1, *c2; 3959 3960 c1 = cpuc->event_constraint[idx]; 3961 3962 /* 3963 * first time only 3964 * - static constraint: no change across incremental scheduling calls 3965 * - dynamic constraint: handled by intel_get_excl_constraints() 3966 */ 3967 c2 = __intel_get_event_constraints(cpuc, idx, event); 3968 if (c1) { 3969 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC)); 3970 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX); 3971 c1->weight = c2->weight; 3972 c2 = c1; 3973 } 3974 3975 if (cpuc->excl_cntrs) 3976 return intel_get_excl_constraints(cpuc, event, idx, c2); 3977 3978 if (event->hw.dyn_constraint != ~0ULL) { 3979 c2 = dyn_constraint(cpuc, c2, idx); 3980 c2->idxmsk64 &= event->hw.dyn_constraint; 3981 c2->weight = hweight64(c2->idxmsk64); 3982 } 3983 3984 return c2; 3985} 3986 3987static void intel_put_excl_constraints(struct cpu_hw_events *cpuc, 3988 struct perf_event *event) 3989{ 3990 struct hw_perf_event *hwc = &event->hw; 3991 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs; 3992 int tid = cpuc->excl_thread_id; 3993 struct intel_excl_states *xl; 3994 3995 /* 3996 * nothing needed if in group validation mode 3997 */ 3998 if (cpuc->is_fake) 3999 return; 4000 4001 if (WARN_ON_ONCE(!excl_cntrs)) 4002 return; 4003 4004 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) { 4005 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT; 4006 if (!--cpuc->n_excl) 4007 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0); 4008 } 4009 4010 /* 4011 * If event was actually assigned, then mark the counter state as 4012 * unused now. 4013 */ 4014 if (hwc->idx >= 0) { 4015 xl = &excl_cntrs->states[tid]; 4016 4017 /* 4018 * put_constraint may be called from x86_schedule_events() 4019 * which already has the lock held so here make locking 4020 * conditional. 4021 */ 4022 if (!xl->sched_started) 4023 raw_spin_lock(&excl_cntrs->lock); 4024 4025 xl->state[hwc->idx] = INTEL_EXCL_UNUSED; 4026 4027 if (!xl->sched_started) 4028 raw_spin_unlock(&excl_cntrs->lock); 4029 } 4030} 4031 4032static void 4033intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, 4034 struct perf_event *event) 4035{ 4036 struct hw_perf_event_extra *reg; 4037 4038 reg = &event->hw.extra_reg; 4039 if (reg->idx != EXTRA_REG_NONE) 4040 __intel_shared_reg_put_constraints(cpuc, reg); 4041 4042 reg = &event->hw.branch_reg; 4043 if (reg->idx != EXTRA_REG_NONE) 4044 __intel_shared_reg_put_constraints(cpuc, reg); 4045} 4046 4047static void intel_put_event_constraints(struct cpu_hw_events *cpuc, 4048 struct perf_event *event) 4049{ 4050 intel_put_shared_regs_event_constraints(cpuc, event); 4051 4052 /* 4053 * is PMU has exclusive counter restrictions, then 4054 * all events are subject to and must call the 4055 * put_excl_constraints() routine 4056 */ 4057 if (cpuc->excl_cntrs) 4058 intel_put_excl_constraints(cpuc, event); 4059} 4060 4061static void intel_pebs_aliases_core2(struct perf_event *event) 4062{ 4063 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 4064 /* 4065 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 4066 * (0x003c) so that we can use it with PEBS. 4067 * 4068 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 4069 * PEBS capable. However we can use INST_RETIRED.ANY_P 4070 * (0x00c0), which is a PEBS capable event, to get the same 4071 * count. 4072 * 4073 * INST_RETIRED.ANY_P counts the number of cycles that retires 4074 * CNTMASK instructions. By setting CNTMASK to a value (16) 4075 * larger than the maximum number of instructions that can be 4076 * retired per cycle (4) and then inverting the condition, we 4077 * count all cycles that retire 16 or less instructions, which 4078 * is every cycle. 4079 * 4080 * Thereby we gain a PEBS capable cycle counter. 4081 */ 4082 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); 4083 4084 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 4085 event->hw.config = alt_config; 4086 } 4087} 4088 4089static void intel_pebs_aliases_snb(struct perf_event *event) 4090{ 4091 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 4092 /* 4093 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 4094 * (0x003c) so that we can use it with PEBS. 4095 * 4096 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 4097 * PEBS capable. However we can use UOPS_RETIRED.ALL 4098 * (0x01c2), which is a PEBS capable event, to get the same 4099 * count. 4100 * 4101 * UOPS_RETIRED.ALL counts the number of cycles that retires 4102 * CNTMASK micro-ops. By setting CNTMASK to a value (16) 4103 * larger than the maximum number of micro-ops that can be 4104 * retired per cycle (4) and then inverting the condition, we 4105 * count all cycles that retire 16 or less micro-ops, which 4106 * is every cycle. 4107 * 4108 * Thereby we gain a PEBS capable cycle counter. 4109 */ 4110 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); 4111 4112 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 4113 event->hw.config = alt_config; 4114 } 4115} 4116 4117static void intel_pebs_aliases_precdist(struct perf_event *event) 4118{ 4119 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { 4120 /* 4121 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P 4122 * (0x003c) so that we can use it with PEBS. 4123 * 4124 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't 4125 * PEBS capable. However we can use INST_RETIRED.PREC_DIST 4126 * (0x01c0), which is a PEBS capable event, to get the same 4127 * count. 4128 * 4129 * The PREC_DIST event has special support to minimize sample 4130 * shadowing effects. One drawback is that it can be 4131 * only programmed on counter 1, but that seems like an 4132 * acceptable trade off. 4133 */ 4134 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); 4135 4136 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); 4137 event->hw.config = alt_config; 4138 } 4139} 4140 4141static void intel_pebs_aliases_ivb(struct perf_event *event) 4142{ 4143 if (event->attr.precise_ip < 3) 4144 return intel_pebs_aliases_snb(event); 4145 return intel_pebs_aliases_precdist(event); 4146} 4147 4148static void intel_pebs_aliases_skl(struct perf_event *event) 4149{ 4150 if (event->attr.precise_ip < 3) 4151 return intel_pebs_aliases_core2(event); 4152 return intel_pebs_aliases_precdist(event); 4153} 4154 4155static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 4156{ 4157 unsigned long flags = x86_pmu.large_pebs_flags; 4158 4159 if (event->attr.use_clockid) 4160 flags &= ~PERF_SAMPLE_TIME; 4161 if (!event->attr.exclude_kernel) 4162 flags &= ~PERF_SAMPLE_REGS_USER; 4163 if (event->attr.sample_regs_user & ~PEBS_GP_REGS) 4164 flags &= ~PERF_SAMPLE_REGS_USER; 4165 if (event->attr.sample_regs_intr & ~PEBS_GP_REGS) 4166 flags &= ~PERF_SAMPLE_REGS_INTR; 4167 return flags; 4168} 4169 4170static int intel_pmu_bts_config(struct perf_event *event) 4171{ 4172 struct perf_event_attr *attr = &event->attr; 4173 4174 if (unlikely(intel_pmu_has_bts(event))) { 4175 /* BTS is not supported by this architecture. */ 4176 if (!x86_pmu.bts_active) 4177 return -EOPNOTSUPP; 4178 4179 /* BTS is currently only allowed for user-mode. */ 4180 if (!attr->exclude_kernel) 4181 return -EOPNOTSUPP; 4182 4183 /* BTS is not allowed for precise events. */ 4184 if (attr->precise_ip) 4185 return -EOPNOTSUPP; 4186 4187 /* disallow bts if conflicting events are present */ 4188 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 4189 return -EBUSY; 4190 4191 event->destroy = hw_perf_lbr_event_destroy; 4192 } 4193 4194 return 0; 4195} 4196 4197static int core_pmu_hw_config(struct perf_event *event) 4198{ 4199 int ret = x86_pmu_hw_config(event); 4200 4201 if (ret) 4202 return ret; 4203 4204 return intel_pmu_bts_config(event); 4205} 4206 4207#define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \ 4208 ((x86_pmu.num_topdown_events - 1) << 8)) 4209 4210static bool is_available_metric_event(struct perf_event *event) 4211{ 4212 return is_metric_event(event) && 4213 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX; 4214} 4215 4216static inline bool is_mem_loads_event(struct perf_event *event) 4217{ 4218 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); 4219} 4220 4221static inline bool is_mem_loads_aux_event(struct perf_event *event) 4222{ 4223 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); 4224} 4225 4226static inline bool require_mem_loads_aux_event(struct perf_event *event) 4227{ 4228 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX)) 4229 return false; 4230 4231 if (is_hybrid()) 4232 return hybrid_pmu(event->pmu)->pmu_type == hybrid_big; 4233 4234 return true; 4235} 4236 4237static inline bool intel_pmu_has_cap(struct perf_event *event, int idx) 4238{ 4239 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap); 4240 4241 return test_bit(idx, (unsigned long *)&intel_cap->capabilities); 4242} 4243 4244static u64 intel_pmu_freq_start_period(struct perf_event *event) 4245{ 4246 int type = event->attr.type; 4247 u64 config, factor; 4248 s64 start; 4249 4250 /* 4251 * The 127 is the lowest possible recommended SAV (sample after value) 4252 * for a 4000 freq (default freq), according to the event list JSON file. 4253 * Also, assume the workload is idle 50% time. 4254 */ 4255 factor = 64 * 4000; 4256 if (type != PERF_TYPE_HARDWARE && type != PERF_TYPE_HW_CACHE) 4257 goto end; 4258 4259 /* 4260 * The estimation of the start period in the freq mode is 4261 * based on the below assumption. 4262 * 4263 * For a cycles or an instructions event, 1GHZ of the 4264 * underlying platform, 1 IPC. The workload is idle 50% time. 4265 * The start period = 1,000,000,000 * 1 / freq / 2. 4266 * = 500,000,000 / freq 4267 * 4268 * Usually, the branch-related events occur less than the 4269 * instructions event. According to the Intel event list JSON 4270 * file, the SAV (sample after value) of a branch-related event 4271 * is usually 1/4 of an instruction event. 4272 * The start period of branch-related events = 125,000,000 / freq. 4273 * 4274 * The cache-related events occurs even less. The SAV is usually 4275 * 1/20 of an instruction event. 4276 * The start period of cache-related events = 25,000,000 / freq. 4277 */ 4278 config = event->attr.config & PERF_HW_EVENT_MASK; 4279 if (type == PERF_TYPE_HARDWARE) { 4280 switch (config) { 4281 case PERF_COUNT_HW_CPU_CYCLES: 4282 case PERF_COUNT_HW_INSTRUCTIONS: 4283 case PERF_COUNT_HW_BUS_CYCLES: 4284 case PERF_COUNT_HW_STALLED_CYCLES_FRONTEND: 4285 case PERF_COUNT_HW_STALLED_CYCLES_BACKEND: 4286 case PERF_COUNT_HW_REF_CPU_CYCLES: 4287 factor = 500000000; 4288 break; 4289 case PERF_COUNT_HW_BRANCH_INSTRUCTIONS: 4290 case PERF_COUNT_HW_BRANCH_MISSES: 4291 factor = 125000000; 4292 break; 4293 case PERF_COUNT_HW_CACHE_REFERENCES: 4294 case PERF_COUNT_HW_CACHE_MISSES: 4295 factor = 25000000; 4296 break; 4297 default: 4298 goto end; 4299 } 4300 } 4301 4302 if (type == PERF_TYPE_HW_CACHE) 4303 factor = 25000000; 4304end: 4305 /* 4306 * Usually, a prime or a number with less factors (close to prime) 4307 * is chosen as an SAV, which makes it less likely that the sampling 4308 * period synchronizes with some periodic event in the workload. 4309 * Minus 1 to make it at least avoiding values near power of twos 4310 * for the default freq. 4311 */ 4312 start = DIV_ROUND_UP_ULL(factor, event->attr.sample_freq) - 1; 4313 4314 if (start > x86_pmu.max_period) 4315 start = x86_pmu.max_period; 4316 4317 if (x86_pmu.limit_period) 4318 x86_pmu.limit_period(event, &start); 4319 4320 return start; 4321} 4322 4323static inline bool intel_pmu_has_acr(struct pmu *pmu) 4324{ 4325 return !!hybrid(pmu, acr_cause_mask64); 4326} 4327 4328static bool intel_pmu_is_acr_group(struct perf_event *event) 4329{ 4330 /* The group leader has the ACR flag set */ 4331 if (is_acr_event_group(event)) 4332 return true; 4333 4334 /* The acr_mask is set */ 4335 if (event->attr.config2) 4336 return true; 4337 4338 return false; 4339} 4340 4341static inline bool intel_pmu_has_pebs_counter_group(struct pmu *pmu) 4342{ 4343 u64 caps; 4344 4345 if (x86_pmu.intel_cap.pebs_format >= 6 && x86_pmu.intel_cap.pebs_baseline) 4346 return true; 4347 4348 caps = hybrid(pmu, arch_pebs_cap).caps; 4349 if (x86_pmu.arch_pebs && (caps & ARCH_PEBS_CNTR_MASK)) 4350 return true; 4351 4352 return false; 4353} 4354 4355static inline void intel_pmu_set_acr_cntr_constr(struct perf_event *event, 4356 u64 *cause_mask, int *num) 4357{ 4358 event->hw.dyn_constraint &= hybrid(event->pmu, acr_cntr_mask64); 4359 *cause_mask |= event->attr.config2; 4360 *num += 1; 4361} 4362 4363static inline void intel_pmu_set_acr_caused_constr(struct perf_event *event, 4364 int idx, u64 cause_mask) 4365{ 4366 if (test_bit(idx, (unsigned long *)&cause_mask)) 4367 event->hw.dyn_constraint &= hybrid(event->pmu, acr_cause_mask64); 4368} 4369 4370static inline int intel_set_branch_counter_constr(struct perf_event *event, 4371 int *num) 4372{ 4373 if (branch_sample_call_stack(event)) 4374 return -EINVAL; 4375 if (branch_sample_counters(event)) { 4376 (*num)++; 4377 event->hw.dyn_constraint &= x86_pmu.lbr_counters; 4378 } 4379 4380 return 0; 4381} 4382 4383static int intel_pmu_hw_config(struct perf_event *event) 4384{ 4385 int ret = x86_pmu_hw_config(event); 4386 4387 if (ret) 4388 return ret; 4389 4390 ret = intel_pmu_bts_config(event); 4391 if (ret) 4392 return ret; 4393 4394 if (event->attr.freq && event->attr.sample_freq) { 4395 event->hw.sample_period = intel_pmu_freq_start_period(event); 4396 event->hw.last_period = event->hw.sample_period; 4397 local64_set(&event->hw.period_left, event->hw.sample_period); 4398 } 4399 4400 if (event->attr.precise_ip) { 4401 struct arch_pebs_cap pebs_cap = hybrid(event->pmu, arch_pebs_cap); 4402 4403 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT) 4404 return -EINVAL; 4405 4406 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) { 4407 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 4408 if (!(event->attr.sample_type & ~intel_pmu_large_pebs_flags(event)) && 4409 !has_aux_action(event)) { 4410 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 4411 event->attach_state |= PERF_ATTACH_SCHED_CB; 4412 } 4413 } 4414 if (x86_pmu.pebs_aliases) 4415 x86_pmu.pebs_aliases(event); 4416 4417 if (x86_pmu.arch_pebs) { 4418 u64 cntr_mask = hybrid(event->pmu, intel_ctrl) & 4419 ~GLOBAL_CTRL_EN_PERF_METRICS; 4420 u64 pebs_mask = event->attr.precise_ip >= 3 ? 4421 pebs_cap.pdists : pebs_cap.counters; 4422 if (cntr_mask != pebs_mask) 4423 event->hw.dyn_constraint &= pebs_mask; 4424 } 4425 } 4426 4427 if (needs_branch_stack(event)) { 4428 /* Avoid branch stack setup for counting events in SAMPLE READ */ 4429 if (is_sampling_event(event) || 4430 !(event->attr.sample_type & PERF_SAMPLE_READ)) 4431 event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK; 4432 } 4433 4434 if (branch_sample_counters(event)) { 4435 struct perf_event *leader, *sibling; 4436 int num = 0; 4437 4438 if (!(x86_pmu.flags & PMU_FL_BR_CNTR) || 4439 (event->attr.config & ~INTEL_ARCH_EVENT_MASK)) 4440 return -EINVAL; 4441 4442 /* 4443 * The branch counter logging is not supported in the call stack 4444 * mode yet, since we cannot simply flush the LBR during e.g., 4445 * multiplexing. Also, there is no obvious usage with the call 4446 * stack mode. Simply forbids it for now. 4447 * 4448 * If any events in the group enable the branch counter logging 4449 * feature, the group is treated as a branch counter logging 4450 * group, which requires the extra space to store the counters. 4451 */ 4452 leader = event->group_leader; 4453 if (intel_set_branch_counter_constr(leader, &num)) 4454 return -EINVAL; 4455 leader->hw.flags |= PERF_X86_EVENT_BRANCH_COUNTERS; 4456 4457 for_each_sibling_event(sibling, leader) { 4458 if (intel_set_branch_counter_constr(sibling, &num)) 4459 return -EINVAL; 4460 } 4461 4462 /* event isn't installed as a sibling yet. */ 4463 if (event != leader) { 4464 if (intel_set_branch_counter_constr(event, &num)) 4465 return -EINVAL; 4466 } 4467 4468 if (num > fls(x86_pmu.lbr_counters)) 4469 return -EINVAL; 4470 /* 4471 * Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't 4472 * require any branch stack setup. 4473 * Clear the bit to avoid unnecessary branch stack setup. 4474 */ 4475 if (0 == (event->attr.branch_sample_type & 4476 ~(PERF_SAMPLE_BRANCH_PLM_ALL | 4477 PERF_SAMPLE_BRANCH_COUNTERS))) 4478 event->hw.flags &= ~PERF_X86_EVENT_NEEDS_BRANCH_STACK; 4479 4480 /* 4481 * Force the leader to be a LBR event. So LBRs can be reset 4482 * with the leader event. See intel_pmu_lbr_del() for details. 4483 */ 4484 if (!intel_pmu_needs_branch_stack(leader)) 4485 return -EINVAL; 4486 } 4487 4488 if (intel_pmu_needs_branch_stack(event)) { 4489 ret = intel_pmu_setup_lbr_filter(event); 4490 if (ret) 4491 return ret; 4492 event->attach_state |= PERF_ATTACH_SCHED_CB; 4493 4494 /* 4495 * BTS is set up earlier in this path, so don't account twice 4496 */ 4497 if (!unlikely(intel_pmu_has_bts(event))) { 4498 /* disallow lbr if conflicting events are present */ 4499 if (x86_add_exclusive(x86_lbr_exclusive_lbr)) 4500 return -EBUSY; 4501 4502 event->destroy = hw_perf_lbr_event_destroy; 4503 } 4504 } 4505 4506 if (event->attr.aux_output) { 4507 if (!event->attr.precise_ip) 4508 return -EINVAL; 4509 4510 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT; 4511 } 4512 4513 if ((event->attr.sample_type & PERF_SAMPLE_READ) && 4514 intel_pmu_has_pebs_counter_group(event->pmu) && 4515 is_sampling_event(event) && 4516 event->attr.precise_ip) 4517 event->group_leader->hw.flags |= PERF_X86_EVENT_PEBS_CNTR; 4518 4519 if (intel_pmu_has_acr(event->pmu) && intel_pmu_is_acr_group(event)) { 4520 struct perf_event *sibling, *leader = event->group_leader; 4521 struct pmu *pmu = event->pmu; 4522 bool has_sw_event = false; 4523 int num = 0, idx = 0; 4524 u64 cause_mask = 0; 4525 4526 /* Not support perf metrics */ 4527 if (is_metric_event(event)) 4528 return -EINVAL; 4529 4530 /* Not support freq mode */ 4531 if (event->attr.freq) 4532 return -EINVAL; 4533 4534 /* PDist is not supported */ 4535 if (event->attr.config2 && event->attr.precise_ip > 2) 4536 return -EINVAL; 4537 4538 /* The reload value cannot exceeds the max period */ 4539 if (event->attr.sample_period > x86_pmu.max_period) 4540 return -EINVAL; 4541 /* 4542 * The counter-constraints of each event cannot be finalized 4543 * unless the whole group is scanned. However, it's hard 4544 * to know whether the event is the last one of the group. 4545 * Recalculate the counter-constraints for each event when 4546 * adding a new event. 4547 * 4548 * The group is traversed twice, which may be optimized later. 4549 * In the first round, 4550 * - Find all events which do reload when other events 4551 * overflow and set the corresponding counter-constraints 4552 * - Add all events, which can cause other events reload, 4553 * in the cause_mask 4554 * - Error out if the number of events exceeds the HW limit 4555 * - The ACR events must be contiguous. 4556 * Error out if there are non-X86 events between ACR events. 4557 * This is not a HW limit, but a SW limit. 4558 * With the assumption, the intel_pmu_acr_late_setup() can 4559 * easily convert the event idx to counter idx without 4560 * traversing the whole event list. 4561 */ 4562 if (!is_x86_event(leader)) 4563 return -EINVAL; 4564 4565 if (leader->attr.config2) 4566 intel_pmu_set_acr_cntr_constr(leader, &cause_mask, &num); 4567 4568 if (leader->nr_siblings) { 4569 for_each_sibling_event(sibling, leader) { 4570 if (!is_x86_event(sibling)) { 4571 has_sw_event = true; 4572 continue; 4573 } 4574 if (!sibling->attr.config2) 4575 continue; 4576 if (has_sw_event) 4577 return -EINVAL; 4578 intel_pmu_set_acr_cntr_constr(sibling, &cause_mask, &num); 4579 } 4580 } 4581 if (leader != event && event->attr.config2) { 4582 if (has_sw_event) 4583 return -EINVAL; 4584 intel_pmu_set_acr_cntr_constr(event, &cause_mask, &num); 4585 } 4586 4587 if (hweight64(cause_mask) > hweight64(hybrid(pmu, acr_cause_mask64)) || 4588 num > hweight64(hybrid(event->pmu, acr_cntr_mask64))) 4589 return -EINVAL; 4590 /* 4591 * In the second round, apply the counter-constraints for 4592 * the events which can cause other events reload. 4593 */ 4594 intel_pmu_set_acr_caused_constr(leader, idx++, cause_mask); 4595 4596 if (leader->nr_siblings) { 4597 for_each_sibling_event(sibling, leader) { 4598 if (is_x86_event(sibling)) 4599 intel_pmu_set_acr_caused_constr(sibling, idx++, cause_mask); 4600 } 4601 } 4602 4603 if (leader != event) 4604 intel_pmu_set_acr_caused_constr(event, idx, cause_mask); 4605 4606 leader->hw.flags |= PERF_X86_EVENT_ACR; 4607 } 4608 4609 if ((event->attr.type == PERF_TYPE_HARDWARE) || 4610 (event->attr.type == PERF_TYPE_HW_CACHE)) 4611 return 0; 4612 4613 /* 4614 * Config Topdown slots and metric events 4615 * 4616 * The slots event on Fixed Counter 3 can support sampling, 4617 * which will be handled normally in x86_perf_event_update(). 4618 * 4619 * Metric events don't support sampling and require being paired 4620 * with a slots event as group leader. When the slots event 4621 * is used in a metrics group, it too cannot support sampling. 4622 */ 4623 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) { 4624 /* The metrics_clear can only be set for the slots event */ 4625 if (event->attr.config1 && 4626 (!is_slots_event(event) || (event->attr.config1 & ~INTEL_TD_CFG_METRIC_CLEAR))) 4627 return -EINVAL; 4628 4629 if (event->attr.config2) 4630 return -EINVAL; 4631 4632 /* 4633 * The TopDown metrics events and slots event don't 4634 * support any filters. 4635 */ 4636 if (event->attr.config & X86_ALL_EVENT_FLAGS) 4637 return -EINVAL; 4638 4639 if (is_available_metric_event(event)) { 4640 struct perf_event *leader = event->group_leader; 4641 4642 /* The metric events don't support sampling. */ 4643 if (is_sampling_event(event)) 4644 return -EINVAL; 4645 4646 /* The metric events require a slots group leader. */ 4647 if (!is_slots_event(leader)) 4648 return -EINVAL; 4649 4650 /* 4651 * The leader/SLOTS must not be a sampling event for 4652 * metric use; hardware requires it starts at 0 when used 4653 * in conjunction with MSR_PERF_METRICS. 4654 */ 4655 if (is_sampling_event(leader)) 4656 return -EINVAL; 4657 4658 event->event_caps |= PERF_EV_CAP_SIBLING; 4659 /* 4660 * Only once we have a METRICs sibling do we 4661 * need TopDown magic. 4662 */ 4663 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN; 4664 event->hw.flags |= PERF_X86_EVENT_TOPDOWN; 4665 } 4666 } 4667 4668 /* 4669 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR 4670 * doesn't function quite right. As a work-around it needs to always be 4671 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82). 4672 * The actual count of this second event is irrelevant it just needs 4673 * to be active to make the first event function correctly. 4674 * 4675 * In a group, the auxiliary event must be in front of the load latency 4676 * event. The rule is to simplify the implementation of the check. 4677 * That's because perf cannot have a complete group at the moment. 4678 */ 4679 if (require_mem_loads_aux_event(event) && 4680 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) && 4681 is_mem_loads_event(event)) { 4682 struct perf_event *leader = event->group_leader; 4683 struct perf_event *sibling = NULL; 4684 4685 /* 4686 * When this memload event is also the first event (no group 4687 * exists yet), then there is no aux event before it. 4688 */ 4689 if (leader == event) 4690 return -ENODATA; 4691 4692 if (!is_mem_loads_aux_event(leader)) { 4693 for_each_sibling_event(sibling, leader) { 4694 if (is_mem_loads_aux_event(sibling)) 4695 break; 4696 } 4697 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list)) 4698 return -ENODATA; 4699 } 4700 } 4701 4702 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) 4703 return 0; 4704 4705 if (x86_pmu.version < 3) 4706 return -EINVAL; 4707 4708 ret = perf_allow_cpu(); 4709 if (ret) 4710 return ret; 4711 4712 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; 4713 4714 return 0; 4715} 4716 4717/* 4718 * Currently, the only caller of this function is the atomic_switch_perf_msrs(). 4719 * The host perf context helps to prepare the values of the real hardware for 4720 * a set of msrs that need to be switched atomically in a vmx transaction. 4721 * 4722 * For example, the pseudocode needed to add a new msr should look like: 4723 * 4724 * arr[(*nr)++] = (struct perf_guest_switch_msr){ 4725 * .msr = the hardware msr address, 4726 * .host = the value the hardware has when it doesn't run a guest, 4727 * .guest = the value the hardware has when it runs a guest, 4728 * }; 4729 * 4730 * These values have nothing to do with the emulated values the guest sees 4731 * when it uses {RD,WR}MSR, which should be handled by the KVM context, 4732 * specifically in the intel_pmu_{get,set}_msr(). 4733 */ 4734static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) 4735{ 4736 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4737 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 4738 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data; 4739 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); 4740 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; 4741 int global_ctrl, pebs_enable; 4742 4743 /* 4744 * In addition to obeying exclude_guest/exclude_host, remove bits being 4745 * used for PEBS when running a guest, because PEBS writes to virtual 4746 * addresses (not physical addresses). 4747 */ 4748 *nr = 0; 4749 global_ctrl = (*nr)++; 4750 arr[global_ctrl] = (struct perf_guest_switch_msr){ 4751 .msr = MSR_CORE_PERF_GLOBAL_CTRL, 4752 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask, 4753 .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask, 4754 }; 4755 4756 if (!x86_pmu.ds_pebs) 4757 return arr; 4758 4759 /* 4760 * If PMU counter has PEBS enabled it is not enough to 4761 * disable counter on a guest entry since PEBS memory 4762 * write can overshoot guest entry and corrupt guest 4763 * memory. Disabling PEBS solves the problem. 4764 * 4765 * Don't do this if the CPU already enforces it. 4766 */ 4767 if (x86_pmu.pebs_no_isolation) { 4768 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4769 .msr = MSR_IA32_PEBS_ENABLE, 4770 .host = cpuc->pebs_enabled, 4771 .guest = 0, 4772 }; 4773 return arr; 4774 } 4775 4776 if (!kvm_pmu || !x86_pmu.pebs_ept) 4777 return arr; 4778 4779 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4780 .msr = MSR_IA32_DS_AREA, 4781 .host = (unsigned long)cpuc->ds, 4782 .guest = kvm_pmu->ds_area, 4783 }; 4784 4785 if (x86_pmu.intel_cap.pebs_baseline) { 4786 arr[(*nr)++] = (struct perf_guest_switch_msr){ 4787 .msr = MSR_PEBS_DATA_CFG, 4788 .host = cpuc->active_pebs_data_cfg, 4789 .guest = kvm_pmu->pebs_data_cfg, 4790 }; 4791 } 4792 4793 pebs_enable = (*nr)++; 4794 arr[pebs_enable] = (struct perf_guest_switch_msr){ 4795 .msr = MSR_IA32_PEBS_ENABLE, 4796 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask, 4797 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask & kvm_pmu->pebs_enable, 4798 }; 4799 4800 if (arr[pebs_enable].host) { 4801 /* Disable guest PEBS if host PEBS is enabled. */ 4802 arr[pebs_enable].guest = 0; 4803 } else { 4804 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */ 4805 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask; 4806 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask; 4807 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ 4808 arr[global_ctrl].guest |= arr[pebs_enable].guest; 4809 } 4810 4811 return arr; 4812} 4813 4814static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data) 4815{ 4816 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4817 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; 4818 int idx; 4819 4820 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { 4821 struct perf_event *event = cpuc->events[idx]; 4822 4823 arr[idx].msr = x86_pmu_config_addr(idx); 4824 arr[idx].host = arr[idx].guest = 0; 4825 4826 if (!test_bit(idx, cpuc->active_mask)) 4827 continue; 4828 4829 arr[idx].host = arr[idx].guest = 4830 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; 4831 4832 if (event->attr.exclude_host) 4833 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 4834 else if (event->attr.exclude_guest) 4835 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 4836 } 4837 4838 *nr = x86_pmu_max_num_counters(cpuc->pmu); 4839 return arr; 4840} 4841 4842static void core_pmu_enable_event(struct perf_event *event) 4843{ 4844 if (!event->attr.exclude_host) 4845 x86_pmu_enable_event(event); 4846} 4847 4848static void core_pmu_enable_all(int added) 4849{ 4850 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 4851 int idx; 4852 4853 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { 4854 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; 4855 4856 if (!test_bit(idx, cpuc->active_mask) || 4857 cpuc->events[idx]->attr.exclude_host) 4858 continue; 4859 4860 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); 4861 } 4862} 4863 4864static int hsw_hw_config(struct perf_event *event) 4865{ 4866 int ret = intel_pmu_hw_config(event); 4867 4868 if (ret) 4869 return ret; 4870 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE)) 4871 return 0; 4872 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); 4873 4874 /* 4875 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with 4876 * PEBS or in ANY thread mode. Since the results are non-sensical forbid 4877 * this combination. 4878 */ 4879 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) && 4880 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) || 4881 event->attr.precise_ip > 0)) 4882 return -EOPNOTSUPP; 4883 4884 if (event_is_checkpointed(event)) { 4885 /* 4886 * Sampling of checkpointed events can cause situations where 4887 * the CPU constantly aborts because of a overflow, which is 4888 * then checkpointed back and ignored. Forbid checkpointing 4889 * for sampling. 4890 * 4891 * But still allow a long sampling period, so that perf stat 4892 * from KVM works. 4893 */ 4894 if (event->attr.sample_period > 0 && 4895 event->attr.sample_period < 0x7fffffff) 4896 return -EOPNOTSUPP; 4897 } 4898 return 0; 4899} 4900 4901static struct event_constraint counter0_constraint = 4902 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 4903 4904static struct event_constraint counter1_constraint = 4905 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2); 4906 4907static struct event_constraint counter0_1_constraint = 4908 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3); 4909 4910static struct event_constraint counter2_constraint = 4911 EVENT_CONSTRAINT(0, 0x4, 0); 4912 4913static struct event_constraint fixed0_constraint = 4914 FIXED_EVENT_CONSTRAINT(0x00c0, 0); 4915 4916static struct event_constraint fixed0_counter0_constraint = 4917 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); 4918 4919static struct event_constraint fixed0_counter0_1_constraint = 4920 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL); 4921 4922static struct event_constraint counters_1_7_constraint = 4923 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL); 4924 4925static struct event_constraint * 4926hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4927 struct perf_event *event) 4928{ 4929 struct event_constraint *c; 4930 4931 c = intel_get_event_constraints(cpuc, idx, event); 4932 4933 /* Handle special quirk on in_tx_checkpointed only in counter 2 */ 4934 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) { 4935 if (c->idxmsk64 & (1U << 2)) 4936 return &counter2_constraint; 4937 return &emptyconstraint; 4938 } 4939 4940 return c; 4941} 4942 4943static struct event_constraint * 4944icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4945 struct perf_event *event) 4946{ 4947 /* 4948 * Fixed counter 0 has less skid. 4949 * Force instruction:ppp in Fixed counter 0 4950 */ 4951 if ((event->attr.precise_ip == 3) && 4952 constraint_match(&fixed0_constraint, event->hw.config)) 4953 return &fixed0_constraint; 4954 4955 return hsw_get_event_constraints(cpuc, idx, event); 4956} 4957 4958static struct event_constraint * 4959glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4960 struct perf_event *event) 4961{ 4962 struct event_constraint *c; 4963 4964 c = icl_get_event_constraints(cpuc, idx, event); 4965 4966 /* 4967 * The :ppp indicates the Precise Distribution (PDist) facility, which 4968 * is only supported on the GP counter 0. If a :ppp event which is not 4969 * available on the GP counter 0, error out. 4970 * Exception: Instruction PDIR is only available on the fixed counter 0. 4971 */ 4972 if ((event->attr.precise_ip == 3) && 4973 !constraint_match(&fixed0_constraint, event->hw.config)) { 4974 if (c->idxmsk64 & BIT_ULL(0)) 4975 return &counter0_constraint; 4976 4977 return &emptyconstraint; 4978 } 4979 4980 return c; 4981} 4982 4983static struct event_constraint * 4984glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 4985 struct perf_event *event) 4986{ 4987 struct event_constraint *c; 4988 4989 /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 4990 if (event->attr.precise_ip == 3) 4991 return &counter0_constraint; 4992 4993 c = intel_get_event_constraints(cpuc, idx, event); 4994 4995 return c; 4996} 4997 4998static struct event_constraint * 4999tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5000 struct perf_event *event) 5001{ 5002 struct event_constraint *c; 5003 5004 c = intel_get_event_constraints(cpuc, idx, event); 5005 5006 /* 5007 * :ppp means to do reduced skid PEBS, 5008 * which is available on PMC0 and fixed counter 0. 5009 */ 5010 if (event->attr.precise_ip == 3) { 5011 /* Force instruction:ppp on PMC0 and Fixed counter 0 */ 5012 if (constraint_match(&fixed0_constraint, event->hw.config)) 5013 return &fixed0_counter0_constraint; 5014 5015 return &counter0_constraint; 5016 } 5017 5018 return c; 5019} 5020 5021static bool allow_tsx_force_abort = true; 5022 5023static struct event_constraint * 5024tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5025 struct perf_event *event) 5026{ 5027 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event); 5028 5029 /* 5030 * Without TFA we must not use PMC3. 5031 */ 5032 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) { 5033 c = dyn_constraint(cpuc, c, idx); 5034 c->idxmsk64 &= ~(1ULL << 3); 5035 c->weight--; 5036 } 5037 5038 return c; 5039} 5040 5041static struct event_constraint * 5042adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5043 struct perf_event *event) 5044{ 5045 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 5046 5047 if (pmu->pmu_type == hybrid_big) 5048 return glc_get_event_constraints(cpuc, idx, event); 5049 else if (pmu->pmu_type == hybrid_small) 5050 return tnt_get_event_constraints(cpuc, idx, event); 5051 5052 WARN_ON(1); 5053 return &emptyconstraint; 5054} 5055 5056static struct event_constraint * 5057cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5058 struct perf_event *event) 5059{ 5060 struct event_constraint *c; 5061 5062 c = intel_get_event_constraints(cpuc, idx, event); 5063 5064 /* 5065 * The :ppp indicates the Precise Distribution (PDist) facility, which 5066 * is only supported on the GP counter 0 & 1 and Fixed counter 0. 5067 * If a :ppp event which is not available on the above eligible counters, 5068 * error out. 5069 */ 5070 if (event->attr.precise_ip == 3) { 5071 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */ 5072 if (constraint_match(&fixed0_constraint, event->hw.config)) { 5073 /* The fixed counter 0 doesn't support LBR event logging. */ 5074 if (branch_sample_counters(event)) 5075 return &counter0_1_constraint; 5076 else 5077 return &fixed0_counter0_1_constraint; 5078 } 5079 5080 switch (c->idxmsk64 & 0x3ull) { 5081 case 0x1: 5082 return &counter0_constraint; 5083 case 0x2: 5084 return &counter1_constraint; 5085 case 0x3: 5086 return &counter0_1_constraint; 5087 } 5088 return &emptyconstraint; 5089 } 5090 5091 return c; 5092} 5093 5094static struct event_constraint * 5095rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5096 struct perf_event *event) 5097{ 5098 struct event_constraint *c; 5099 5100 c = glc_get_event_constraints(cpuc, idx, event); 5101 5102 /* The Retire Latency is not supported by the fixed counter 0. */ 5103 if (event->attr.precise_ip && 5104 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) && 5105 constraint_match(&fixed0_constraint, event->hw.config)) { 5106 /* 5107 * The Instruction PDIR is only available 5108 * on the fixed counter 0. Error out for this case. 5109 */ 5110 if (event->attr.precise_ip == 3) 5111 return &emptyconstraint; 5112 return &counters_1_7_constraint; 5113 } 5114 5115 return c; 5116} 5117 5118static struct event_constraint * 5119mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5120 struct perf_event *event) 5121{ 5122 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 5123 5124 if (pmu->pmu_type == hybrid_big) 5125 return rwc_get_event_constraints(cpuc, idx, event); 5126 if (pmu->pmu_type == hybrid_small) 5127 return cmt_get_event_constraints(cpuc, idx, event); 5128 5129 WARN_ON(1); 5130 return &emptyconstraint; 5131} 5132 5133static int adl_hw_config(struct perf_event *event) 5134{ 5135 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 5136 5137 if (pmu->pmu_type == hybrid_big) 5138 return hsw_hw_config(event); 5139 else if (pmu->pmu_type == hybrid_small) 5140 return intel_pmu_hw_config(event); 5141 5142 WARN_ON(1); 5143 return -EOPNOTSUPP; 5144} 5145 5146static enum intel_cpu_type adl_get_hybrid_cpu_type(void) 5147{ 5148 return INTEL_CPU_TYPE_CORE; 5149} 5150 5151static inline bool erratum_hsw11(struct perf_event *event) 5152{ 5153 return (event->hw.config & INTEL_ARCH_EVENT_MASK) == 5154 X86_CONFIG(.event=0xc0, .umask=0x01); 5155} 5156 5157static struct event_constraint * 5158arl_h_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 5159 struct perf_event *event) 5160{ 5161 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 5162 5163 if (pmu->pmu_type == hybrid_tiny) 5164 return cmt_get_event_constraints(cpuc, idx, event); 5165 5166 return mtl_get_event_constraints(cpuc, idx, event); 5167} 5168 5169static int arl_h_hw_config(struct perf_event *event) 5170{ 5171 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); 5172 5173 if (pmu->pmu_type == hybrid_tiny) 5174 return intel_pmu_hw_config(event); 5175 5176 return adl_hw_config(event); 5177} 5178 5179/* 5180 * The HSW11 requires a period larger than 100 which is the same as the BDM11. 5181 * A minimum period of 128 is enforced as well for the INST_RETIRED.ALL. 5182 * 5183 * The message 'interrupt took too long' can be observed on any counter which 5184 * was armed with a period < 32 and two events expired in the same NMI. 5185 * A minimum period of 32 is enforced for the rest of the events. 5186 */ 5187static void hsw_limit_period(struct perf_event *event, s64 *left) 5188{ 5189 *left = max(*left, erratum_hsw11(event) ? 128 : 32); 5190} 5191 5192/* 5193 * Broadwell: 5194 * 5195 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared 5196 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine 5197 * the two to enforce a minimum period of 128 (the smallest value that has bits 5198 * 0-5 cleared and >= 100). 5199 * 5200 * Because of how the code in x86_perf_event_set_period() works, the truncation 5201 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period 5202 * to make up for the 'lost' events due to carrying the 'error' in period_left. 5203 * 5204 * Therefore the effective (average) period matches the requested period, 5205 * despite coarser hardware granularity. 5206 */ 5207static void bdw_limit_period(struct perf_event *event, s64 *left) 5208{ 5209 if (erratum_hsw11(event)) { 5210 if (*left < 128) 5211 *left = 128; 5212 *left &= ~0x3fULL; 5213 } 5214} 5215 5216static void nhm_limit_period(struct perf_event *event, s64 *left) 5217{ 5218 *left = max(*left, 32LL); 5219} 5220 5221static void glc_limit_period(struct perf_event *event, s64 *left) 5222{ 5223 if (event->attr.precise_ip == 3) 5224 *left = max(*left, 128LL); 5225} 5226 5227PMU_FORMAT_ATTR(event, "config:0-7" ); 5228PMU_FORMAT_ATTR(umask, "config:8-15" ); 5229PMU_FORMAT_ATTR(edge, "config:18" ); 5230PMU_FORMAT_ATTR(pc, "config:19" ); 5231PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ 5232PMU_FORMAT_ATTR(inv, "config:23" ); 5233PMU_FORMAT_ATTR(cmask, "config:24-31" ); 5234PMU_FORMAT_ATTR(in_tx, "config:32" ); 5235PMU_FORMAT_ATTR(in_tx_cp, "config:33" ); 5236PMU_FORMAT_ATTR(eq, "config:36" ); /* v6 + */ 5237 5238PMU_FORMAT_ATTR(metrics_clear, "config1:0"); /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */ 5239 5240static ssize_t umask2_show(struct device *dev, 5241 struct device_attribute *attr, 5242 char *page) 5243{ 5244 u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2; 5245 5246 if (mask == ARCH_PERFMON_EVENTSEL_UMASK2) 5247 return sprintf(page, "config:8-15,40-47\n"); 5248 5249 /* Roll back to the old format if umask2 is not supported. */ 5250 return sprintf(page, "config:8-15\n"); 5251} 5252 5253static struct device_attribute format_attr_umask2 = 5254 __ATTR(umask, 0444, umask2_show, NULL); 5255 5256static struct attribute *format_evtsel_ext_attrs[] = { 5257 &format_attr_umask2.attr, 5258 &format_attr_eq.attr, 5259 &format_attr_metrics_clear.attr, 5260 NULL 5261}; 5262 5263static umode_t 5264evtsel_ext_is_visible(struct kobject *kobj, struct attribute *attr, int i) 5265{ 5266 struct device *dev = kobj_to_dev(kobj); 5267 u64 mask; 5268 5269 /* 5270 * The umask and umask2 have different formats but share the 5271 * same attr name. In update mode, the previous value of the 5272 * umask is unconditionally removed before is_visible. If 5273 * umask2 format is not enumerated, it's impossible to roll 5274 * back to the old format. 5275 * Does the check in umask2_show rather than is_visible. 5276 */ 5277 if (i == 0) 5278 return attr->mode; 5279 5280 mask = hybrid(dev_get_drvdata(dev), config_mask); 5281 if (i == 1) 5282 return (mask & ARCH_PERFMON_EVENTSEL_EQ) ? attr->mode : 0; 5283 5284 /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */ 5285 if (i == 2) { 5286 union perf_capabilities intel_cap = hybrid(dev_get_drvdata(dev), intel_cap); 5287 5288 return intel_cap.rdpmc_metrics_clear ? attr->mode : 0; 5289 } 5290 5291 return 0; 5292} 5293 5294static struct attribute *intel_arch_formats_attr[] = { 5295 &format_attr_event.attr, 5296 &format_attr_umask.attr, 5297 &format_attr_edge.attr, 5298 &format_attr_pc.attr, 5299 &format_attr_inv.attr, 5300 &format_attr_cmask.attr, 5301 NULL, 5302}; 5303 5304ssize_t intel_event_sysfs_show(char *page, u64 config) 5305{ 5306 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT); 5307 5308 return x86_event_sysfs_show(page, config, event); 5309} 5310 5311static struct intel_shared_regs *allocate_shared_regs(int cpu) 5312{ 5313 struct intel_shared_regs *regs; 5314 int i; 5315 5316 regs = kzalloc_node(sizeof(struct intel_shared_regs), 5317 GFP_KERNEL, cpu_to_node(cpu)); 5318 if (regs) { 5319 /* 5320 * initialize the locks to keep lockdep happy 5321 */ 5322 for (i = 0; i < EXTRA_REG_MAX; i++) 5323 raw_spin_lock_init(®s->regs[i].lock); 5324 5325 regs->core_id = -1; 5326 } 5327 return regs; 5328} 5329 5330static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu) 5331{ 5332 struct intel_excl_cntrs *c; 5333 5334 c = kzalloc_node(sizeof(struct intel_excl_cntrs), 5335 GFP_KERNEL, cpu_to_node(cpu)); 5336 if (c) { 5337 raw_spin_lock_init(&c->lock); 5338 c->core_id = -1; 5339 } 5340 return c; 5341} 5342 5343 5344int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) 5345{ 5346 cpuc->pebs_record_size = x86_pmu.pebs_record_size; 5347 5348 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { 5349 cpuc->shared_regs = allocate_shared_regs(cpu); 5350 if (!cpuc->shared_regs) 5351 goto err; 5352 } 5353 5354 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA | PMU_FL_DYN_CONSTRAINT)) { 5355 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); 5356 5357 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); 5358 if (!cpuc->constraint_list) 5359 goto err_shared_regs; 5360 } 5361 5362 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 5363 cpuc->excl_cntrs = allocate_excl_cntrs(cpu); 5364 if (!cpuc->excl_cntrs) 5365 goto err_constraint_list; 5366 5367 cpuc->excl_thread_id = 0; 5368 } 5369 5370 return 0; 5371 5372err_constraint_list: 5373 kfree(cpuc->constraint_list); 5374 cpuc->constraint_list = NULL; 5375 5376err_shared_regs: 5377 kfree(cpuc->shared_regs); 5378 cpuc->shared_regs = NULL; 5379 5380err: 5381 return -ENOMEM; 5382} 5383 5384static int intel_pmu_cpu_prepare(int cpu) 5385{ 5386 int ret; 5387 5388 ret = intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); 5389 if (ret) 5390 return ret; 5391 5392 return alloc_arch_pebs_buf_on_cpu(cpu); 5393} 5394 5395static void flip_smm_bit(void *data) 5396{ 5397 unsigned long set = *(unsigned long *)data; 5398 5399 if (set > 0) { 5400 msr_set_bit(MSR_IA32_DEBUGCTLMSR, 5401 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 5402 } else { 5403 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, 5404 DEBUGCTLMSR_FREEZE_IN_SMM_BIT); 5405 } 5406} 5407 5408static void intel_pmu_check_counters_mask(u64 *cntr_mask, 5409 u64 *fixed_cntr_mask, 5410 u64 *intel_ctrl) 5411{ 5412 unsigned int bit; 5413 5414 bit = fls64(*cntr_mask); 5415 if (bit > INTEL_PMC_MAX_GENERIC) { 5416 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", 5417 bit, INTEL_PMC_MAX_GENERIC); 5418 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); 5419 } 5420 *intel_ctrl = *cntr_mask; 5421 5422 bit = fls64(*fixed_cntr_mask); 5423 if (bit > INTEL_PMC_MAX_FIXED) { 5424 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", 5425 bit, INTEL_PMC_MAX_FIXED); 5426 *fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0); 5427 } 5428 5429 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED; 5430} 5431 5432static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 5433 u64 cntr_mask, 5434 u64 fixed_cntr_mask, 5435 u64 intel_ctrl); 5436 5437enum dyn_constr_type { 5438 DYN_CONSTR_NONE, 5439 DYN_CONSTR_BR_CNTR, 5440 DYN_CONSTR_ACR_CNTR, 5441 DYN_CONSTR_ACR_CAUSE, 5442 DYN_CONSTR_PEBS, 5443 DYN_CONSTR_PDIST, 5444 5445 DYN_CONSTR_MAX, 5446}; 5447 5448static const char * const dyn_constr_type_name[] = { 5449 [DYN_CONSTR_NONE] = "a normal event", 5450 [DYN_CONSTR_BR_CNTR] = "a branch counter logging event", 5451 [DYN_CONSTR_ACR_CNTR] = "an auto-counter reload event", 5452 [DYN_CONSTR_ACR_CAUSE] = "an auto-counter reload cause event", 5453 [DYN_CONSTR_PEBS] = "a PEBS event", 5454 [DYN_CONSTR_PDIST] = "a PEBS PDIST event", 5455}; 5456 5457static void __intel_pmu_check_dyn_constr(struct event_constraint *constr, 5458 enum dyn_constr_type type, u64 mask) 5459{ 5460 struct event_constraint *c1, *c2; 5461 int new_weight, check_weight; 5462 u64 new_mask, check_mask; 5463 5464 for_each_event_constraint(c1, constr) { 5465 new_mask = c1->idxmsk64 & mask; 5466 new_weight = hweight64(new_mask); 5467 5468 /* ignore topdown perf metrics event */ 5469 if (c1->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) 5470 continue; 5471 5472 if (!new_weight && fls64(c1->idxmsk64) < INTEL_PMC_IDX_FIXED) { 5473 pr_info("The event 0x%llx is not supported as %s.\n", 5474 c1->code, dyn_constr_type_name[type]); 5475 } 5476 5477 if (new_weight <= 1) 5478 continue; 5479 5480 for_each_event_constraint(c2, c1 + 1) { 5481 bool check_fail = false; 5482 5483 check_mask = c2->idxmsk64 & mask; 5484 check_weight = hweight64(check_mask); 5485 5486 if (c2->idxmsk64 & INTEL_PMC_MSK_TOPDOWN || 5487 !check_weight) 5488 continue; 5489 5490 /* The same constraints or no overlap */ 5491 if (new_mask == check_mask || 5492 (new_mask ^ check_mask) == (new_mask | check_mask)) 5493 continue; 5494 5495 /* 5496 * A scheduler issue may be triggered in the following cases. 5497 * - Two overlap constraints have the same weight. 5498 * E.g., A constraints: 0x3, B constraints: 0x6 5499 * event counter failure case 5500 * B PMC[2:1] 1 5501 * A PMC[1:0] 0 5502 * A PMC[1:0] FAIL 5503 * - Two overlap constraints have different weight. 5504 * The constraint has a low weight, but has high last bit. 5505 * E.g., A constraints: 0x7, B constraints: 0xC 5506 * event counter failure case 5507 * B PMC[3:2] 2 5508 * A PMC[2:0] 0 5509 * A PMC[2:0] 1 5510 * A PMC[2:0] FAIL 5511 */ 5512 if (new_weight == check_weight) { 5513 check_fail = true; 5514 } else if (new_weight < check_weight) { 5515 if ((new_mask | check_mask) != check_mask && 5516 fls64(new_mask) > fls64(check_mask)) 5517 check_fail = true; 5518 } else { 5519 if ((new_mask | check_mask) != new_mask && 5520 fls64(new_mask) < fls64(check_mask)) 5521 check_fail = true; 5522 } 5523 5524 if (check_fail) { 5525 pr_info("The two events 0x%llx and 0x%llx may not be " 5526 "fully scheduled under some circumstances as " 5527 "%s.\n", 5528 c1->code, c2->code, dyn_constr_type_name[type]); 5529 } 5530 } 5531 } 5532} 5533 5534static void intel_pmu_check_dyn_constr(struct pmu *pmu, 5535 struct event_constraint *constr, 5536 u64 cntr_mask) 5537{ 5538 enum dyn_constr_type i; 5539 u64 mask; 5540 5541 for (i = DYN_CONSTR_NONE; i < DYN_CONSTR_MAX; i++) { 5542 mask = 0; 5543 switch (i) { 5544 case DYN_CONSTR_NONE: 5545 mask = cntr_mask; 5546 break; 5547 case DYN_CONSTR_BR_CNTR: 5548 if (x86_pmu.flags & PMU_FL_BR_CNTR) 5549 mask = x86_pmu.lbr_counters; 5550 break; 5551 case DYN_CONSTR_ACR_CNTR: 5552 mask = hybrid(pmu, acr_cntr_mask64) & GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); 5553 break; 5554 case DYN_CONSTR_ACR_CAUSE: 5555 if (hybrid(pmu, acr_cntr_mask64) == hybrid(pmu, acr_cause_mask64)) 5556 continue; 5557 mask = hybrid(pmu, acr_cause_mask64) & GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); 5558 break; 5559 case DYN_CONSTR_PEBS: 5560 if (x86_pmu.arch_pebs) 5561 mask = hybrid(pmu, arch_pebs_cap).counters; 5562 break; 5563 case DYN_CONSTR_PDIST: 5564 if (x86_pmu.arch_pebs) 5565 mask = hybrid(pmu, arch_pebs_cap).pdists; 5566 break; 5567 default: 5568 pr_warn("Unsupported dynamic constraint type %d\n", i); 5569 } 5570 5571 if (mask) 5572 __intel_pmu_check_dyn_constr(constr, i, mask); 5573 } 5574} 5575 5576static void intel_pmu_check_event_constraints_all(struct pmu *pmu) 5577{ 5578 struct event_constraint *event_constraints = hybrid(pmu, event_constraints); 5579 struct event_constraint *pebs_constraints = hybrid(pmu, pebs_constraints); 5580 u64 cntr_mask = hybrid(pmu, cntr_mask64); 5581 u64 fixed_cntr_mask = hybrid(pmu, fixed_cntr_mask64); 5582 u64 intel_ctrl = hybrid(pmu, intel_ctrl); 5583 5584 intel_pmu_check_event_constraints(event_constraints, cntr_mask, 5585 fixed_cntr_mask, intel_ctrl); 5586 5587 if (event_constraints) 5588 intel_pmu_check_dyn_constr(pmu, event_constraints, cntr_mask); 5589 5590 if (pebs_constraints) 5591 intel_pmu_check_dyn_constr(pmu, pebs_constraints, cntr_mask); 5592} 5593 5594static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs); 5595 5596static inline bool intel_pmu_broken_perf_cap(void) 5597{ 5598 /* The Perf Metric (Bit 15) is always cleared */ 5599 if (boot_cpu_data.x86_vfm == INTEL_METEORLAKE || 5600 boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L) 5601 return true; 5602 5603 return false; 5604} 5605 5606static inline void __intel_update_pmu_caps(struct pmu *pmu) 5607{ 5608 struct pmu *dest_pmu = pmu ? pmu : x86_get_pmu(smp_processor_id()); 5609 5610 if (hybrid(pmu, arch_pebs_cap).caps & ARCH_PEBS_VECR_XMM) 5611 dest_pmu->capabilities |= PERF_PMU_CAP_EXTENDED_REGS; 5612} 5613 5614static inline void __intel_update_large_pebs_flags(struct pmu *pmu) 5615{ 5616 u64 caps = hybrid(pmu, arch_pebs_cap).caps; 5617 5618 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME; 5619 if (caps & ARCH_PEBS_LBR) 5620 x86_pmu.large_pebs_flags |= PERF_SAMPLE_BRANCH_STACK; 5621 if (caps & ARCH_PEBS_CNTR_MASK) 5622 x86_pmu.large_pebs_flags |= PERF_SAMPLE_READ; 5623 5624 if (!(caps & ARCH_PEBS_AUX)) 5625 x86_pmu.large_pebs_flags &= ~PERF_SAMPLE_DATA_SRC; 5626 if (!(caps & ARCH_PEBS_GPR)) { 5627 x86_pmu.large_pebs_flags &= 5628 ~(PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER); 5629 } 5630} 5631 5632#define counter_mask(_gp, _fixed) ((_gp) | ((u64)(_fixed) << INTEL_PMC_IDX_FIXED)) 5633 5634static void update_pmu_cap(struct pmu *pmu) 5635{ 5636 unsigned int eax, ebx, ecx, edx; 5637 union cpuid35_eax eax_0; 5638 union cpuid35_ebx ebx_0; 5639 u64 cntrs_mask = 0; 5640 u64 pebs_mask = 0; 5641 u64 pdists_mask = 0; 5642 5643 cpuid(ARCH_PERFMON_EXT_LEAF, &eax_0.full, &ebx_0.full, &ecx, &edx); 5644 5645 if (ebx_0.split.umask2) 5646 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_UMASK2; 5647 if (ebx_0.split.eq) 5648 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_EQ; 5649 5650 if (eax_0.split.cntr_subleaf) { 5651 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF, 5652 &eax, &ebx, &ecx, &edx); 5653 hybrid(pmu, cntr_mask64) = eax; 5654 hybrid(pmu, fixed_cntr_mask64) = ebx; 5655 cntrs_mask = counter_mask(eax, ebx); 5656 } 5657 5658 if (eax_0.split.acr_subleaf) { 5659 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_ACR_LEAF, 5660 &eax, &ebx, &ecx, &edx); 5661 /* The mask of the counters which can be reloaded */ 5662 hybrid(pmu, acr_cntr_mask64) = counter_mask(eax, ebx); 5663 /* The mask of the counters which can cause a reload of reloadable counters */ 5664 hybrid(pmu, acr_cause_mask64) = counter_mask(ecx, edx); 5665 } 5666 5667 /* Bits[5:4] should be set simultaneously if arch-PEBS is supported */ 5668 if (eax_0.split.pebs_caps_subleaf && eax_0.split.pebs_cnts_subleaf) { 5669 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_CAP_LEAF, 5670 &eax, &ebx, &ecx, &edx); 5671 hybrid(pmu, arch_pebs_cap).caps = (u64)ebx << 32; 5672 5673 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_COUNTER_LEAF, 5674 &eax, &ebx, &ecx, &edx); 5675 pebs_mask = counter_mask(eax, ecx); 5676 pdists_mask = counter_mask(ebx, edx); 5677 hybrid(pmu, arch_pebs_cap).counters = pebs_mask; 5678 hybrid(pmu, arch_pebs_cap).pdists = pdists_mask; 5679 5680 if (WARN_ON((pebs_mask | pdists_mask) & ~cntrs_mask)) { 5681 x86_pmu.arch_pebs = 0; 5682 } else { 5683 __intel_update_pmu_caps(pmu); 5684 __intel_update_large_pebs_flags(pmu); 5685 } 5686 } else { 5687 WARN_ON(x86_pmu.arch_pebs == 1); 5688 x86_pmu.arch_pebs = 0; 5689 } 5690 5691 if (!intel_pmu_broken_perf_cap()) { 5692 /* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */ 5693 rdmsrq(MSR_IA32_PERF_CAPABILITIES, hybrid(pmu, intel_cap).capabilities); 5694 } 5695} 5696 5697static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu) 5698{ 5699 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64, 5700 &pmu->intel_ctrl); 5701 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 5702 pmu->unconstrained = (struct event_constraint) 5703 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 5704 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 5705 5706 if (pmu->intel_cap.perf_metrics) 5707 pmu->intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS; 5708 else 5709 pmu->intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS; 5710 5711 intel_pmu_check_event_constraints_all(&pmu->pmu); 5712 5713 intel_pmu_check_extra_regs(pmu->extra_regs); 5714} 5715 5716static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void) 5717{ 5718 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 5719 enum intel_cpu_type cpu_type = c->topo.intel_type; 5720 int i; 5721 5722 /* 5723 * This is running on a CPU model that is known to have hybrid 5724 * configurations. But the CPU told us it is not hybrid, shame 5725 * on it. There should be a fixup function provided for these 5726 * troublesome CPUs (->get_hybrid_cpu_type). 5727 */ 5728 if (cpu_type == INTEL_CPU_TYPE_UNKNOWN) { 5729 if (x86_pmu.get_hybrid_cpu_type) 5730 cpu_type = x86_pmu.get_hybrid_cpu_type(); 5731 else 5732 return NULL; 5733 } 5734 5735 /* 5736 * This essentially just maps between the 'hybrid_cpu_type' 5737 * and 'hybrid_pmu_type' enums except for ARL-H processor 5738 * which needs to compare atom uarch native id since ARL-H 5739 * contains two different atom uarchs. 5740 */ 5741 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { 5742 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type; 5743 u32 native_id; 5744 5745 if (cpu_type == INTEL_CPU_TYPE_CORE && pmu_type == hybrid_big) 5746 return &x86_pmu.hybrid_pmu[i]; 5747 if (cpu_type == INTEL_CPU_TYPE_ATOM) { 5748 if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small) 5749 return &x86_pmu.hybrid_pmu[i]; 5750 5751 native_id = c->topo.intel_native_model_id; 5752 if (native_id == INTEL_ATOM_SKT_NATIVE_ID && pmu_type == hybrid_small) 5753 return &x86_pmu.hybrid_pmu[i]; 5754 if (native_id == INTEL_ATOM_CMT_NATIVE_ID && pmu_type == hybrid_tiny) 5755 return &x86_pmu.hybrid_pmu[i]; 5756 } 5757 } 5758 5759 return NULL; 5760} 5761 5762static bool init_hybrid_pmu(int cpu) 5763{ 5764 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 5765 struct x86_hybrid_pmu *pmu = find_hybrid_pmu_for_cpu(); 5766 5767 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) { 5768 cpuc->pmu = NULL; 5769 return false; 5770 } 5771 5772 /* Only check and dump the PMU information for the first CPU */ 5773 if (!cpumask_empty(&pmu->supported_cpus)) 5774 goto end; 5775 5776 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) 5777 update_pmu_cap(&pmu->pmu); 5778 5779 intel_pmu_check_hybrid_pmus(pmu); 5780 5781 if (!check_hw_exists(&pmu->pmu, pmu->cntr_mask, pmu->fixed_cntr_mask)) 5782 return false; 5783 5784 pr_info("%s PMU driver: ", pmu->name); 5785 5786 pr_cont("\n"); 5787 5788 x86_pmu_show_pmu_cap(&pmu->pmu); 5789 5790end: 5791 cpumask_set_cpu(cpu, &pmu->supported_cpus); 5792 cpuc->pmu = &pmu->pmu; 5793 5794 return true; 5795} 5796 5797static void intel_pmu_cpu_starting(int cpu) 5798{ 5799 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 5800 int core_id = topology_core_id(cpu); 5801 int i; 5802 5803 if (is_hybrid() && !init_hybrid_pmu(cpu)) 5804 return; 5805 5806 init_debug_store_on_cpu(cpu); 5807 init_arch_pebs_on_cpu(cpu); 5808 /* 5809 * Deal with CPUs that don't clear their LBRs on power-up, and that may 5810 * even boot with LBRs enabled. 5811 */ 5812 if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr) 5813 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_LBR_BIT); 5814 intel_pmu_lbr_reset(); 5815 5816 cpuc->lbr_sel = NULL; 5817 5818 if (x86_pmu.flags & PMU_FL_TFA) { 5819 WARN_ON_ONCE(cpuc->tfa_shadow); 5820 cpuc->tfa_shadow = ~0ULL; 5821 intel_set_tfa(cpuc, false); 5822 } 5823 5824 if (x86_pmu.version > 1) 5825 flip_smm_bit(&x86_pmu.attr_freeze_on_smi); 5826 5827 /* 5828 * Disable perf metrics if any added CPU doesn't support it. 5829 * 5830 * Turn off the check for a hybrid architecture, because the 5831 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate 5832 * the architecture features. The perf metrics is a model-specific 5833 * feature for now. The corresponding bit should always be 0 on 5834 * a hybrid platform, e.g., Alder Lake. 5835 */ 5836 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { 5837 union perf_capabilities perf_cap; 5838 5839 rdmsrq(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 5840 if (!perf_cap.perf_metrics) { 5841 x86_pmu.intel_cap.perf_metrics = 0; 5842 x86_pmu.intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS; 5843 } 5844 } 5845 5846 __intel_update_pmu_caps(cpuc->pmu); 5847 5848 if (!cpuc->shared_regs) 5849 return; 5850 5851 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { 5852 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 5853 struct intel_shared_regs *pc; 5854 5855 pc = per_cpu(cpu_hw_events, i).shared_regs; 5856 if (pc && pc->core_id == core_id) { 5857 cpuc->kfree_on_online[0] = cpuc->shared_regs; 5858 cpuc->shared_regs = pc; 5859 break; 5860 } 5861 } 5862 cpuc->shared_regs->core_id = core_id; 5863 cpuc->shared_regs->refcnt++; 5864 } 5865 5866 if (x86_pmu.lbr_sel_map) 5867 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; 5868 5869 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { 5870 for_each_cpu(i, topology_sibling_cpumask(cpu)) { 5871 struct cpu_hw_events *sibling; 5872 struct intel_excl_cntrs *c; 5873 5874 sibling = &per_cpu(cpu_hw_events, i); 5875 c = sibling->excl_cntrs; 5876 if (c && c->core_id == core_id) { 5877 cpuc->kfree_on_online[1] = cpuc->excl_cntrs; 5878 cpuc->excl_cntrs = c; 5879 if (!sibling->excl_thread_id) 5880 cpuc->excl_thread_id = 1; 5881 break; 5882 } 5883 } 5884 cpuc->excl_cntrs->core_id = core_id; 5885 cpuc->excl_cntrs->refcnt++; 5886 } 5887} 5888 5889static void free_excl_cntrs(struct cpu_hw_events *cpuc) 5890{ 5891 struct intel_excl_cntrs *c; 5892 5893 c = cpuc->excl_cntrs; 5894 if (c) { 5895 if (c->core_id == -1 || --c->refcnt == 0) 5896 kfree(c); 5897 cpuc->excl_cntrs = NULL; 5898 } 5899 5900 kfree(cpuc->constraint_list); 5901 cpuc->constraint_list = NULL; 5902} 5903 5904static void intel_pmu_cpu_dying(int cpu) 5905{ 5906 fini_debug_store_on_cpu(cpu); 5907 fini_arch_pebs_on_cpu(cpu); 5908} 5909 5910void intel_cpuc_finish(struct cpu_hw_events *cpuc) 5911{ 5912 struct intel_shared_regs *pc; 5913 5914 pc = cpuc->shared_regs; 5915 if (pc) { 5916 if (pc->core_id == -1 || --pc->refcnt == 0) 5917 kfree(pc); 5918 cpuc->shared_regs = NULL; 5919 } 5920 5921 free_excl_cntrs(cpuc); 5922} 5923 5924static void intel_pmu_cpu_dead(int cpu) 5925{ 5926 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 5927 5928 release_arch_pebs_buf_on_cpu(cpu); 5929 intel_cpuc_finish(cpuc); 5930 5931 if (is_hybrid() && cpuc->pmu) 5932 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); 5933} 5934 5935static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, 5936 struct task_struct *task, bool sched_in) 5937{ 5938 intel_pmu_pebs_sched_task(pmu_ctx, sched_in); 5939 intel_pmu_lbr_sched_task(pmu_ctx, task, sched_in); 5940} 5941 5942static int intel_pmu_check_period(struct perf_event *event, u64 value) 5943{ 5944 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0; 5945} 5946 5947static void intel_aux_output_init(void) 5948{ 5949 /* Refer also intel_pmu_aux_output_match() */ 5950 if (x86_pmu.intel_cap.pebs_output_pt_available) 5951 x86_pmu.assign = intel_pmu_assign_event; 5952} 5953 5954static int intel_pmu_aux_output_match(struct perf_event *event) 5955{ 5956 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */ 5957 if (!x86_pmu.intel_cap.pebs_output_pt_available) 5958 return 0; 5959 5960 return is_intel_pt_event(event); 5961} 5962 5963static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret) 5964{ 5965 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu); 5966 5967 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus); 5968} 5969 5970PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); 5971 5972PMU_FORMAT_ATTR(ldlat, "config1:0-15"); 5973 5974PMU_FORMAT_ATTR(frontend, "config1:0-23"); 5975 5976PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63"); 5977 5978static struct attribute *intel_arch3_formats_attr[] = { 5979 &format_attr_event.attr, 5980 &format_attr_umask.attr, 5981 &format_attr_edge.attr, 5982 &format_attr_pc.attr, 5983 &format_attr_any.attr, 5984 &format_attr_inv.attr, 5985 &format_attr_cmask.attr, 5986 NULL, 5987}; 5988 5989static struct attribute *hsw_format_attr[] = { 5990 &format_attr_in_tx.attr, 5991 &format_attr_in_tx_cp.attr, 5992 &format_attr_offcore_rsp.attr, 5993 &format_attr_ldlat.attr, 5994 NULL 5995}; 5996 5997static struct attribute *nhm_format_attr[] = { 5998 &format_attr_offcore_rsp.attr, 5999 &format_attr_ldlat.attr, 6000 NULL 6001}; 6002 6003static struct attribute *slm_format_attr[] = { 6004 &format_attr_offcore_rsp.attr, 6005 NULL 6006}; 6007 6008static struct attribute *cmt_format_attr[] = { 6009 &format_attr_offcore_rsp.attr, 6010 &format_attr_ldlat.attr, 6011 &format_attr_snoop_rsp.attr, 6012 NULL 6013}; 6014 6015static struct attribute *skl_format_attr[] = { 6016 &format_attr_frontend.attr, 6017 NULL, 6018}; 6019 6020static __initconst const struct x86_pmu core_pmu = { 6021 .name = "core", 6022 .handle_irq = x86_pmu_handle_irq, 6023 .disable_all = x86_pmu_disable_all, 6024 .enable_all = core_pmu_enable_all, 6025 .enable = core_pmu_enable_event, 6026 .disable = x86_pmu_disable_event, 6027 .hw_config = core_pmu_hw_config, 6028 .schedule_events = x86_schedule_events, 6029 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 6030 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 6031 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0, 6032 .event_map = intel_pmu_event_map, 6033 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 6034 .apic = 1, 6035 .large_pebs_flags = LARGE_PEBS_FLAGS, 6036 6037 /* 6038 * Intel PMCs cannot be accessed sanely above 32-bit width, 6039 * so we install an artificial 1<<31 period regardless of 6040 * the generic event period: 6041 */ 6042 .max_period = (1ULL<<31) - 1, 6043 .get_event_constraints = intel_get_event_constraints, 6044 .put_event_constraints = intel_put_event_constraints, 6045 .event_constraints = intel_core_event_constraints, 6046 .guest_get_msrs = core_guest_get_msrs, 6047 .format_attrs = intel_arch_formats_attr, 6048 .events_sysfs_show = intel_event_sysfs_show, 6049 6050 /* 6051 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs 6052 * together with PMU version 1 and thus be using core_pmu with 6053 * shared_regs. We need following callbacks here to allocate 6054 * it properly. 6055 */ 6056 .cpu_prepare = intel_pmu_cpu_prepare, 6057 .cpu_starting = intel_pmu_cpu_starting, 6058 .cpu_dying = intel_pmu_cpu_dying, 6059 .cpu_dead = intel_pmu_cpu_dead, 6060 6061 .check_period = intel_pmu_check_period, 6062 6063 .lbr_reset = intel_pmu_lbr_reset_64, 6064 .lbr_read = intel_pmu_lbr_read_64, 6065 .lbr_save = intel_pmu_lbr_save, 6066 .lbr_restore = intel_pmu_lbr_restore, 6067}; 6068 6069static __initconst const struct x86_pmu intel_pmu = { 6070 .name = "Intel", 6071 .handle_irq = intel_pmu_handle_irq, 6072 .disable_all = intel_pmu_disable_all, 6073 .enable_all = intel_pmu_enable_all, 6074 .enable = intel_pmu_enable_event, 6075 .disable = intel_pmu_disable_event, 6076 .add = intel_pmu_add_event, 6077 .del = intel_pmu_del_event, 6078 .read = intel_pmu_read_event, 6079 .set_period = intel_pmu_set_period, 6080 .update = intel_pmu_update, 6081 .hw_config = intel_pmu_hw_config, 6082 .schedule_events = x86_schedule_events, 6083 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, 6084 .perfctr = MSR_ARCH_PERFMON_PERFCTR0, 6085 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0, 6086 .event_map = intel_pmu_event_map, 6087 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 6088 .apic = 1, 6089 .large_pebs_flags = LARGE_PEBS_FLAGS, 6090 /* 6091 * Intel PMCs cannot be accessed sanely above 32 bit width, 6092 * so we install an artificial 1<<31 period regardless of 6093 * the generic event period: 6094 */ 6095 .max_period = (1ULL << 31) - 1, 6096 .get_event_constraints = intel_get_event_constraints, 6097 .put_event_constraints = intel_put_event_constraints, 6098 .pebs_aliases = intel_pebs_aliases_core2, 6099 6100 .format_attrs = intel_arch3_formats_attr, 6101 .events_sysfs_show = intel_event_sysfs_show, 6102 6103 .cpu_prepare = intel_pmu_cpu_prepare, 6104 .cpu_starting = intel_pmu_cpu_starting, 6105 .cpu_dying = intel_pmu_cpu_dying, 6106 .cpu_dead = intel_pmu_cpu_dead, 6107 6108 .guest_get_msrs = intel_guest_get_msrs, 6109 .sched_task = intel_pmu_sched_task, 6110 6111 .check_period = intel_pmu_check_period, 6112 6113 .aux_output_match = intel_pmu_aux_output_match, 6114 6115 .lbr_reset = intel_pmu_lbr_reset_64, 6116 .lbr_read = intel_pmu_lbr_read_64, 6117 .lbr_save = intel_pmu_lbr_save, 6118 .lbr_restore = intel_pmu_lbr_restore, 6119 6120 /* 6121 * SMM has access to all 4 rings and while traditionally SMM code only 6122 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM. 6123 * 6124 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction 6125 * between SMM or not, this results in what should be pure userspace 6126 * counters including SMM data. 6127 * 6128 * This is a clear privilege issue, therefore globally disable 6129 * counting SMM by default. 6130 */ 6131 .attr_freeze_on_smi = 1, 6132}; 6133 6134static __init void intel_clovertown_quirk(void) 6135{ 6136 /* 6137 * PEBS is unreliable due to: 6138 * 6139 * AJ67 - PEBS may experience CPL leaks 6140 * AJ68 - PEBS PMI may be delayed by one event 6141 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] 6142 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS 6143 * 6144 * AJ67 could be worked around by restricting the OS/USR flags. 6145 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. 6146 * 6147 * AJ106 could possibly be worked around by not allowing LBR 6148 * usage from PEBS, including the fixup. 6149 * AJ68 could possibly be worked around by always programming 6150 * a pebs_event_reset[0] value and coping with the lost events. 6151 * 6152 * But taken together it might just make sense to not enable PEBS on 6153 * these chips. 6154 */ 6155 pr_warn("PEBS disabled due to CPU errata\n"); 6156 x86_pmu.ds_pebs = 0; 6157 x86_pmu.pebs_constraints = NULL; 6158} 6159 6160static const struct x86_cpu_id isolation_ucodes[] = { 6161 X86_MATCH_VFM_STEPS(INTEL_HASWELL, 3, 3, 0x0000001f), 6162 X86_MATCH_VFM_STEPS(INTEL_HASWELL_L, 1, 1, 0x0000001e), 6163 X86_MATCH_VFM_STEPS(INTEL_HASWELL_G, 1, 1, 0x00000015), 6164 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 2, 2, 0x00000037), 6165 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 4, 4, 0x0000000a), 6166 X86_MATCH_VFM_STEPS(INTEL_BROADWELL, 4, 4, 0x00000023), 6167 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_G, 1, 1, 0x00000014), 6168 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 2, 2, 0x00000010), 6169 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 3, 3, 0x07000009), 6170 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 4, 4, 0x0f000009), 6171 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 5, 5, 0x0e000002), 6172 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_X, 1, 1, 0x0b000014), 6173 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 3, 3, 0x00000021), 6174 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 4, 7, 0x00000000), 6175 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 11, 11, 0x00000000), 6176 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_L, 3, 3, 0x0000007c), 6177 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE, 3, 3, 0x0000007c), 6178 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE, 9, 13, 0x0000004e), 6179 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE_L, 9, 12, 0x0000004e), 6180 {} 6181}; 6182 6183static void intel_check_pebs_isolation(void) 6184{ 6185 x86_pmu.pebs_no_isolation = !x86_match_min_microcode_rev(isolation_ucodes); 6186} 6187 6188static __init void intel_pebs_isolation_quirk(void) 6189{ 6190 WARN_ON_ONCE(x86_pmu.check_microcode); 6191 x86_pmu.check_microcode = intel_check_pebs_isolation; 6192 intel_check_pebs_isolation(); 6193} 6194 6195static const struct x86_cpu_id pebs_ucodes[] = { 6196 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE, 7, 7, 0x00000028), 6197 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 6, 6, 0x00000618), 6198 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 7, 7, 0x0000070c), 6199 {} 6200}; 6201 6202static bool intel_snb_pebs_broken(void) 6203{ 6204 return !x86_match_min_microcode_rev(pebs_ucodes); 6205} 6206 6207static void intel_snb_check_microcode(void) 6208{ 6209 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken) 6210 return; 6211 6212 /* 6213 * Serialized by the microcode lock.. 6214 */ 6215 if (x86_pmu.pebs_broken) { 6216 pr_info("PEBS enabled due to microcode update\n"); 6217 x86_pmu.pebs_broken = 0; 6218 } else { 6219 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); 6220 x86_pmu.pebs_broken = 1; 6221 } 6222} 6223 6224static bool is_lbr_from(unsigned long msr) 6225{ 6226 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; 6227 6228 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; 6229} 6230 6231/* 6232 * Under certain circumstances, access certain MSR may cause #GP. 6233 * The function tests if the input MSR can be safely accessed. 6234 */ 6235static bool check_msr(unsigned long msr, u64 mask) 6236{ 6237 u64 val_old, val_new, val_tmp; 6238 6239 /* 6240 * Disable the check for real HW, so we don't 6241 * mess with potentially enabled registers: 6242 */ 6243 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 6244 return true; 6245 6246 /* 6247 * Read the current value, change it and read it back to see if it 6248 * matches, this is needed to detect certain hardware emulators 6249 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 6250 */ 6251 if (rdmsrq_safe(msr, &val_old)) 6252 return false; 6253 6254 /* 6255 * Only change the bits which can be updated by wrmsrq. 6256 */ 6257 val_tmp = val_old ^ mask; 6258 6259 if (is_lbr_from(msr)) 6260 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 6261 6262 if (wrmsrq_safe(msr, val_tmp) || 6263 rdmsrq_safe(msr, &val_new)) 6264 return false; 6265 6266 /* 6267 * Quirk only affects validation in wrmsr(), so wrmsrq()'s value 6268 * should equal rdmsrq()'s even with the quirk. 6269 */ 6270 if (val_new != val_tmp) 6271 return false; 6272 6273 if (is_lbr_from(msr)) 6274 val_old = lbr_from_signext_quirk_wr(val_old); 6275 6276 /* Here it's sure that the MSR can be safely accessed. 6277 * Restore the old value and return. 6278 */ 6279 wrmsrq(msr, val_old); 6280 6281 return true; 6282} 6283 6284static __init void intel_sandybridge_quirk(void) 6285{ 6286 x86_pmu.check_microcode = intel_snb_check_microcode; 6287 cpus_read_lock(); 6288 intel_snb_check_microcode(); 6289 cpus_read_unlock(); 6290} 6291 6292static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { 6293 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, 6294 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, 6295 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, 6296 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, 6297 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, 6298 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, 6299 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, 6300}; 6301 6302static __init void intel_arch_events_quirk(void) 6303{ 6304 int bit; 6305 6306 /* disable event that reported as not present by cpuid */ 6307 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { 6308 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; 6309 pr_warn("CPUID marked event: \'%s\' unavailable\n", 6310 intel_arch_events_map[bit].name); 6311 } 6312} 6313 6314static __init void intel_nehalem_quirk(void) 6315{ 6316 union cpuid10_ebx ebx; 6317 6318 ebx.full = x86_pmu.events_maskl; 6319 if (ebx.split.no_branch_misses_retired) { 6320 /* 6321 * Erratum AAJ80 detected, we work it around by using 6322 * the BR_MISP_EXEC.ANY event. This will over-count 6323 * branch-misses, but it's still much better than the 6324 * architectural event which is often completely bogus: 6325 */ 6326 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; 6327 ebx.split.no_branch_misses_retired = 0; 6328 x86_pmu.events_maskl = ebx.full; 6329 pr_info("CPU erratum AAJ80 worked around\n"); 6330 } 6331} 6332 6333/* 6334 * enable software workaround for errata: 6335 * SNB: BJ122 6336 * IVB: BV98 6337 * HSW: HSD29 6338 * 6339 * Only needed when HT is enabled. However detecting 6340 * if HT is enabled is difficult (model specific). So instead, 6341 * we enable the workaround in the early boot, and verify if 6342 * it is needed in a later initcall phase once we have valid 6343 * topology information to check if HT is actually enabled 6344 */ 6345static __init void intel_ht_bug(void) 6346{ 6347 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; 6348 6349 x86_pmu.start_scheduling = intel_start_scheduling; 6350 x86_pmu.commit_scheduling = intel_commit_scheduling; 6351 x86_pmu.stop_scheduling = intel_stop_scheduling; 6352} 6353 6354EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3"); 6355EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82") 6356 6357/* Haswell special events */ 6358EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1"); 6359EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2"); 6360EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4"); 6361EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2"); 6362EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1"); 6363EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1"); 6364EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2"); 6365EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4"); 6366EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2"); 6367EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1"); 6368EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1"); 6369EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1"); 6370 6371static struct attribute *hsw_events_attrs[] = { 6372 EVENT_PTR(td_slots_issued), 6373 EVENT_PTR(td_slots_retired), 6374 EVENT_PTR(td_fetch_bubbles), 6375 EVENT_PTR(td_total_slots), 6376 EVENT_PTR(td_total_slots_scale), 6377 EVENT_PTR(td_recovery_bubbles), 6378 EVENT_PTR(td_recovery_bubbles_scale), 6379 NULL 6380}; 6381 6382static struct attribute *hsw_mem_events_attrs[] = { 6383 EVENT_PTR(mem_ld_hsw), 6384 EVENT_PTR(mem_st_hsw), 6385 NULL, 6386}; 6387 6388static struct attribute *hsw_tsx_events_attrs[] = { 6389 EVENT_PTR(tx_start), 6390 EVENT_PTR(tx_commit), 6391 EVENT_PTR(tx_abort), 6392 EVENT_PTR(tx_capacity), 6393 EVENT_PTR(tx_conflict), 6394 EVENT_PTR(el_start), 6395 EVENT_PTR(el_commit), 6396 EVENT_PTR(el_abort), 6397 EVENT_PTR(el_capacity), 6398 EVENT_PTR(el_conflict), 6399 EVENT_PTR(cycles_t), 6400 EVENT_PTR(cycles_ct), 6401 NULL 6402}; 6403 6404EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80"); 6405EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2"); 6406EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80"); 6407EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2"); 6408 6409static struct attribute *icl_events_attrs[] = { 6410 EVENT_PTR(mem_ld_hsw), 6411 EVENT_PTR(mem_st_hsw), 6412 NULL, 6413}; 6414 6415static struct attribute *icl_td_events_attrs[] = { 6416 EVENT_PTR(slots), 6417 EVENT_PTR(td_retiring), 6418 EVENT_PTR(td_bad_spec), 6419 EVENT_PTR(td_fe_bound), 6420 EVENT_PTR(td_be_bound), 6421 NULL, 6422}; 6423 6424static struct attribute *icl_tsx_events_attrs[] = { 6425 EVENT_PTR(tx_start), 6426 EVENT_PTR(tx_abort), 6427 EVENT_PTR(tx_commit), 6428 EVENT_PTR(tx_capacity_read), 6429 EVENT_PTR(tx_capacity_write), 6430 EVENT_PTR(tx_conflict), 6431 EVENT_PTR(el_start), 6432 EVENT_PTR(el_abort), 6433 EVENT_PTR(el_commit), 6434 EVENT_PTR(el_capacity_read), 6435 EVENT_PTR(el_capacity_write), 6436 EVENT_PTR(el_conflict), 6437 EVENT_PTR(cycles_t), 6438 EVENT_PTR(cycles_ct), 6439 NULL, 6440}; 6441 6442 6443EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2"); 6444EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82"); 6445 6446static struct attribute *glc_events_attrs[] = { 6447 EVENT_PTR(mem_ld_hsw), 6448 EVENT_PTR(mem_st_spr), 6449 EVENT_PTR(mem_ld_aux), 6450 NULL, 6451}; 6452 6453static struct attribute *glc_td_events_attrs[] = { 6454 EVENT_PTR(slots), 6455 EVENT_PTR(td_retiring), 6456 EVENT_PTR(td_bad_spec), 6457 EVENT_PTR(td_fe_bound), 6458 EVENT_PTR(td_be_bound), 6459 EVENT_PTR(td_heavy_ops), 6460 EVENT_PTR(td_br_mispredict), 6461 EVENT_PTR(td_fetch_lat), 6462 EVENT_PTR(td_mem_bound), 6463 NULL, 6464}; 6465 6466static struct attribute *glc_tsx_events_attrs[] = { 6467 EVENT_PTR(tx_start), 6468 EVENT_PTR(tx_abort), 6469 EVENT_PTR(tx_commit), 6470 EVENT_PTR(tx_capacity_read), 6471 EVENT_PTR(tx_capacity_write), 6472 EVENT_PTR(tx_conflict), 6473 EVENT_PTR(cycles_t), 6474 EVENT_PTR(cycles_ct), 6475 NULL, 6476}; 6477 6478static ssize_t freeze_on_smi_show(struct device *cdev, 6479 struct device_attribute *attr, 6480 char *buf) 6481{ 6482 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi); 6483} 6484 6485static DEFINE_MUTEX(freeze_on_smi_mutex); 6486 6487static ssize_t freeze_on_smi_store(struct device *cdev, 6488 struct device_attribute *attr, 6489 const char *buf, size_t count) 6490{ 6491 unsigned long val; 6492 ssize_t ret; 6493 6494 ret = kstrtoul(buf, 0, &val); 6495 if (ret) 6496 return ret; 6497 6498 if (val > 1) 6499 return -EINVAL; 6500 6501 mutex_lock(&freeze_on_smi_mutex); 6502 6503 if (x86_pmu.attr_freeze_on_smi == val) 6504 goto done; 6505 6506 x86_pmu.attr_freeze_on_smi = val; 6507 6508 cpus_read_lock(); 6509 on_each_cpu(flip_smm_bit, &val, 1); 6510 cpus_read_unlock(); 6511done: 6512 mutex_unlock(&freeze_on_smi_mutex); 6513 6514 return count; 6515} 6516 6517static void update_tfa_sched(void *ignored) 6518{ 6519 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 6520 6521 /* 6522 * check if PMC3 is used 6523 * and if so force schedule out for all event types all contexts 6524 */ 6525 if (test_bit(3, cpuc->active_mask)) 6526 perf_pmu_resched(x86_get_pmu(smp_processor_id())); 6527} 6528 6529static ssize_t show_sysctl_tfa(struct device *cdev, 6530 struct device_attribute *attr, 6531 char *buf) 6532{ 6533 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort); 6534} 6535 6536static ssize_t set_sysctl_tfa(struct device *cdev, 6537 struct device_attribute *attr, 6538 const char *buf, size_t count) 6539{ 6540 bool val; 6541 ssize_t ret; 6542 6543 ret = kstrtobool(buf, &val); 6544 if (ret) 6545 return ret; 6546 6547 /* no change */ 6548 if (val == allow_tsx_force_abort) 6549 return count; 6550 6551 allow_tsx_force_abort = val; 6552 6553 cpus_read_lock(); 6554 on_each_cpu(update_tfa_sched, NULL, 1); 6555 cpus_read_unlock(); 6556 6557 return count; 6558} 6559 6560 6561static DEVICE_ATTR_RW(freeze_on_smi); 6562 6563static ssize_t branches_show(struct device *cdev, 6564 struct device_attribute *attr, 6565 char *buf) 6566{ 6567 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); 6568} 6569 6570static DEVICE_ATTR_RO(branches); 6571 6572static ssize_t branch_counter_nr_show(struct device *cdev, 6573 struct device_attribute *attr, 6574 char *buf) 6575{ 6576 return snprintf(buf, PAGE_SIZE, "%d\n", fls(x86_pmu.lbr_counters)); 6577} 6578 6579static DEVICE_ATTR_RO(branch_counter_nr); 6580 6581static ssize_t branch_counter_width_show(struct device *cdev, 6582 struct device_attribute *attr, 6583 char *buf) 6584{ 6585 return snprintf(buf, PAGE_SIZE, "%d\n", LBR_INFO_BR_CNTR_BITS); 6586} 6587 6588static DEVICE_ATTR_RO(branch_counter_width); 6589 6590static struct attribute *lbr_attrs[] = { 6591 &dev_attr_branches.attr, 6592 &dev_attr_branch_counter_nr.attr, 6593 &dev_attr_branch_counter_width.attr, 6594 NULL 6595}; 6596 6597static umode_t 6598lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6599{ 6600 /* branches */ 6601 if (i == 0) 6602 return x86_pmu.lbr_nr ? attr->mode : 0; 6603 6604 return (x86_pmu.flags & PMU_FL_BR_CNTR) ? attr->mode : 0; 6605} 6606 6607static char pmu_name_str[30]; 6608 6609static DEVICE_STRING_ATTR_RO(pmu_name, 0444, pmu_name_str); 6610 6611static struct attribute *intel_pmu_caps_attrs[] = { 6612 &dev_attr_pmu_name.attr.attr, 6613 NULL 6614}; 6615 6616static DEVICE_ATTR(allow_tsx_force_abort, 0644, 6617 show_sysctl_tfa, 6618 set_sysctl_tfa); 6619 6620static struct attribute *intel_pmu_attrs[] = { 6621 &dev_attr_freeze_on_smi.attr, 6622 &dev_attr_allow_tsx_force_abort.attr, 6623 NULL, 6624}; 6625 6626static umode_t 6627default_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6628{ 6629 if (attr == &dev_attr_allow_tsx_force_abort.attr) 6630 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0; 6631 6632 return attr->mode; 6633} 6634 6635static umode_t 6636tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6637{ 6638 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0; 6639} 6640 6641static umode_t 6642pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6643{ 6644 return intel_pmu_has_pebs() ? attr->mode : 0; 6645} 6646 6647static umode_t 6648mem_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6649{ 6650 if (attr == &event_attr_mem_ld_aux.attr.attr) 6651 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0; 6652 6653 return pebs_is_visible(kobj, attr, i); 6654} 6655 6656static umode_t 6657exra_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6658{ 6659 return x86_pmu.version >= 2 ? attr->mode : 0; 6660} 6661 6662static umode_t 6663td_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6664{ 6665 /* 6666 * Hide the perf metrics topdown events 6667 * if the feature is not enumerated. 6668 */ 6669 if (x86_pmu.num_topdown_events) 6670 return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0; 6671 6672 return attr->mode; 6673} 6674 6675PMU_FORMAT_ATTR(acr_mask, "config2:0-63"); 6676 6677static struct attribute *format_acr_attrs[] = { 6678 &format_attr_acr_mask.attr, 6679 NULL 6680}; 6681 6682static umode_t 6683acr_is_visible(struct kobject *kobj, struct attribute *attr, int i) 6684{ 6685 struct device *dev = kobj_to_dev(kobj); 6686 6687 return intel_pmu_has_acr(dev_get_drvdata(dev)) ? attr->mode : 0; 6688} 6689 6690static struct attribute_group group_events_td = { 6691 .name = "events", 6692 .is_visible = td_is_visible, 6693}; 6694 6695static struct attribute_group group_events_mem = { 6696 .name = "events", 6697 .is_visible = mem_is_visible, 6698}; 6699 6700static struct attribute_group group_events_tsx = { 6701 .name = "events", 6702 .is_visible = tsx_is_visible, 6703}; 6704 6705static struct attribute_group group_caps_gen = { 6706 .name = "caps", 6707 .attrs = intel_pmu_caps_attrs, 6708}; 6709 6710static struct attribute_group group_caps_lbr = { 6711 .name = "caps", 6712 .attrs = lbr_attrs, 6713 .is_visible = lbr_is_visible, 6714}; 6715 6716static struct attribute_group group_format_extra = { 6717 .name = "format", 6718 .is_visible = exra_is_visible, 6719}; 6720 6721static struct attribute_group group_format_extra_skl = { 6722 .name = "format", 6723 .is_visible = exra_is_visible, 6724}; 6725 6726static struct attribute_group group_format_evtsel_ext = { 6727 .name = "format", 6728 .attrs = format_evtsel_ext_attrs, 6729 .is_visible = evtsel_ext_is_visible, 6730}; 6731 6732static struct attribute_group group_format_acr = { 6733 .name = "format", 6734 .attrs = format_acr_attrs, 6735 .is_visible = acr_is_visible, 6736}; 6737 6738static struct attribute_group group_default = { 6739 .attrs = intel_pmu_attrs, 6740 .is_visible = default_is_visible, 6741}; 6742 6743static const struct attribute_group *attr_update[] = { 6744 &group_events_td, 6745 &group_events_mem, 6746 &group_events_tsx, 6747 &group_caps_gen, 6748 &group_caps_lbr, 6749 &group_format_extra, 6750 &group_format_extra_skl, 6751 &group_format_evtsel_ext, 6752 &group_format_acr, 6753 &group_default, 6754 NULL, 6755}; 6756 6757EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big); 6758EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small); 6759EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small); 6760EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small); 6761EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small); 6762EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big); 6763EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big); 6764EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big); 6765EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big); 6766 6767static struct attribute *adl_hybrid_events_attrs[] = { 6768 EVENT_PTR(slots_adl), 6769 EVENT_PTR(td_retiring_adl), 6770 EVENT_PTR(td_bad_spec_adl), 6771 EVENT_PTR(td_fe_bound_adl), 6772 EVENT_PTR(td_be_bound_adl), 6773 EVENT_PTR(td_heavy_ops_adl), 6774 EVENT_PTR(td_br_mis_adl), 6775 EVENT_PTR(td_fetch_lat_adl), 6776 EVENT_PTR(td_mem_bound_adl), 6777 NULL, 6778}; 6779 6780EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_lnl, "event=0xc2,umask=0x02;event=0x00,umask=0x80", hybrid_big_small); 6781EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_lnl, "event=0x9c,umask=0x01;event=0x00,umask=0x82", hybrid_big_small); 6782EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_lnl, "event=0xa4,umask=0x02;event=0x00,umask=0x83", hybrid_big_small); 6783 6784static struct attribute *lnl_hybrid_events_attrs[] = { 6785 EVENT_PTR(slots_adl), 6786 EVENT_PTR(td_retiring_lnl), 6787 EVENT_PTR(td_bad_spec_adl), 6788 EVENT_PTR(td_fe_bound_lnl), 6789 EVENT_PTR(td_be_bound_lnl), 6790 EVENT_PTR(td_heavy_ops_adl), 6791 EVENT_PTR(td_br_mis_adl), 6792 EVENT_PTR(td_fetch_lat_adl), 6793 EVENT_PTR(td_mem_bound_adl), 6794 NULL 6795}; 6796 6797/* The event string must be in PMU IDX order. */ 6798EVENT_ATTR_STR_HYBRID(topdown-retiring, 6799 td_retiring_arl_h, 6800 "event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0", 6801 hybrid_big_small_tiny); 6802EVENT_ATTR_STR_HYBRID(topdown-bad-spec, 6803 td_bad_spec_arl_h, 6804 "event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0", 6805 hybrid_big_small_tiny); 6806EVENT_ATTR_STR_HYBRID(topdown-fe-bound, 6807 td_fe_bound_arl_h, 6808 "event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0", 6809 hybrid_big_small_tiny); 6810EVENT_ATTR_STR_HYBRID(topdown-be-bound, 6811 td_be_bound_arl_h, 6812 "event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0", 6813 hybrid_big_small_tiny); 6814 6815static struct attribute *arl_h_hybrid_events_attrs[] = { 6816 EVENT_PTR(slots_adl), 6817 EVENT_PTR(td_retiring_arl_h), 6818 EVENT_PTR(td_bad_spec_arl_h), 6819 EVENT_PTR(td_fe_bound_arl_h), 6820 EVENT_PTR(td_be_bound_arl_h), 6821 EVENT_PTR(td_heavy_ops_adl), 6822 EVENT_PTR(td_br_mis_adl), 6823 EVENT_PTR(td_fetch_lat_adl), 6824 EVENT_PTR(td_mem_bound_adl), 6825 NULL, 6826}; 6827 6828/* Must be in IDX order */ 6829EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small); 6830EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small); 6831EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big); 6832 6833static struct attribute *adl_hybrid_mem_attrs[] = { 6834 EVENT_PTR(mem_ld_adl), 6835 EVENT_PTR(mem_st_adl), 6836 EVENT_PTR(mem_ld_aux_adl), 6837 NULL, 6838}; 6839 6840static struct attribute *mtl_hybrid_mem_attrs[] = { 6841 EVENT_PTR(mem_ld_adl), 6842 EVENT_PTR(mem_st_adl), 6843 NULL 6844}; 6845 6846EVENT_ATTR_STR_HYBRID(mem-loads, 6847 mem_ld_arl_h, 6848 "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3", 6849 hybrid_big_small_tiny); 6850EVENT_ATTR_STR_HYBRID(mem-stores, 6851 mem_st_arl_h, 6852 "event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6", 6853 hybrid_big_small_tiny); 6854 6855static struct attribute *arl_h_hybrid_mem_attrs[] = { 6856 EVENT_PTR(mem_ld_arl_h), 6857 EVENT_PTR(mem_st_arl_h), 6858 NULL, 6859}; 6860 6861EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big); 6862EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big); 6863EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big); 6864EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big); 6865EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big); 6866EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big); 6867EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big); 6868EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big); 6869 6870static struct attribute *adl_hybrid_tsx_attrs[] = { 6871 EVENT_PTR(tx_start_adl), 6872 EVENT_PTR(tx_abort_adl), 6873 EVENT_PTR(tx_commit_adl), 6874 EVENT_PTR(tx_capacity_read_adl), 6875 EVENT_PTR(tx_capacity_write_adl), 6876 EVENT_PTR(tx_conflict_adl), 6877 EVENT_PTR(cycles_t_adl), 6878 EVENT_PTR(cycles_ct_adl), 6879 NULL, 6880}; 6881 6882FORMAT_ATTR_HYBRID(in_tx, hybrid_big); 6883FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); 6884FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny); 6885FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_tiny); 6886FORMAT_ATTR_HYBRID(frontend, hybrid_big); 6887 6888#define ADL_HYBRID_RTM_FORMAT_ATTR \ 6889 FORMAT_HYBRID_PTR(in_tx), \ 6890 FORMAT_HYBRID_PTR(in_tx_cp) 6891 6892#define ADL_HYBRID_FORMAT_ATTR \ 6893 FORMAT_HYBRID_PTR(offcore_rsp), \ 6894 FORMAT_HYBRID_PTR(ldlat), \ 6895 FORMAT_HYBRID_PTR(frontend) 6896 6897static struct attribute *adl_hybrid_extra_attr_rtm[] = { 6898 ADL_HYBRID_RTM_FORMAT_ATTR, 6899 ADL_HYBRID_FORMAT_ATTR, 6900 NULL 6901}; 6902 6903static struct attribute *adl_hybrid_extra_attr[] = { 6904 ADL_HYBRID_FORMAT_ATTR, 6905 NULL 6906}; 6907 6908FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small_tiny); 6909 6910static struct attribute *mtl_hybrid_extra_attr_rtm[] = { 6911 ADL_HYBRID_RTM_FORMAT_ATTR, 6912 ADL_HYBRID_FORMAT_ATTR, 6913 FORMAT_HYBRID_PTR(snoop_rsp), 6914 NULL 6915}; 6916 6917static struct attribute *mtl_hybrid_extra_attr[] = { 6918 ADL_HYBRID_FORMAT_ATTR, 6919 FORMAT_HYBRID_PTR(snoop_rsp), 6920 NULL 6921}; 6922 6923static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr) 6924{ 6925 struct device *dev = kobj_to_dev(kobj); 6926 struct x86_hybrid_pmu *pmu = 6927 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6928 struct perf_pmu_events_hybrid_attr *pmu_attr = 6929 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr); 6930 6931 return pmu->pmu_type & pmu_attr->pmu_type; 6932} 6933 6934static umode_t hybrid_events_is_visible(struct kobject *kobj, 6935 struct attribute *attr, int i) 6936{ 6937 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0; 6938} 6939 6940static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu) 6941{ 6942 int cpu = cpumask_first(&pmu->supported_cpus); 6943 6944 return (cpu >= nr_cpu_ids) ? -1 : cpu; 6945} 6946 6947static umode_t hybrid_tsx_is_visible(struct kobject *kobj, 6948 struct attribute *attr, int i) 6949{ 6950 struct device *dev = kobj_to_dev(kobj); 6951 struct x86_hybrid_pmu *pmu = 6952 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6953 int cpu = hybrid_find_supported_cpu(pmu); 6954 6955 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0; 6956} 6957 6958static umode_t hybrid_format_is_visible(struct kobject *kobj, 6959 struct attribute *attr, int i) 6960{ 6961 struct device *dev = kobj_to_dev(kobj); 6962 struct x86_hybrid_pmu *pmu = 6963 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6964 struct perf_pmu_format_hybrid_attr *pmu_attr = 6965 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr); 6966 int cpu = hybrid_find_supported_cpu(pmu); 6967 6968 return (cpu >= 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode : 0; 6969} 6970 6971static umode_t hybrid_td_is_visible(struct kobject *kobj, 6972 struct attribute *attr, int i) 6973{ 6974 struct device *dev = kobj_to_dev(kobj); 6975 struct x86_hybrid_pmu *pmu = 6976 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 6977 6978 if (!is_attr_for_this_pmu(kobj, attr)) 6979 return 0; 6980 6981 6982 /* Only the big core supports perf metrics */ 6983 if (pmu->pmu_type == hybrid_big) 6984 return pmu->intel_cap.perf_metrics ? attr->mode : 0; 6985 6986 return attr->mode; 6987} 6988 6989static struct attribute_group hybrid_group_events_td = { 6990 .name = "events", 6991 .is_visible = hybrid_td_is_visible, 6992}; 6993 6994static struct attribute_group hybrid_group_events_mem = { 6995 .name = "events", 6996 .is_visible = hybrid_events_is_visible, 6997}; 6998 6999static struct attribute_group hybrid_group_events_tsx = { 7000 .name = "events", 7001 .is_visible = hybrid_tsx_is_visible, 7002}; 7003 7004static struct attribute_group hybrid_group_format_extra = { 7005 .name = "format", 7006 .is_visible = hybrid_format_is_visible, 7007}; 7008 7009static ssize_t intel_hybrid_get_attr_cpus(struct device *dev, 7010 struct device_attribute *attr, 7011 char *buf) 7012{ 7013 struct x86_hybrid_pmu *pmu = 7014 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); 7015 7016 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus); 7017} 7018 7019static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL); 7020static struct attribute *intel_hybrid_cpus_attrs[] = { 7021 &dev_attr_cpus.attr, 7022 NULL, 7023}; 7024 7025static struct attribute_group hybrid_group_cpus = { 7026 .attrs = intel_hybrid_cpus_attrs, 7027}; 7028 7029static const struct attribute_group *hybrid_attr_update[] = { 7030 &hybrid_group_events_td, 7031 &hybrid_group_events_mem, 7032 &hybrid_group_events_tsx, 7033 &group_caps_gen, 7034 &group_caps_lbr, 7035 &hybrid_group_format_extra, 7036 &group_format_evtsel_ext, 7037 &group_format_acr, 7038 &group_default, 7039 &hybrid_group_cpus, 7040 NULL, 7041}; 7042 7043static struct attribute *empty_attrs; 7044 7045static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints, 7046 u64 cntr_mask, 7047 u64 fixed_cntr_mask, 7048 u64 intel_ctrl) 7049{ 7050 struct event_constraint *c; 7051 7052 if (!event_constraints) 7053 return; 7054 7055 /* 7056 * event on fixed counter2 (REF_CYCLES) only works on this 7057 * counter, so do not extend mask to generic counters 7058 */ 7059 for_each_event_constraint(c, event_constraints) { 7060 /* 7061 * Don't extend the topdown slots and metrics 7062 * events to the generic counters. 7063 */ 7064 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) { 7065 /* 7066 * Disable topdown slots and metrics events, 7067 * if slots event is not in CPUID. 7068 */ 7069 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl)) 7070 c->idxmsk64 = 0; 7071 c->weight = hweight64(c->idxmsk64); 7072 continue; 7073 } 7074 7075 if (c->cmask == FIXED_EVENT_FLAGS) { 7076 /* Disabled fixed counters which are not in CPUID */ 7077 c->idxmsk64 &= intel_ctrl; 7078 7079 /* 7080 * Don't extend the pseudo-encoding to the 7081 * generic counters 7082 */ 7083 if (!use_fixed_pseudo_encoding(c->code)) 7084 c->idxmsk64 |= cntr_mask; 7085 } 7086 c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED); 7087 c->weight = hweight64(c->idxmsk64); 7088 } 7089} 7090 7091static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs) 7092{ 7093 struct extra_reg *er; 7094 7095 /* 7096 * Access extra MSR may cause #GP under certain circumstances. 7097 * E.g. KVM doesn't support offcore event 7098 * Check all extra_regs here. 7099 */ 7100 if (!extra_regs) 7101 return; 7102 7103 for (er = extra_regs; er->msr; er++) { 7104 er->extra_msr_access = check_msr(er->msr, 0x11UL); 7105 /* Disable LBR select mapping */ 7106 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) 7107 x86_pmu.lbr_sel_map = NULL; 7108 } 7109} 7110 7111static inline int intel_pmu_v6_addr_offset(int index, bool eventsel) 7112{ 7113 return MSR_IA32_PMC_V6_STEP * index; 7114} 7115 7116static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = { 7117 { hybrid_small, "cpu_atom" }, 7118 { hybrid_big, "cpu_core" }, 7119 { hybrid_tiny, "cpu_lowpower" }, 7120}; 7121 7122static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus) 7123{ 7124 unsigned long pmus_mask = pmus; 7125 struct x86_hybrid_pmu *pmu; 7126 int idx = 0, bit; 7127 7128 x86_pmu.num_hybrid_pmus = hweight_long(pmus_mask); 7129 x86_pmu.hybrid_pmu = kcalloc(x86_pmu.num_hybrid_pmus, 7130 sizeof(struct x86_hybrid_pmu), 7131 GFP_KERNEL); 7132 if (!x86_pmu.hybrid_pmu) 7133 return -ENOMEM; 7134 7135 static_branch_enable(&perf_is_hybrid); 7136 x86_pmu.filter = intel_pmu_filter; 7137 7138 for_each_set_bit(bit, &pmus_mask, ARRAY_SIZE(intel_hybrid_pmu_type_map)) { 7139 pmu = &x86_pmu.hybrid_pmu[idx++]; 7140 pmu->pmu_type = intel_hybrid_pmu_type_map[bit].id; 7141 pmu->name = intel_hybrid_pmu_type_map[bit].name; 7142 7143 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 7144 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 7145 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 7146 pmu->config_mask = X86_RAW_EVENT_MASK; 7147 pmu->unconstrained = (struct event_constraint) 7148 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 7149 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 7150 7151 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; 7152 if (pmu->pmu_type & hybrid_small_tiny) { 7153 pmu->intel_cap.perf_metrics = 0; 7154 pmu->mid_ack = true; 7155 } else if (pmu->pmu_type & hybrid_big) { 7156 pmu->intel_cap.perf_metrics = 1; 7157 pmu->late_ack = true; 7158 } 7159 } 7160 7161 return 0; 7162} 7163 7164static __always_inline void intel_pmu_ref_cycles_ext(void) 7165{ 7166 if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED))) 7167 intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c; 7168} 7169 7170static __always_inline void intel_pmu_init_glc(struct pmu *pmu) 7171{ 7172 x86_pmu.late_ack = true; 7173 x86_pmu.limit_period = glc_limit_period; 7174 x86_pmu.pebs_aliases = NULL; 7175 x86_pmu.pebs_prec_dist = true; 7176 x86_pmu.pebs_block = true; 7177 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7178 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7179 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 7180 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 7181 x86_pmu.lbr_pt_coexist = true; 7182 x86_pmu.num_topdown_events = 8; 7183 static_call_update(intel_pmu_update_topdown_event, 7184 &icl_update_topdown_event); 7185 static_call_update(intel_pmu_set_topdown_event_period, 7186 &icl_set_topdown_event_period); 7187 7188 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7189 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7190 hybrid(pmu, event_constraints) = intel_glc_event_constraints; 7191 hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints; 7192 7193 intel_pmu_ref_cycles_ext(); 7194} 7195 7196static __always_inline void intel_pmu_init_grt(struct pmu *pmu) 7197{ 7198 x86_pmu.mid_ack = true; 7199 x86_pmu.limit_period = glc_limit_period; 7200 x86_pmu.pebs_aliases = NULL; 7201 x86_pmu.pebs_prec_dist = true; 7202 x86_pmu.pebs_block = true; 7203 x86_pmu.lbr_pt_coexist = true; 7204 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7205 x86_pmu.flags |= PMU_FL_INSTR_LATENCY; 7206 7207 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7208 memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7209 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 7210 hybrid(pmu, event_constraints) = intel_grt_event_constraints; 7211 hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints; 7212 hybrid(pmu, extra_regs) = intel_grt_extra_regs; 7213 7214 intel_pmu_ref_cycles_ext(); 7215} 7216 7217static __always_inline void intel_pmu_init_lnc(struct pmu *pmu) 7218{ 7219 intel_pmu_init_glc(pmu); 7220 hybrid(pmu, event_constraints) = intel_lnc_event_constraints; 7221 hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints; 7222 hybrid(pmu, extra_regs) = intel_lnc_extra_regs; 7223} 7224 7225static __always_inline void intel_pmu_init_skt(struct pmu *pmu) 7226{ 7227 intel_pmu_init_grt(pmu); 7228 hybrid(pmu, event_constraints) = intel_skt_event_constraints; 7229 hybrid(pmu, extra_regs) = intel_cmt_extra_regs; 7230 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr); 7231} 7232 7233__init int intel_pmu_init(void) 7234{ 7235 struct attribute **extra_skl_attr = &empty_attrs; 7236 struct attribute **extra_attr = &empty_attrs; 7237 struct attribute **td_attr = &empty_attrs; 7238 struct attribute **mem_attr = &empty_attrs; 7239 struct attribute **tsx_attr = &empty_attrs; 7240 union cpuid10_edx edx; 7241 union cpuid10_eax eax; 7242 union cpuid10_ebx ebx; 7243 unsigned int fixed_mask; 7244 bool pmem = false; 7245 int version, i; 7246 char *name; 7247 struct x86_hybrid_pmu *pmu; 7248 7249 /* Architectural Perfmon was introduced starting with Core "Yonah" */ 7250 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { 7251 switch (boot_cpu_data.x86) { 7252 case 6: 7253 if (boot_cpu_data.x86_vfm < INTEL_CORE_YONAH) 7254 return p6_pmu_init(); 7255 break; 7256 case 11: 7257 return knc_pmu_init(); 7258 case 15: 7259 return p4_pmu_init(); 7260 } 7261 7262 pr_cont("unsupported CPU family %d model %d ", 7263 boot_cpu_data.x86, boot_cpu_data.x86_model); 7264 return -ENODEV; 7265 } 7266 7267 /* 7268 * Check whether the Architectural PerfMon supports 7269 * Branch Misses Retired hw_event or not. 7270 */ 7271 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); 7272 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) 7273 return -ENODEV; 7274 7275 version = eax.split.version_id; 7276 if (version < 2) 7277 x86_pmu = core_pmu; 7278 else 7279 x86_pmu = intel_pmu; 7280 7281 x86_pmu.version = version; 7282 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0); 7283 x86_pmu.cntval_bits = eax.split.bit_width; 7284 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; 7285 7286 x86_pmu.events_maskl = ebx.full; 7287 x86_pmu.events_mask_len = eax.split.mask_length; 7288 7289 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64); 7290 x86_pmu.pebs_capable = PEBS_COUNTER_MASK; 7291 x86_pmu.config_mask = X86_RAW_EVENT_MASK; 7292 7293 /* 7294 * Quirk: v2 perfmon does not report fixed-purpose events, so 7295 * assume at least 3 events, when not running in a hypervisor: 7296 */ 7297 if (version > 1 && version < 5) { 7298 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); 7299 7300 x86_pmu.fixed_cntr_mask64 = 7301 GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0); 7302 } else if (version >= 5) 7303 x86_pmu.fixed_cntr_mask64 = fixed_mask; 7304 7305 if (boot_cpu_has(X86_FEATURE_PDCM)) { 7306 u64 capabilities; 7307 7308 rdmsrq(MSR_IA32_PERF_CAPABILITIES, capabilities); 7309 x86_pmu.intel_cap.capabilities = capabilities; 7310 } 7311 7312 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) { 7313 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32; 7314 x86_pmu.lbr_read = intel_pmu_lbr_read_32; 7315 } 7316 7317 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) 7318 intel_pmu_arch_lbr_init(); 7319 7320 intel_pebs_init(); 7321 7322 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ 7323 7324 if (version >= 5) { 7325 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated; 7326 if (x86_pmu.intel_cap.anythread_deprecated) 7327 pr_cont(" AnyThread deprecated, "); 7328 } 7329 7330 /* 7331 * Many features on and after V6 require dynamic constraint, 7332 * e.g., Arch PEBS, ACR. 7333 */ 7334 if (version >= 6) { 7335 x86_pmu.flags |= PMU_FL_DYN_CONSTRAINT; 7336 x86_pmu.late_setup = intel_pmu_late_setup; 7337 } 7338 7339 /* 7340 * Install the hw-cache-events table: 7341 */ 7342 switch (boot_cpu_data.x86_vfm) { 7343 case INTEL_CORE_YONAH: 7344 pr_cont("Core events, "); 7345 name = "core"; 7346 break; 7347 7348 case INTEL_CORE2_MEROM: 7349 x86_add_quirk(intel_clovertown_quirk); 7350 fallthrough; 7351 7352 case INTEL_CORE2_MEROM_L: 7353 case INTEL_CORE2_PENRYN: 7354 case INTEL_CORE2_DUNNINGTON: 7355 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, 7356 sizeof(hw_cache_event_ids)); 7357 7358 intel_pmu_lbr_init_core(); 7359 7360 x86_pmu.event_constraints = intel_core2_event_constraints; 7361 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; 7362 pr_cont("Core2 events, "); 7363 name = "core2"; 7364 break; 7365 7366 case INTEL_NEHALEM: 7367 case INTEL_NEHALEM_EP: 7368 case INTEL_NEHALEM_EX: 7369 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, 7370 sizeof(hw_cache_event_ids)); 7371 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 7372 sizeof(hw_cache_extra_regs)); 7373 7374 intel_pmu_lbr_init_nhm(); 7375 7376 x86_pmu.event_constraints = intel_nehalem_event_constraints; 7377 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; 7378 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 7379 x86_pmu.extra_regs = intel_nehalem_extra_regs; 7380 x86_pmu.limit_period = nhm_limit_period; 7381 7382 mem_attr = nhm_mem_events_attrs; 7383 7384 /* UOPS_ISSUED.STALLED_CYCLES */ 7385 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 7386 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 7387 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 7388 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 7389 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 7390 7391 intel_pmu_pebs_data_source_nhm(); 7392 x86_add_quirk(intel_nehalem_quirk); 7393 x86_pmu.pebs_no_tlb = 1; 7394 extra_attr = nhm_format_attr; 7395 7396 pr_cont("Nehalem events, "); 7397 name = "nehalem"; 7398 break; 7399 7400 case INTEL_ATOM_BONNELL: 7401 case INTEL_ATOM_BONNELL_MID: 7402 case INTEL_ATOM_SALTWELL: 7403 case INTEL_ATOM_SALTWELL_MID: 7404 case INTEL_ATOM_SALTWELL_TABLET: 7405 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, 7406 sizeof(hw_cache_event_ids)); 7407 7408 intel_pmu_lbr_init_atom(); 7409 7410 x86_pmu.event_constraints = intel_gen_event_constraints; 7411 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; 7412 x86_pmu.pebs_aliases = intel_pebs_aliases_core2; 7413 pr_cont("Atom events, "); 7414 name = "bonnell"; 7415 break; 7416 7417 case INTEL_ATOM_SILVERMONT: 7418 case INTEL_ATOM_SILVERMONT_D: 7419 case INTEL_ATOM_SILVERMONT_MID: 7420 case INTEL_ATOM_AIRMONT: 7421 case INTEL_ATOM_AIRMONT_NP: 7422 case INTEL_ATOM_SILVERMONT_MID2: 7423 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids, 7424 sizeof(hw_cache_event_ids)); 7425 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, 7426 sizeof(hw_cache_extra_regs)); 7427 7428 intel_pmu_lbr_init_slm(); 7429 7430 x86_pmu.event_constraints = intel_slm_event_constraints; 7431 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 7432 x86_pmu.extra_regs = intel_slm_extra_regs; 7433 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7434 td_attr = slm_events_attrs; 7435 extra_attr = slm_format_attr; 7436 pr_cont("Silvermont events, "); 7437 name = "silvermont"; 7438 break; 7439 7440 case INTEL_ATOM_GOLDMONT: 7441 case INTEL_ATOM_GOLDMONT_D: 7442 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids, 7443 sizeof(hw_cache_event_ids)); 7444 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs, 7445 sizeof(hw_cache_extra_regs)); 7446 7447 intel_pmu_lbr_init_skl(); 7448 7449 x86_pmu.event_constraints = intel_slm_event_constraints; 7450 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints; 7451 x86_pmu.extra_regs = intel_glm_extra_regs; 7452 /* 7453 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 7454 * for precise cycles. 7455 * :pp is identical to :ppp 7456 */ 7457 x86_pmu.pebs_aliases = NULL; 7458 x86_pmu.pebs_prec_dist = true; 7459 x86_pmu.lbr_pt_coexist = true; 7460 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7461 td_attr = glm_events_attrs; 7462 extra_attr = slm_format_attr; 7463 pr_cont("Goldmont events, "); 7464 name = "goldmont"; 7465 break; 7466 7467 case INTEL_ATOM_GOLDMONT_PLUS: 7468 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 7469 sizeof(hw_cache_event_ids)); 7470 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 7471 sizeof(hw_cache_extra_regs)); 7472 7473 intel_pmu_lbr_init_skl(); 7474 7475 x86_pmu.event_constraints = intel_slm_event_constraints; 7476 x86_pmu.extra_regs = intel_glm_extra_regs; 7477 /* 7478 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 7479 * for precise cycles. 7480 */ 7481 x86_pmu.pebs_aliases = NULL; 7482 x86_pmu.pebs_prec_dist = true; 7483 x86_pmu.lbr_pt_coexist = true; 7484 x86_pmu.pebs_capable = ~0ULL; 7485 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7486 x86_pmu.flags |= PMU_FL_PEBS_ALL; 7487 x86_pmu.get_event_constraints = glp_get_event_constraints; 7488 td_attr = glm_events_attrs; 7489 /* Goldmont Plus has 4-wide pipeline */ 7490 event_attr_td_total_slots_scale_glm.event_str = "4"; 7491 extra_attr = slm_format_attr; 7492 pr_cont("Goldmont plus events, "); 7493 name = "goldmont_plus"; 7494 break; 7495 7496 case INTEL_ATOM_TREMONT_D: 7497 case INTEL_ATOM_TREMONT: 7498 case INTEL_ATOM_TREMONT_L: 7499 x86_pmu.late_ack = true; 7500 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 7501 sizeof(hw_cache_event_ids)); 7502 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, 7503 sizeof(hw_cache_extra_regs)); 7504 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 7505 7506 intel_pmu_lbr_init_skl(); 7507 7508 x86_pmu.event_constraints = intel_slm_event_constraints; 7509 x86_pmu.extra_regs = intel_tnt_extra_regs; 7510 /* 7511 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 7512 * for precise cycles. 7513 */ 7514 x86_pmu.pebs_aliases = NULL; 7515 x86_pmu.pebs_prec_dist = true; 7516 x86_pmu.lbr_pt_coexist = true; 7517 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7518 x86_pmu.get_event_constraints = tnt_get_event_constraints; 7519 td_attr = tnt_events_attrs; 7520 extra_attr = slm_format_attr; 7521 pr_cont("Tremont events, "); 7522 name = "Tremont"; 7523 break; 7524 7525 case INTEL_ATOM_GRACEMONT: 7526 intel_pmu_init_grt(NULL); 7527 intel_pmu_pebs_data_source_grt(); 7528 x86_pmu.pebs_latency_data = grt_latency_data; 7529 x86_pmu.get_event_constraints = tnt_get_event_constraints; 7530 td_attr = tnt_events_attrs; 7531 mem_attr = grt_mem_attrs; 7532 extra_attr = nhm_format_attr; 7533 pr_cont("Gracemont events, "); 7534 name = "gracemont"; 7535 break; 7536 7537 case INTEL_ATOM_CRESTMONT: 7538 case INTEL_ATOM_CRESTMONT_X: 7539 intel_pmu_init_grt(NULL); 7540 x86_pmu.extra_regs = intel_cmt_extra_regs; 7541 intel_pmu_pebs_data_source_cmt(); 7542 x86_pmu.pebs_latency_data = cmt_latency_data; 7543 x86_pmu.get_event_constraints = cmt_get_event_constraints; 7544 td_attr = cmt_events_attrs; 7545 mem_attr = grt_mem_attrs; 7546 extra_attr = cmt_format_attr; 7547 pr_cont("Crestmont events, "); 7548 name = "crestmont"; 7549 break; 7550 7551 case INTEL_ATOM_DARKMONT_X: 7552 intel_pmu_init_skt(NULL); 7553 intel_pmu_pebs_data_source_cmt(); 7554 x86_pmu.pebs_latency_data = cmt_latency_data; 7555 x86_pmu.get_event_constraints = cmt_get_event_constraints; 7556 td_attr = skt_events_attrs; 7557 mem_attr = grt_mem_attrs; 7558 extra_attr = cmt_format_attr; 7559 pr_cont("Darkmont events, "); 7560 name = "darkmont"; 7561 break; 7562 7563 case INTEL_WESTMERE: 7564 case INTEL_WESTMERE_EP: 7565 case INTEL_WESTMERE_EX: 7566 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, 7567 sizeof(hw_cache_event_ids)); 7568 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, 7569 sizeof(hw_cache_extra_regs)); 7570 7571 intel_pmu_lbr_init_nhm(); 7572 7573 x86_pmu.event_constraints = intel_westmere_event_constraints; 7574 x86_pmu.enable_all = intel_pmu_nhm_enable_all; 7575 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; 7576 x86_pmu.extra_regs = intel_westmere_extra_regs; 7577 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7578 7579 mem_attr = nhm_mem_events_attrs; 7580 7581 /* UOPS_ISSUED.STALLED_CYCLES */ 7582 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 7583 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 7584 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ 7585 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 7586 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); 7587 7588 intel_pmu_pebs_data_source_nhm(); 7589 extra_attr = nhm_format_attr; 7590 pr_cont("Westmere events, "); 7591 name = "westmere"; 7592 break; 7593 7594 case INTEL_SANDYBRIDGE: 7595 case INTEL_SANDYBRIDGE_X: 7596 x86_add_quirk(intel_sandybridge_quirk); 7597 x86_add_quirk(intel_ht_bug); 7598 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 7599 sizeof(hw_cache_event_ids)); 7600 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 7601 sizeof(hw_cache_extra_regs)); 7602 7603 intel_pmu_lbr_init_snb(); 7604 7605 x86_pmu.event_constraints = intel_snb_event_constraints; 7606 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; 7607 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; 7608 if (boot_cpu_data.x86_vfm == INTEL_SANDYBRIDGE_X) 7609 x86_pmu.extra_regs = intel_snbep_extra_regs; 7610 else 7611 x86_pmu.extra_regs = intel_snb_extra_regs; 7612 7613 7614 /* all extra regs are per-cpu when HT is on */ 7615 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7616 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7617 7618 td_attr = snb_events_attrs; 7619 mem_attr = snb_mem_events_attrs; 7620 7621 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 7622 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 7623 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 7624 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ 7625 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 7626 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); 7627 7628 extra_attr = nhm_format_attr; 7629 7630 pr_cont("SandyBridge events, "); 7631 name = "sandybridge"; 7632 break; 7633 7634 case INTEL_IVYBRIDGE: 7635 case INTEL_IVYBRIDGE_X: 7636 x86_add_quirk(intel_ht_bug); 7637 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, 7638 sizeof(hw_cache_event_ids)); 7639 /* dTLB-load-misses on IVB is different than SNB */ 7640 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */ 7641 7642 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, 7643 sizeof(hw_cache_extra_regs)); 7644 7645 intel_pmu_lbr_init_snb(); 7646 7647 x86_pmu.event_constraints = intel_ivb_event_constraints; 7648 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; 7649 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 7650 x86_pmu.pebs_prec_dist = true; 7651 if (boot_cpu_data.x86_vfm == INTEL_IVYBRIDGE_X) 7652 x86_pmu.extra_regs = intel_snbep_extra_regs; 7653 else 7654 x86_pmu.extra_regs = intel_snb_extra_regs; 7655 /* all extra regs are per-cpu when HT is on */ 7656 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7657 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7658 7659 td_attr = snb_events_attrs; 7660 mem_attr = snb_mem_events_attrs; 7661 7662 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ 7663 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 7664 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); 7665 7666 extra_attr = nhm_format_attr; 7667 7668 pr_cont("IvyBridge events, "); 7669 name = "ivybridge"; 7670 break; 7671 7672 7673 case INTEL_HASWELL: 7674 case INTEL_HASWELL_X: 7675 case INTEL_HASWELL_L: 7676 case INTEL_HASWELL_G: 7677 x86_add_quirk(intel_ht_bug); 7678 x86_add_quirk(intel_pebs_isolation_quirk); 7679 x86_pmu.late_ack = true; 7680 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7681 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7682 7683 intel_pmu_lbr_init_hsw(); 7684 7685 x86_pmu.event_constraints = intel_hsw_event_constraints; 7686 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; 7687 x86_pmu.extra_regs = intel_snbep_extra_regs; 7688 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 7689 x86_pmu.pebs_prec_dist = true; 7690 /* all extra regs are per-cpu when HT is on */ 7691 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7692 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7693 7694 x86_pmu.hw_config = hsw_hw_config; 7695 x86_pmu.get_event_constraints = hsw_get_event_constraints; 7696 x86_pmu.limit_period = hsw_limit_period; 7697 x86_pmu.lbr_double_abort = true; 7698 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7699 hsw_format_attr : nhm_format_attr; 7700 td_attr = hsw_events_attrs; 7701 mem_attr = hsw_mem_events_attrs; 7702 tsx_attr = hsw_tsx_events_attrs; 7703 pr_cont("Haswell events, "); 7704 name = "haswell"; 7705 break; 7706 7707 case INTEL_BROADWELL: 7708 case INTEL_BROADWELL_D: 7709 case INTEL_BROADWELL_G: 7710 case INTEL_BROADWELL_X: 7711 x86_add_quirk(intel_pebs_isolation_quirk); 7712 x86_pmu.late_ack = true; 7713 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7714 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7715 7716 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */ 7717 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | 7718 BDW_L3_MISS|HSW_SNOOP_DRAM; 7719 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| 7720 HSW_SNOOP_DRAM; 7721 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| 7722 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 7723 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| 7724 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; 7725 7726 intel_pmu_lbr_init_hsw(); 7727 7728 x86_pmu.event_constraints = intel_bdw_event_constraints; 7729 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints; 7730 x86_pmu.extra_regs = intel_snbep_extra_regs; 7731 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb; 7732 x86_pmu.pebs_prec_dist = true; 7733 /* all extra regs are per-cpu when HT is on */ 7734 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7735 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7736 7737 x86_pmu.hw_config = hsw_hw_config; 7738 x86_pmu.get_event_constraints = hsw_get_event_constraints; 7739 x86_pmu.limit_period = bdw_limit_period; 7740 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7741 hsw_format_attr : nhm_format_attr; 7742 td_attr = hsw_events_attrs; 7743 mem_attr = hsw_mem_events_attrs; 7744 tsx_attr = hsw_tsx_events_attrs; 7745 pr_cont("Broadwell events, "); 7746 name = "broadwell"; 7747 break; 7748 7749 case INTEL_XEON_PHI_KNL: 7750 case INTEL_XEON_PHI_KNM: 7751 memcpy(hw_cache_event_ids, 7752 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7753 memcpy(hw_cache_extra_regs, 7754 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7755 intel_pmu_lbr_init_knl(); 7756 7757 x86_pmu.event_constraints = intel_slm_event_constraints; 7758 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; 7759 x86_pmu.extra_regs = intel_knl_extra_regs; 7760 7761 /* all extra regs are per-cpu when HT is on */ 7762 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7763 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7764 extra_attr = slm_format_attr; 7765 pr_cont("Knights Landing/Mill events, "); 7766 name = "knights-landing"; 7767 break; 7768 7769 case INTEL_SKYLAKE_X: 7770 pmem = true; 7771 fallthrough; 7772 case INTEL_SKYLAKE_L: 7773 case INTEL_SKYLAKE: 7774 case INTEL_KABYLAKE_L: 7775 case INTEL_KABYLAKE: 7776 case INTEL_COMETLAKE_L: 7777 case INTEL_COMETLAKE: 7778 x86_add_quirk(intel_pebs_isolation_quirk); 7779 x86_pmu.late_ack = true; 7780 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7781 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7782 intel_pmu_lbr_init_skl(); 7783 7784 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */ 7785 event_attr_td_recovery_bubbles.event_str_noht = 7786 "event=0xd,umask=0x1,cmask=1"; 7787 event_attr_td_recovery_bubbles.event_str_ht = 7788 "event=0xd,umask=0x1,cmask=1,any=1"; 7789 7790 x86_pmu.event_constraints = intel_skl_event_constraints; 7791 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints; 7792 x86_pmu.extra_regs = intel_skl_extra_regs; 7793 x86_pmu.pebs_aliases = intel_pebs_aliases_skl; 7794 x86_pmu.pebs_prec_dist = true; 7795 /* all extra regs are per-cpu when HT is on */ 7796 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7797 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7798 7799 x86_pmu.hw_config = hsw_hw_config; 7800 x86_pmu.get_event_constraints = hsw_get_event_constraints; 7801 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7802 hsw_format_attr : nhm_format_attr; 7803 extra_skl_attr = skl_format_attr; 7804 td_attr = hsw_events_attrs; 7805 mem_attr = hsw_mem_events_attrs; 7806 tsx_attr = hsw_tsx_events_attrs; 7807 intel_pmu_pebs_data_source_skl(pmem); 7808 7809 /* 7810 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default. 7811 * TSX force abort hooks are not required on these systems. Only deploy 7812 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT. 7813 */ 7814 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) && 7815 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) { 7816 x86_pmu.flags |= PMU_FL_TFA; 7817 x86_pmu.get_event_constraints = tfa_get_event_constraints; 7818 x86_pmu.enable_all = intel_tfa_pmu_enable_all; 7819 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling; 7820 } 7821 7822 pr_cont("Skylake events, "); 7823 name = "skylake"; 7824 break; 7825 7826 case INTEL_ICELAKE_X: 7827 case INTEL_ICELAKE_D: 7828 x86_pmu.pebs_ept = 1; 7829 pmem = true; 7830 fallthrough; 7831 case INTEL_ICELAKE_L: 7832 case INTEL_ICELAKE: 7833 case INTEL_TIGERLAKE_L: 7834 case INTEL_TIGERLAKE: 7835 case INTEL_ROCKETLAKE: 7836 x86_pmu.late_ack = true; 7837 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 7838 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 7839 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; 7840 intel_pmu_lbr_init_skl(); 7841 7842 x86_pmu.event_constraints = intel_icl_event_constraints; 7843 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints; 7844 x86_pmu.extra_regs = intel_icl_extra_regs; 7845 x86_pmu.pebs_aliases = NULL; 7846 x86_pmu.pebs_prec_dist = true; 7847 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 7848 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; 7849 7850 x86_pmu.hw_config = hsw_hw_config; 7851 x86_pmu.get_event_constraints = icl_get_event_constraints; 7852 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7853 hsw_format_attr : nhm_format_attr; 7854 extra_skl_attr = skl_format_attr; 7855 mem_attr = icl_events_attrs; 7856 td_attr = icl_td_events_attrs; 7857 tsx_attr = icl_tsx_events_attrs; 7858 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); 7859 x86_pmu.lbr_pt_coexist = true; 7860 intel_pmu_pebs_data_source_skl(pmem); 7861 x86_pmu.num_topdown_events = 4; 7862 static_call_update(intel_pmu_update_topdown_event, 7863 &icl_update_topdown_event); 7864 static_call_update(intel_pmu_set_topdown_event_period, 7865 &icl_set_topdown_event_period); 7866 pr_cont("Icelake events, "); 7867 name = "icelake"; 7868 break; 7869 7870 case INTEL_SAPPHIRERAPIDS_X: 7871 case INTEL_EMERALDRAPIDS_X: 7872 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 7873 x86_pmu.extra_regs = intel_glc_extra_regs; 7874 pr_cont("Sapphire Rapids events, "); 7875 name = "sapphire_rapids"; 7876 goto glc_common; 7877 7878 case INTEL_GRANITERAPIDS_X: 7879 case INTEL_GRANITERAPIDS_D: 7880 x86_pmu.extra_regs = intel_rwc_extra_regs; 7881 pr_cont("Granite Rapids events, "); 7882 name = "granite_rapids"; 7883 7884 glc_common: 7885 intel_pmu_init_glc(NULL); 7886 x86_pmu.pebs_ept = 1; 7887 x86_pmu.hw_config = hsw_hw_config; 7888 x86_pmu.get_event_constraints = glc_get_event_constraints; 7889 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7890 hsw_format_attr : nhm_format_attr; 7891 extra_skl_attr = skl_format_attr; 7892 mem_attr = glc_events_attrs; 7893 td_attr = glc_td_events_attrs; 7894 tsx_attr = glc_tsx_events_attrs; 7895 intel_pmu_pebs_data_source_skl(true); 7896 break; 7897 7898 case INTEL_ALDERLAKE: 7899 case INTEL_ALDERLAKE_L: 7900 case INTEL_RAPTORLAKE: 7901 case INTEL_RAPTORLAKE_P: 7902 case INTEL_RAPTORLAKE_S: 7903 /* 7904 * Alder Lake has 2 types of CPU, core and atom. 7905 * 7906 * Initialize the common PerfMon capabilities here. 7907 */ 7908 intel_pmu_init_hybrid(hybrid_big_small); 7909 7910 x86_pmu.pebs_latency_data = grt_latency_data; 7911 x86_pmu.get_event_constraints = adl_get_event_constraints; 7912 x86_pmu.hw_config = adl_hw_config; 7913 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type; 7914 7915 td_attr = adl_hybrid_events_attrs; 7916 mem_attr = adl_hybrid_mem_attrs; 7917 tsx_attr = adl_hybrid_tsx_attrs; 7918 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7919 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr; 7920 7921 /* Initialize big core specific PerfMon capabilities.*/ 7922 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7923 intel_pmu_init_glc(&pmu->pmu); 7924 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 7925 pmu->cntr_mask64 <<= 2; 7926 pmu->cntr_mask64 |= 0x3; 7927 pmu->fixed_cntr_mask64 <<= 1; 7928 pmu->fixed_cntr_mask64 |= 0x1; 7929 } else { 7930 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 7931 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 7932 } 7933 7934 /* 7935 * Quirk: For some Alder Lake machine, when all E-cores are disabled in 7936 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However, 7937 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will 7938 * mistakenly add extra counters for P-cores. Correct the number of 7939 * counters here. 7940 */ 7941 if ((x86_pmu_num_counters(&pmu->pmu) > 8) || (x86_pmu_num_counters_fixed(&pmu->pmu) > 4)) { 7942 pmu->cntr_mask64 = x86_pmu.cntr_mask64; 7943 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64; 7944 } 7945 7946 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); 7947 pmu->unconstrained = (struct event_constraint) 7948 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, 7949 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 7950 7951 pmu->extra_regs = intel_glc_extra_regs; 7952 7953 /* Initialize Atom core specific PerfMon capabilities.*/ 7954 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7955 intel_pmu_init_grt(&pmu->pmu); 7956 7957 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; 7958 intel_pmu_pebs_data_source_adl(); 7959 pr_cont("Alderlake Hybrid events, "); 7960 name = "alderlake_hybrid"; 7961 break; 7962 7963 case INTEL_METEORLAKE: 7964 case INTEL_METEORLAKE_L: 7965 case INTEL_ARROWLAKE_U: 7966 intel_pmu_init_hybrid(hybrid_big_small); 7967 7968 x86_pmu.pebs_latency_data = cmt_latency_data; 7969 x86_pmu.get_event_constraints = mtl_get_event_constraints; 7970 x86_pmu.hw_config = adl_hw_config; 7971 7972 td_attr = adl_hybrid_events_attrs; 7973 mem_attr = mtl_hybrid_mem_attrs; 7974 tsx_attr = adl_hybrid_tsx_attrs; 7975 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 7976 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 7977 7978 /* Initialize big core specific PerfMon capabilities.*/ 7979 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 7980 intel_pmu_init_glc(&pmu->pmu); 7981 pmu->extra_regs = intel_rwc_extra_regs; 7982 7983 /* Initialize Atom core specific PerfMon capabilities.*/ 7984 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 7985 intel_pmu_init_grt(&pmu->pmu); 7986 pmu->extra_regs = intel_cmt_extra_regs; 7987 7988 intel_pmu_pebs_data_source_mtl(); 7989 pr_cont("Meteorlake Hybrid events, "); 7990 name = "meteorlake_hybrid"; 7991 break; 7992 7993 case INTEL_PANTHERLAKE_L: 7994 case INTEL_WILDCATLAKE_L: 7995 pr_cont("Pantherlake Hybrid events, "); 7996 name = "pantherlake_hybrid"; 7997 goto lnl_common; 7998 7999 case INTEL_LUNARLAKE_M: 8000 case INTEL_ARROWLAKE: 8001 pr_cont("Lunarlake Hybrid events, "); 8002 name = "lunarlake_hybrid"; 8003 8004 lnl_common: 8005 intel_pmu_init_hybrid(hybrid_big_small); 8006 8007 x86_pmu.pebs_latency_data = lnl_latency_data; 8008 x86_pmu.get_event_constraints = mtl_get_event_constraints; 8009 x86_pmu.hw_config = adl_hw_config; 8010 8011 td_attr = lnl_hybrid_events_attrs; 8012 mem_attr = mtl_hybrid_mem_attrs; 8013 tsx_attr = adl_hybrid_tsx_attrs; 8014 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8015 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 8016 8017 /* Initialize big core specific PerfMon capabilities.*/ 8018 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 8019 intel_pmu_init_lnc(&pmu->pmu); 8020 8021 /* Initialize Atom core specific PerfMon capabilities.*/ 8022 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 8023 intel_pmu_init_skt(&pmu->pmu); 8024 8025 intel_pmu_pebs_data_source_lnl(); 8026 break; 8027 8028 case INTEL_ARROWLAKE_H: 8029 intel_pmu_init_hybrid(hybrid_big_small_tiny); 8030 8031 x86_pmu.pebs_latency_data = arl_h_latency_data; 8032 x86_pmu.get_event_constraints = arl_h_get_event_constraints; 8033 x86_pmu.hw_config = arl_h_hw_config; 8034 8035 td_attr = arl_h_hybrid_events_attrs; 8036 mem_attr = arl_h_hybrid_mem_attrs; 8037 tsx_attr = adl_hybrid_tsx_attrs; 8038 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ? 8039 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; 8040 8041 /* Initialize big core specific PerfMon capabilities. */ 8042 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; 8043 intel_pmu_init_lnc(&pmu->pmu); 8044 8045 /* Initialize Atom core specific PerfMon capabilities. */ 8046 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; 8047 intel_pmu_init_skt(&pmu->pmu); 8048 8049 /* Initialize Lower Power Atom specific PerfMon capabilities. */ 8050 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX]; 8051 intel_pmu_init_grt(&pmu->pmu); 8052 pmu->extra_regs = intel_cmt_extra_regs; 8053 8054 intel_pmu_pebs_data_source_arl_h(); 8055 pr_cont("ArrowLake-H Hybrid events, "); 8056 name = "arrowlake_h_hybrid"; 8057 break; 8058 8059 default: 8060 switch (x86_pmu.version) { 8061 case 1: 8062 x86_pmu.event_constraints = intel_v1_event_constraints; 8063 pr_cont("generic architected perfmon v1, "); 8064 name = "generic_arch_v1"; 8065 break; 8066 case 2: 8067 case 3: 8068 case 4: 8069 /* 8070 * default constraints for v2 and up 8071 */ 8072 x86_pmu.event_constraints = intel_gen_event_constraints; 8073 pr_cont("generic architected perfmon, "); 8074 name = "generic_arch_v2+"; 8075 break; 8076 default: 8077 /* 8078 * The default constraints for v5 and up can support up to 8079 * 16 fixed counters. For the fixed counters 4 and later, 8080 * the pseudo-encoding is applied. 8081 * The constraints may be cut according to the CPUID enumeration 8082 * by inserting the EVENT_CONSTRAINT_END. 8083 */ 8084 if (fls64(x86_pmu.fixed_cntr_mask64) > INTEL_PMC_MAX_FIXED) 8085 x86_pmu.fixed_cntr_mask64 &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0); 8086 intel_v5_gen_event_constraints[fls64(x86_pmu.fixed_cntr_mask64)].weight = -1; 8087 x86_pmu.event_constraints = intel_v5_gen_event_constraints; 8088 pr_cont("generic architected perfmon, "); 8089 name = "generic_arch_v5+"; 8090 break; 8091 } 8092 } 8093 8094 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name); 8095 8096 if (!is_hybrid()) { 8097 group_events_td.attrs = td_attr; 8098 group_events_mem.attrs = mem_attr; 8099 group_events_tsx.attrs = tsx_attr; 8100 group_format_extra.attrs = extra_attr; 8101 group_format_extra_skl.attrs = extra_skl_attr; 8102 8103 x86_pmu.attr_update = attr_update; 8104 } else { 8105 hybrid_group_events_td.attrs = td_attr; 8106 hybrid_group_events_mem.attrs = mem_attr; 8107 hybrid_group_events_tsx.attrs = tsx_attr; 8108 hybrid_group_format_extra.attrs = extra_attr; 8109 8110 x86_pmu.attr_update = hybrid_attr_update; 8111 } 8112 8113 /* 8114 * The archPerfmonExt (0x23) includes an enhanced enumeration of 8115 * PMU architectural features with a per-core view. For non-hybrid, 8116 * each core has the same PMU capabilities. It's good enough to 8117 * update the x86_pmu from the booting CPU. For hybrid, the x86_pmu 8118 * is used to keep the common capabilities. Still keep the values 8119 * from the leaf 0xa. The core specific update will be done later 8120 * when a new type is online. 8121 */ 8122 if (!is_hybrid() && boot_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) 8123 update_pmu_cap(NULL); 8124 8125 if (x86_pmu.arch_pebs) { 8126 static_call_update(intel_pmu_disable_event_ext, 8127 intel_pmu_disable_event_ext); 8128 static_call_update(intel_pmu_enable_event_ext, 8129 intel_pmu_enable_event_ext); 8130 pr_cont("Architectural PEBS, "); 8131 } 8132 8133 intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64, 8134 &x86_pmu.fixed_cntr_mask64, 8135 &x86_pmu.intel_ctrl); 8136 8137 /* AnyThread may be deprecated on arch perfmon v5 or later */ 8138 if (x86_pmu.intel_cap.anythread_deprecated) 8139 x86_pmu.format_attrs = intel_arch_formats_attr; 8140 8141 intel_pmu_check_event_constraints_all(NULL); 8142 8143 /* 8144 * Access LBR MSR may cause #GP under certain circumstances. 8145 * Check all LBR MSR here. 8146 * Disable LBR access if any LBR MSRs can not be accessed. 8147 */ 8148 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) 8149 x86_pmu.lbr_nr = 0; 8150 for (i = 0; i < x86_pmu.lbr_nr; i++) { 8151 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && 8152 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) 8153 x86_pmu.lbr_nr = 0; 8154 } 8155 8156 if (x86_pmu.lbr_nr) { 8157 intel_pmu_lbr_init(); 8158 8159 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); 8160 8161 /* only support branch_stack snapshot for perfmon >= v2 */ 8162 if (x86_pmu.disable_all == intel_pmu_disable_all) { 8163 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) { 8164 static_call_update(perf_snapshot_branch_stack, 8165 intel_pmu_snapshot_arch_branch_stack); 8166 } else { 8167 static_call_update(perf_snapshot_branch_stack, 8168 intel_pmu_snapshot_branch_stack); 8169 } 8170 } 8171 } 8172 8173 intel_pmu_check_extra_regs(x86_pmu.extra_regs); 8174 8175 /* Support full width counters using alternative MSR range */ 8176 if (x86_pmu.intel_cap.full_width_write) { 8177 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; 8178 x86_pmu.perfctr = MSR_IA32_PMC0; 8179 pr_cont("full-width counters, "); 8180 } 8181 8182 /* Support V6+ MSR Aliasing */ 8183 if (x86_pmu.version >= 6) { 8184 x86_pmu.perfctr = MSR_IA32_PMC_V6_GP0_CTR; 8185 x86_pmu.eventsel = MSR_IA32_PMC_V6_GP0_CFG_A; 8186 x86_pmu.fixedctr = MSR_IA32_PMC_V6_FX0_CTR; 8187 x86_pmu.addr_offset = intel_pmu_v6_addr_offset; 8188 } 8189 8190 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) 8191 x86_pmu.intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS; 8192 8193 if (x86_pmu.intel_cap.pebs_timing_info) 8194 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY; 8195 8196 intel_aux_output_init(); 8197 8198 return 0; 8199} 8200 8201/* 8202 * HT bug: phase 2 init 8203 * Called once we have valid topology information to check 8204 * whether or not HT is enabled 8205 * If HT is off, then we disable the workaround 8206 */ 8207static __init int fixup_ht_bug(void) 8208{ 8209 int c; 8210 /* 8211 * problem not present on this CPU model, nothing to do 8212 */ 8213 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) 8214 return 0; 8215 8216 if (topology_max_smt_threads() > 1) { 8217 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n"); 8218 return 0; 8219 } 8220 8221 cpus_read_lock(); 8222 8223 hardlockup_detector_perf_stop(); 8224 8225 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); 8226 8227 x86_pmu.start_scheduling = NULL; 8228 x86_pmu.commit_scheduling = NULL; 8229 x86_pmu.stop_scheduling = NULL; 8230 8231 hardlockup_detector_perf_restart(); 8232 8233 for_each_online_cpu(c) 8234 free_excl_cntrs(&per_cpu(cpu_hw_events, c)); 8235 8236 cpus_read_unlock(); 8237 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n"); 8238 return 0; 8239} 8240subsys_initcall(fixup_ht_bug)
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