cpucheck.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/* -*- linux-c -*- ------------------------------------------------------- *
  3 *
  4 *   Copyright (C) 1991, 1992 Linus Torvalds
  5 *   Copyright 2007 rPath, Inc. - All Rights Reserved
  6 *
  7 * ----------------------------------------------------------------------- */
  8
  9/*
 10 * Check for obligatory CPU features and abort if the features are not
 11 * present.  This code should be compilable as 16-, 32- or 64-bit
 12 * code, so be very careful with types and inline assembly.
 13 *
 14 * This code should not contain any messages; that requires an
 15 * additional wrapper.
 16 *
 17 * As written, this code is not safe for inclusion into the kernel
 18 * proper (after FPU initialization, in particular).
 19 */
 20
 21#ifdef _SETUP
 22# include "boot.h"
 23#endif
 24#include <linux/types.h>
 25#include <asm/cpufeaturemasks.h>
 26#include <asm/intel-family.h>
 27#include <asm/processor-flags.h>
 28#include <asm/msr-index.h>
 29#include <asm/shared/msr.h>
 30
 31#include "string.h"
 32
 33static u32 err_flags[NCAPINTS];
 34
 35static const int req_level = CONFIG_X86_MINIMUM_CPU_FAMILY;
 36
 37static const u32 req_flags[NCAPINTS] =
 38{
 39	REQUIRED_MASK0,
 40	REQUIRED_MASK1,
 41	0, /* REQUIRED_MASK2 not implemented in this file */
 42	0, /* REQUIRED_MASK3 not implemented in this file */
 43	REQUIRED_MASK4,
 44	0, /* REQUIRED_MASK5 not implemented in this file */
 45	REQUIRED_MASK6,
 46	0, /* REQUIRED_MASK7 not implemented in this file */
 47	0, /* REQUIRED_MASK8 not implemented in this file */
 48	0, /* REQUIRED_MASK9 not implemented in this file */
 49	0, /* REQUIRED_MASK10 not implemented in this file */
 50	0, /* REQUIRED_MASK11 not implemented in this file */
 51	0, /* REQUIRED_MASK12 not implemented in this file */
 52	0, /* REQUIRED_MASK13 not implemented in this file */
 53	0, /* REQUIRED_MASK14 not implemented in this file */
 54	0, /* REQUIRED_MASK15 not implemented in this file */
 55	REQUIRED_MASK16,
 56};
 57
 58#define A32(a, b, c, d) (((d) << 24)+((c) << 16)+((b) << 8)+(a))
 59
 60static int is_amd(void)
 61{
 62	return cpu_vendor[0] == A32('A', 'u', 't', 'h') &&
 63	       cpu_vendor[1] == A32('e', 'n', 't', 'i') &&
 64	       cpu_vendor[2] == A32('c', 'A', 'M', 'D');
 65}
 66
 67static int is_centaur(void)
 68{
 69	return cpu_vendor[0] == A32('C', 'e', 'n', 't') &&
 70	       cpu_vendor[1] == A32('a', 'u', 'r', 'H') &&
 71	       cpu_vendor[2] == A32('a', 'u', 'l', 's');
 72}
 73
 74static int is_transmeta(void)
 75{
 76	return cpu_vendor[0] == A32('G', 'e', 'n', 'u') &&
 77	       cpu_vendor[1] == A32('i', 'n', 'e', 'T') &&
 78	       cpu_vendor[2] == A32('M', 'x', '8', '6');
 79}
 80
 81static int is_intel(void)
 82{
 83	return cpu_vendor[0] == A32('G', 'e', 'n', 'u') &&
 84	       cpu_vendor[1] == A32('i', 'n', 'e', 'I') &&
 85	       cpu_vendor[2] == A32('n', 't', 'e', 'l');
 86}
 87
 88/* Returns a bitmask of which words we have error bits in */
 89static int check_cpuflags(void)
 90{
 91	u32 err;
 92	int i;
 93
 94	err = 0;
 95	for (i = 0; i < NCAPINTS; i++) {
 96		err_flags[i] = req_flags[i] & ~cpu.flags[i];
 97		if (err_flags[i])
 98			err |= 1 << i;
 99	}
100
101	return err;
102}
103
104/*
105 * Returns -1 on error.
106 *
107 * *cpu_level is set to the current CPU level; *req_level to the required
108 * level.  x86-64 is considered level 64 for this purpose.
109 *
110 * *err_flags_ptr is set to the flags error array if there are flags missing.
111 */
112int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u32 **err_flags_ptr)
113{
114	int err;
115
116	memset(&cpu.flags, 0, sizeof(cpu.flags));
117	cpu.level = 3;
118
119	if (has_eflag(X86_EFLAGS_AC))
120		cpu.level = 4;
121
122	get_cpuflags();
123	err = check_cpuflags();
124
125	if (test_bit(X86_FEATURE_LM, cpu.flags))
126		cpu.level = 64;
127
128	if (err == 0x01 &&
129	    !(err_flags[0] &
130	      ~((1 << X86_FEATURE_XMM)|(1 << X86_FEATURE_XMM2))) &&
131	    is_amd()) {
132		/* If this is an AMD and we're only missing SSE+SSE2, try to
133		   turn them on */
134
135		struct msr m;
136
137		raw_rdmsr(MSR_K7_HWCR, &m);
138		m.l &= ~(1 << 15);
139		raw_wrmsr(MSR_K7_HWCR, &m);
140
141		get_cpuflags();	/* Make sure it really did something */
142		err = check_cpuflags();
143	} else if (err == 0x01 &&
144		   !(err_flags[0] & ~(1 << X86_FEATURE_CX8)) &&
145		   is_centaur() && cpu.model >= 6) {
146		/* If this is a VIA C3, we might have to enable CX8
147		   explicitly */
148
149		struct msr m;
150
151		raw_rdmsr(MSR_VIA_FCR, &m);
152		m.l |= (1 << 1) | (1 << 7);
153		raw_wrmsr(MSR_VIA_FCR, &m);
154
155		set_bit(X86_FEATURE_CX8, cpu.flags);
156		err = check_cpuflags();
157	} else if (err == 0x01 && is_transmeta()) {
158		/* Transmeta might have masked feature bits in word 0 */
159
160		struct msr m, m_tmp;
161		u32 level = 1;
162
163		raw_rdmsr(0x80860004, &m);
164		m_tmp = m;
165		m_tmp.l = ~0;
166		raw_wrmsr(0x80860004, &m_tmp);
167		asm("cpuid"
168		    : "+a" (level), "=d" (cpu.flags[0])
169		    : : "ecx", "ebx");
170		raw_wrmsr(0x80860004, &m);
171
172		err = check_cpuflags();
173	} else if (err == 0x01 &&
174		   !(err_flags[0] & ~(1 << X86_FEATURE_PAE)) &&
175		   is_intel() && cpu.level == 6 &&
176		   (cpu.model == 9 || cpu.model == 13)) {
177		/* PAE is disabled on this Pentium M but can be forced */
178		if (cmdline_find_option_bool("forcepae")) {
179			puts("WARNING: Forcing PAE in CPU flags\n");
180			set_bit(X86_FEATURE_PAE, cpu.flags);
181			err = check_cpuflags();
182		}
183		else {
184			puts("WARNING: PAE disabled. Use parameter 'forcepae' to enable at your own risk!\n");
185		}
186	}
187	if (!err)
188		err = check_knl_erratum();
189
190	if (err_flags_ptr)
191		*err_flags_ptr = err ? err_flags : NULL;
192	if (cpu_level_ptr)
193		*cpu_level_ptr = cpu.level;
194	if (req_level_ptr)
195		*req_level_ptr = req_level;
196
197	return (cpu.level < req_level || err) ? -1 : 0;
198}
199
200int check_knl_erratum(void)
201{
202	/*
203	 * First check for the affected model/family:
204	 */
205	if (!is_intel() ||
206	    cpu.family != 6 ||
207	    cpu.model != 0x57 /*INTEL_XEON_PHI_KNL*/)
208		return 0;
209
210	/*
211	 * This erratum affects the Accessed/Dirty bits, and can
212	 * cause stray bits to be set in !Present PTEs.  We have
213	 * enough bits in our 64-bit PTEs (which we have on real
214	 * 64-bit mode or PAE) to avoid using these troublesome
215	 * bits.  But, we do not have enough space in our 32-bit
216	 * PTEs.  So, refuse to run on 32-bit non-PAE kernels.
217	 */
218	if (IS_ENABLED(CONFIG_X86_64) || IS_ENABLED(CONFIG_X86_PAE))
219		return 0;
220
221	puts("This 32-bit kernel can not run on this Xeon Phi x200\n"
222	     "processor due to a processor erratum.  Use a 64-bit\n"
223	     "kernel, or enable PAE in this 32-bit kernel.\n\n");
224
225	return -1;
226}
227
228