pcic.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * pcic.c: MicroSPARC-IIep PCI controller support
  4 *
  5 * Copyright (C) 1998 V. Roganov and G. Raiko
  6 *
  7 * Code is derived from Ultra/PCI PSYCHO controller support, see that
  8 * for author info.
  9 *
 10 * Support for diverse IIep based platforms by Pete Zaitcev.
 11 * CP-1200 by Eric Brower.
 12 */
 13
 14#include <linux/kernel.h>
 15#include <linux/types.h>
 16#include <linux/init.h>
 17#include <linux/mm.h>
 18#include <linux/slab.h>
 19#include <linux/string.h>
 20#include <linux/jiffies.h>
 21
 22#include <asm/swift.h> /* for cache flushing. */
 23#include <asm/io.h>
 24
 25#include <linux/ctype.h>
 26#include <linux/pci.h>
 27#include <linux/time.h>
 28#include <linux/timex.h>
 29#include <linux/interrupt.h>
 30#include <linux/export.h>
 31
 32#include <asm/irq.h>
 33#include <asm/oplib.h>
 34#include <asm/prom.h>
 35#include <asm/pcic.h>
 36#include <asm/timex.h>
 37#include <asm/timer.h>
 38#include <linux/uaccess.h>
 39#include <asm/irq_regs.h>
 40
 41#include "kernel.h"
 42#include "irq.h"
 43
 44/*
 45 * I studied different documents and many live PROMs both from 2.30
 46 * family and 3.xx versions. I came to the amazing conclusion: there is
 47 * absolutely no way to route interrupts in IIep systems relying on
 48 * information which PROM presents. We must hardcode interrupt routing
 49 * schematics. And this actually sucks.   -- zaitcev 1999/05/12
 50 *
 51 * To find irq for a device we determine which routing map
 52 * is in effect or, in other words, on which machine we are running.
 53 * We use PROM name for this although other techniques may be used
 54 * in special cases (Gleb reports a PROMless IIep based system).
 55 * Once we know the map we take device configuration address and
 56 * find PCIC pin number where INT line goes. Then we may either program
 57 * preferred irq into the PCIC or supply the preexisting irq to the device.
 58 */
 59struct pcic_ca2irq {
 60	unsigned char busno;		/* PCI bus number */
 61	unsigned char devfn;		/* Configuration address */
 62	unsigned char pin;		/* PCIC external interrupt pin */
 63	unsigned char irq;		/* Preferred IRQ (mappable in PCIC) */
 64	unsigned int force;		/* Enforce preferred IRQ */
 65};
 66
 67struct pcic_sn2list {
 68	char *sysname;
 69	struct pcic_ca2irq *intmap;
 70	int mapdim;
 71};
 72
 73/*
 74 * JavaEngine-1 apparently has different versions.
 75 *
 76 * According to communications with Sun folks, for P2 build 501-4628-03:
 77 * pin 0 - parallel, audio;
 78 * pin 1 - Ethernet;
 79 * pin 2 - su;
 80 * pin 3 - PS/2 kbd and mouse.
 81 *
 82 * OEM manual (805-1486):
 83 * pin 0: Ethernet
 84 * pin 1: All EBus
 85 * pin 2: IGA (unused)
 86 * pin 3: Not connected
 87 * OEM manual says that 501-4628 & 501-4811 are the same thing,
 88 * only the latter has NAND flash in place.
 89 *
 90 * So far unofficial Sun wins over the OEM manual. Poor OEMs...
 91 */
 92static struct pcic_ca2irq pcic_i_je1a[] = {	/* 501-4811-03 */
 93	{ 0, 0x00, 2, 12, 0 },		/* EBus: hogs all */
 94	{ 0, 0x01, 1,  6, 1 },		/* Happy Meal */
 95	{ 0, 0x80, 0,  7, 0 },		/* IGA (unused) */
 96};
 97
 98/* XXX JS-E entry is incomplete - PCI Slot 2 address (pin 7)? */
 99static struct pcic_ca2irq pcic_i_jse[] = {
100	{ 0, 0x00, 0, 13, 0 },		/* Ebus - serial and keyboard */
101	{ 0, 0x01, 1,  6, 0 },		/* hme */
102	{ 0, 0x08, 2,  9, 0 },		/* VGA - we hope not used :) */
103	{ 0, 0x10, 6,  8, 0 },		/* PCI INTA# in Slot 1 */
104	{ 0, 0x18, 7, 12, 0 },		/* PCI INTA# in Slot 2, shared w. RTC */
105	{ 0, 0x38, 4,  9, 0 },		/* All ISA devices. Read 8259. */
106	{ 0, 0x80, 5, 11, 0 },		/* EIDE */
107	/* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */
108	{ 0, 0xA0, 4,  9, 0 },		/* USB */
109	/*
110	 * Some pins belong to non-PCI devices, we hardcode them in drivers.
111	 * sun4m timers - irq 10, 14
112	 * PC style RTC - pin 7, irq 4 ?
113	 * Smart card, Parallel - pin 4 shared with USB, ISA
114	 * audio - pin 3, irq 5 ?
115	 */
116};
117
118/* SPARCengine-6 was the original release name of CP1200.
119 * The documentation differs between the two versions
120 */
121static struct pcic_ca2irq pcic_i_se6[] = {
122	{ 0, 0x08, 0,  2, 0 },		/* SCSI	*/
123	{ 0, 0x01, 1,  6, 0 },		/* HME	*/
124	{ 0, 0x00, 3, 13, 0 },		/* EBus	*/
125};
126
127/*
128 * Krups (courtesy of Varol Kaptan)
129 * No documentation available, but it was easy to guess
130 * because it was very similar to Espresso.
131 *  
132 * pin 0 - kbd, mouse, serial;
133 * pin 1 - Ethernet;
134 * pin 2 - igs (we do not use it);
135 * pin 3 - audio;
136 * pin 4,5,6 - unused;
137 * pin 7 - RTC (from P2 onwards as David B. says).
138 */
139static struct pcic_ca2irq pcic_i_jk[] = {
140	{ 0, 0x00, 0, 13, 0 },		/* Ebus - serial and keyboard */
141	{ 0, 0x01, 1,  6, 0 },		/* hme */
142};
143
144/*
145 * Several entries in this list may point to the same routing map
146 * as several PROMs may be installed on the same physical board.
147 */
148#define SN2L_INIT(name, map)	\
149  { name, map, ARRAY_SIZE(map) }
150
151static struct pcic_sn2list pcic_known_sysnames[] = {
152	SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a),	/* JE1, PROM 2.32 */
153	SN2L_INIT("SUNW,JS-E", pcic_i_jse),	/* PROLL JavaStation-E */
154	SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */
155	SN2L_INIT("SUNW,JS-NC", pcic_i_jk),	/* PROLL JavaStation-NC */
156	SN2L_INIT("SUNW,JSIIep", pcic_i_jk),	/* OBP JavaStation-NC */
157	{ NULL, NULL, 0 }
158};
159
160/*
161 * Only one PCIC per IIep,
162 * and since we have no SMP IIep, only one per system.
163 */
164static int pcic0_up;
165static struct linux_pcic pcic0;
166
167void __iomem *pcic_regs;
168static volatile int pcic_speculative;
169static volatile int pcic_trapped;
170
171/* forward */
172unsigned int pcic_build_device_irq(struct platform_device *op,
173                                   unsigned int real_irq);
174
175#define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3))
176
177static int pcic_read_config_dword(unsigned int busno, unsigned int devfn,
178    int where, u32 *value)
179{
180	struct linux_pcic *pcic;
181	unsigned long flags;
182
183	pcic = &pcic0;
184
185	local_irq_save(flags);
186#if 0 /* does not fail here */
187	pcic_speculative = 1;
188	pcic_trapped = 0;
189#endif
190	writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
191#if 0 /* does not fail here */
192	nop();
193	if (pcic_trapped) {
194		local_irq_restore(flags);
195		*value = ~0;
196		return 0;
197	}
198#endif
199	pcic_speculative = 2;
200	pcic_trapped = 0;
201	*value = readl(pcic->pcic_config_space_data + (where&4));
202	nop();
203	if (pcic_trapped) {
204		pcic_speculative = 0;
205		local_irq_restore(flags);
206		*value = ~0;
207		return 0;
208	}
209	pcic_speculative = 0;
210	local_irq_restore(flags);
211	return 0;
212}
213
214static int pcic_read_config(struct pci_bus *bus, unsigned int devfn,
215   int where, int size, u32 *val)
216{
217	unsigned int v;
218
219	if (bus->number != 0) return -EINVAL;
220	switch (size) {
221	case 1:
222		pcic_read_config_dword(bus->number, devfn, where&~3, &v);
223		*val = 0xff & (v >> (8*(where & 3)));
224		return 0;
225	case 2:
226		if (where&1) return -EINVAL;
227		pcic_read_config_dword(bus->number, devfn, where&~3, &v);
228		*val = 0xffff & (v >> (8*(where & 3)));
229		return 0;
230	case 4:
231		if (where&3) return -EINVAL;
232		pcic_read_config_dword(bus->number, devfn, where&~3, val);
233		return 0;
234	}
235	return -EINVAL;
236}
237
238static int pcic_write_config_dword(unsigned int busno, unsigned int devfn,
239    int where, u32 value)
240{
241	struct linux_pcic *pcic;
242	unsigned long flags;
243
244	pcic = &pcic0;
245
246	local_irq_save(flags);
247	writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
248	writel(value, pcic->pcic_config_space_data + (where&4));
249	local_irq_restore(flags);
250	return 0;
251}
252
253static int pcic_write_config(struct pci_bus *bus, unsigned int devfn,
254   int where, int size, u32 val)
255{
256	unsigned int v;
257
258	if (bus->number != 0) return -EINVAL;
259	switch (size) {
260	case 1:
261		pcic_read_config_dword(bus->number, devfn, where&~3, &v);
262		v = (v & ~(0xff << (8*(where&3)))) |
263		    ((0xff&val) << (8*(where&3)));
264		return pcic_write_config_dword(bus->number, devfn, where&~3, v);
265	case 2:
266		if (where&1) return -EINVAL;
267		pcic_read_config_dword(bus->number, devfn, where&~3, &v);
268		v = (v & ~(0xffff << (8*(where&3)))) |
269		    ((0xffff&val) << (8*(where&3)));
270		return pcic_write_config_dword(bus->number, devfn, where&~3, v);
271	case 4:
272		if (where&3) return -EINVAL;
273		return pcic_write_config_dword(bus->number, devfn, where, val);
274	}
275	return -EINVAL;
276}
277
278static struct pci_ops pcic_ops = {
279	.read =		pcic_read_config,
280	.write =	pcic_write_config,
281};
282
283/*
284 * On sparc64 pcibios_init() calls pci_controller_probe().
285 * We want PCIC probed little ahead so that interrupt controller
286 * would be operational.
287 */
288int __init pcic_probe(void)
289{
290	struct linux_pcic *pcic;
291	struct linux_prom_registers regs[PROMREG_MAX];
292	struct linux_pbm_info* pbm;
293	char namebuf[64];
294	phandle node;
295	int err;
296
297	if (pcic0_up) {
298		prom_printf("PCIC: called twice!\n");
299		prom_halt();
300	}
301	pcic = &pcic0;
302
303	node = prom_getchild (prom_root_node);
304	node = prom_searchsiblings (node, "pci");
305	if (node == 0)
306		return -ENODEV;
307	/*
308	 * Map in PCIC register set, config space, and IO base
309	 */
310	err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs));
311	if (err == 0 || err == -1) {
312		prom_printf("PCIC: Error, cannot get PCIC registers "
313			    "from PROM.\n");
314		prom_halt();
315	}
316
317	pcic0_up = 1;
318
319	pcic->pcic_res_regs.name = "pcic_registers";
320	pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size);
321	if (!pcic->pcic_regs) {
322		prom_printf("PCIC: Error, cannot map PCIC registers.\n");
323		prom_halt();
324	}
325
326	pcic->pcic_res_io.name = "pcic_io";
327	if ((pcic->pcic_io = (unsigned long)
328	    ioremap(regs[1].phys_addr, 0x10000)) == 0) {
329		prom_printf("PCIC: Error, cannot map PCIC IO Base.\n");
330		prom_halt();
331	}
332
333	pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr";
334	if ((pcic->pcic_config_space_addr =
335	    ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == NULL) {
336		prom_printf("PCIC: Error, cannot map "
337			    "PCI Configuration Space Address.\n");
338		prom_halt();
339	}
340
341	/*
342	 * Docs say three least significant bits in address and data
343	 * must be the same. Thus, we need adjust size of data.
344	 */
345	pcic->pcic_res_cfg_data.name = "pcic_cfg_data";
346	if ((pcic->pcic_config_space_data =
347	    ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == NULL) {
348		prom_printf("PCIC: Error, cannot map "
349			    "PCI Configuration Space Data.\n");
350		prom_halt();
351	}
352
353	pbm = &pcic->pbm;
354	pbm->prom_node = node;
355	prom_getstring(node, "name", namebuf, 63);  namebuf[63] = 0;
356	strscpy(pbm->prom_name, namebuf);
357
358	{
359		extern int pcic_nmi_trap_patch[4];
360
361		t_nmi[0] = pcic_nmi_trap_patch[0];
362		t_nmi[1] = pcic_nmi_trap_patch[1];
363		t_nmi[2] = pcic_nmi_trap_patch[2];
364		t_nmi[3] = pcic_nmi_trap_patch[3];
365		swift_flush_dcache();
366		pcic_regs = pcic->pcic_regs;
367	}
368
369	prom_getstring(prom_root_node, "name", namebuf, 63);  namebuf[63] = 0;
370	{
371		struct pcic_sn2list *p;
372
373		for (p = pcic_known_sysnames; p->sysname != NULL; p++) {
374			if (strcmp(namebuf, p->sysname) == 0)
375				break;
376		}
377		pcic->pcic_imap = p->intmap;
378		pcic->pcic_imdim = p->mapdim;
379	}
380	if (pcic->pcic_imap == NULL) {
381		/*
382		 * We do not panic here for the sake of embedded systems.
383		 */
384		printk("PCIC: System %s is unknown, cannot route interrupts\n",
385		    namebuf);
386	}
387
388	return 0;
389}
390
391static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic)
392{
393	struct linux_pbm_info *pbm = &pcic->pbm;
394
395	pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm);
396	if (!pbm->pci_bus)
397		return;
398
399#if 0 /* deadwood transplanted from sparc64 */
400	pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
401	pci_record_assignments(pbm, pbm->pci_bus);
402	pci_assign_unassigned(pbm, pbm->pci_bus);
403	pci_fixup_irq(pbm, pbm->pci_bus);
404#endif
405	pci_bus_add_devices(pbm->pci_bus);
406}
407
408/*
409 * Main entry point from the PCI subsystem.
410 */
411static int __init pcic_init(void)
412{
413	struct linux_pcic *pcic;
414
415	/*
416	 * PCIC should be initialized at start of the timer.
417	 * So, here we report the presence of PCIC and do some magic passes.
418	 */
419	if(!pcic0_up)
420		return 0;
421	pcic = &pcic0;
422
423	/*
424	 *      Switch off IOTLB translation.
425	 */
426	writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE, 
427	       pcic->pcic_regs+PCI_DVMA_CONTROL);
428
429	/*
430	 *      Increase mapped size for PCI memory space (DMA access).
431	 *      Should be done in that order (size first, address second).
432	 *      Why we couldn't set up 4GB and forget about it? XXX
433	 */
434	writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0);
435	writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY, 
436	       pcic->pcic_regs+PCI_BASE_ADDRESS_0);
437
438	pcic_pbm_scan_bus(pcic);
439
440	return 0;
441}
442
443int pcic_present(void)
444{
445	return pcic0_up;
446}
447
448static int pdev_to_pnode(struct linux_pbm_info *pbm, struct pci_dev *pdev)
449{
450	struct linux_prom_pci_registers regs[PROMREG_MAX];
451	int err;
452	phandle node = prom_getchild(pbm->prom_node);
453
454	while(node) {
455		err = prom_getproperty(node, "reg", 
456				       (char *)&regs[0], sizeof(regs));
457		if(err != 0 && err != -1) {
458			unsigned long devfn = (regs[0].which_io >> 8) & 0xff;
459			if(devfn == pdev->devfn)
460				return node;
461		}
462		node = prom_getsibling(node);
463	}
464	return 0;
465}
466
467static inline struct pcidev_cookie *pci_devcookie_alloc(void)
468{
469	return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC);
470}
471
472static void pcic_map_pci_device(struct linux_pcic *pcic,
473    struct pci_dev *dev, int node)
474{
475	char namebuf[64];
476	unsigned long address;
477	unsigned long flags;
478	int j;
479
480	if (node == 0 || node == -1) {
481		strscpy(namebuf, "???");
482	} else {
483		prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
484	}
485
486	for (j = 0; j < 6; j++) {
487		address = dev->resource[j].start;
488		if (address == 0) break;	/* are sequential */
489		flags = dev->resource[j].flags;
490		if ((flags & IORESOURCE_IO) != 0) {
491			if (address < 0x10000) {
492				/*
493				 * A device responds to I/O cycles on PCI.
494				 * We generate these cycles with memory
495				 * access into the fixed map (phys 0x30000000).
496				 *
497				 * Since a device driver does not want to
498				 * do ioremap() before accessing PC-style I/O,
499				 * we supply virtual, ready to access address.
500				 *
501				 * Note that request_region()
502				 * works for these devices.
503				 *
504				 * XXX Neat trick, but it's a *bad* idea
505				 * to shit into regions like that.
506				 * What if we want to allocate one more
507				 * PCI base address...
508				 */
509				dev->resource[j].start =
510				    pcic->pcic_io + address;
511				dev->resource[j].end = 1;  /* XXX */
512				dev->resource[j].flags =
513				    (flags & ~IORESOURCE_IO) | IORESOURCE_MEM;
514			} else {
515				/*
516				 * OOPS... PCI Spec allows this. Sun does
517				 * not have any devices getting above 64K
518				 * so it must be user with a weird I/O
519				 * board in a PCI slot. We must remap it
520				 * under 64K but it is not done yet. XXX
521				 */
522				pci_info(dev, "PCIC: Skipping I/O space at "
523					 "0x%lx, this will Oops if a driver "
524					 "attaches device '%s'\n", address,
525					 namebuf);
526			}
527		}
528	}
529}
530
531static void
532pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node)
533{
534	struct pcic_ca2irq *p;
535	unsigned int real_irq;
536	int i, ivec;
537	char namebuf[64];
538
539	if (node == 0 || node == -1) {
540		strscpy(namebuf, "???");
541	} else {
542		prom_getstring(node, "name", namebuf, sizeof(namebuf));
543	}
544
545	if ((p = pcic->pcic_imap) == NULL) {
546		dev->irq = 0;
547		return;
548	}
549	for (i = 0; i < pcic->pcic_imdim; i++) {
550		if (p->busno == dev->bus->number && p->devfn == dev->devfn)
551			break;
552		p++;
553	}
554	if (i >= pcic->pcic_imdim) {
555		pci_info(dev, "PCIC: device %s not found in %d\n", namebuf,
556			 pcic->pcic_imdim);
557		dev->irq = 0;
558		return;
559	}
560
561	i = p->pin;
562	if (i >= 0 && i < 4) {
563		ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
564		real_irq = ivec >> (i << 2) & 0xF;
565	} else if (i >= 4 && i < 8) {
566		ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
567		real_irq = ivec >> ((i-4) << 2) & 0xF;
568	} else {					/* Corrupted map */
569		pci_info(dev, "PCIC: BAD PIN %d\n", i); for (;;) {}
570	}
571/* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */
572
573	/* real_irq means PROM did not bother to program the upper
574	 * half of PCIC. This happens on JS-E with PROM 3.11, for instance.
575	 */
576	if (real_irq == 0 || p->force) {
577		if (p->irq == 0 || p->irq >= 15) {	/* Corrupted map */
578			pci_info(dev, "PCIC: BAD IRQ %d\n", p->irq); for (;;) {}
579		}
580		pci_info(dev, "PCIC: setting irq %d at pin %d\n", p->irq,
581			 p->pin);
582		real_irq = p->irq;
583
584		i = p->pin;
585		if (i >= 4) {
586			ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
587			ivec &= ~(0xF << ((i - 4) << 2));
588			ivec |= p->irq << ((i - 4) << 2);
589			writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI);
590		} else {
591			ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
592			ivec &= ~(0xF << (i << 2));
593			ivec |= p->irq << (i << 2);
594			writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO);
595		}
596	}
597	dev->irq = pcic_build_device_irq(NULL, real_irq);
598}
599
600/*
601 * Normally called from {do_}pci_scan_bus...
602 */
603void pcibios_fixup_bus(struct pci_bus *bus)
604{
605	struct pci_dev *dev;
606	struct linux_pcic *pcic;
607	/* struct linux_pbm_info* pbm = &pcic->pbm; */
608	int node;
609	struct pcidev_cookie *pcp;
610
611	if (!pcic0_up) {
612		pci_info(bus, "pcibios_fixup_bus: no PCIC\n");
613		return;
614	}
615	pcic = &pcic0;
616
617	/*
618	 * Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus);
619	 */
620	if (bus->number != 0) {
621		pci_info(bus, "pcibios_fixup_bus: nonzero bus 0x%x\n",
622			 bus->number);
623		return;
624	}
625
626	list_for_each_entry(dev, &bus->devices, bus_list) {
627		node = pdev_to_pnode(&pcic->pbm, dev);
628		if(node == 0)
629			node = -1;
630
631		/* cookies */
632		pcp = pci_devcookie_alloc();
633		pcp->pbm = &pcic->pbm;
634		pcp->prom_node = of_find_node_by_phandle(node);
635		dev->sysdata = pcp;
636
637		/* fixing I/O to look like memory */
638		if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE)
639			pcic_map_pci_device(pcic, dev, node);
640
641		pcic_fill_irq(pcic, dev, node);
642	}
643}
644
645/* Makes compiler happy */
646static volatile int pcic_timer_dummy;
647
648static void pcic_clear_clock_irq(void)
649{
650	pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT);
651}
652
653/* CPU frequency is 100 MHz, timer increments every 4 CPU clocks */
654#define USECS_PER_JIFFY  (1000000 / HZ)
655#define TICK_TIMER_LIMIT ((100 * 1000000 / 4) / HZ)
656
657static unsigned int pcic_cycles_offset(void)
658{
659	u32 value, count;
660
661	value = readl(pcic0.pcic_regs + PCI_SYS_COUNTER);
662	count = value & ~PCI_SYS_COUNTER_OVERFLOW;
663
664	if (value & PCI_SYS_COUNTER_OVERFLOW)
665		count += TICK_TIMER_LIMIT;
666	/*
667	 * We divide all by HZ
668	 * to have microsecond resolution and to avoid overflow
669	 */
670	count = ((count / HZ) * USECS_PER_JIFFY) / (TICK_TIMER_LIMIT / HZ);
671
672	/* Coordinate with the sparc_config.clock_rate setting */
673	return count * 2;
674}
675
676void __init pci_time_init(void)
677{
678	struct linux_pcic *pcic = &pcic0;
679	unsigned long v;
680	int timer_irq, irq;
681	int err;
682
683#ifndef CONFIG_SMP
684	/*
685	 * The clock_rate is in SBUS dimension.
686	 * We take into account this in pcic_cycles_offset()
687	 */
688	sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ;
689	sparc_config.features |= FEAT_L10_CLOCKEVENT;
690#endif
691	sparc_config.features |= FEAT_L10_CLOCKSOURCE;
692	sparc_config.get_cycles_offset = pcic_cycles_offset;
693
694	writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);
695	/* PROM should set appropriate irq */
696	v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ);
697	timer_irq = PCI_COUNTER_IRQ_SYS(v);
698	writel (PCI_COUNTER_IRQ_SET(timer_irq, 0),
699		pcic->pcic_regs+PCI_COUNTER_IRQ);
700	irq = pcic_build_device_irq(NULL, timer_irq);
701	err = request_irq(irq, timer_interrupt,
702			  IRQF_TIMER, "timer", NULL);
703	if (err) {
704		prom_printf("time_init: unable to attach IRQ%d\n", timer_irq);
705		prom_halt();
706	}
707	local_irq_enable();
708}
709
710
711#if 0
712static void watchdog_reset() {
713	writeb(0, pcic->pcic_regs+PCI_SYS_STATUS);
714}
715#endif
716
717/*
718 * NMI
719 */
720void pcic_nmi(unsigned int pend, struct pt_regs *regs)
721{
722	pend = swab32(pend);
723
724	if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) {
725		/*
726		 * XXX On CP-1200 PCI #SERR may happen, we do not know
727		 * what to do about it yet.
728		 */
729		printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n",
730		    pend, (int)regs->pc, pcic_speculative);
731		for (;;) { }
732	}
733	pcic_speculative = 0;
734	pcic_trapped = 1;
735	regs->pc = regs->npc;
736	regs->npc += 4;
737}
738
739static inline unsigned long get_irqmask(int irq_nr)
740{
741	return 1 << irq_nr;
742}
743
744static void pcic_mask_irq(struct irq_data *data)
745{
746	unsigned long mask, flags;
747
748	mask = (unsigned long)data->chip_data;
749	local_irq_save(flags);
750	writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);
751	local_irq_restore(flags);
752}
753
754static void pcic_unmask_irq(struct irq_data *data)
755{
756	unsigned long mask, flags;
757
758	mask = (unsigned long)data->chip_data;
759	local_irq_save(flags);
760	writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);
761	local_irq_restore(flags);
762}
763
764static unsigned int pcic_startup_irq(struct irq_data *data)
765{
766	irq_link(data->irq);
767	pcic_unmask_irq(data);
768	return 0;
769}
770
771static struct irq_chip pcic_irq = {
772	.name		= "pcic",
773	.irq_startup	= pcic_startup_irq,
774	.irq_mask	= pcic_mask_irq,
775	.irq_unmask	= pcic_unmask_irq,
776};
777
778unsigned int pcic_build_device_irq(struct platform_device *op,
779                                   unsigned int real_irq)
780{
781	unsigned int irq;
782	unsigned long mask;
783
784	irq = 0;
785	mask = get_irqmask(real_irq);
786	if (mask == 0)
787		goto out;
788
789	irq = irq_alloc(real_irq, real_irq);
790	if (irq == 0)
791		goto out;
792
793	irq_set_chip_and_handler_name(irq, &pcic_irq,
794	                              handle_level_irq, "PCIC");
795	irq_set_chip_data(irq, (void *)mask);
796
797out:
798	return irq;
799}
800
801
802static void pcic_load_profile_irq(int cpu, unsigned int limit)
803{
804	printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__);
805}
806
807void __init sun4m_pci_init_IRQ(void)
808{
809	sparc_config.build_device_irq = pcic_build_device_irq;
810	sparc_config.clear_clock_irq  = pcic_clear_clock_irq;
811	sparc_config.load_profile_irq = pcic_load_profile_irq;
812}
813
814subsys_initcall(pcic_init);