pci_sun4v.c

   1// SPDX-License-Identifier: GPL-2.0
   2/* pci_sun4v.c: SUN4V specific PCI controller support.
   3 *
   4 * Copyright (C) 2006, 2007, 2008 David S. Miller (davem@davemloft.net)
   5 */
   6
   7#include <linux/kernel.h>
   8#include <linux/types.h>
   9#include <linux/pci.h>
  10#include <linux/init.h>
  11#include <linux/slab.h>
  12#include <linux/interrupt.h>
  13#include <linux/percpu.h>
  14#include <linux/irq.h>
  15#include <linux/msi.h>
  16#include <linux/export.h>
  17#include <linux/log2.h>
  18#include <linux/of.h>
  19#include <linux/platform_device.h>
  20#include <linux/dma-map-ops.h>
  21#include <asm/iommu-common.h>
  22
  23#include <asm/iommu.h>
  24#include <asm/irq.h>
  25#include <asm/hypervisor.h>
  26#include <asm/prom.h>
  27
  28#include "pci_impl.h"
  29#include "iommu_common.h"
  30#include "kernel.h"
  31
  32#include "pci_sun4v.h"
  33
  34#define DRIVER_NAME	"pci_sun4v"
  35#define PFX		DRIVER_NAME ": "
  36
  37static unsigned long vpci_major;
  38static unsigned long vpci_minor;
  39
  40struct vpci_version {
  41	unsigned long major;
  42	unsigned long minor;
  43};
  44
  45/* Ordered from largest major to lowest */
  46static struct vpci_version vpci_versions[] = {
  47	{ .major = 2, .minor = 0 },
  48	{ .major = 1, .minor = 1 },
  49};
  50
  51static unsigned long vatu_major = 1;
  52static unsigned long vatu_minor = 1;
  53
  54#define PGLIST_NENTS	(PAGE_SIZE / sizeof(u64))
  55
  56struct iommu_batch {
  57	struct device	*dev;		/* Device mapping is for.	*/
  58	unsigned long	prot;		/* IOMMU page protections	*/
  59	unsigned long	entry;		/* Index into IOTSB.		*/
  60	u64		*pglist;	/* List of physical pages	*/
  61	unsigned long	npages;		/* Number of pages in list.	*/
  62};
  63
  64static DEFINE_PER_CPU(struct iommu_batch, iommu_batch);
  65static int iommu_batch_initialized;
  66
  67/* Interrupts must be disabled.  */
  68static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry)
  69{
  70	struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
  71
  72	p->dev		= dev;
  73	p->prot		= prot;
  74	p->entry	= entry;
  75	p->npages	= 0;
  76}
  77
  78static inline bool iommu_use_atu(struct iommu *iommu, u64 mask)
  79{
  80	return iommu->atu && mask > DMA_BIT_MASK(32);
  81}
  82
  83/* Interrupts must be disabled.  */
  84static long iommu_batch_flush(struct iommu_batch *p, u64 mask)
  85{
  86	struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
  87	u64 *pglist = p->pglist;
  88	u64 index_count;
  89	unsigned long devhandle = pbm->devhandle;
  90	unsigned long prot = p->prot;
  91	unsigned long entry = p->entry;
  92	unsigned long npages = p->npages;
  93	unsigned long iotsb_num;
  94	unsigned long ret;
  95	long num;
  96
  97	/* VPCI maj=1, min=[0,1] only supports read and write */
  98	if (vpci_major < 2)
  99		prot &= (HV_PCI_MAP_ATTR_READ | HV_PCI_MAP_ATTR_WRITE);
 100
 101	while (npages != 0) {
 102		if (!iommu_use_atu(pbm->iommu, mask)) {
 103			num = pci_sun4v_iommu_map(devhandle,
 104						  HV_PCI_TSBID(0, entry),
 105						  npages,
 106						  prot,
 107						  __pa(pglist));
 108			if (unlikely(num < 0)) {
 109				pr_err_ratelimited("%s: IOMMU map of [%08lx:%08llx:%lx:%lx:%lx] failed with status %ld\n",
 110						   __func__,
 111						   devhandle,
 112						   HV_PCI_TSBID(0, entry),
 113						   npages, prot, __pa(pglist),
 114						   num);
 115				return -1;
 116			}
 117		} else {
 118			index_count = HV_PCI_IOTSB_INDEX_COUNT(npages, entry),
 119			iotsb_num = pbm->iommu->atu->iotsb->iotsb_num;
 120			ret = pci_sun4v_iotsb_map(devhandle,
 121						  iotsb_num,
 122						  index_count,
 123						  prot,
 124						  __pa(pglist),
 125						  &num);
 126			if (unlikely(ret != HV_EOK)) {
 127				pr_err_ratelimited("%s: ATU map of [%08lx:%lx:%llx:%lx:%lx] failed with status %ld\n",
 128						   __func__,
 129						   devhandle, iotsb_num,
 130						   index_count, prot,
 131						   __pa(pglist), ret);
 132				return -1;
 133			}
 134		}
 135		entry += num;
 136		npages -= num;
 137		pglist += num;
 138	}
 139
 140	p->entry = entry;
 141	p->npages = 0;
 142
 143	return 0;
 144}
 145
 146static inline void iommu_batch_new_entry(unsigned long entry, u64 mask)
 147{
 148	struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
 149
 150	if (p->entry + p->npages == entry)
 151		return;
 152	if (p->entry != ~0UL)
 153		iommu_batch_flush(p, mask);
 154	p->entry = entry;
 155}
 156
 157/* Interrupts must be disabled.  */
 158static inline long iommu_batch_add(u64 phys_page, u64 mask)
 159{
 160	struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
 161
 162	BUG_ON(p->npages >= PGLIST_NENTS);
 163
 164	p->pglist[p->npages++] = phys_page;
 165	if (p->npages == PGLIST_NENTS)
 166		return iommu_batch_flush(p, mask);
 167
 168	return 0;
 169}
 170
 171/* Interrupts must be disabled.  */
 172static inline long iommu_batch_end(u64 mask)
 173{
 174	struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
 175
 176	BUG_ON(p->npages >= PGLIST_NENTS);
 177
 178	return iommu_batch_flush(p, mask);
 179}
 180
 181static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
 182				   dma_addr_t *dma_addrp, gfp_t gfp,
 183				   unsigned long attrs)
 184{
 185	u64 mask;
 186	unsigned long flags, order, first_page, npages, n;
 187	unsigned long prot = 0;
 188	struct iommu *iommu;
 189	struct iommu_map_table *tbl;
 190	struct page *page;
 191	void *ret;
 192	long entry;
 193	int nid;
 194
 195	size = IO_PAGE_ALIGN(size);
 196	order = get_order(size);
 197	if (unlikely(order > MAX_PAGE_ORDER))
 198		return NULL;
 199
 200	npages = size >> IO_PAGE_SHIFT;
 201
 202	if (attrs & DMA_ATTR_WEAK_ORDERING)
 203		prot = HV_PCI_MAP_ATTR_RELAXED_ORDER;
 204
 205	nid = dev->archdata.numa_node;
 206	page = alloc_pages_node(nid, gfp, order);
 207	if (unlikely(!page))
 208		return NULL;
 209
 210	first_page = (unsigned long) page_address(page);
 211	memset((char *)first_page, 0, PAGE_SIZE << order);
 212
 213	iommu = dev->archdata.iommu;
 214	mask = dev->coherent_dma_mask;
 215	if (!iommu_use_atu(iommu, mask))
 216		tbl = &iommu->tbl;
 217	else
 218		tbl = &iommu->atu->tbl;
 219
 220	entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
 221				      (unsigned long)(-1), 0);
 222
 223	if (unlikely(entry == IOMMU_ERROR_CODE))
 224		goto range_alloc_fail;
 225
 226	*dma_addrp = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
 227	ret = (void *) first_page;
 228	first_page = __pa(first_page);
 229
 230	local_irq_save(flags);
 231
 232	iommu_batch_start(dev,
 233			  (HV_PCI_MAP_ATTR_READ | prot |
 234			   HV_PCI_MAP_ATTR_WRITE),
 235			  entry);
 236
 237	for (n = 0; n < npages; n++) {
 238		long err = iommu_batch_add(first_page + (n * PAGE_SIZE), mask);
 239		if (unlikely(err < 0L))
 240			goto iommu_map_fail;
 241	}
 242
 243	if (unlikely(iommu_batch_end(mask) < 0L))
 244		goto iommu_map_fail;
 245
 246	local_irq_restore(flags);
 247
 248	return ret;
 249
 250iommu_map_fail:
 251	local_irq_restore(flags);
 252	iommu_tbl_range_free(tbl, *dma_addrp, npages, IOMMU_ERROR_CODE);
 253
 254range_alloc_fail:
 255	free_pages(first_page, order);
 256	return NULL;
 257}
 258
 259static unsigned long dma_4v_iotsb_bind(unsigned long devhandle,
 260				       unsigned long iotsb_num,
 261				       struct pci_bus *bus_dev)
 262{
 263	struct pci_dev *pdev;
 264	unsigned long err;
 265	unsigned int bus;
 266	unsigned int device;
 267	unsigned int fun;
 268
 269	list_for_each_entry(pdev, &bus_dev->devices, bus_list) {
 270		if (pdev->subordinate) {
 271			/* No need to bind pci bridge */
 272			dma_4v_iotsb_bind(devhandle, iotsb_num,
 273					  pdev->subordinate);
 274		} else {
 275			bus = bus_dev->number;
 276			device = PCI_SLOT(pdev->devfn);
 277			fun = PCI_FUNC(pdev->devfn);
 278			err = pci_sun4v_iotsb_bind(devhandle, iotsb_num,
 279						   HV_PCI_DEVICE_BUILD(bus,
 280								       device,
 281								       fun));
 282
 283			/* If bind fails for one device it is going to fail
 284			 * for rest of the devices because we are sharing
 285			 * IOTSB. So in case of failure simply return with
 286			 * error.
 287			 */
 288			if (err)
 289				return err;
 290		}
 291	}
 292
 293	return 0;
 294}
 295
 296static void dma_4v_iommu_demap(struct device *dev, unsigned long devhandle,
 297			       dma_addr_t dvma, unsigned long iotsb_num,
 298			       unsigned long entry, unsigned long npages)
 299{
 300	unsigned long num, flags;
 301	unsigned long ret;
 302
 303	local_irq_save(flags);
 304	do {
 305		if (dvma <= DMA_BIT_MASK(32)) {
 306			num = pci_sun4v_iommu_demap(devhandle,
 307						    HV_PCI_TSBID(0, entry),
 308						    npages);
 309		} else {
 310			ret = pci_sun4v_iotsb_demap(devhandle, iotsb_num,
 311						    entry, npages, &num);
 312			if (unlikely(ret != HV_EOK)) {
 313				pr_err_ratelimited("pci_iotsb_demap() failed with error: %ld\n",
 314						   ret);
 315			}
 316		}
 317		entry += num;
 318		npages -= num;
 319	} while (npages != 0);
 320	local_irq_restore(flags);
 321}
 322
 323static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
 324				 dma_addr_t dvma, unsigned long attrs)
 325{
 326	struct pci_pbm_info *pbm;
 327	struct iommu *iommu;
 328	struct atu *atu;
 329	struct iommu_map_table *tbl;
 330	unsigned long order, npages, entry;
 331	unsigned long iotsb_num;
 332	u32 devhandle;
 333
 334	npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
 335	iommu = dev->archdata.iommu;
 336	pbm = dev->archdata.host_controller;
 337	atu = iommu->atu;
 338	devhandle = pbm->devhandle;
 339
 340	if (!iommu_use_atu(iommu, dvma)) {
 341		tbl = &iommu->tbl;
 342		iotsb_num = 0; /* we don't care for legacy iommu */
 343	} else {
 344		tbl = &atu->tbl;
 345		iotsb_num = atu->iotsb->iotsb_num;
 346	}
 347	entry = ((dvma - tbl->table_map_base) >> IO_PAGE_SHIFT);
 348	dma_4v_iommu_demap(dev, devhandle, dvma, iotsb_num, entry, npages);
 349	iommu_tbl_range_free(tbl, dvma, npages, IOMMU_ERROR_CODE);
 350	order = get_order(size);
 351	if (order < 10)
 352		free_pages((unsigned long)cpu, order);
 353}
 354
 355static dma_addr_t dma_4v_map_phys(struct device *dev, phys_addr_t phys,
 356				  size_t sz, enum dma_data_direction direction,
 357				  unsigned long attrs)
 358{
 359	struct iommu *iommu;
 360	struct atu *atu;
 361	struct iommu_map_table *tbl;
 362	u64 mask;
 363	unsigned long flags, npages, oaddr;
 364	unsigned long i, prot;
 365	dma_addr_t bus_addr, ret;
 366	long entry;
 367
 368	if (unlikely(attrs & DMA_ATTR_MMIO))
 369		/*
 370		 * This check is included because older versions of the code
 371		 * lacked MMIO path support, and my ability to test this path
 372		 * is limited. However, from a software technical standpoint,
 373		 * there is no restriction, as the following code operates
 374		 * solely on physical addresses.
 375		 */
 376		goto bad;
 377
 378	iommu = dev->archdata.iommu;
 379	atu = iommu->atu;
 380
 381	if (unlikely(direction == DMA_NONE))
 382		goto bad;
 383
 384	oaddr = (unsigned long)(phys_to_virt(phys));
 385	npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
 386	npages >>= IO_PAGE_SHIFT;
 387
 388	mask = *dev->dma_mask;
 389	if (!iommu_use_atu(iommu, mask))
 390		tbl = &iommu->tbl;
 391	else
 392		tbl = &atu->tbl;
 393
 394	entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
 395				      (unsigned long)(-1), 0);
 396
 397	if (unlikely(entry == IOMMU_ERROR_CODE))
 398		goto bad;
 399
 400	bus_addr = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
 401	ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
 402	prot = HV_PCI_MAP_ATTR_READ;
 403	if (direction != DMA_TO_DEVICE)
 404		prot |= HV_PCI_MAP_ATTR_WRITE;
 405
 406	if (attrs & DMA_ATTR_WEAK_ORDERING)
 407		prot |= HV_PCI_MAP_ATTR_RELAXED_ORDER;
 408
 409	local_irq_save(flags);
 410
 411	iommu_batch_start(dev, prot, entry);
 412
 413	phys &= IO_PAGE_MASK;
 414
 415	for (i = 0; i < npages; i++, phys += IO_PAGE_SIZE) {
 416		long err = iommu_batch_add(phys, mask);
 417		if (unlikely(err < 0L))
 418			goto iommu_map_fail;
 419	}
 420	if (unlikely(iommu_batch_end(mask) < 0L))
 421		goto iommu_map_fail;
 422
 423	local_irq_restore(flags);
 424
 425	return ret;
 426
 427bad:
 428	if (printk_ratelimit())
 429		WARN_ON(1);
 430	return DMA_MAPPING_ERROR;
 431
 432iommu_map_fail:
 433	local_irq_restore(flags);
 434	iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
 435	return DMA_MAPPING_ERROR;
 436}
 437
 438static void dma_4v_unmap_phys(struct device *dev, dma_addr_t bus_addr,
 439			      size_t sz, enum dma_data_direction direction,
 440			      unsigned long attrs)
 441{
 442	struct pci_pbm_info *pbm;
 443	struct iommu *iommu;
 444	struct atu *atu;
 445	struct iommu_map_table *tbl;
 446	unsigned long npages;
 447	unsigned long iotsb_num;
 448	long entry;
 449	u32 devhandle;
 450
 451	if (unlikely(direction == DMA_NONE)) {
 452		if (printk_ratelimit())
 453			WARN_ON(1);
 454		return;
 455	}
 456
 457	iommu = dev->archdata.iommu;
 458	pbm = dev->archdata.host_controller;
 459	atu = iommu->atu;
 460	devhandle = pbm->devhandle;
 461
 462	npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
 463	npages >>= IO_PAGE_SHIFT;
 464	bus_addr &= IO_PAGE_MASK;
 465
 466	if (bus_addr <= DMA_BIT_MASK(32)) {
 467		iotsb_num = 0; /* we don't care for legacy iommu */
 468		tbl = &iommu->tbl;
 469	} else {
 470		iotsb_num = atu->iotsb->iotsb_num;
 471		tbl = &atu->tbl;
 472	}
 473	entry = (bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT;
 474	dma_4v_iommu_demap(dev, devhandle, bus_addr, iotsb_num, entry, npages);
 475	iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
 476}
 477
 478static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
 479			 int nelems, enum dma_data_direction direction,
 480			 unsigned long attrs)
 481{
 482	struct scatterlist *s, *outs, *segstart;
 483	unsigned long flags, handle, prot;
 484	dma_addr_t dma_next = 0, dma_addr;
 485	unsigned int max_seg_size;
 486	unsigned long seg_boundary_size;
 487	int outcount, incount, i;
 488	struct iommu *iommu;
 489	struct atu *atu;
 490	struct iommu_map_table *tbl;
 491	u64 mask;
 492	unsigned long base_shift;
 493	long err;
 494
 495	BUG_ON(direction == DMA_NONE);
 496
 497	iommu = dev->archdata.iommu;
 498	if (nelems == 0 || !iommu)
 499		return -EINVAL;
 500	atu = iommu->atu;
 501
 502	prot = HV_PCI_MAP_ATTR_READ;
 503	if (direction != DMA_TO_DEVICE)
 504		prot |= HV_PCI_MAP_ATTR_WRITE;
 505
 506	if (attrs & DMA_ATTR_WEAK_ORDERING)
 507		prot |= HV_PCI_MAP_ATTR_RELAXED_ORDER;
 508
 509	outs = s = segstart = &sglist[0];
 510	outcount = 1;
 511	incount = nelems;
 512	handle = 0;
 513
 514	/* Init first segment length for backout at failure */
 515	outs->dma_length = 0;
 516
 517	local_irq_save(flags);
 518
 519	iommu_batch_start(dev, prot, ~0UL);
 520
 521	max_seg_size = dma_get_max_seg_size(dev);
 522	seg_boundary_size = dma_get_seg_boundary_nr_pages(dev, IO_PAGE_SHIFT);
 523
 524	mask = *dev->dma_mask;
 525	if (!iommu_use_atu(iommu, mask))
 526		tbl = &iommu->tbl;
 527	else
 528		tbl = &atu->tbl;
 529
 530	base_shift = tbl->table_map_base >> IO_PAGE_SHIFT;
 531
 532	for_each_sg(sglist, s, nelems, i) {
 533		unsigned long paddr, npages, entry, out_entry = 0, slen;
 534
 535		slen = s->length;
 536		/* Sanity check */
 537		if (slen == 0) {
 538			dma_next = 0;
 539			continue;
 540		}
 541		/* Allocate iommu entries for that segment */
 542		paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
 543		npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
 544		entry = iommu_tbl_range_alloc(dev, tbl, npages,
 545					      &handle, (unsigned long)(-1), 0);
 546
 547		/* Handle failure */
 548		if (unlikely(entry == IOMMU_ERROR_CODE)) {
 549			pr_err_ratelimited("iommu_alloc failed, iommu %p paddr %lx npages %lx\n",
 550					   tbl, paddr, npages);
 551			goto iommu_map_failed;
 552		}
 553
 554		iommu_batch_new_entry(entry, mask);
 555
 556		/* Convert entry to a dma_addr_t */
 557		dma_addr = tbl->table_map_base + (entry << IO_PAGE_SHIFT);
 558		dma_addr |= (s->offset & ~IO_PAGE_MASK);
 559
 560		/* Insert into HW table */
 561		paddr &= IO_PAGE_MASK;
 562		while (npages--) {
 563			err = iommu_batch_add(paddr, mask);
 564			if (unlikely(err < 0L))
 565				goto iommu_map_failed;
 566			paddr += IO_PAGE_SIZE;
 567		}
 568
 569		/* If we are in an open segment, try merging */
 570		if (segstart != s) {
 571			/* We cannot merge if:
 572			 * - allocated dma_addr isn't contiguous to previous allocation
 573			 */
 574			if ((dma_addr != dma_next) ||
 575			    (outs->dma_length + s->length > max_seg_size) ||
 576			    (is_span_boundary(out_entry, base_shift,
 577					      seg_boundary_size, outs, s))) {
 578				/* Can't merge: create a new segment */
 579				segstart = s;
 580				outcount++;
 581				outs = sg_next(outs);
 582			} else {
 583				outs->dma_length += s->length;
 584			}
 585		}
 586
 587		if (segstart == s) {
 588			/* This is a new segment, fill entries */
 589			outs->dma_address = dma_addr;
 590			outs->dma_length = slen;
 591			out_entry = entry;
 592		}
 593
 594		/* Calculate next page pointer for contiguous check */
 595		dma_next = dma_addr + slen;
 596	}
 597
 598	err = iommu_batch_end(mask);
 599
 600	if (unlikely(err < 0L))
 601		goto iommu_map_failed;
 602
 603	local_irq_restore(flags);
 604
 605	if (outcount < incount) {
 606		outs = sg_next(outs);
 607		outs->dma_length = 0;
 608	}
 609
 610	return outcount;
 611
 612iommu_map_failed:
 613	for_each_sg(sglist, s, nelems, i) {
 614		if (s->dma_length != 0) {
 615			unsigned long vaddr, npages;
 616
 617			vaddr = s->dma_address & IO_PAGE_MASK;
 618			npages = iommu_num_pages(s->dma_address, s->dma_length,
 619						 IO_PAGE_SIZE);
 620			iommu_tbl_range_free(tbl, vaddr, npages,
 621					     IOMMU_ERROR_CODE);
 622			/* XXX demap? XXX */
 623			s->dma_length = 0;
 624		}
 625		if (s == outs)
 626			break;
 627	}
 628	local_irq_restore(flags);
 629
 630	return -EINVAL;
 631}
 632
 633static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
 634			    int nelems, enum dma_data_direction direction,
 635			    unsigned long attrs)
 636{
 637	struct pci_pbm_info *pbm;
 638	struct scatterlist *sg;
 639	struct iommu *iommu;
 640	struct atu *atu;
 641	unsigned long flags, entry;
 642	unsigned long iotsb_num;
 643	u32 devhandle;
 644
 645	BUG_ON(direction == DMA_NONE);
 646
 647	iommu = dev->archdata.iommu;
 648	pbm = dev->archdata.host_controller;
 649	atu = iommu->atu;
 650	devhandle = pbm->devhandle;
 651	
 652	local_irq_save(flags);
 653
 654	sg = sglist;
 655	while (nelems--) {
 656		dma_addr_t dma_handle = sg->dma_address;
 657		unsigned int len = sg->dma_length;
 658		unsigned long npages;
 659		struct iommu_map_table *tbl;
 660		unsigned long shift = IO_PAGE_SHIFT;
 661
 662		if (!len)
 663			break;
 664		npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
 665
 666		if (dma_handle <= DMA_BIT_MASK(32)) {
 667			iotsb_num = 0; /* we don't care for legacy iommu */
 668			tbl = &iommu->tbl;
 669		} else {
 670			iotsb_num = atu->iotsb->iotsb_num;
 671			tbl = &atu->tbl;
 672		}
 673		entry = ((dma_handle - tbl->table_map_base) >> shift);
 674		dma_4v_iommu_demap(dev, devhandle, dma_handle, iotsb_num,
 675				   entry, npages);
 676		iommu_tbl_range_free(tbl, dma_handle, npages,
 677				     IOMMU_ERROR_CODE);
 678		sg = sg_next(sg);
 679	}
 680
 681	local_irq_restore(flags);
 682}
 683
 684static int dma_4v_supported(struct device *dev, u64 device_mask)
 685{
 686	struct iommu *iommu = dev->archdata.iommu;
 687
 688	if (ali_sound_dma_hack(dev, device_mask))
 689		return 1;
 690	if (device_mask < iommu->dma_addr_mask)
 691		return 0;
 692	return 1;
 693}
 694
 695static const struct dma_map_ops sun4v_dma_ops = {
 696	.alloc				= dma_4v_alloc_coherent,
 697	.free				= dma_4v_free_coherent,
 698	.map_phys			= dma_4v_map_phys,
 699	.unmap_phys			= dma_4v_unmap_phys,
 700	.map_sg				= dma_4v_map_sg,
 701	.unmap_sg			= dma_4v_unmap_sg,
 702	.dma_supported			= dma_4v_supported,
 703};
 704
 705static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
 706{
 707	struct property *prop;
 708	struct device_node *dp;
 709
 710	dp = pbm->op->dev.of_node;
 711	prop = of_find_property(dp, "66mhz-capable", NULL);
 712	pbm->is_66mhz_capable = (prop != NULL);
 713	pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
 714
 715	/* XXX register error interrupt handlers XXX */
 716}
 717
 718static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
 719					    struct iommu_map_table *iommu)
 720{
 721	struct iommu_pool *pool;
 722	unsigned long i, pool_nr, cnt = 0;
 723	u32 devhandle;
 724
 725	devhandle = pbm->devhandle;
 726	for (pool_nr = 0; pool_nr < iommu->nr_pools; pool_nr++) {
 727		pool = &(iommu->pools[pool_nr]);
 728		for (i = pool->start; i <= pool->end; i++) {
 729			unsigned long ret, io_attrs, ra;
 730
 731			ret = pci_sun4v_iommu_getmap(devhandle,
 732						     HV_PCI_TSBID(0, i),
 733						     &io_attrs, &ra);
 734			if (ret == HV_EOK) {
 735				if (page_in_phys_avail(ra)) {
 736					pci_sun4v_iommu_demap(devhandle,
 737							      HV_PCI_TSBID(0,
 738							      i), 1);
 739				} else {
 740					cnt++;
 741					__set_bit(i, iommu->map);
 742				}
 743			}
 744		}
 745	}
 746	return cnt;
 747}
 748
 749static int pci_sun4v_atu_alloc_iotsb(struct pci_pbm_info *pbm)
 750{
 751	struct atu *atu = pbm->iommu->atu;
 752	struct atu_iotsb *iotsb;
 753	void *table;
 754	u64 table_size;
 755	u64 iotsb_num;
 756	unsigned long order;
 757	unsigned long err;
 758
 759	iotsb = kzalloc(sizeof(*iotsb), GFP_KERNEL);
 760	if (!iotsb) {
 761		err = -ENOMEM;
 762		goto out_err;
 763	}
 764	atu->iotsb = iotsb;
 765
 766	/* calculate size of IOTSB */
 767	table_size = (atu->size / IO_PAGE_SIZE) * 8;
 768	order = get_order(table_size);
 769	table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
 770	if (!table) {
 771		err = -ENOMEM;
 772		goto table_failed;
 773	}
 774	iotsb->table = table;
 775	iotsb->ra = __pa(table);
 776	iotsb->dvma_size = atu->size;
 777	iotsb->dvma_base = atu->base;
 778	iotsb->table_size = table_size;
 779	iotsb->page_size = IO_PAGE_SIZE;
 780
 781	/* configure and register IOTSB with HV */
 782	err = pci_sun4v_iotsb_conf(pbm->devhandle,
 783				   iotsb->ra,
 784				   iotsb->table_size,
 785				   iotsb->page_size,
 786				   iotsb->dvma_base,
 787				   &iotsb_num);
 788	if (err) {
 789		pr_err(PFX "pci_iotsb_conf failed error: %ld\n", err);
 790		goto iotsb_conf_failed;
 791	}
 792	iotsb->iotsb_num = iotsb_num;
 793
 794	err = dma_4v_iotsb_bind(pbm->devhandle, iotsb_num, pbm->pci_bus);
 795	if (err) {
 796		pr_err(PFX "pci_iotsb_bind failed error: %ld\n", err);
 797		goto iotsb_conf_failed;
 798	}
 799
 800	return 0;
 801
 802iotsb_conf_failed:
 803	free_pages((unsigned long)table, order);
 804table_failed:
 805	kfree(iotsb);
 806out_err:
 807	return err;
 808}
 809
 810static int pci_sun4v_atu_init(struct pci_pbm_info *pbm)
 811{
 812	struct atu *atu = pbm->iommu->atu;
 813	unsigned long err;
 814	const u64 *ranges;
 815	u64 map_size, num_iotte;
 816	u64 dma_mask;
 817	const u32 *page_size;
 818	int len;
 819
 820	ranges = of_get_property(pbm->op->dev.of_node, "iommu-address-ranges",
 821				 &len);
 822	if (!ranges) {
 823		pr_err(PFX "No iommu-address-ranges\n");
 824		return -EINVAL;
 825	}
 826
 827	page_size = of_get_property(pbm->op->dev.of_node, "iommu-pagesizes",
 828				    NULL);
 829	if (!page_size) {
 830		pr_err(PFX "No iommu-pagesizes\n");
 831		return -EINVAL;
 832	}
 833
 834	/* There are 4 iommu-address-ranges supported. Each range is pair of
 835	 * {base, size}. The ranges[0] and ranges[1] are 32bit address space
 836	 * while ranges[2] and ranges[3] are 64bit space.  We want to use 64bit
 837	 * address ranges to support 64bit addressing. Because 'size' for
 838	 * address ranges[2] and ranges[3] are same we can select either of
 839	 * ranges[2] or ranges[3] for mapping. However due to 'size' is too
 840	 * large for OS to allocate IOTSB we are using fix size 32G
 841	 * (ATU_64_SPACE_SIZE) which is more than enough for all PCIe devices
 842	 * to share.
 843	 */
 844	atu->ranges = (struct atu_ranges *)ranges;
 845	atu->base = atu->ranges[3].base;
 846	atu->size = ATU_64_SPACE_SIZE;
 847
 848	/* Create IOTSB */
 849	err = pci_sun4v_atu_alloc_iotsb(pbm);
 850	if (err) {
 851		pr_err(PFX "Error creating ATU IOTSB\n");
 852		return err;
 853	}
 854
 855	/* Create ATU iommu map.
 856	 * One bit represents one iotte in IOTSB table.
 857	 */
 858	dma_mask = (roundup_pow_of_two(atu->size) - 1UL);
 859	num_iotte = atu->size / IO_PAGE_SIZE;
 860	map_size = num_iotte / 8;
 861	atu->tbl.table_map_base = atu->base;
 862	atu->dma_addr_mask = dma_mask;
 863	atu->tbl.map = kzalloc(map_size, GFP_KERNEL);
 864	if (!atu->tbl.map)
 865		return -ENOMEM;
 866
 867	iommu_tbl_pool_init(&atu->tbl, num_iotte, IO_PAGE_SHIFT,
 868			    NULL, false /* no large_pool */,
 869			    0 /* default npools */,
 870			    false /* want span boundary checking */);
 871
 872	return 0;
 873}
 874
 875static int pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
 876{
 877	static const u32 vdma_default[] = { 0x80000000, 0x80000000 };
 878	struct iommu *iommu = pbm->iommu;
 879	unsigned long num_tsb_entries, sz;
 880	u32 dma_mask, dma_offset;
 881	const u32 *vdma;
 882
 883	vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
 884	if (!vdma)
 885		vdma = vdma_default;
 886
 887	if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
 888		printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n",
 889		       vdma[0], vdma[1]);
 890		return -EINVAL;
 891	}
 892
 893	dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
 894	num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
 895
 896	dma_offset = vdma[0];
 897
 898	/* Setup initial software IOMMU state. */
 899	spin_lock_init(&iommu->lock);
 900	iommu->ctx_lowest_free = 1;
 901	iommu->tbl.table_map_base = dma_offset;
 902	iommu->dma_addr_mask = dma_mask;
 903
 904	/* Allocate and initialize the free area map.  */
 905	sz = (num_tsb_entries + 7) / 8;
 906	sz = (sz + 7UL) & ~7UL;
 907	iommu->tbl.map = kzalloc(sz, GFP_KERNEL);
 908	if (!iommu->tbl.map) {
 909		printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n");
 910		return -ENOMEM;
 911	}
 912	iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT,
 913			    NULL, false /* no large_pool */,
 914			    0 /* default npools */,
 915			    false /* want span boundary checking */);
 916	sz = probe_existing_entries(pbm, &iommu->tbl);
 917	if (sz)
 918		printk("%s: Imported %lu TSB entries from OBP\n",
 919		       pbm->name, sz);
 920
 921	return 0;
 922}
 923
 924#ifdef CONFIG_PCI_MSI
 925struct pci_sun4v_msiq_entry {
 926	u64		version_type;
 927#define MSIQ_VERSION_MASK		0xffffffff00000000UL
 928#define MSIQ_VERSION_SHIFT		32
 929#define MSIQ_TYPE_MASK			0x00000000000000ffUL
 930#define MSIQ_TYPE_SHIFT			0
 931#define MSIQ_TYPE_NONE			0x00
 932#define MSIQ_TYPE_MSG			0x01
 933#define MSIQ_TYPE_MSI32			0x02
 934#define MSIQ_TYPE_MSI64			0x03
 935#define MSIQ_TYPE_INTX			0x08
 936#define MSIQ_TYPE_NONE2			0xff
 937
 938	u64		intx_sysino;
 939	u64		reserved1;
 940	u64		stick;
 941	u64		req_id;  /* bus/device/func */
 942#define MSIQ_REQID_BUS_MASK		0xff00UL
 943#define MSIQ_REQID_BUS_SHIFT		8
 944#define MSIQ_REQID_DEVICE_MASK		0x00f8UL
 945#define MSIQ_REQID_DEVICE_SHIFT		3
 946#define MSIQ_REQID_FUNC_MASK		0x0007UL
 947#define MSIQ_REQID_FUNC_SHIFT		0
 948
 949	u64		msi_address;
 950
 951	/* The format of this value is message type dependent.
 952	 * For MSI bits 15:0 are the data from the MSI packet.
 953	 * For MSI-X bits 31:0 are the data from the MSI packet.
 954	 * For MSG, the message code and message routing code where:
 955	 * 	bits 39:32 is the bus/device/fn of the msg target-id
 956	 *	bits 18:16 is the message routing code
 957	 *	bits 7:0 is the message code
 958	 * For INTx the low order 2-bits are:
 959	 *	00 - INTA
 960	 *	01 - INTB
 961	 *	10 - INTC
 962	 *	11 - INTD
 963	 */
 964	u64		msi_data;
 965
 966	u64		reserved2;
 967};
 968
 969static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
 970			      unsigned long *head)
 971{
 972	unsigned long err, limit;
 973
 974	err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head);
 975	if (unlikely(err))
 976		return -ENXIO;
 977
 978	limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
 979	if (unlikely(*head >= limit))
 980		return -EFBIG;
 981
 982	return 0;
 983}
 984
 985static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm,
 986				 unsigned long msiqid, unsigned long *head,
 987				 unsigned long *msi)
 988{
 989	struct pci_sun4v_msiq_entry *ep;
 990	unsigned long err, type;
 991
 992	/* Note: void pointer arithmetic, 'head' is a byte offset  */
 993	ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
 994				 (pbm->msiq_ent_count *
 995				  sizeof(struct pci_sun4v_msiq_entry))) +
 996	      *head);
 997
 998	if ((ep->version_type & MSIQ_TYPE_MASK) == 0)
 999		return 0;
1000
1001	type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
1002	if (unlikely(type != MSIQ_TYPE_MSI32 &&
1003		     type != MSIQ_TYPE_MSI64))
1004		return -EINVAL;
1005
1006	*msi = ep->msi_data;
1007
1008	err = pci_sun4v_msi_setstate(pbm->devhandle,
1009				     ep->msi_data /* msi_num */,
1010				     HV_MSISTATE_IDLE);
1011	if (unlikely(err))
1012		return -ENXIO;
1013
1014	/* Clear the entry.  */
1015	ep->version_type &= ~MSIQ_TYPE_MASK;
1016
1017	(*head) += sizeof(struct pci_sun4v_msiq_entry);
1018	if (*head >=
1019	    (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry)))
1020		*head = 0;
1021
1022	return 1;
1023}
1024
1025static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
1026			      unsigned long head)
1027{
1028	unsigned long err;
1029
1030	err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
1031	if (unlikely(err))
1032		return -EINVAL;
1033
1034	return 0;
1035}
1036
1037static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
1038			       unsigned long msi, int is_msi64)
1039{
1040	if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid,
1041				  (is_msi64 ?
1042				   HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
1043		return -ENXIO;
1044	if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE))
1045		return -ENXIO;
1046	if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID))
1047		return -ENXIO;
1048	return 0;
1049}
1050
1051static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
1052{
1053	unsigned long err, msiqid;
1054
1055	err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid);
1056	if (err)
1057		return -ENXIO;
1058
1059	pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID);
1060
1061	return 0;
1062}
1063
1064static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm)
1065{
1066	unsigned long q_size, alloc_size, pages, order;
1067	int i;
1068
1069	q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
1070	alloc_size = (pbm->msiq_num * q_size);
1071	order = get_order(alloc_size);
1072	pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
1073	if (pages == 0UL) {
1074		printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
1075		       order);
1076		return -ENOMEM;
1077	}
1078	memset((char *)pages, 0, PAGE_SIZE << order);
1079	pbm->msi_queues = (void *) pages;
1080
1081	for (i = 0; i < pbm->msiq_num; i++) {
1082		unsigned long err, base = __pa(pages + (i * q_size));
1083		unsigned long ret1, ret2;
1084
1085		err = pci_sun4v_msiq_conf(pbm->devhandle,
1086					  pbm->msiq_first + i,
1087					  base, pbm->msiq_ent_count);
1088		if (err) {
1089			printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
1090			       err);
1091			goto h_error;
1092		}
1093
1094		err = pci_sun4v_msiq_info(pbm->devhandle,
1095					  pbm->msiq_first + i,
1096					  &ret1, &ret2);
1097		if (err) {
1098			printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
1099			       err);
1100			goto h_error;
1101		}
1102		if (ret1 != base || ret2 != pbm->msiq_ent_count) {
1103			printk(KERN_ERR "MSI: Bogus qconf "
1104			       "expected[%lx:%x] got[%lx:%lx]\n",
1105			       base, pbm->msiq_ent_count,
1106			       ret1, ret2);
1107			goto h_error;
1108		}
1109	}
1110
1111	return 0;
1112
1113h_error:
1114	free_pages(pages, order);
1115	return -EINVAL;
1116}
1117
1118static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm)
1119{
1120	unsigned long q_size, alloc_size, pages, order;
1121	int i;
1122
1123	for (i = 0; i < pbm->msiq_num; i++) {
1124		unsigned long msiqid = pbm->msiq_first + i;
1125
1126		(void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0);
1127	}
1128
1129	q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
1130	alloc_size = (pbm->msiq_num * q_size);
1131	order = get_order(alloc_size);
1132
1133	pages = (unsigned long) pbm->msi_queues;
1134
1135	free_pages(pages, order);
1136
1137	pbm->msi_queues = NULL;
1138}
1139
1140static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm,
1141				    unsigned long msiqid,
1142				    unsigned long devino)
1143{
1144	unsigned int irq = sun4v_build_irq(pbm->devhandle, devino);
1145
1146	if (!irq)
1147		return -ENOMEM;
1148
1149	if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
1150		return -EINVAL;
1151	if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
1152		return -EINVAL;
1153
1154	return irq;
1155}
1156
1157static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = {
1158	.get_head	=	pci_sun4v_get_head,
1159	.dequeue_msi	=	pci_sun4v_dequeue_msi,
1160	.set_head	=	pci_sun4v_set_head,
1161	.msi_setup	=	pci_sun4v_msi_setup,
1162	.msi_teardown	=	pci_sun4v_msi_teardown,
1163	.msiq_alloc	=	pci_sun4v_msiq_alloc,
1164	.msiq_free	=	pci_sun4v_msiq_free,
1165	.msiq_build_irq	=	pci_sun4v_msiq_build_irq,
1166};
1167
1168static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1169{
1170	sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops);
1171}
1172#else /* CONFIG_PCI_MSI */
1173static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1174{
1175}
1176#endif /* !(CONFIG_PCI_MSI) */
1177
1178static int pci_sun4v_pbm_init(struct pci_pbm_info *pbm,
1179			      struct platform_device *op, u32 devhandle)
1180{
1181	struct device_node *dp = op->dev.of_node;
1182	int err;
1183
1184	pbm->numa_node = of_node_to_nid(dp);
1185
1186	pbm->pci_ops = &sun4v_pci_ops;
1187	pbm->config_space_reg_bits = 12;
1188
1189	pbm->index = pci_num_pbms++;
1190
1191	pbm->op = op;
1192
1193	pbm->devhandle = devhandle;
1194
1195	pbm->name = dp->full_name;
1196
1197	printk("%s: SUN4V PCI Bus Module\n", pbm->name);
1198	printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node);
1199
1200	pci_determine_mem_io_space(pbm);
1201
1202	pci_get_pbm_props(pbm);
1203
1204	err = pci_sun4v_iommu_init(pbm);
1205	if (err)
1206		return err;
1207
1208	pci_sun4v_msi_init(pbm);
1209
1210	pci_sun4v_scan_bus(pbm, &op->dev);
1211
1212	/* if atu_init fails its not complete failure.
1213	 * we can still continue using legacy iommu.
1214	 */
1215	if (pbm->iommu->atu) {
1216		err = pci_sun4v_atu_init(pbm);
1217		if (err) {
1218			kfree(pbm->iommu->atu);
1219			pbm->iommu->atu = NULL;
1220			pr_err(PFX "ATU init failed, err=%d\n", err);
1221		}
1222	}
1223
1224	pbm->next = pci_pbm_root;
1225	pci_pbm_root = pbm;
1226
1227	return 0;
1228}
1229
1230static int pci_sun4v_probe(struct platform_device *op)
1231{
1232	const struct linux_prom64_registers *regs;
1233	static int hvapi_negotiated = 0;
1234	struct pci_pbm_info *pbm;
1235	struct device_node *dp;
1236	struct iommu *iommu;
1237	struct atu *atu;
1238	u32 devhandle;
1239	int i, err = -ENODEV;
1240	static bool hv_atu = true;
1241
1242	dp = op->dev.of_node;
1243
1244	if (!hvapi_negotiated++) {
1245		for (i = 0; i < ARRAY_SIZE(vpci_versions); i++) {
1246			vpci_major = vpci_versions[i].major;
1247			vpci_minor = vpci_versions[i].minor;
1248
1249			err = sun4v_hvapi_register(HV_GRP_PCI, vpci_major,
1250						   &vpci_minor);
1251			if (!err)
1252				break;
1253		}
1254
1255		if (err) {
1256			pr_err(PFX "Could not register hvapi, err=%d\n", err);
1257			return err;
1258		}
1259		pr_info(PFX "Registered hvapi major[%lu] minor[%lu]\n",
1260			vpci_major, vpci_minor);
1261
1262		err = sun4v_hvapi_register(HV_GRP_ATU, vatu_major, &vatu_minor);
1263		if (err) {
1264			/* don't return an error if we fail to register the
1265			 * ATU group, but ATU hcalls won't be available.
1266			 */
1267			hv_atu = false;
1268		} else {
1269			pr_info(PFX "Registered hvapi ATU major[%lu] minor[%lu]\n",
1270				vatu_major, vatu_minor);
1271		}
1272
1273		dma_ops = &sun4v_dma_ops;
1274	}
1275
1276	regs = of_get_property(dp, "reg", NULL);
1277	err = -ENODEV;
1278	if (!regs) {
1279		printk(KERN_ERR PFX "Could not find config registers\n");
1280		goto out_err;
1281	}
1282	devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1283
1284	err = -ENOMEM;
1285	if (!iommu_batch_initialized) {
1286		for_each_possible_cpu(i) {
1287			unsigned long page = get_zeroed_page(GFP_KERNEL);
1288
1289			if (!page)
1290				goto out_err;
1291
1292			per_cpu(iommu_batch, i).pglist = (u64 *) page;
1293		}
1294		iommu_batch_initialized = 1;
1295	}
1296
1297	pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
1298	if (!pbm) {
1299		printk(KERN_ERR PFX "Could not allocate pci_pbm_info\n");
1300		goto out_err;
1301	}
1302
1303	iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
1304	if (!iommu) {
1305		printk(KERN_ERR PFX "Could not allocate pbm iommu\n");
1306		goto out_free_controller;
1307	}
1308
1309	pbm->iommu = iommu;
1310	iommu->atu = NULL;
1311	if (hv_atu) {
1312		atu = kzalloc(sizeof(*atu), GFP_KERNEL);
1313		if (!atu)
1314			pr_err(PFX "Could not allocate atu\n");
1315		else
1316			iommu->atu = atu;
1317	}
1318
1319	err = pci_sun4v_pbm_init(pbm, op, devhandle);
1320	if (err)
1321		goto out_free_iommu;
1322
1323	dev_set_drvdata(&op->dev, pbm);
1324
1325	return 0;
1326
1327out_free_iommu:
1328	kfree(iommu->atu);
1329	kfree(pbm->iommu);
1330
1331out_free_controller:
1332	kfree(pbm);
1333
1334out_err:
1335	return err;
1336}
1337
1338static const struct of_device_id pci_sun4v_match[] = {
1339	{
1340		.name = "pci",
1341		.compatible = "SUNW,sun4v-pci",
1342	},
1343	{},
1344};
1345
1346static struct platform_driver pci_sun4v_driver = {
1347	.driver = {
1348		.name = DRIVER_NAME,
1349		.of_match_table = pci_sun4v_match,
1350	},
1351	.probe		= pci_sun4v_probe,
1352};
1353
1354static int __init pci_sun4v_init(void)
1355{
1356	return platform_driver_register(&pci_sun4v_driver);
1357}
1358
1359subsys_initcall(pci_sun4v_init);