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pci.c
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linux-6.19.14/arch/sparc/kernel/pci.c
1// SPDX-License-Identifier: GPL-2.0 2/* pci.c: UltraSparc PCI controller support. 3 * 4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) 5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) 6 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) 7 * 8 * OF tree based PCI bus probing taken from the PowerPC port 9 * with minor modifications, see there for credits. 10 */ 11 12#include <linux/export.h> 13#include <linux/kernel.h> 14#include <linux/string.h> 15#include <linux/sched.h> 16#include <linux/capability.h> 17#include <linux/errno.h> 18#include <linux/pci.h> 19#include <linux/msi.h> 20#include <linux/irq.h> 21#include <linux/init.h> 22#include <linux/of.h> 23#include <linux/of_platform.h> 24#include <linux/pgtable.h> 25#include <linux/platform_device.h> 26 27#include <linux/uaccess.h> 28#include <asm/irq.h> 29#include <asm/prom.h> 30#include <asm/apb.h> 31 32#include "pci_impl.h" 33#include "kernel.h" 34 35/* List of all PCI controllers found in the system. */ 36struct pci_pbm_info *pci_pbm_root = NULL; 37 38/* Each PBM found gets a unique index. */ 39int pci_num_pbms = 0; 40 41volatile int pci_poke_in_progress; 42volatile int pci_poke_cpu = -1; 43volatile int pci_poke_faulted; 44 45static DEFINE_SPINLOCK(pci_poke_lock); 46 47void pci_config_read8(u8 *addr, u8 *ret) 48{ 49 unsigned long flags; 50 u8 byte; 51 52 spin_lock_irqsave(&pci_poke_lock, flags); 53 pci_poke_cpu = smp_processor_id(); 54 pci_poke_in_progress = 1; 55 pci_poke_faulted = 0; 56 __asm__ __volatile__("membar #Sync\n\t" 57 "lduba [%1] %2, %0\n\t" 58 "membar #Sync" 59 : "=r" (byte) 60 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 61 : "memory"); 62 pci_poke_in_progress = 0; 63 pci_poke_cpu = -1; 64 if (!pci_poke_faulted) 65 *ret = byte; 66 spin_unlock_irqrestore(&pci_poke_lock, flags); 67} 68 69void pci_config_read16(u16 *addr, u16 *ret) 70{ 71 unsigned long flags; 72 u16 word; 73 74 spin_lock_irqsave(&pci_poke_lock, flags); 75 pci_poke_cpu = smp_processor_id(); 76 pci_poke_in_progress = 1; 77 pci_poke_faulted = 0; 78 __asm__ __volatile__("membar #Sync\n\t" 79 "lduha [%1] %2, %0\n\t" 80 "membar #Sync" 81 : "=r" (word) 82 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 83 : "memory"); 84 pci_poke_in_progress = 0; 85 pci_poke_cpu = -1; 86 if (!pci_poke_faulted) 87 *ret = word; 88 spin_unlock_irqrestore(&pci_poke_lock, flags); 89} 90 91void pci_config_read32(u32 *addr, u32 *ret) 92{ 93 unsigned long flags; 94 u32 dword; 95 96 spin_lock_irqsave(&pci_poke_lock, flags); 97 pci_poke_cpu = smp_processor_id(); 98 pci_poke_in_progress = 1; 99 pci_poke_faulted = 0; 100 __asm__ __volatile__("membar #Sync\n\t" 101 "lduwa [%1] %2, %0\n\t" 102 "membar #Sync" 103 : "=r" (dword) 104 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 105 : "memory"); 106 pci_poke_in_progress = 0; 107 pci_poke_cpu = -1; 108 if (!pci_poke_faulted) 109 *ret = dword; 110 spin_unlock_irqrestore(&pci_poke_lock, flags); 111} 112 113void pci_config_write8(u8 *addr, u8 val) 114{ 115 unsigned long flags; 116 117 spin_lock_irqsave(&pci_poke_lock, flags); 118 pci_poke_cpu = smp_processor_id(); 119 pci_poke_in_progress = 1; 120 pci_poke_faulted = 0; 121 __asm__ __volatile__("membar #Sync\n\t" 122 "stba %0, [%1] %2\n\t" 123 "membar #Sync" 124 : /* no outputs */ 125 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 126 : "memory"); 127 pci_poke_in_progress = 0; 128 pci_poke_cpu = -1; 129 spin_unlock_irqrestore(&pci_poke_lock, flags); 130} 131 132void pci_config_write16(u16 *addr, u16 val) 133{ 134 unsigned long flags; 135 136 spin_lock_irqsave(&pci_poke_lock, flags); 137 pci_poke_cpu = smp_processor_id(); 138 pci_poke_in_progress = 1; 139 pci_poke_faulted = 0; 140 __asm__ __volatile__("membar #Sync\n\t" 141 "stha %0, [%1] %2\n\t" 142 "membar #Sync" 143 : /* no outputs */ 144 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 145 : "memory"); 146 pci_poke_in_progress = 0; 147 pci_poke_cpu = -1; 148 spin_unlock_irqrestore(&pci_poke_lock, flags); 149} 150 151void pci_config_write32(u32 *addr, u32 val) 152{ 153 unsigned long flags; 154 155 spin_lock_irqsave(&pci_poke_lock, flags); 156 pci_poke_cpu = smp_processor_id(); 157 pci_poke_in_progress = 1; 158 pci_poke_faulted = 0; 159 __asm__ __volatile__("membar #Sync\n\t" 160 "stwa %0, [%1] %2\n\t" 161 "membar #Sync" 162 : /* no outputs */ 163 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 164 : "memory"); 165 pci_poke_in_progress = 0; 166 pci_poke_cpu = -1; 167 spin_unlock_irqrestore(&pci_poke_lock, flags); 168} 169 170static int ofpci_verbose; 171 172static int __init ofpci_debug(char *str) 173{ 174 int val = 0; 175 176 get_option(&str, &val); 177 if (val) 178 ofpci_verbose = 1; 179 return 1; 180} 181 182__setup("ofpci_debug=", ofpci_debug); 183 184static void of_fixup_pci_pref(struct pci_dev *dev, int index, 185 struct resource *res) 186{ 187 struct pci_bus_region region; 188 189 if (!(res->flags & IORESOURCE_MEM_64)) 190 return; 191 192 if (!resource_size(res)) 193 return; 194 195 pcibios_resource_to_bus(dev->bus, ®ion, res); 196 if (region.end <= ~((u32)0)) 197 return; 198 199 if (!(res->flags & IORESOURCE_PREFETCH)) { 200 res->flags |= IORESOURCE_PREFETCH; 201 pci_info(dev, "reg 0x%x: fixup: pref added to 64-bit resource\n", 202 index); 203 } 204} 205 206static unsigned long pci_parse_of_flags(u32 addr0) 207{ 208 unsigned long flags = 0; 209 210 if (addr0 & 0x02000000) { 211 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; 212 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; 213 if (addr0 & 0x01000000) 214 flags |= IORESOURCE_MEM_64 215 | PCI_BASE_ADDRESS_MEM_TYPE_64; 216 if (addr0 & 0x40000000) 217 flags |= IORESOURCE_PREFETCH 218 | PCI_BASE_ADDRESS_MEM_PREFETCH; 219 } else if (addr0 & 0x01000000) 220 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; 221 return flags; 222} 223 224/* The of_device layer has translated all of the assigned-address properties 225 * into physical address resources, we only have to figure out the register 226 * mapping. 227 */ 228static void pci_parse_of_addrs(struct platform_device *op, 229 struct device_node *node, 230 struct pci_dev *dev) 231{ 232 struct resource *op_res; 233 const u32 *addrs; 234 int proplen; 235 236 addrs = of_get_property(node, "assigned-addresses", &proplen); 237 if (!addrs) 238 return; 239 if (ofpci_verbose) 240 pci_info(dev, " parse addresses (%d bytes) @ %p\n", 241 proplen, addrs); 242 op_res = &op->resource[0]; 243 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) { 244 struct resource *res; 245 unsigned long flags; 246 int i; 247 248 flags = pci_parse_of_flags(addrs[0]); 249 if (!flags) 250 continue; 251 i = addrs[0] & 0xff; 252 if (ofpci_verbose) 253 pci_info(dev, " start: %llx, end: %llx, i: %x\n", 254 op_res->start, op_res->end, i); 255 256 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { 257 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; 258 } else if (i == dev->rom_base_reg) { 259 res = &dev->resource[PCI_ROM_RESOURCE]; 260 flags |= IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 261 } else { 262 pci_err(dev, "bad cfg reg num 0x%x\n", i); 263 continue; 264 } 265 res->start = op_res->start; 266 res->end = op_res->end; 267 res->flags = flags; 268 res->name = pci_name(dev); 269 of_fixup_pci_pref(dev, i, res); 270 271 pci_info(dev, "reg 0x%x: %pR\n", i, res); 272 } 273} 274 275static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu, 276 void *stc, void *host_controller, 277 struct platform_device *op, 278 int numa_node) 279{ 280 sd->iommu = iommu; 281 sd->stc = stc; 282 sd->host_controller = host_controller; 283 sd->op = op; 284 sd->numa_node = numa_node; 285} 286 287static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, 288 struct device_node *node, 289 struct pci_bus *bus, int devfn) 290{ 291 struct dev_archdata *sd; 292 struct platform_device *op; 293 struct pci_dev *dev; 294 u32 class; 295 296 dev = pci_alloc_dev(bus); 297 if (!dev) 298 return NULL; 299 300 op = of_find_device_by_node(node); 301 sd = &dev->dev.archdata; 302 pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op, 303 pbm->numa_node); 304 sd = &op->dev.archdata; 305 sd->iommu = pbm->iommu; 306 sd->stc = &pbm->stc; 307 sd->numa_node = pbm->numa_node; 308 309 if (of_node_name_eq(node, "ebus")) 310 of_propagate_archdata(op); 311 312 if (ofpci_verbose) 313 pci_info(bus," create device, devfn: %x, type: %s\n", 314 devfn, of_node_get_device_type(node)); 315 316 dev->sysdata = node; 317 dev->dev.parent = bus->bridge; 318 dev->dev.bus = &pci_bus_type; 319 dev->dev.of_node = of_node_get(node); 320 dev->devfn = devfn; 321 dev->multifunction = 0; /* maybe a lie? */ 322 set_pcie_port_type(dev); 323 324 pci_dev_assign_slot(dev); 325 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff); 326 dev->device = of_getintprop_default(node, "device-id", 0xffff); 327 dev->subsystem_vendor = 328 of_getintprop_default(node, "subsystem-vendor-id", 0); 329 dev->subsystem_device = 330 of_getintprop_default(node, "subsystem-id", 0); 331 332 dev->cfg_size = pci_cfg_space_size(dev); 333 334 /* We can't actually use the firmware value, we have 335 * to read what is in the register right now. One 336 * reason is that in the case of IDE interfaces the 337 * firmware can sample the value before the IDE 338 * interface is programmed into native mode. 339 */ 340 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 341 dev->class = class >> 8; 342 dev->revision = class & 0xff; 343 344 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), 345 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); 346 347 /* I have seen IDE devices which will not respond to 348 * the bmdma simplex check reads if bus mastering is 349 * disabled. 350 */ 351 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) 352 pci_set_master(dev); 353 354 dev->current_state = PCI_UNKNOWN; /* unknown power state */ 355 dev->error_state = pci_channel_io_normal; 356 dev->dma_mask = 0xffffffff; 357 358 if (of_node_name_eq(node, "pci")) { 359 /* a PCI-PCI bridge */ 360 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; 361 dev->rom_base_reg = PCI_ROM_ADDRESS1; 362 } else if (of_node_is_type(node, "cardbus")) { 363 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; 364 } else { 365 dev->hdr_type = PCI_HEADER_TYPE_NORMAL; 366 dev->rom_base_reg = PCI_ROM_ADDRESS; 367 368 dev->irq = sd->op->archdata.irqs[0]; 369 if (dev->irq == 0xffffffff) 370 dev->irq = PCI_IRQ_NONE; 371 } 372 373 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n", 374 dev->vendor, dev->device, dev->hdr_type, dev->class); 375 376 pci_parse_of_addrs(sd->op, node, dev); 377 378 if (ofpci_verbose) 379 pci_info(dev, " adding to system ...\n"); 380 381 pci_device_add(dev, bus); 382 383 return dev; 384} 385 386static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p) 387{ 388 u32 idx, first, last; 389 390 first = 8; 391 last = 0; 392 for (idx = 0; idx < 8; idx++) { 393 if ((map & (1 << idx)) != 0) { 394 if (first > idx) 395 first = idx; 396 if (last < idx) 397 last = idx; 398 } 399 } 400 401 *first_p = first; 402 *last_p = last; 403} 404 405/* Cook up fake bus resources for SUNW,simba PCI bridges which lack 406 * a proper 'ranges' property. 407 */ 408static void apb_fake_ranges(struct pci_dev *dev, 409 struct pci_bus *bus, 410 struct pci_pbm_info *pbm) 411{ 412 struct pci_bus_region region; 413 struct resource *res; 414 u32 first, last; 415 u8 map; 416 417 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map); 418 apb_calc_first_last(map, &first, &last); 419 res = bus->resource[0]; 420 res->flags = IORESOURCE_IO; 421 region.start = (first << 21); 422 region.end = (last << 21) + ((1 << 21) - 1); 423 pcibios_bus_to_resource(dev->bus, res, ®ion); 424 425 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map); 426 apb_calc_first_last(map, &first, &last); 427 res = bus->resource[1]; 428 res->flags = IORESOURCE_MEM; 429 region.start = (first << 29); 430 region.end = (last << 29) + ((1 << 29) - 1); 431 pcibios_bus_to_resource(dev->bus, res, ®ion); 432} 433 434static void pci_of_scan_bus(struct pci_pbm_info *pbm, 435 struct device_node *node, 436 struct pci_bus *bus); 437 438#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) 439 440static void of_scan_pci_bridge(struct pci_pbm_info *pbm, 441 struct device_node *node, 442 struct pci_dev *dev) 443{ 444 struct pci_bus *bus; 445 const u32 *busrange, *ranges; 446 int len, i, simba; 447 struct pci_bus_region region; 448 struct resource *res; 449 unsigned int flags; 450 u64 size; 451 452 if (ofpci_verbose) 453 pci_info(dev, "of_scan_pci_bridge(%pOF)\n", node); 454 455 /* parse bus-range property */ 456 busrange = of_get_property(node, "bus-range", &len); 457 if (busrange == NULL || len != 8) { 458 pci_info(dev, "Can't get bus-range for PCI-PCI bridge %pOF\n", 459 node); 460 return; 461 } 462 463 if (ofpci_verbose) 464 pci_info(dev, " Bridge bus range [%u --> %u]\n", 465 busrange[0], busrange[1]); 466 467 ranges = of_get_property(node, "ranges", &len); 468 simba = 0; 469 if (ranges == NULL) { 470 const char *model = of_get_property(node, "model", NULL); 471 if (model && !strcmp(model, "SUNW,simba")) 472 simba = 1; 473 } 474 475 bus = pci_add_new_bus(dev->bus, dev, busrange[0]); 476 if (!bus) { 477 pci_err(dev, "Failed to create pci bus for %pOF\n", 478 node); 479 return; 480 } 481 482 bus->primary = dev->bus->number; 483 pci_bus_insert_busn_res(bus, busrange[0], busrange[1]); 484 bus->bridge_ctl = 0; 485 486 if (ofpci_verbose) 487 pci_info(dev, " Bridge ranges[%p] simba[%d]\n", 488 ranges, simba); 489 490 /* parse ranges property, or cook one up by hand for Simba */ 491 /* PCI #address-cells == 3 and #size-cells == 2 always */ 492 res = &dev->resource[PCI_BRIDGE_RESOURCES]; 493 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { 494 res->flags = 0; 495 bus->resource[i] = res; 496 ++res; 497 } 498 if (simba) { 499 apb_fake_ranges(dev, bus, pbm); 500 goto after_ranges; 501 } else if (ranges == NULL) { 502 pci_read_bridge_bases(bus); 503 goto after_ranges; 504 } 505 i = 1; 506 for (; len >= 32; len -= 32, ranges += 8) { 507 u64 start; 508 509 if (ofpci_verbose) 510 pci_info(dev, " RAW Range[%08x:%08x:%08x:%08x:%08x:%08x:" 511 "%08x:%08x]\n", 512 ranges[0], ranges[1], ranges[2], ranges[3], 513 ranges[4], ranges[5], ranges[6], ranges[7]); 514 515 flags = pci_parse_of_flags(ranges[0]); 516 size = GET_64BIT(ranges, 6); 517 if (flags == 0 || size == 0) 518 continue; 519 520 /* On PCI-Express systems, PCI bridges that have no devices downstream 521 * have a bogus size value where the first 32-bit cell is 0xffffffff. 522 * This results in a bogus range where start + size overflows. 523 * 524 * Just skip these otherwise the kernel will complain when the resource 525 * tries to be claimed. 526 */ 527 if (size >> 32 == 0xffffffff) 528 continue; 529 530 if (flags & IORESOURCE_IO) { 531 res = bus->resource[0]; 532 if (res->flags) { 533 pci_err(dev, "ignoring extra I/O range" 534 " for bridge %pOF\n", node); 535 continue; 536 } 537 } else { 538 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { 539 pci_err(dev, "too many memory ranges" 540 " for bridge %pOF\n", node); 541 continue; 542 } 543 res = bus->resource[i]; 544 ++i; 545 } 546 547 res->flags = flags; 548 region.start = start = GET_64BIT(ranges, 1); 549 region.end = region.start + size - 1; 550 551 if (ofpci_verbose) 552 pci_info(dev, " Using flags[%08x] start[%016llx] size[%016llx]\n", 553 flags, start, size); 554 555 pcibios_bus_to_resource(dev->bus, res, ®ion); 556 } 557after_ranges: 558 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), 559 bus->number); 560 if (ofpci_verbose) 561 pci_info(dev, " bus name: %s\n", bus->name); 562 563 pci_of_scan_bus(pbm, node, bus); 564} 565 566static void pci_of_scan_bus(struct pci_pbm_info *pbm, 567 struct device_node *node, 568 struct pci_bus *bus) 569{ 570 struct device_node *child; 571 const u32 *reg; 572 int reglen, devfn, prev_devfn; 573 struct pci_dev *dev; 574 575 if (ofpci_verbose) 576 pci_info(bus, "scan_bus[%pOF] bus no %d\n", 577 node, bus->number); 578 579 prev_devfn = -1; 580 for_each_child_of_node(node, child) { 581 if (ofpci_verbose) 582 pci_info(bus, " * %pOF\n", child); 583 reg = of_get_property(child, "reg", ®len); 584 if (reg == NULL || reglen < 20) 585 continue; 586 587 devfn = (reg[0] >> 8) & 0xff; 588 589 /* This is a workaround for some device trees 590 * which list PCI devices twice. On the V100 591 * for example, device number 3 is listed twice. 592 * Once as "pm" and once again as "lomp". 593 */ 594 if (devfn == prev_devfn) 595 continue; 596 prev_devfn = devfn; 597 598 /* create a new pci_dev for this device */ 599 dev = of_create_pci_dev(pbm, child, bus, devfn); 600 if (!dev) 601 continue; 602 if (ofpci_verbose) 603 pci_info(dev, "dev header type: %x\n", dev->hdr_type); 604 605 if (pci_is_bridge(dev)) 606 of_scan_pci_bridge(pbm, child, dev); 607 } 608} 609 610static ssize_t 611show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf) 612{ 613 struct pci_dev *pdev; 614 struct device_node *dp; 615 616 pdev = to_pci_dev(dev); 617 dp = pdev->dev.of_node; 618 619 return scnprintf(buf, PAGE_SIZE, "%pOF\n", dp); 620} 621 622static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL); 623 624static void pci_bus_register_of_sysfs(struct pci_bus *bus) 625{ 626 struct pci_dev *dev; 627 struct pci_bus *child_bus; 628 int err; 629 630 list_for_each_entry(dev, &bus->devices, bus_list) { 631 /* we don't really care if we can create this file or 632 * not, but we need to assign the result of the call 633 * or the world will fall under alien invasion and 634 * everybody will be frozen on a spaceship ready to be 635 * eaten on alpha centauri by some green and jelly 636 * humanoid. 637 */ 638 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr); 639 (void) err; 640 } 641 list_for_each_entry(child_bus, &bus->children, node) 642 pci_bus_register_of_sysfs(child_bus); 643} 644 645static void pci_claim_legacy_resources(struct pci_dev *dev) 646{ 647 struct pci_bus_region region; 648 struct resource *p, *root, *conflict; 649 650 if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) 651 return; 652 653 p = kzalloc(sizeof(*p), GFP_KERNEL); 654 if (!p) 655 return; 656 657 p->name = "Video RAM area"; 658 p->flags = IORESOURCE_MEM | IORESOURCE_BUSY; 659 660 region.start = 0xa0000UL; 661 region.end = region.start + 0x1ffffUL; 662 pcibios_bus_to_resource(dev->bus, p, ®ion); 663 664 root = pci_find_parent_resource(dev, p); 665 if (!root) { 666 pci_info(dev, "can't claim VGA legacy %pR: no compatible bridge window\n", p); 667 goto err; 668 } 669 670 conflict = request_resource_conflict(root, p); 671 if (conflict) { 672 pci_info(dev, "can't claim VGA legacy %pR: address conflict with %s %pR\n", 673 p, conflict->name, conflict); 674 goto err; 675 } 676 677 pci_info(dev, "VGA legacy framebuffer %pR\n", p); 678 return; 679 680err: 681 kfree(p); 682} 683 684static void pci_claim_bus_resources(struct pci_bus *bus) 685{ 686 struct pci_bus *child_bus; 687 struct pci_dev *dev; 688 689 list_for_each_entry(dev, &bus->devices, bus_list) { 690 struct resource *r; 691 int i; 692 693 pci_dev_for_each_resource(dev, r, i) { 694 if (r->parent || !r->start || !r->flags) 695 continue; 696 697 if (ofpci_verbose) 698 pci_info(dev, "Claiming Resource %d: %pR\n", 699 i, r); 700 701 pci_claim_resource(dev, i); 702 } 703 704 pci_claim_legacy_resources(dev); 705 } 706 707 list_for_each_entry(child_bus, &bus->children, node) 708 pci_claim_bus_resources(child_bus); 709} 710 711struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm, 712 struct device *parent) 713{ 714 LIST_HEAD(resources); 715 struct device_node *node = pbm->op->dev.of_node; 716 struct pci_bus *bus; 717 718 printk("PCI: Scanning PBM %pOF\n", node); 719 720 pci_add_resource_offset(&resources, &pbm->io_space, 721 pbm->io_offset); 722 pci_add_resource_offset(&resources, &pbm->mem_space, 723 pbm->mem_offset); 724 if (pbm->mem64_space.flags) 725 pci_add_resource_offset(&resources, &pbm->mem64_space, 726 pbm->mem64_offset); 727 pbm->busn.start = pbm->pci_first_busno; 728 pbm->busn.end = pbm->pci_last_busno; 729 pbm->busn.flags = IORESOURCE_BUS; 730 pci_add_resource(&resources, &pbm->busn); 731 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops, 732 pbm, &resources); 733 if (!bus) { 734 printk(KERN_ERR "Failed to create bus for %pOF\n", node); 735 pci_free_resource_list(&resources); 736 return NULL; 737 } 738 739 pci_of_scan_bus(pbm, node, bus); 740 pci_bus_register_of_sysfs(bus); 741 742 pci_claim_bus_resources(bus); 743 744 pci_bus_add_devices(bus); 745 return bus; 746} 747 748/* Platform support for /proc/bus/pci/X/Y mmap()s. */ 749int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma) 750{ 751 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 752 resource_size_t ioaddr = pci_resource_start(pdev, bar); 753 754 if (!pbm) 755 return -EINVAL; 756 757 vma->vm_pgoff += (ioaddr + pbm->io_space.start) >> PAGE_SHIFT; 758 759 return 0; 760} 761 762#ifdef CONFIG_NUMA 763int pcibus_to_node(struct pci_bus *pbus) 764{ 765 struct pci_pbm_info *pbm = pbus->sysdata; 766 767 return pbm->numa_node; 768} 769EXPORT_SYMBOL(pcibus_to_node); 770#endif 771 772/* Return the domain number for this pci bus */ 773 774int pci_domain_nr(struct pci_bus *pbus) 775{ 776 struct pci_pbm_info *pbm = pbus->sysdata; 777 int ret; 778 779 if (!pbm) { 780 ret = -ENXIO; 781 } else { 782 ret = pbm->index; 783 } 784 785 return ret; 786} 787EXPORT_SYMBOL(pci_domain_nr); 788 789#ifdef CONFIG_PCI_MSI 790int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) 791{ 792 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 793 unsigned int irq; 794 795 if (!pbm->setup_msi_irq) 796 return -EINVAL; 797 798 return pbm->setup_msi_irq(&irq, pdev, desc); 799} 800 801void arch_teardown_msi_irq(unsigned int irq) 802{ 803 struct msi_desc *entry = irq_get_msi_desc(irq); 804 struct pci_dev *pdev = msi_desc_to_pci_dev(entry); 805 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; 806 807 if (pbm->teardown_msi_irq) 808 pbm->teardown_msi_irq(irq, pdev); 809} 810#endif /* !(CONFIG_PCI_MSI) */ 811 812/* ALI sound chips generate 31-bits of DMA, a special register 813 * determines what bit 31 is emitted as. 814 */ 815int ali_sound_dma_hack(struct device *dev, u64 device_mask) 816{ 817 struct iommu *iommu = dev->archdata.iommu; 818 struct pci_dev *ali_isa_bridge; 819 u8 val; 820 821 if (!dev_is_pci(dev)) 822 return 0; 823 824 if (to_pci_dev(dev)->vendor != PCI_VENDOR_ID_AL || 825 to_pci_dev(dev)->device != PCI_DEVICE_ID_AL_M5451 || 826 device_mask != 0x7fffffff) 827 return 0; 828 829 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, 830 PCI_DEVICE_ID_AL_M1533, 831 NULL); 832 833 pci_read_config_byte(ali_isa_bridge, 0x7e, &val); 834 if (iommu->dma_addr_mask & 0x80000000) 835 val |= 0x01; 836 else 837 val &= ~0x01; 838 pci_write_config_byte(ali_isa_bridge, 0x7e, val); 839 pci_dev_put(ali_isa_bridge); 840 return 1; 841} 842 843void pci_resource_to_user(const struct pci_dev *pdev, int bar, 844 const struct resource *rp, resource_size_t *start, 845 resource_size_t *end) 846{ 847 struct pci_bus_region region; 848 849 /* 850 * "User" addresses are shown in /sys/devices/pci.../.../resource 851 * and /proc/bus/pci/devices and used as mmap offsets for 852 * /proc/bus/pci/BB/DD.F files (see proc_bus_pci_mmap()). 853 * 854 * On sparc, these are PCI bus addresses, i.e., raw BAR values. 855 */ 856 pcibios_resource_to_bus(pdev->bus, ®ion, (struct resource *) rp); 857 *start = region.start; 858 *end = region.end; 859} 860 861void pcibios_set_master(struct pci_dev *dev) 862{ 863 /* No special bus mastering setup handling */ 864} 865 866#ifdef CONFIG_PCI_IOV 867int pcibios_device_add(struct pci_dev *dev) 868{ 869 struct pci_dev *pdev; 870 871 /* Add sriov arch specific initialization here. 872 * Copy dev_archdata from PF to VF 873 */ 874 if (dev->is_virtfn) { 875 struct dev_archdata *psd; 876 877 pdev = dev->physfn; 878 psd = &pdev->dev.archdata; 879 pci_init_dev_archdata(&dev->dev.archdata, psd->iommu, 880 psd->stc, psd->host_controller, NULL, 881 psd->numa_node); 882 } 883 return 0; 884} 885#endif /* CONFIG_PCI_IOV */ 886 887static int __init pcibios_init(void) 888{ 889 pci_dfl_cache_line_size = 64 >> 2; 890 return 0; 891} 892subsys_initcall(pcibios_init); 893 894#ifdef CONFIG_SYSFS 895 896#define SLOT_NAME_SIZE 11 /* Max decimal digits + null in u32 */ 897 898static void pcie_bus_slot_names(struct pci_bus *pbus) 899{ 900 struct pci_dev *pdev; 901 struct pci_bus *bus; 902 903 list_for_each_entry(pdev, &pbus->devices, bus_list) { 904 char name[SLOT_NAME_SIZE]; 905 struct pci_slot *pci_slot; 906 const u32 *slot_num; 907 int len; 908 909 slot_num = of_get_property(pdev->dev.of_node, 910 "physical-slot#", &len); 911 912 if (slot_num == NULL || len != 4) 913 continue; 914 915 snprintf(name, sizeof(name), "%u", slot_num[0]); 916 pci_slot = pci_create_slot(pbus, slot_num[0], name, NULL); 917 918 if (IS_ERR(pci_slot)) 919 pr_err("PCI: pci_create_slot returned %ld.\n", 920 PTR_ERR(pci_slot)); 921 } 922 923 list_for_each_entry(bus, &pbus->children, node) 924 pcie_bus_slot_names(bus); 925} 926 927static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus) 928{ 929 const struct pci_slot_names { 930 u32 slot_mask; 931 char names[]; 932 } *prop; 933 const char *sp; 934 int len, i; 935 u32 mask; 936 937 prop = of_get_property(node, "slot-names", &len); 938 if (!prop) 939 return; 940 941 mask = prop->slot_mask; 942 sp = prop->names; 943 944 if (ofpci_verbose) 945 pci_info(bus, "Making slots for [%pOF] mask[0x%02x]\n", 946 node, mask); 947 948 i = 0; 949 while (mask) { 950 struct pci_slot *pci_slot; 951 u32 this_bit = 1 << i; 952 953 if (!(mask & this_bit)) { 954 i++; 955 continue; 956 } 957 958 if (ofpci_verbose) 959 pci_info(bus, "Making slot [%s]\n", sp); 960 961 pci_slot = pci_create_slot(bus, i, sp, NULL); 962 if (IS_ERR(pci_slot)) 963 pci_err(bus, "pci_create_slot returned %ld\n", 964 PTR_ERR(pci_slot)); 965 966 sp += strlen(sp) + 1; 967 mask &= ~this_bit; 968 i++; 969 } 970} 971 972static int __init of_pci_slot_init(void) 973{ 974 struct pci_bus *pbus = NULL; 975 976 while ((pbus = pci_find_next_bus(pbus)) != NULL) { 977 struct device_node *node; 978 struct pci_dev *pdev; 979 980 pdev = list_first_entry(&pbus->devices, struct pci_dev, 981 bus_list); 982 983 if (pdev && pci_is_pcie(pdev)) { 984 pcie_bus_slot_names(pbus); 985 } else { 986 987 if (pbus->self) { 988 989 /* PCI->PCI bridge */ 990 node = pbus->self->dev.of_node; 991 992 } else { 993 struct pci_pbm_info *pbm = pbus->sysdata; 994 995 /* Host PCI controller */ 996 node = pbm->op->dev.of_node; 997 } 998 999 pci_bus_slot_names(node, pbus); 1000 } 1001 } 1002 1003 return 0; 1004} 1005device_initcall(of_pci_slot_init); 1006#endif
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