setup-sh7786.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * SH7786 Setup
  4 *
  5 * Copyright (C) 2009 - 2011  Renesas Solutions Corp.
  6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  7 * Paul Mundt <paul.mundt@renesas.com>
  8 *
  9 * Based on SH7785 Setup
 10 *
 11 *  Copyright (C) 2007  Paul Mundt
 12 */
 13#include <linux/platform_device.h>
 14#include <linux/init.h>
 15#include <linux/serial.h>
 16#include <linux/serial_sci.h>
 17#include <linux/io.h>
 18#include <linux/mm.h>
 19#include <linux/dma-mapping.h>
 20#include <linux/sh_timer.h>
 21#include <linux/sh_dma.h>
 22#include <linux/sh_intc.h>
 23#include <linux/usb/ohci_pdriver.h>
 24#include <cpu/dma-register.h>
 25#include <asm/mmzone.h>
 26#include <asm/platform_early.h>
 27
 28static struct plat_sci_port scif0_platform_data = {
 29	.scscr		= SCSCR_REIE | SCSCR_CKE1,
 30	.type		= PORT_SCIF,
 31	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 32};
 33
 34static struct resource scif0_resources[] = {
 35	DEFINE_RES_MEM(0xffea0000, 0x100),
 36	DEFINE_RES_IRQ(evt2irq(0x700)),
 37	DEFINE_RES_IRQ(evt2irq(0x720)),
 38	DEFINE_RES_IRQ(evt2irq(0x760)),
 39	DEFINE_RES_IRQ(evt2irq(0x740)),
 40};
 41
 42static struct platform_device scif0_device = {
 43	.name		= "sh-sci",
 44	.id		= 0,
 45	.resource	= scif0_resources,
 46	.num_resources	= ARRAY_SIZE(scif0_resources),
 47	.dev		= {
 48		.platform_data	= &scif0_platform_data,
 49	},
 50};
 51
 52/*
 53 * The rest of these all have multiplexed IRQs
 54 */
 55static struct plat_sci_port scif1_platform_data = {
 56	.scscr		= SCSCR_REIE | SCSCR_CKE1,
 57	.type		= PORT_SCIF,
 58	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 59};
 60
 61static struct resource scif1_resources[] = {
 62	DEFINE_RES_MEM(0xffeb0000, 0x100),
 63	DEFINE_RES_IRQ(evt2irq(0x780)),
 64};
 65
 66static struct resource scif1_demux_resources[] = {
 67	DEFINE_RES_MEM(0xffeb0000, 0x100),
 68	/* Placeholders, see sh7786_devices_setup() */
 69	DEFINE_RES_IRQ(0),
 70	DEFINE_RES_IRQ(0),
 71	DEFINE_RES_IRQ(0),
 72	DEFINE_RES_IRQ(0),
 73};
 74
 75static struct platform_device scif1_device = {
 76	.name		= "sh-sci",
 77	.id		= 1,
 78	.resource	= scif1_resources,
 79	.num_resources	= ARRAY_SIZE(scif1_resources),
 80	.dev		= {
 81		.platform_data	= &scif1_platform_data,
 82	},
 83};
 84
 85static struct plat_sci_port scif2_platform_data = {
 86	.scscr		= SCSCR_REIE | SCSCR_CKE1,
 87	.type		= PORT_SCIF,
 88	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 89};
 90
 91static struct resource scif2_resources[] = {
 92	DEFINE_RES_MEM(0xffec0000, 0x100),
 93	DEFINE_RES_IRQ(evt2irq(0x840)),
 94};
 95
 96static struct platform_device scif2_device = {
 97	.name		= "sh-sci",
 98	.id		= 2,
 99	.resource	= scif2_resources,
100	.num_resources	= ARRAY_SIZE(scif2_resources),
101	.dev		= {
102		.platform_data	= &scif2_platform_data,
103	},
104};
105
106static struct plat_sci_port scif3_platform_data = {
107	.scscr		= SCSCR_REIE | SCSCR_CKE1,
108	.type		= PORT_SCIF,
109	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
110};
111
112static struct resource scif3_resources[] = {
113	DEFINE_RES_MEM(0xffed0000, 0x100),
114	DEFINE_RES_IRQ(evt2irq(0x860)),
115};
116
117static struct platform_device scif3_device = {
118	.name		= "sh-sci",
119	.id		= 3,
120	.resource	= scif3_resources,
121	.num_resources	= ARRAY_SIZE(scif3_resources),
122	.dev		= {
123		.platform_data	= &scif3_platform_data,
124	},
125};
126
127static struct plat_sci_port scif4_platform_data = {
128	.scscr		= SCSCR_REIE | SCSCR_CKE1,
129	.type		= PORT_SCIF,
130	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
131};
132
133static struct resource scif4_resources[] = {
134	DEFINE_RES_MEM(0xffee0000, 0x100),
135	DEFINE_RES_IRQ(evt2irq(0x880)),
136};
137
138static struct platform_device scif4_device = {
139	.name		= "sh-sci",
140	.id		= 4,
141	.resource	= scif4_resources,
142	.num_resources	= ARRAY_SIZE(scif4_resources),
143	.dev		= {
144		.platform_data	= &scif4_platform_data,
145	},
146};
147
148static struct plat_sci_port scif5_platform_data = {
149	.scscr		= SCSCR_REIE | SCSCR_CKE1,
150	.type		= PORT_SCIF,
151	.regtype	= SCIx_SH4_SCIF_FIFODATA_REGTYPE,
152};
153
154static struct resource scif5_resources[] = {
155	DEFINE_RES_MEM(0xffef0000, 0x100),
156	DEFINE_RES_IRQ(evt2irq(0x8a0)),
157};
158
159static struct platform_device scif5_device = {
160	.name		= "sh-sci",
161	.id		= 5,
162	.resource	= scif5_resources,
163	.num_resources	= ARRAY_SIZE(scif5_resources),
164	.dev		= {
165		.platform_data	= &scif5_platform_data,
166	},
167};
168
169static struct sh_timer_config tmu0_platform_data = {
170	.channels_mask = 7,
171};
172
173static struct resource tmu0_resources[] = {
174	DEFINE_RES_MEM(0xffd80000, 0x30),
175	DEFINE_RES_IRQ(evt2irq(0x400)),
176	DEFINE_RES_IRQ(evt2irq(0x420)),
177	DEFINE_RES_IRQ(evt2irq(0x440)),
178};
179
180static struct platform_device tmu0_device = {
181	.name		= "sh-tmu",
182	.id		= 0,
183	.dev = {
184		.platform_data	= &tmu0_platform_data,
185	},
186	.resource	= tmu0_resources,
187	.num_resources	= ARRAY_SIZE(tmu0_resources),
188};
189
190static struct sh_timer_config tmu1_platform_data = {
191	.channels_mask = 7,
192};
193
194static struct resource tmu1_resources[] = {
195	DEFINE_RES_MEM(0xffda0000, 0x2c),
196	DEFINE_RES_IRQ(evt2irq(0x480)),
197	DEFINE_RES_IRQ(evt2irq(0x4a0)),
198	DEFINE_RES_IRQ(evt2irq(0x4c0)),
199};
200
201static struct platform_device tmu1_device = {
202	.name		= "sh-tmu",
203	.id		= 1,
204	.dev = {
205		.platform_data	= &tmu1_platform_data,
206	},
207	.resource	= tmu1_resources,
208	.num_resources	= ARRAY_SIZE(tmu1_resources),
209};
210
211static struct sh_timer_config tmu2_platform_data = {
212	.channels_mask = 7,
213};
214
215static struct resource tmu2_resources[] = {
216	DEFINE_RES_MEM(0xffdc0000, 0x2c),
217	DEFINE_RES_IRQ(evt2irq(0x7a0)),
218	DEFINE_RES_IRQ(evt2irq(0x7a0)),
219	DEFINE_RES_IRQ(evt2irq(0x7a0)),
220};
221
222static struct platform_device tmu2_device = {
223	.name		= "sh-tmu",
224	.id		= 2,
225	.dev = {
226		.platform_data	= &tmu2_platform_data,
227	},
228	.resource	= tmu2_resources,
229	.num_resources	= ARRAY_SIZE(tmu2_resources),
230};
231
232static struct sh_timer_config tmu3_platform_data = {
233	.channels_mask = 7,
234};
235
236static struct resource tmu3_resources[] = {
237	DEFINE_RES_MEM(0xffde0000, 0x2c),
238	DEFINE_RES_IRQ(evt2irq(0x7c0)),
239	DEFINE_RES_IRQ(evt2irq(0x7c0)),
240	DEFINE_RES_IRQ(evt2irq(0x7c0)),
241};
242
243static struct platform_device tmu3_device = {
244	.name		= "sh-tmu",
245	.id		= 3,
246	.dev = {
247		.platform_data	= &tmu3_platform_data,
248	},
249	.resource	= tmu3_resources,
250	.num_resources	= ARRAY_SIZE(tmu3_resources),
251};
252
253static const struct sh_dmae_channel dmac0_channels[] = {
254	{
255		.offset = 0,
256		.dmars = 0,
257		.dmars_bit = 0,
258	}, {
259		.offset = 0x10,
260		.dmars = 0,
261		.dmars_bit = 8,
262	}, {
263		.offset = 0x20,
264		.dmars = 4,
265		.dmars_bit = 0,
266	}, {
267		.offset = 0x30,
268		.dmars = 4,
269		.dmars_bit = 8,
270	}, {
271		.offset = 0x50,
272		.dmars = 8,
273		.dmars_bit = 0,
274	}, {
275		.offset = 0x60,
276		.dmars = 8,
277		.dmars_bit = 8,
278	}
279};
280
281static const unsigned int ts_shift[] = TS_SHIFT;
282
283static struct sh_dmae_pdata dma0_platform_data = {
284	.channel	= dmac0_channels,
285	.channel_num	= ARRAY_SIZE(dmac0_channels),
286	.ts_low_shift	= CHCR_TS_LOW_SHIFT,
287	.ts_low_mask	= CHCR_TS_LOW_MASK,
288	.ts_high_shift	= CHCR_TS_HIGH_SHIFT,
289	.ts_high_mask	= CHCR_TS_HIGH_MASK,
290	.ts_shift	= ts_shift,
291	.ts_shift_num	= ARRAY_SIZE(ts_shift),
292	.dmaor_init	= DMAOR_INIT,
293};
294
295/* Resource order important! */
296static struct resource dmac0_resources[] = {
297	{
298		/* Channel registers and DMAOR */
299		.start	= 0xfe008020,
300		.end	= 0xfe00808f,
301		.flags	= IORESOURCE_MEM,
302	}, {
303		/* DMARSx */
304		.start	= 0xfe009000,
305		.end	= 0xfe00900b,
306		.flags	= IORESOURCE_MEM,
307	}, {
308		.name	= "error_irq",
309		.start	= evt2irq(0x5c0),
310		.end	= evt2irq(0x5c0),
311		.flags	= IORESOURCE_IRQ,
312	}, {
313		/* IRQ for channels 0-5 */
314		.start	= evt2irq(0x500),
315		.end	= evt2irq(0x5a0),
316		.flags	= IORESOURCE_IRQ,
317	},
318};
319
320static struct platform_device dma0_device = {
321	.name		= "sh-dma-engine",
322	.id		= 0,
323	.resource	= dmac0_resources,
324	.num_resources	= ARRAY_SIZE(dmac0_resources),
325	.dev		= {
326		.platform_data	= &dma0_platform_data,
327	},
328};
329
330#define USB_EHCI_START 0xffe70000
331#define USB_OHCI_START 0xffe70400
332
333static struct resource usb_ehci_resources[] = {
334	[0] = {
335		.start	= USB_EHCI_START,
336		.end	= USB_EHCI_START + 0x3ff,
337		.flags	= IORESOURCE_MEM,
338	},
339	[1] = {
340		.start	= evt2irq(0xba0),
341		.end	= evt2irq(0xba0),
342		.flags	= IORESOURCE_IRQ,
343	},
344};
345
346static struct platform_device usb_ehci_device = {
347	.name		= "sh_ehci",
348	.id		= -1,
349	.dev = {
350		.dma_mask		= &usb_ehci_device.dev.coherent_dma_mask,
351		.coherent_dma_mask	= DMA_BIT_MASK(32),
352	},
353	.num_resources	= ARRAY_SIZE(usb_ehci_resources),
354	.resource	= usb_ehci_resources,
355};
356
357static struct resource usb_ohci_resources[] = {
358	[0] = {
359		.start	= USB_OHCI_START,
360		.end	= USB_OHCI_START + 0x3ff,
361		.flags	= IORESOURCE_MEM,
362	},
363	[1] = {
364		.start	= evt2irq(0xba0),
365		.end	= evt2irq(0xba0),
366		.flags	= IORESOURCE_IRQ,
367	},
368};
369
370static struct usb_ohci_pdata usb_ohci_pdata;
371
372static struct platform_device usb_ohci_device = {
373	.name		= "ohci-platform",
374	.id		= -1,
375	.dev = {
376		.dma_mask		= &usb_ohci_device.dev.coherent_dma_mask,
377		.coherent_dma_mask	= DMA_BIT_MASK(32),
378		.platform_data		= &usb_ohci_pdata,
379	},
380	.num_resources	= ARRAY_SIZE(usb_ohci_resources),
381	.resource	= usb_ohci_resources,
382};
383
384static struct platform_device *sh7786_early_devices[] __initdata = {
385	&scif0_device,
386	&scif1_device,
387	&scif2_device,
388	&scif3_device,
389	&scif4_device,
390	&scif5_device,
391	&tmu0_device,
392	&tmu1_device,
393	&tmu2_device,
394	&tmu3_device,
395};
396
397static struct platform_device *sh7786_devices[] __initdata = {
398	&dma0_device,
399	&usb_ehci_device,
400	&usb_ohci_device,
401};
402
403#define USBINITREG1	0xffe70094
404#define USBINITREG2	0xffe7009c
405#define USBINITVAL1	0x00ff0040
406#define USBINITVAL2	0x00000001
407
408#define USBPCTL1	0xffe70804
409#define USBST		0xffe70808
410#define PHY_ENB		0x00000001
411#define PLL_ENB		0x00000002
412#define PHY_RST		0x00000004
413#define ACT_PLL_STATUS	0xc0000000
414
415static void __init sh7786_usb_setup(void)
416{
417	int i = 1000000;
418
419	/*
420	 * USB initial settings
421	 *
422	 * The following settings are necessary
423	 * for using the USB modules.
424	 *
425	 * see "USB Initial Settings" for detail
426	 */
427	__raw_writel(USBINITVAL1, USBINITREG1);
428	__raw_writel(USBINITVAL2, USBINITREG2);
429
430	/*
431	 * Set the PHY and PLL enable bit
432	 */
433	__raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
434	while (i--) {
435		if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
436			/* Set the PHY RST bit */
437			__raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
438			printk(KERN_INFO "sh7786 usb setup done\n");
439			break;
440		}
441		cpu_relax();
442	}
443}
444
445enum {
446	UNUSED = 0,
447
448	/* interrupt sources */
449	IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
450	IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
451	IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
452	IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
453
454	IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
455	IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
456	IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
457	IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
458
459	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
460	WDT,
461	TMU0_0, TMU0_1, TMU0_2, TMU0_3,
462	TMU1_0, TMU1_1, TMU1_2,
463	DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
464	HUDI1, HUDI0,
465	DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
466	HPB_0, HPB_1, HPB_2,
467	SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
468	SCIF1,
469	TMU2, TMU3,
470	SCIF2, SCIF3, SCIF4, SCIF5,
471	Eth_0, Eth_1,
472	PCIeC0_0, PCIeC0_1, PCIeC0_2,
473	PCIeC1_0, PCIeC1_1, PCIeC1_2,
474	USB,
475	I2C0, I2C1,
476	DU,
477	SSI0, SSI1, SSI2, SSI3,
478	PCIeC2_0, PCIeC2_1, PCIeC2_2,
479	HAC0, HAC1,
480	FLCTL,
481	HSPI,
482	GPIO0, GPIO1,
483	Thermal,
484	INTICI0, INTICI1, INTICI2, INTICI3,
485	INTICI4, INTICI5, INTICI6, INTICI7,
486
487	/* Muxed sub-events */
488	TXI1, BRI1, RXI1, ERI1,
489};
490
491static struct intc_vect sh7786_vectors[] __initdata = {
492	INTC_VECT(WDT, 0x3e0),
493	INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
494	INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
495	INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
496	INTC_VECT(TMU1_2, 0x4c0),
497	INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
498	INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
499	INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
500	INTC_VECT(DMAC0_6, 0x5c0),
501	INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
502	INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
503	INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
504	INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
505	INTC_VECT(HPB_2, 0x6e0),
506	INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
507	INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
508	INTC_VECT(SCIF1, 0x780),
509	INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
510	INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
511	INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
512	INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
513	INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
514	INTC_VECT(PCIeC0_2, 0xb20),
515	INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
516	INTC_VECT(PCIeC1_2, 0xb80),
517	INTC_VECT(USB, 0xba0),
518	INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
519	INTC_VECT(DU, 0xd00),
520	INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
521	INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
522	INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
523	INTC_VECT(PCIeC2_2, 0xde0),
524	INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
525	INTC_VECT(FLCTL, 0xe40),
526	INTC_VECT(HSPI, 0xe80),
527	INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
528	INTC_VECT(Thermal, 0xee0),
529	INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
530	INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
531	INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
532	INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
533};
534
535#define CnINTMSK0	0xfe410030
536#define CnINTMSK1	0xfe410040
537#define CnINTMSKCLR0	0xfe410050
538#define CnINTMSKCLR1	0xfe410060
539#define CnINT2MSKR0	0xfe410a20
540#define CnINT2MSKR1	0xfe410a24
541#define CnINT2MSKR2	0xfe410a28
542#define CnINT2MSKR3	0xfe410a2c
543#define CnINT2MSKCR0	0xfe410a30
544#define CnINT2MSKCR1	0xfe410a34
545#define CnINT2MSKCR2	0xfe410a38
546#define CnINT2MSKCR3	0xfe410a3c
547#define INTMSK2		0xfe410068
548#define INTMSKCLR2	0xfe41006c
549
550#define INTDISTCR0	0xfe4100b0
551#define INTDISTCR1	0xfe4100b4
552#define INT2DISTCR0	0xfe410900
553#define INT2DISTCR1	0xfe410904
554#define INT2DISTCR2	0xfe410908
555#define INT2DISTCR3	0xfe41090c
556
557static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
558	{ CnINTMSK0, CnINTMSKCLR0, 32,
559	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
560	    INTC_SMP_BALANCING(INTDISTCR0) },
561	{ INTMSK2, INTMSKCLR2, 32,
562	  { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
563	    IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
564	    IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
565	    IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
566	    IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
567	    IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
568	    IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
569	    IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
570	{ CnINT2MSKR0, CnINT2MSKCR0 , 32,
571	  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
572	    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
573	    INTC_SMP_BALANCING(INT2DISTCR0) },
574	{ CnINT2MSKR1, CnINT2MSKCR1, 32,
575	  { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
576	    DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
577	    HUDI1, HUDI0,
578	    DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
579	    HPB_0, HPB_1, HPB_2,
580	    SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
581	    SCIF1,
582	    TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
583	{ CnINT2MSKR2, CnINT2MSKCR2, 32,
584	  { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
585	    Eth_0, Eth_1,
586	    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
587	    PCIeC0_0, PCIeC0_1, PCIeC0_2,
588	    PCIeC1_0, PCIeC1_1, PCIeC1_2,
589	    USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
590	{ CnINT2MSKR3, CnINT2MSKCR3, 32,
591	  { 0, 0, 0, 0, 0, 0,
592	    I2C0, I2C1,
593	    DU, SSI0, SSI1, SSI2, SSI3,
594	    PCIeC2_0, PCIeC2_1, PCIeC2_2,
595	    HAC0, HAC1,
596	    FLCTL, 0,
597	    HSPI, GPIO0, GPIO1, Thermal,
598	    0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
599};
600
601static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
602	{ 0xfe410010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
603						 IRQ4, IRQ5, IRQ6, IRQ7 } },
604	{ 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
605	{ 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
606						 TMU0_2, TMU0_3 } },
607	{ 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
608						 TMU1_2, 0 } },
609	{ 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
610						 DMAC0_2, DMAC0_3 } },
611	{ 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
612						 DMAC0_6, HUDI1 } },
613	{ 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
614						 DMAC1_1, DMAC1_2 } },
615	{ 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
616						 HPB_1, HPB_2 } },
617	{ 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
618						 SCIF0_2, SCIF0_3 } },
619	{ 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
620	{ 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
621	{ 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
622						  Eth_0, Eth_1 } },
623	{ 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
624	{ 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
625	{ 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
626	{ 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
627	{ 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
628						  PCIeC1_0, PCIeC1_1 } },
629	{ 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
630	{ 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
631	{ 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
632	{ 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
633	{ 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
634						  PCIeC2_1, PCIeC2_2 } },
635	{ 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
636	{ 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
637						  GPIO1, Thermal } },
638	{ 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
639	{ 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
640	{ 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
641	  { INTICI7, INTICI6, INTICI5, INTICI4,
642	    INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
643};
644
645static struct intc_subgroup sh7786_subgroups[] __initdata = {
646	{ 0xfe410c20, 32, SCIF1,
647	  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
648	    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
649};
650
651static struct intc_desc sh7786_intc_desc __initdata = {
652	.name		= "sh7786",
653	.hw		= {
654		.vectors	= sh7786_vectors,
655		.nr_vectors	= ARRAY_SIZE(sh7786_vectors),
656		.mask_regs	= sh7786_mask_registers,
657		.nr_mask_regs	= ARRAY_SIZE(sh7786_mask_registers),
658		.subgroups	= sh7786_subgroups,
659		.nr_subgroups	= ARRAY_SIZE(sh7786_subgroups),
660		.prio_regs	= sh7786_prio_registers,
661		.nr_prio_regs	= ARRAY_SIZE(sh7786_prio_registers),
662	},
663};
664
665/* Support for external interrupt pins in IRQ mode */
666static struct intc_vect vectors_irq0123[] __initdata = {
667	INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
668	INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
669};
670
671static struct intc_vect vectors_irq4567[] __initdata = {
672	INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
673	INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
674};
675
676static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
677	{ 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
678					    IRQ4, IRQ5, IRQ6, IRQ7 } },
679};
680
681static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
682	{ 0xfe410024, 0, 32, /* INTREQ */
683	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
684};
685
686static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
687			     vectors_irq0123, NULL, sh7786_mask_registers,
688			     sh7786_prio_registers, sh7786_sense_registers,
689			     sh7786_ack_registers);
690
691static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
692			     vectors_irq4567, NULL, sh7786_mask_registers,
693			     sh7786_prio_registers, sh7786_sense_registers,
694			     sh7786_ack_registers);
695
696/* External interrupt pins in IRL mode */
697
698static struct intc_vect vectors_irl0123[] __initdata = {
699	INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
700	INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
701	INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
702	INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
703	INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
704	INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
705	INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
706	INTC_VECT(IRL0_HHHL, 0x3c0),
707};
708
709static struct intc_vect vectors_irl4567[] __initdata = {
710	INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
711	INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
712	INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
713	INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
714	INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
715	INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
716	INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
717	INTC_VECT(IRL4_HHHL, 0xac0),
718};
719
720static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
721			 NULL, sh7786_mask_registers, NULL, NULL);
722
723static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
724			 NULL, sh7786_mask_registers, NULL, NULL);
725
726#define INTC_ICR0	0xfe410000
727#define INTC_INTMSK0	CnINTMSK0
728#define INTC_INTMSK1	CnINTMSK1
729#define INTC_INTMSK2	INTMSK2
730#define INTC_INTMSKCLR1	CnINTMSKCLR1
731#define INTC_INTMSKCLR2	INTMSKCLR2
732
733void __init plat_irq_setup(void)
734{
735	/* disable IRQ3-0 + IRQ7-4 */
736	__raw_writel(0xff000000, INTC_INTMSK0);
737
738	/* disable IRL3-0 + IRL7-4 */
739	__raw_writel(0xc0000000, INTC_INTMSK1);
740	__raw_writel(0xfffefffe, INTC_INTMSK2);
741
742	/* select IRL mode for IRL3-0 + IRL7-4 */
743	__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
744
745	register_intc_controller(&sh7786_intc_desc);
746}
747
748void __init plat_irq_setup_pins(int mode)
749{
750	switch (mode) {
751	case IRQ_MODE_IRQ7654:
752		/* select IRQ mode for IRL7-4 */
753		__raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
754		register_intc_controller(&intc_desc_irq4567);
755		break;
756	case IRQ_MODE_IRQ3210:
757		/* select IRQ mode for IRL3-0 */
758		__raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
759		register_intc_controller(&intc_desc_irq0123);
760		break;
761	case IRQ_MODE_IRL7654:
762		/* enable IRL7-4 but don't provide any masking */
763		__raw_writel(0x40000000, INTC_INTMSKCLR1);
764		__raw_writel(0x0000fffe, INTC_INTMSKCLR2);
765		break;
766	case IRQ_MODE_IRL3210:
767		/* enable IRL0-3 but don't provide any masking */
768		__raw_writel(0x80000000, INTC_INTMSKCLR1);
769		__raw_writel(0xfffe0000, INTC_INTMSKCLR2);
770		break;
771	case IRQ_MODE_IRL7654_MASK:
772		/* enable IRL7-4 and mask using cpu intc controller */
773		__raw_writel(0x40000000, INTC_INTMSKCLR1);
774		register_intc_controller(&intc_desc_irl4567);
775		break;
776	case IRQ_MODE_IRL3210_MASK:
777		/* enable IRL0-3 and mask using cpu intc controller */
778		__raw_writel(0x80000000, INTC_INTMSKCLR1);
779		register_intc_controller(&intc_desc_irl0123);
780		break;
781	default:
782		BUG();
783	}
784}
785
786void __init plat_mem_setup(void)
787{
788}
789
790static int __init sh7786_devices_setup(void)
791{
792	int ret, irq;
793
794	sh7786_usb_setup();
795
796	/*
797	 * De-mux SCIF1 IRQs if possible
798	 */
799	irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
800	if (irq > 0) {
801		scif1_demux_resources[1].start =
802			intc_irq_lookup(sh7786_intc_desc.name, ERI1);
803		scif1_demux_resources[2].start =
804			intc_irq_lookup(sh7786_intc_desc.name, RXI1);
805		scif1_demux_resources[3].start = irq;
806		scif1_demux_resources[4].start =
807			intc_irq_lookup(sh7786_intc_desc.name, BRI1);
808
809		scif1_device.resource = scif1_demux_resources;
810		scif1_device.num_resources = ARRAY_SIZE(scif1_demux_resources);
811	}
812
813	ret = platform_add_devices(sh7786_early_devices,
814				   ARRAY_SIZE(sh7786_early_devices));
815	if (unlikely(ret != 0))
816		return ret;
817
818	return platform_add_devices(sh7786_devices,
819				    ARRAY_SIZE(sh7786_devices));
820}
821arch_initcall(sh7786_devices_setup);
822
823void __init plat_early_device_setup(void)
824{
825	sh_early_platform_add_devices(sh7786_early_devices,
826				   ARRAY_SIZE(sh7786_early_devices));
827}