setup-sh7723.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * SH7723 Setup
  4 *
  5 *  Copyright (C) 2008  Paul Mundt
  6 */
  7#include <linux/platform_device.h>
  8#include <linux/init.h>
  9#include <linux/serial.h>
 10#include <linux/mm.h>
 11#include <linux/serial_sci.h>
 12#include <linux/uio_driver.h>
 13#include <linux/usb/r8a66597.h>
 14#include <linux/sh_timer.h>
 15#include <linux/sh_intc.h>
 16#include <linux/io.h>
 17
 18#include <asm/cacheflush.h>
 19#include <asm/clock.h>
 20#include <asm/mmzone.h>
 21#include <asm/platform_early.h>
 22
 23#include <cpu/sh7723.h>
 24
 25/* Serial */
 26static struct plat_sci_port scif0_platform_data = {
 27	.scscr		= SCSCR_REIE,
 28	.type           = PORT_SCIF,
 29	.regtype	= SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 30};
 31
 32static struct resource scif0_resources[] = {
 33	DEFINE_RES_MEM(0xffe00000, 0x100),
 34	DEFINE_RES_IRQ(evt2irq(0xc00)),
 35};
 36
 37static struct platform_device scif0_device = {
 38	.name		= "sh-sci",
 39	.id		= 0,
 40	.resource	= scif0_resources,
 41	.num_resources	= ARRAY_SIZE(scif0_resources),
 42	.dev		= {
 43		.platform_data	= &scif0_platform_data,
 44	},
 45};
 46
 47static struct plat_sci_port scif1_platform_data = {
 48	.scscr		= SCSCR_REIE,
 49	.type           = PORT_SCIF,
 50	.regtype	= SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 51};
 52
 53static struct resource scif1_resources[] = {
 54	DEFINE_RES_MEM(0xffe10000, 0x100),
 55	DEFINE_RES_IRQ(evt2irq(0xc20)),
 56};
 57
 58static struct platform_device scif1_device = {
 59	.name		= "sh-sci",
 60	.id		= 1,
 61	.resource	= scif1_resources,
 62	.num_resources	= ARRAY_SIZE(scif1_resources),
 63	.dev		= {
 64		.platform_data	= &scif1_platform_data,
 65	},
 66};
 67
 68static struct plat_sci_port scif2_platform_data = {
 69	.scscr		= SCSCR_REIE,
 70	.type           = PORT_SCIF,
 71	.regtype	= SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 72};
 73
 74static struct resource scif2_resources[] = {
 75	DEFINE_RES_MEM(0xffe20000, 0x100),
 76	DEFINE_RES_IRQ(evt2irq(0xc40)),
 77};
 78
 79static struct platform_device scif2_device = {
 80	.name		= "sh-sci",
 81	.id		= 2,
 82	.resource	= scif2_resources,
 83	.num_resources	= ARRAY_SIZE(scif2_resources),
 84	.dev		= {
 85		.platform_data	= &scif2_platform_data,
 86	},
 87};
 88
 89static struct plat_sci_port scif3_platform_data = {
 90	.sampling_rate	= 8,
 91	.type           = PORT_SCIFA,
 92};
 93
 94static struct resource scif3_resources[] = {
 95	DEFINE_RES_MEM(0xa4e30000, 0x100),
 96	DEFINE_RES_IRQ(evt2irq(0x900)),
 97};
 98
 99static struct platform_device scif3_device = {
100	.name		= "sh-sci",
101	.id		= 3,
102	.resource	= scif3_resources,
103	.num_resources	= ARRAY_SIZE(scif3_resources),
104	.dev		= {
105		.platform_data	= &scif3_platform_data,
106	},
107};
108
109static struct plat_sci_port scif4_platform_data = {
110	.sampling_rate	= 8,
111	.type           = PORT_SCIFA,
112};
113
114static struct resource scif4_resources[] = {
115	DEFINE_RES_MEM(0xa4e40000, 0x100),
116	DEFINE_RES_IRQ(evt2irq(0xd00)),
117};
118
119static struct platform_device scif4_device = {
120	.name		= "sh-sci",
121	.id		= 4,
122	.resource	= scif4_resources,
123	.num_resources	= ARRAY_SIZE(scif4_resources),
124	.dev		= {
125		.platform_data	= &scif4_platform_data,
126	},
127};
128
129static struct plat_sci_port scif5_platform_data = {
130	.sampling_rate	= 8,
131	.type           = PORT_SCIFA,
132};
133
134static struct resource scif5_resources[] = {
135	DEFINE_RES_MEM(0xa4e50000, 0x100),
136	DEFINE_RES_IRQ(evt2irq(0xfa0)),
137};
138
139static struct platform_device scif5_device = {
140	.name		= "sh-sci",
141	.id		= 5,
142	.resource	= scif5_resources,
143	.num_resources	= ARRAY_SIZE(scif5_resources),
144	.dev		= {
145		.platform_data	= &scif5_platform_data,
146	},
147};
148
149static struct uio_info vpu_platform_data = {
150	.name = "VPU5",
151	.version = "0",
152	.irq = evt2irq(0x980),
153};
154
155static struct resource vpu_resources[] = {
156	[0] = {
157		.name	= "VPU",
158		.start	= 0xfe900000,
159		.end	= 0xfe902807,
160		.flags	= IORESOURCE_MEM,
161	},
162	[1] = {
163		/* place holder for contiguous memory */
164	},
165};
166
167static struct platform_device vpu_device = {
168	.name		= "uio_pdrv_genirq",
169	.id		= 0,
170	.dev = {
171		.platform_data	= &vpu_platform_data,
172	},
173	.resource	= vpu_resources,
174	.num_resources	= ARRAY_SIZE(vpu_resources),
175};
176
177static struct uio_info veu0_platform_data = {
178	.name = "VEU2H",
179	.version = "0",
180	.irq = evt2irq(0x8c0),
181};
182
183static struct resource veu0_resources[] = {
184	[0] = {
185		.name	= "VEU2H0",
186		.start	= 0xfe920000,
187		.end	= 0xfe92027b,
188		.flags	= IORESOURCE_MEM,
189	},
190	[1] = {
191		/* place holder for contiguous memory */
192	},
193};
194
195static struct platform_device veu0_device = {
196	.name		= "uio_pdrv_genirq",
197	.id		= 1,
198	.dev = {
199		.platform_data	= &veu0_platform_data,
200	},
201	.resource	= veu0_resources,
202	.num_resources	= ARRAY_SIZE(veu0_resources),
203};
204
205static struct uio_info veu1_platform_data = {
206	.name = "VEU2H",
207	.version = "0",
208	.irq = evt2irq(0x560),
209};
210
211static struct resource veu1_resources[] = {
212	[0] = {
213		.name	= "VEU2H1",
214		.start	= 0xfe924000,
215		.end	= 0xfe92427b,
216		.flags	= IORESOURCE_MEM,
217	},
218	[1] = {
219		/* place holder for contiguous memory */
220	},
221};
222
223static struct platform_device veu1_device = {
224	.name		= "uio_pdrv_genirq",
225	.id		= 2,
226	.dev = {
227		.platform_data	= &veu1_platform_data,
228	},
229	.resource	= veu1_resources,
230	.num_resources	= ARRAY_SIZE(veu1_resources),
231};
232
233static struct sh_timer_config cmt_platform_data = {
234	.channels_mask = 0x20,
235};
236
237static struct resource cmt_resources[] = {
238	DEFINE_RES_MEM(0x044a0000, 0x70),
239	DEFINE_RES_IRQ(evt2irq(0xf00)),
240};
241
242static struct platform_device cmt_device = {
243	.name		= "sh-cmt-32",
244	.id		= 0,
245	.dev = {
246		.platform_data	= &cmt_platform_data,
247	},
248	.resource	= cmt_resources,
249	.num_resources	= ARRAY_SIZE(cmt_resources),
250};
251
252static struct sh_timer_config tmu0_platform_data = {
253	.channels_mask = 7,
254};
255
256static struct resource tmu0_resources[] = {
257	DEFINE_RES_MEM(0xffd80000, 0x2c),
258	DEFINE_RES_IRQ(evt2irq(0x400)),
259	DEFINE_RES_IRQ(evt2irq(0x420)),
260	DEFINE_RES_IRQ(evt2irq(0x440)),
261};
262
263static struct platform_device tmu0_device = {
264	.name		= "sh-tmu",
265	.id		= 0,
266	.dev = {
267		.platform_data	= &tmu0_platform_data,
268	},
269	.resource	= tmu0_resources,
270	.num_resources	= ARRAY_SIZE(tmu0_resources),
271};
272
273static struct sh_timer_config tmu1_platform_data = {
274	.channels_mask = 7,
275};
276
277static struct resource tmu1_resources[] = {
278	DEFINE_RES_MEM(0xffd90000, 0x2c),
279	DEFINE_RES_IRQ(evt2irq(0x920)),
280	DEFINE_RES_IRQ(evt2irq(0x940)),
281	DEFINE_RES_IRQ(evt2irq(0x960)),
282};
283
284static struct platform_device tmu1_device = {
285	.name		= "sh-tmu",
286	.id		= 1,
287	.dev = {
288		.platform_data	= &tmu1_platform_data,
289	},
290	.resource	= tmu1_resources,
291	.num_resources	= ARRAY_SIZE(tmu1_resources),
292};
293
294static struct resource rtc_resources[] = {
295	[0] = {
296		.start	= 0xa465fec0,
297		.end	= 0xa465fec0 + 0x58 - 1,
298		.flags	= IORESOURCE_IO,
299	},
300	[1] = {
301		/* Period IRQ */
302		.start	= evt2irq(0xaa0),
303		.flags	= IORESOURCE_IRQ,
304	},
305	[2] = {
306		/* Carry IRQ */
307		.start	= evt2irq(0xac0),
308		.flags	= IORESOURCE_IRQ,
309	},
310	[3] = {
311		/* Alarm IRQ */
312		.start	= evt2irq(0xa80),
313		.flags	= IORESOURCE_IRQ,
314	},
315};
316
317static struct platform_device rtc_device = {
318	.name		= "sh-rtc",
319	.id		= -1,
320	.num_resources	= ARRAY_SIZE(rtc_resources),
321	.resource	= rtc_resources,
322};
323
324static struct r8a66597_platdata r8a66597_data = {
325	.on_chip = 1,
326};
327
328static struct resource sh7723_usb_host_resources[] = {
329	[0] = {
330		.start	= 0xa4d80000,
331		.end	= 0xa4d800ff,
332		.flags	= IORESOURCE_MEM,
333	},
334	[1] = {
335		.start	= evt2irq(0xa20),
336		.end	= evt2irq(0xa20),
337		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
338	},
339};
340
341static struct platform_device sh7723_usb_host_device = {
342	.name		= "r8a66597_hcd",
343	.id		= 0,
344	.dev = {
345		.dma_mask		= NULL,         /*  not use dma */
346		.coherent_dma_mask	= 0xffffffff,
347		.platform_data		= &r8a66597_data,
348	},
349	.num_resources	= ARRAY_SIZE(sh7723_usb_host_resources),
350	.resource	= sh7723_usb_host_resources,
351};
352
353static struct resource iic_resources[] = {
354	[0] = {
355		.name	= "IIC",
356		.start  = 0x04470000,
357		.end    = 0x04470017,
358		.flags  = IORESOURCE_MEM,
359	},
360	[1] = {
361		.start  = evt2irq(0xe00),
362		.end    = evt2irq(0xe60),
363		.flags  = IORESOURCE_IRQ,
364       },
365};
366
367static struct platform_device iic_device = {
368	.name           = "i2c-sh_mobile",
369	.id             = 0, /* "i2c0" clock */
370	.num_resources  = ARRAY_SIZE(iic_resources),
371	.resource       = iic_resources,
372};
373
374static struct platform_device *sh7723_devices[] __initdata = {
375	&scif0_device,
376	&scif1_device,
377	&scif2_device,
378	&scif3_device,
379	&scif4_device,
380	&scif5_device,
381	&cmt_device,
382	&tmu0_device,
383	&tmu1_device,
384	&rtc_device,
385	&iic_device,
386	&sh7723_usb_host_device,
387	&vpu_device,
388	&veu0_device,
389	&veu1_device,
390};
391
392static int __init sh7723_devices_setup(void)
393{
394	platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
395	platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
396	platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
397
398	return platform_add_devices(sh7723_devices,
399				    ARRAY_SIZE(sh7723_devices));
400}
401arch_initcall(sh7723_devices_setup);
402
403static struct platform_device *sh7723_early_devices[] __initdata = {
404	&scif0_device,
405	&scif1_device,
406	&scif2_device,
407	&scif3_device,
408	&scif4_device,
409	&scif5_device,
410	&cmt_device,
411	&tmu0_device,
412	&tmu1_device,
413};
414
415void __init plat_early_device_setup(void)
416{
417	sh_early_platform_add_devices(sh7723_early_devices,
418				   ARRAY_SIZE(sh7723_early_devices));
419}
420
421#define RAMCR_CACHE_L2FC	0x0002
422#define RAMCR_CACHE_L2E		0x0001
423#define L2_CACHE_ENABLE		(RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
424
425void l2_cache_init(void)
426{
427	/* Enable L2 cache */
428	__raw_writel(L2_CACHE_ENABLE, RAMCR);
429}
430
431enum {
432	UNUSED=0,
433	ENABLED,
434	DISABLED,
435
436	/* interrupt sources */
437	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
438	HUDI,
439	DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
440	_2DG_TRI,_2DG_INI,_2DG_CEI,
441	DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
442	VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
443	SCIFA_SCIFA0,
444	VPU_VPUI,
445	TPU_TPUI,
446	ADC_ADI,
447	USB_USI0,
448	RTC_ATI,RTC_PRI,RTC_CUI,
449	DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
450	DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
451	KEYSC_KEYI,
452	SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
453	MSIOF_MSIOFI0,MSIOF_MSIOFI1,
454	SCIFA_SCIFA1,
455	FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
456	I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
457	CMT_CMTI,
458	TSIF_TSIFI,
459	SIU_SIUI,
460	SCIFA_SCIFA2,
461	TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
462	IRDA_IRDAI,
463	ATAPI_ATAPII,
464	VEU2H1_VEU2HI,
465	LCDC_LCDCI,
466	TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
467
468	/* interrupt groups */
469	DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
470	SDHI1, RTC, DMAC1B, SDHI0,
471};
472
473static struct intc_vect vectors[] __initdata = {
474	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
475	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
476	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
477	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
478
479	INTC_VECT(DMAC1A_DEI0,0x700),
480	INTC_VECT(DMAC1A_DEI1,0x720),
481	INTC_VECT(DMAC1A_DEI2,0x740),
482	INTC_VECT(DMAC1A_DEI3,0x760),
483
484	INTC_VECT(_2DG_TRI, 0x780),
485	INTC_VECT(_2DG_INI, 0x7A0),
486	INTC_VECT(_2DG_CEI, 0x7C0),
487
488	INTC_VECT(DMAC0A_DEI0,0x800),
489	INTC_VECT(DMAC0A_DEI1,0x820),
490	INTC_VECT(DMAC0A_DEI2,0x840),
491	INTC_VECT(DMAC0A_DEI3,0x860),
492
493	INTC_VECT(VIO_CEUI,0x880),
494	INTC_VECT(VIO_BEUI,0x8A0),
495	INTC_VECT(VIO_VEU2HI,0x8C0),
496	INTC_VECT(VIO_VOUI,0x8E0),
497
498	INTC_VECT(SCIFA_SCIFA0,0x900),
499	INTC_VECT(VPU_VPUI,0x980),
500	INTC_VECT(TPU_TPUI,0x9A0),
501	INTC_VECT(ADC_ADI,0x9E0),
502	INTC_VECT(USB_USI0,0xA20),
503
504	INTC_VECT(RTC_ATI,0xA80),
505	INTC_VECT(RTC_PRI,0xAA0),
506	INTC_VECT(RTC_CUI,0xAC0),
507
508	INTC_VECT(DMAC1B_DEI4,0xB00),
509	INTC_VECT(DMAC1B_DEI5,0xB20),
510	INTC_VECT(DMAC1B_DADERR,0xB40),
511
512	INTC_VECT(DMAC0B_DEI4,0xB80),
513	INTC_VECT(DMAC0B_DEI5,0xBA0),
514	INTC_VECT(DMAC0B_DADERR,0xBC0),
515
516	INTC_VECT(KEYSC_KEYI,0xBE0),
517	INTC_VECT(SCIF_SCIF0,0xC00),
518	INTC_VECT(SCIF_SCIF1,0xC20),
519	INTC_VECT(SCIF_SCIF2,0xC40),
520	INTC_VECT(MSIOF_MSIOFI0,0xC80),
521	INTC_VECT(MSIOF_MSIOFI1,0xCA0),
522	INTC_VECT(SCIFA_SCIFA1,0xD00),
523
524	INTC_VECT(FLCTL_FLSTEI,0xD80),
525	INTC_VECT(FLCTL_FLTENDI,0xDA0),
526	INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
527	INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
528
529	INTC_VECT(I2C_ALI,0xE00),
530	INTC_VECT(I2C_TACKI,0xE20),
531	INTC_VECT(I2C_WAITI,0xE40),
532	INTC_VECT(I2C_DTEI,0xE60),
533
534	INTC_VECT(SDHI0, 0xE80),
535	INTC_VECT(SDHI0, 0xEA0),
536	INTC_VECT(SDHI0, 0xEC0),
537
538	INTC_VECT(CMT_CMTI,0xF00),
539	INTC_VECT(TSIF_TSIFI,0xF20),
540	INTC_VECT(SIU_SIUI,0xF80),
541	INTC_VECT(SCIFA_SCIFA2,0xFA0),
542
543	INTC_VECT(TMU0_TUNI0,0x400),
544	INTC_VECT(TMU0_TUNI1,0x420),
545	INTC_VECT(TMU0_TUNI2,0x440),
546
547	INTC_VECT(IRDA_IRDAI,0x480),
548	INTC_VECT(ATAPI_ATAPII,0x4A0),
549
550	INTC_VECT(SDHI1, 0x4E0),
551	INTC_VECT(SDHI1, 0x500),
552	INTC_VECT(SDHI1, 0x520),
553
554	INTC_VECT(VEU2H1_VEU2HI,0x560),
555	INTC_VECT(LCDC_LCDCI,0x580),
556
557	INTC_VECT(TMU1_TUNI0,0x920),
558	INTC_VECT(TMU1_TUNI1,0x940),
559	INTC_VECT(TMU1_TUNI2,0x960),
560
561};
562
563static struct intc_group groups[] __initdata = {
564	INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
565	INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
566	INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
567	INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
568	INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
569	INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
570	INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
571	INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
572	INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
573};
574
575static struct intc_mask_reg mask_registers[] __initdata = {
576	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
577	  { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
578	    0, ENABLED, ENABLED, ENABLED } },
579	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
580	  { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
581	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
582	  { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
583	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
584	  { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
585	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
586	  { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
587	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
588	  { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
589	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
590	  { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
591	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
592	  { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
593	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
594	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
595	  { 0, ENABLED, ENABLED, ENABLED,
596	    0, 0, SCIFA_SCIFA2, SIU_SIUI } },
597	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
598	  { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
599	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
600	  { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
601	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
602	  { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
603	{ 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
604	  { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
605	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
606	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
607};
608
609static struct intc_prio_reg prio_registers[] __initdata = {
610	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
611	{ 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
612	{ 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
613	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
614	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
615	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
616	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
617	{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
618	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
619	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
620	{ 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
621	{ 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
622	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
623	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
624};
625
626static struct intc_sense_reg sense_registers[] __initdata = {
627	{ 0xa414001c, 16, 2, /* ICR1 */
628	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
629};
630
631static struct intc_mask_reg ack_registers[] __initdata = {
632	{ 0xa4140024, 0, 8, /* INTREQ00 */
633	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
634};
635
636static struct intc_desc intc_desc __initdata = {
637	.name = "sh7723",
638	.force_enable = ENABLED,
639	.force_disable = DISABLED,
640	.hw = INTC_HW_DESC(vectors, groups, mask_registers,
641			   prio_registers, sense_registers, ack_registers),
642};
643
644void __init plat_irq_setup(void)
645{
646	register_intc_controller(&intc_desc);
647}