fpga.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2#ifndef __MACH_SDK7786_FPGA_H
  3#define __MACH_SDK7786_FPGA_H
  4
  5#include <linux/io.h>
  6#include <linux/types.h>
  7#include <linux/bitops.h>
  8
  9#define SRSTR		0x000
 10#define  SRSTR_MAGIC	0x1971	/* Fixed magical read value */
 11
 12#define INTASR		0x010
 13#define INTAMR		0x020
 14#define MODSWR		0x030
 15#define INTTESTR	0x040
 16#define SYSSR		0x050
 17#define NRGPR		0x060
 18
 19#define NMISR		0x070
 20#define  NMISR_MAN_NMI	BIT(0)
 21#define  NMISR_AUX_NMI	BIT(1)
 22#define  NMISR_MASK	(NMISR_MAN_NMI | NMISR_AUX_NMI)
 23
 24#define NMIMR		0x080
 25#define  NMIMR_MAN_NMIM	BIT(0)	/* Manual NMI mask */
 26#define  NMIMR_AUX_NMIM	BIT(1)	/* Auxiliary NMI mask */
 27#define  NMIMR_MASK	(NMIMR_MAN_NMIM | NMIMR_AUX_NMIM)
 28
 29#define INTBSR		0x090
 30#define INTBMR		0x0a0
 31#define USRLEDR		0x0b0
 32#define MAPSWR		0x0c0
 33#define FPGAVR		0x0d0
 34#define FPGADR		0x0e0
 35#define PCBRR		0x0f0
 36#define RSR		0x100
 37#define EXTASR		0x110
 38#define SPCAR		0x120
 39#define INTMSR		0x130
 40
 41#define PCIECR		0x140
 42#define  PCIECR_PCIEMUX1	BIT(15)
 43#define  PCIECR_PCIEMUX0	BIT(14)
 44#define  PCIECR_PRST4		BIT(12) /* slot 4 card present */
 45#define  PCIECR_PRST3		BIT(11) /* slot 3 card present */
 46#define  PCIECR_PRST2		BIT(10) /* slot 2 card present */
 47#define  PCIECR_PRST1		BIT(9)  /* slot 1 card present */
 48#define  PCIECR_CLKEN		BIT(4)	/* oscillator enable */
 49
 50#define FAER		0x150
 51#define USRGPIR		0x160
 52
 53/* 0x170 reserved */
 54
 55#define LCLASR			0x180
 56#define  LCLASR_FRAMEN		BIT(15)
 57
 58#define  LCLASR_FPGA_SEL_SHIFT	12
 59#define  LCLASR_NAND_SEL_SHIFT	8
 60#define  LCLASR_NORB_SEL_SHIFT	4
 61#define  LCLASR_NORA_SEL_SHIFT	0
 62
 63#define  LCLASR_AREA_MASK	0x7
 64
 65#define  LCLASR_FPGA_SEL_MASK	(LCLASR_AREA_MASK << LCLASR_FPGA_SEL_SHIFT)
 66#define  LCLASR_NAND_SEL_MASK	(LCLASR_AREA_MASK << LCLASR_NAND_SEL_SHIFT)
 67#define  LCLASR_NORB_SEL_MASK	(LCLASR_AREA_MASK << LCLASR_NORB_SEL_SHIFT)
 68#define  LCLASR_NORA_SEL_MASK	(LCLASR_AREA_MASK << LCLASR_NORA_SEL_SHIFT)
 69
 70#define SBCR		0x190
 71#define  SCBR_I2CMEN	BIT(0)	/* FPGA I2C master enable */
 72#define  SCBR_I2CCEN	BIT(1)	/* CPU I2C master enable */
 73
 74#define PWRCR		0x1a0
 75#define  PWRCR_SCISEL0	BIT(0)
 76#define  PWRCR_SCISEL1	BIT(1)
 77#define  PWRCR_SCIEN	BIT(2)	/* Serial port enable */
 78#define  PWRCR_PDWNACK	BIT(5)	/* Power down acknowledge */
 79#define  PWRCR_PDWNREQ	BIT(7)	/* Power down request */
 80#define  PWRCR_INT2	BIT(11)	/* INT2 connection to power manager */
 81#define  PWRCR_BUPINIT	BIT(13)	/* DDR backup initialize */
 82#define  PWRCR_BKPRST	BIT(15) /* Backup power reset */
 83
 84#define SPCBR		0x1b0
 85#define SPICR		0x1c0
 86#define SPIDR		0x1d0
 87#define I2CCR		0x1e0
 88#define I2CDR		0x1f0
 89#define FPGACR		0x200
 90#define IASELR1		0x210
 91#define IASELR2		0x220
 92#define IASELR3		0x230
 93#define IASELR4		0x240
 94#define IASELR5		0x250
 95#define IASELR6		0x260
 96#define IASELR7		0x270
 97#define IASELR8		0x280
 98#define IASELR9		0x290
 99#define IASELR10	0x2a0
100#define IASELR11	0x2b0
101#define IASELR12	0x2c0
102#define IASELR13	0x2d0
103#define IASELR14	0x2e0
104#define IASELR15	0x2f0
105/* 0x300 reserved */
106#define IBSELR1		0x310
107#define IBSELR2		0x320
108#define IBSELR3		0x330
109#define IBSELR4		0x340
110#define IBSELR5		0x350
111#define IBSELR6		0x360
112#define IBSELR7		0x370
113#define IBSELR8		0x380
114#define IBSELR9		0x390
115#define IBSELR10	0x3a0
116#define IBSELR11	0x3b0
117#define IBSELR12	0x3c0
118#define IBSELR13	0x3d0
119#define IBSELR14	0x3e0
120#define IBSELR15	0x3f0
121#define USRACR		0x400
122#define BEEPR		0x410
123#define USRLCDR		0x420
124#define SMBCR		0x430
125#define SMBDR		0x440
126#define USBCR		0x450
127#define AMSR		0x460
128#define ACCR		0x470
129#define SDIFCR		0x480
130
131/* arch/sh/boards/mach-sdk7786/fpga.c */
132extern void __iomem *sdk7786_fpga_base;
133extern void sdk7786_fpga_init(void);
134
135/* arch/sh/boards/mach-sdk7786/nmi.c */
136extern void sdk7786_nmi_init(void);
137
138#define SDK7786_FPGA_REGADDR(reg)	(sdk7786_fpga_base + (reg))
139
140/*
141 * A convenience wrapper from register offset to internal I2C address,
142 * when the FPGA is in I2C slave mode.
143 */
144#define SDK7786_FPGA_I2CADDR(reg)	((reg) >> 3)
145
146static inline u16 fpga_read_reg(unsigned int reg)
147{
148	return ioread16(sdk7786_fpga_base + reg);
149}
150
151static inline void fpga_write_reg(u16 val, unsigned int reg)
152{
153	iowrite16(val, sdk7786_fpga_base + reg);
154}
155
156#endif /* __MACH_SDK7786_FPGA_H */