irq.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 *    Copyright IBM Corp. 2004, 2011
  4 *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
  5 *		 Holger Smolinski <Holger.Smolinski@de.ibm.com>,
  6 *		 Thomas Spatzier <tspat@de.ibm.com>,
  7 *
  8 * This file contains interrupt related functions.
  9 */
 10
 11#include <linux/kernel_stat.h>
 12#include <linux/cpufeature.h>
 13#include <linux/interrupt.h>
 14#include <linux/seq_file.h>
 15#include <linux/proc_fs.h>
 16#include <linux/profile.h>
 17#include <linux/export.h>
 18#include <linux/kernel.h>
 19#include <linux/ftrace.h>
 20#include <linux/errno.h>
 21#include <linux/slab.h>
 22#include <linux/init.h>
 23#include <linux/cpu.h>
 24#include <linux/irq.h>
 25#include <linux/entry-common.h>
 26#include <asm/irq_regs.h>
 27#include <asm/cputime.h>
 28#include <asm/lowcore.h>
 29#include <asm/machine.h>
 30#include <asm/irq.h>
 31#include <asm/hw_irq.h>
 32#include <asm/stacktrace.h>
 33#include <asm/softirq_stack.h>
 34#include <asm/vtime.h>
 35#include <asm/asm.h>
 36#include "entry.h"
 37
 38DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);
 39EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);
 40
 41struct irq_class {
 42	int irq;
 43	char *name;
 44	char *desc;
 45};
 46
 47/*
 48 * The list of "main" irq classes on s390. This is the list of interrupts
 49 * that appear both in /proc/stat ("intr" line) and /proc/interrupts.
 50 * Historically only external and I/O interrupts have been part of /proc/stat.
 51 * We can't add the split external and I/O sub classes since the first field
 52 * in the "intr" line in /proc/stat is supposed to be the sum of all other
 53 * fields.
 54 * Since the external and I/O interrupt fields are already sums we would end
 55 * up with having a sum which accounts each interrupt twice.
 56 */
 57static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {
 58	{.irq = EXT_INTERRUPT,	.name = "EXT"},
 59	{.irq = IO_INTERRUPT,	.name = "I/O"},
 60	{.irq = THIN_INTERRUPT, .name = "AIO"},
 61};
 62
 63/*
 64 * The list of split external and I/O interrupts that appear only in
 65 * /proc/interrupts.
 66 * In addition this list contains non external / I/O events like NMIs.
 67 */
 68static const struct irq_class irqclass_sub_desc[] = {
 69	{.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"},
 70	{.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"},
 71	{.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"},
 72	{.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"},
 73	{.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"},
 74	{.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"},
 75	{.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"},
 76	{.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"},
 77	{.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"},
 78	{.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"},
 79	{.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},
 80	{.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},
 81	{.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"},
 82	{.irq = IRQEXT_WTI, .name = "WTI", .desc = "[EXT] Warning Track"},
 83	{.irq = IRQIO_CIO,  .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},
 84	{.irq = IRQIO_DAS,  .name = "DAS", .desc = "[I/O] DASD"},
 85	{.irq = IRQIO_C15,  .name = "C15", .desc = "[I/O] 3215"},
 86	{.irq = IRQIO_C70,  .name = "C70", .desc = "[I/O] 3270"},
 87	{.irq = IRQIO_TAP,  .name = "TAP", .desc = "[I/O] Tape"},
 88	{.irq = IRQIO_VMR,  .name = "VMR", .desc = "[I/O] Unit Record Devices"},
 89	{.irq = IRQIO_CTC,  .name = "CTC", .desc = "[I/O] CTC"},
 90	{.irq = IRQIO_ADM,  .name = "ADM", .desc = "[I/O] EADM Subchannel"},
 91	{.irq = IRQIO_CSC,  .name = "CSC", .desc = "[I/O] CHSC Subchannel"},
 92	{.irq = IRQIO_VIR,  .name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
 93	{.irq = IRQIO_QAI,  .name = "QAI", .desc = "[AIO] QDIO Adapter Interrupt"},
 94	{.irq = IRQIO_APB,  .name = "APB", .desc = "[AIO] AP Bus"},
 95	{.irq = IRQIO_PCF,  .name = "PCF", .desc = "[AIO] PCI Floating Interrupt"},
 96	{.irq = IRQIO_PCD,  .name = "PCD", .desc = "[AIO] PCI Directed Interrupt"},
 97	{.irq = IRQIO_MSI,  .name = "MSI", .desc = "[AIO] MSI Interrupt"},
 98	{.irq = IRQIO_VAI,  .name = "VAI", .desc = "[AIO] Virtual I/O Devices AI"},
 99	{.irq = IRQIO_GAL,  .name = "GAL", .desc = "[AIO] GIB Alert"},
100	{.irq = NMI_NMI,    .name = "NMI", .desc = "[NMI] Machine Check"},
101	{.irq = CPU_RST,    .name = "RST", .desc = "[CPU] CPU Restart"},
102};
103
104static void do_IRQ(struct pt_regs *regs, int irq)
105{
106	if (tod_after_eq(get_lowcore()->int_clock,
107			 get_lowcore()->clock_comparator))
108		/* Serve timer interrupts first. */
109		clock_comparator_work();
110	generic_handle_irq(irq);
111}
112
113static int on_async_stack(void)
114{
115	unsigned long frame = current_frame_address();
116
117	return ((get_lowcore()->async_stack ^ frame) & ~(THREAD_SIZE - 1)) == 0;
118}
119
120static void do_irq_async(struct pt_regs *regs, int irq)
121{
122	if (on_async_stack()) {
123		do_IRQ(regs, irq);
124	} else {
125		call_on_stack(2, get_lowcore()->async_stack, void, do_IRQ,
126			      struct pt_regs *, regs, int, irq);
127	}
128}
129
130static int irq_pending(struct pt_regs *regs)
131{
132	int cc;
133
134	asm volatile(
135		"	tpi	 0\n"
136		CC_IPM(cc)
137		: CC_OUT(cc, cc)
138		:
139		: CC_CLOBBER);
140	return CC_TRANSFORM(cc);
141}
142
143void noinstr do_io_irq(struct pt_regs *regs)
144{
145	irqentry_state_t state = irqentry_enter(regs);
146	struct pt_regs *old_regs = set_irq_regs(regs);
147	bool from_idle;
148
149	from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT);
150	if (from_idle)
151		update_timer_idle();
152
153	irq_enter_rcu();
154
155	if (user_mode(regs)) {
156		update_timer_sys();
157		if (cpu_has_bear())
158			current->thread.last_break = regs->last_break;
159	}
160
161	if (from_idle)
162		account_idle_time_irq();
163
164	set_cpu_flag(CIF_NOHZ_DELAY);
165	do {
166		regs->tpi_info = get_lowcore()->tpi_info;
167		if (get_lowcore()->tpi_info.adapter_IO)
168			do_irq_async(regs, THIN_INTERRUPT);
169		else
170			do_irq_async(regs, IO_INTERRUPT);
171	} while (machine_is_lpar() && irq_pending(regs));
172
173	irq_exit_rcu();
174
175	set_irq_regs(old_regs);
176	irqentry_exit(regs, state);
177
178	if (from_idle)
179		regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT);
180}
181
182void noinstr do_ext_irq(struct pt_regs *regs)
183{
184	irqentry_state_t state = irqentry_enter(regs);
185	struct pt_regs *old_regs = set_irq_regs(regs);
186	bool from_idle;
187
188	from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT);
189	if (from_idle)
190		update_timer_idle();
191
192	irq_enter_rcu();
193
194	if (user_mode(regs)) {
195		update_timer_sys();
196		if (cpu_has_bear())
197			current->thread.last_break = regs->last_break;
198	}
199
200	regs->int_code = get_lowcore()->ext_int_code_addr;
201	regs->int_parm = get_lowcore()->ext_params;
202	regs->int_parm_long = get_lowcore()->ext_params2;
203
204	if (from_idle)
205		account_idle_time_irq();
206
207	do_irq_async(regs, EXT_INTERRUPT);
208
209	irq_exit_rcu();
210	set_irq_regs(old_regs);
211	irqentry_exit(regs, state);
212
213	if (from_idle)
214		regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT);
215}
216
217static void show_msi_interrupt(struct seq_file *p, int irq)
218{
219	struct irq_desc *desc;
220	unsigned long flags;
221	int cpu;
222
223	rcu_read_lock();
224	desc = irq_to_desc(irq);
225	if (!desc)
226		goto out;
227
228	raw_spin_lock_irqsave(&desc->lock, flags);
229	seq_printf(p, "%3d: ", irq);
230	for_each_online_cpu(cpu)
231		seq_printf(p, "%10u ", irq_desc_kstat_cpu(desc, cpu));
232
233	if (desc->irq_data.chip)
234		seq_printf(p, " %8s", desc->irq_data.chip->name);
235
236	if (desc->action)
237		seq_printf(p, "  %s", desc->action->name);
238
239	seq_putc(p, '\n');
240	raw_spin_unlock_irqrestore(&desc->lock, flags);
241out:
242	rcu_read_unlock();
243}
244
245/*
246 * show_interrupts is needed by /proc/interrupts.
247 */
248int show_interrupts(struct seq_file *p, void *v)
249{
250	int index = *(loff_t *) v;
251	int cpu, irq;
252
253	cpus_read_lock();
254	if (index == 0) {
255		seq_puts(p, "           ");
256		for_each_online_cpu(cpu)
257			seq_printf(p, "CPU%-8d", cpu);
258		seq_putc(p, '\n');
259	}
260	if (index < NR_IRQS_BASE) {
261		seq_printf(p, "%s: ", irqclass_main_desc[index].name);
262		irq = irqclass_main_desc[index].irq;
263		for_each_online_cpu(cpu)
264			seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
265		seq_putc(p, '\n');
266		goto out;
267	}
268	if (index < irq_get_nr_irqs()) {
269		show_msi_interrupt(p, index);
270		goto out;
271	}
272	for (index = 0; index < NR_ARCH_IRQS; index++) {
273		seq_printf(p, "%s: ", irqclass_sub_desc[index].name);
274		irq = irqclass_sub_desc[index].irq;
275		for_each_online_cpu(cpu)
276			seq_printf(p, "%10u ",
277				   per_cpu(irq_stat, cpu).irqs[irq]);
278		if (irqclass_sub_desc[index].desc)
279			seq_printf(p, "  %s", irqclass_sub_desc[index].desc);
280		seq_putc(p, '\n');
281	}
282out:
283	cpus_read_unlock();
284	return 0;
285}
286
287unsigned int arch_dynirq_lower_bound(unsigned int from)
288{
289	return from < NR_IRQS_BASE ? NR_IRQS_BASE : from;
290}
291
292/*
293 * ext_int_hash[index] is the list head for all external interrupts that hash
294 * to this index.
295 */
296static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
297
298struct ext_int_info {
299	ext_int_handler_t handler;
300	struct hlist_node entry;
301	struct rcu_head rcu;
302	u16 code;
303};
304
305/* ext_int_hash_lock protects the handler lists for external interrupts */
306static DEFINE_SPINLOCK(ext_int_hash_lock);
307
308static inline int ext_hash(u16 code)
309{
310	BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash)));
311
312	return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
313}
314
315int register_external_irq(u16 code, ext_int_handler_t handler)
316{
317	struct ext_int_info *p;
318	unsigned long flags;
319	int index;
320
321	p = kmalloc(sizeof(*p), GFP_ATOMIC);
322	if (!p)
323		return -ENOMEM;
324	p->code = code;
325	p->handler = handler;
326	index = ext_hash(code);
327
328	spin_lock_irqsave(&ext_int_hash_lock, flags);
329	hlist_add_head_rcu(&p->entry, &ext_int_hash[index]);
330	spin_unlock_irqrestore(&ext_int_hash_lock, flags);
331	return 0;
332}
333EXPORT_SYMBOL(register_external_irq);
334
335int unregister_external_irq(u16 code, ext_int_handler_t handler)
336{
337	struct ext_int_info *p;
338	unsigned long flags;
339	int index = ext_hash(code);
340
341	spin_lock_irqsave(&ext_int_hash_lock, flags);
342	hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
343		if (p->code == code && p->handler == handler) {
344			hlist_del_rcu(&p->entry);
345			kfree_rcu(p, rcu);
346		}
347	}
348	spin_unlock_irqrestore(&ext_int_hash_lock, flags);
349	return 0;
350}
351EXPORT_SYMBOL(unregister_external_irq);
352
353static irqreturn_t do_ext_interrupt(int irq, void *dummy)
354{
355	struct pt_regs *regs = get_irq_regs();
356	struct ext_code ext_code;
357	struct ext_int_info *p;
358	int index;
359
360	ext_code.int_code = regs->int_code;
361	if (ext_code.code != EXT_IRQ_CLK_COMP)
362		set_cpu_flag(CIF_NOHZ_DELAY);
363
364	index = ext_hash(ext_code.code);
365	rcu_read_lock();
366	hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
367		if (unlikely(p->code != ext_code.code))
368			continue;
369		p->handler(ext_code, regs->int_parm, regs->int_parm_long);
370	}
371	rcu_read_unlock();
372	return IRQ_HANDLED;
373}
374
375static void __init init_ext_interrupts(void)
376{
377	int idx;
378
379	for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)
380		INIT_HLIST_HEAD(&ext_int_hash[idx]);
381
382	irq_set_chip_and_handler(EXT_INTERRUPT,
383				 &dummy_irq_chip, handle_percpu_irq);
384	if (request_irq(EXT_INTERRUPT, do_ext_interrupt, 0, "EXT", NULL))
385		panic("Failed to register EXT interrupt\n");
386}
387
388void __init init_IRQ(void)
389{
390	BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS);
391	init_cio_interrupts();
392	init_airq_interrupts();
393	init_ext_interrupts();
394}
395
396static DEFINE_SPINLOCK(irq_subclass_lock);
397static unsigned char irq_subclass_refcount[64];
398
399void irq_subclass_register(enum irq_subclass subclass)
400{
401	spin_lock(&irq_subclass_lock);
402	if (!irq_subclass_refcount[subclass])
403		system_ctl_set_bit(0, subclass);
404	irq_subclass_refcount[subclass]++;
405	spin_unlock(&irq_subclass_lock);
406}
407EXPORT_SYMBOL(irq_subclass_register);
408
409void irq_subclass_unregister(enum irq_subclass subclass)
410{
411	spin_lock(&irq_subclass_lock);
412	irq_subclass_refcount[subclass]--;
413	if (!irq_subclass_refcount[subclass])
414		system_ctl_clear_bit(0, subclass);
415	spin_unlock(&irq_subclass_lock);
416}
417EXPORT_SYMBOL(irq_subclass_unregister);