entry.S

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 *    S390 low-level entry points.
  4 *
  5 *    Copyright IBM Corp. 1999, 2012
  6 *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  7 *		 Hartmut Penner (hp@de.ibm.com),
  8 *		 Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
  9 */
 10
 11#include <linux/export.h>
 12#include <linux/init.h>
 13#include <linux/linkage.h>
 14#include <asm/asm-extable.h>
 15#include <asm/alternative.h>
 16#include <asm/processor.h>
 17#include <asm/cache.h>
 18#include <asm/dwarf.h>
 19#include <asm/errno.h>
 20#include <asm/ptrace.h>
 21#include <asm/thread_info.h>
 22#include <asm/asm-offsets.h>
 23#include <asm/unistd.h>
 24#include <asm/page.h>
 25#include <asm/sigp.h>
 26#include <asm/irq.h>
 27#include <asm/fpu-insn.h>
 28#include <asm/setup.h>
 29#include <asm/nmi.h>
 30#include <asm/nospec-insn.h>
 31#include <asm/lowcore.h>
 32#include <asm/machine.h>
 33
 34_LPP_OFFSET	= __LC_LPP
 35
 36	.macro STBEAR address
 37	ALTERNATIVE "nop", ".insn s,0xb2010000,\address", ALT_FACILITY(193)
 38	.endm
 39
 40	.macro LBEAR address
 41	ALTERNATIVE "nop", ".insn s,0xb2000000,\address", ALT_FACILITY(193)
 42	.endm
 43
 44	.macro LPSWEY address, lpswe
 45	ALTERNATIVE_2 "b \lpswe;nopr", \
 46		".insn siy,0xeb0000000071,\address,0", ALT_FACILITY(193),		\
 47		__stringify(.insn siy,0xeb0000000071,LOWCORE_ALT_ADDRESS+\address,0),	\
 48		ALT_FEATURE(MFEATURE_LOWCORE)
 49	.endm
 50
 51	.macro MBEAR reg, lowcore
 52	ALTERNATIVE "brcl 0,0", __stringify(mvc __PT_LAST_BREAK(8,\reg),__LC_LAST_BREAK(\lowcore)),\
 53		ALT_FACILITY(193)
 54	.endm
 55
 56	.macro	CHECK_VMAP_STACK savearea, lowcore, oklabel
 57	lgr	%r14,%r15
 58	nill	%r14,0x10000 - THREAD_SIZE
 59	oill	%r14,STACK_INIT_OFFSET
 60	clg	%r14,__LC_KERNEL_STACK(\lowcore)
 61	je	\oklabel
 62	clg	%r14,__LC_ASYNC_STACK(\lowcore)
 63	je	\oklabel
 64	clg	%r14,__LC_MCCK_STACK(\lowcore)
 65	je	\oklabel
 66	clg	%r14,__LC_NODAT_STACK(\lowcore)
 67	je	\oklabel
 68	clg	%r14,__LC_RESTART_STACK(\lowcore)
 69	je	\oklabel
 70	la	%r14,\savearea(\lowcore)
 71	j	stack_invalid
 72	.endm
 73
 74	/*
 75	 * The TSTMSK macro generates a test-under-mask instruction by
 76	 * calculating the memory offset for the specified mask value.
 77	 * Mask value can be any constant.  The macro shifts the mask
 78	 * value to calculate the memory offset for the test-under-mask
 79	 * instruction.
 80	 */
 81	.macro TSTMSK addr, mask, size=8, bytepos=0
 82		.if (\bytepos < \size) && (\mask >> 8)
 83			.if (\mask & 0xff)
 84				.error "Mask exceeds byte boundary"
 85			.endif
 86			TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)"
 87			.exitm
 88		.endif
 89		.ifeq \mask
 90			.error "Mask must not be zero"
 91		.endif
 92		off = \size - \bytepos - 1
 93		tm	off+\addr, \mask
 94	.endm
 95
 96	.macro BPOFF
 97	ALTERNATIVE "nop", ".insn rrf,0xb2e80000,0,0,12,0", ALT_SPEC(82)
 98	.endm
 99
100	.macro BPON
101	ALTERNATIVE "nop", ".insn rrf,0xb2e80000,0,0,13,0", ALT_SPEC(82)
102	.endm
103
104	.macro BPENTER tif_ptr,tif_mask
105	ALTERNATIVE "TSTMSK \tif_ptr,\tif_mask; jz .+8; .insn rrf,0xb2e80000,0,0,13,0", \
106		    "j .+12; nop; nop", ALT_SPEC(82)
107	.endm
108
109	.macro BPEXIT tif_ptr,tif_mask
110	TSTMSK	\tif_ptr,\tif_mask
111	ALTERNATIVE "jz .+8;  .insn rrf,0xb2e80000,0,0,12,0", \
112		    "jnz .+8; .insn rrf,0xb2e80000,0,0,13,0", ALT_SPEC(82)
113	.endm
114
115#if IS_ENABLED(CONFIG_KVM)
116	.macro SIEEXIT sie_control,lowcore
117	lg	%r9,\sie_control			# get control block pointer
118	ni	__SIE_PROG0C+3(%r9),0xfe		# no longer in SIE
119	lctlg	%c1,%c1,__LC_USER_ASCE(\lowcore)	# load primary asce
120	lg	%r9,__LC_CURRENT(\lowcore)
121	mvi	__TI_sie(%r9),0
122	larl	%r9,sie_exit			# skip forward to sie_exit
123	.endm
124#endif
125
126	.macro STACKLEAK_ERASE
127#ifdef CONFIG_KSTACK_ERASE
128	brasl	%r14,stackleak_erase_on_task_stack
129#endif
130	.endm
131
132	GEN_BR_THUNK %r14
133
134	.section .kprobes.text, "ax"
135.Ldummy:
136	/*
137	 * The following nop exists only in order to avoid that the next
138	 * symbol starts at the beginning of the kprobes text section.
139	 * In that case there would be several symbols at the same address.
140	 * E.g. objdump would take an arbitrary symbol when disassembling
141	 * the code.
142	 * With the added nop in between this cannot happen.
143	 */
144	nop	0
145
146/*
147 * Scheduler resume function, called by __switch_to
148 *  gpr2 = (task_struct *)prev
149 *  gpr3 = (task_struct *)next
150 * Returns:
151 *  gpr2 = prev
152 */
153SYM_FUNC_START(__switch_to_asm)
154	stmg	%r6,%r15,__SF_GPRS(%r15)	# store gprs of prev task
155	lghi	%r4,__TASK_stack
156	lghi	%r1,__TASK_thread
157	llill	%r5,STACK_INIT_OFFSET
158	stg	%r15,__THREAD_ksp(%r1,%r2)	# store kernel stack of prev
159	lg	%r15,0(%r4,%r3)			# start of kernel stack of next
160	agr	%r15,%r5			# end of kernel stack of next
161	GET_LC	%r13
162	stg	%r3,__LC_CURRENT(%r13)		# store task struct of next
163	stg	%r15,__LC_KERNEL_STACK(%r13)	# store end of kernel stack
164	lg	%r15,__THREAD_ksp(%r1,%r3)	# load kernel stack of next
165	lay	%r4,__TASK_pid(%r3)
166	mvc	__LC_CURRENT_PID(4,%r13),0(%r4) # store pid of next
167	ALTERNATIVE "nop", "lpp _LPP_OFFSET(%r13)", ALT_FACILITY(40)
168#ifdef CONFIG_STACKPROTECTOR
169	lg	%r3,__TASK_stack_canary(%r3)
170	stg	%r3,__LC_STACK_CANARY(%r13)
171#endif
172	lmg	%r6,%r15,__SF_GPRS(%r15)	# load gprs of next task
173	BR_EX	%r14
174SYM_FUNC_END(__switch_to_asm)
175
176#if IS_ENABLED(CONFIG_KVM)
177/*
178 * __sie64a calling convention:
179 * %r2 pointer to sie control block phys
180 * %r3 pointer to sie control block virt
181 * %r4 guest register save area
182 * %r5 guest asce
183 */
184SYM_FUNC_START(__sie64a)
185	stmg	%r6,%r14,__SF_GPRS(%r15)	# save kernel registers
186	GET_LC	%r13
187	lg	%r14,__LC_CURRENT(%r13)
188	stg	%r2,__SF_SIE_CONTROL_PHYS(%r15)	# save sie block physical..
189	stg	%r3,__SF_SIE_CONTROL(%r15)	# ...and virtual addresses
190	stg	%r4,__SF_SIE_SAVEAREA(%r15)	# save guest register save area
191	stg	%r5,__SF_SIE_GUEST_ASCE(%r15)	# save guest asce
192	xc	__SF_SIE_REASON(8,%r15),__SF_SIE_REASON(%r15) # reason code = 0
193	mvc	__SF_SIE_FLAGS(8,%r15),__TI_flags(%r14) # copy thread flags
194	lmg	%r0,%r13,0(%r4)			# load guest gprs 0-13
195	mvi	__TI_sie(%r14),1
196	stosm	__SF_SIE_IRQ(%r15),0x03		# enable interrupts
197	lctlg	%c1,%c1,__SF_SIE_GUEST_ASCE(%r15) # load primary asce
198	lg	%r14,__SF_SIE_CONTROL(%r15)	# get control block pointer
199	oi	__SIE_PROG0C+3(%r14),1		# we are going into SIE now
200	tm	__SIE_PROG20+3(%r14),3		# last exit...
201	jnz	.Lsie_skip
202	lg	%r14,__SF_SIE_CONTROL_PHYS(%r15)	# get sie block phys addr
203	BPEXIT	__SF_SIE_FLAGS(%r15),_TIF_ISOLATE_BP_GUEST
204.Lsie_entry:
205	sie	0(%r14)
206# Let the next instruction be NOP to avoid triggering a machine check
207# and handling it in a guest as result of the instruction execution.
208	nopr	7
209.Lsie_leave:
210	BPOFF
211	BPENTER	__SF_SIE_FLAGS(%r15),_TIF_ISOLATE_BP_GUEST
212.Lsie_skip:
213	lg	%r14,__SF_SIE_CONTROL(%r15)	# get control block pointer
214	ni	__SIE_PROG0C+3(%r14),0xfe	# no longer in SIE
215	GET_LC	%r14
216	lctlg	%c1,%c1,__LC_USER_ASCE(%r14)	# load primary asce
217	lg	%r14,__LC_CURRENT(%r14)
218	mvi	__TI_sie(%r14),0
219SYM_INNER_LABEL(sie_exit, SYM_L_GLOBAL)
220	stnsm	__SF_SIE_IRQ(%r15),0xfc		# disable interrupts
221	lg	%r14,__SF_SIE_SAVEAREA(%r15)	# load guest register save area
222	stmg	%r0,%r13,0(%r14)		# save guest gprs 0-13
223	xgr	%r0,%r0				# clear guest registers to
224	xgr	%r1,%r1				# prevent speculative use
225	xgr	%r3,%r3
226	xgr	%r4,%r4
227	xgr	%r5,%r5
228	lmg	%r6,%r14,__SF_GPRS(%r15)	# restore kernel registers
229	lg	%r2,__SF_SIE_REASON(%r15)	# return exit reason code
230	BR_EX	%r14
231SYM_FUNC_END(__sie64a)
232EXPORT_SYMBOL(__sie64a)
233EXPORT_SYMBOL(sie_exit)
234#endif
235
236/*
237 * SVC interrupt handler routine. System calls are synchronous events and
238 * are entered with interrupts disabled.
239 */
240
241SYM_CODE_START(system_call)
242	STMG_LC	%r8,%r15,__LC_SAVE_AREA
243	GET_LC	%r13
244	stpt	__LC_SYS_ENTER_TIMER(%r13)
245	BPOFF
246	lghi	%r14,0
247.Lsysc_per:
248	STBEAR	__LC_LAST_BREAK(%r13)
249	lg	%r15,__LC_KERNEL_STACK(%r13)
250	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
251	stmg	%r0,%r7,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
252	# clear user controlled register to prevent speculative use
253	xgr	%r0,%r0
254	xgr	%r1,%r1
255	xgr	%r4,%r4
256	xgr	%r5,%r5
257	xgr	%r6,%r6
258	xgr	%r7,%r7
259	xgr	%r8,%r8
260	xgr	%r9,%r9
261	xgr	%r10,%r10
262	xgr	%r11,%r11
263	xgr	%r12,%r12
264	la	%r2,STACK_FRAME_OVERHEAD(%r15)	# pointer to pt_regs
265	mvc	__PT_R8(64,%r2),__LC_SAVE_AREA(%r13)
266	MBEAR	%r2,%r13
267	lgr	%r3,%r14
268	brasl	%r14,__do_syscall
269	STACKLEAK_ERASE
270	mvc	__LC_RETURN_PSW(16,%r13),STACK_FRAME_OVERHEAD+__PT_PSW(%r15)
271	BPON
272	LBEAR	STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15)
273	stpt	__LC_EXIT_TIMER(%r13)
274	lmg	%r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
275	LPSWEY	__LC_RETURN_PSW,__LC_RETURN_LPSWE
276SYM_CODE_END(system_call)
277
278#
279# a new process exits the kernel with ret_from_fork
280#
281SYM_CODE_START(ret_from_fork)
282	lgr	%r3,%r11
283	brasl	%r14,__ret_from_fork
284	STACKLEAK_ERASE
285	GET_LC	%r13
286	mvc	__LC_RETURN_PSW(16,%r13),STACK_FRAME_OVERHEAD+__PT_PSW(%r15)
287	BPON
288	LBEAR	STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15)
289	stpt	__LC_EXIT_TIMER(%r13)
290	lmg	%r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
291	LPSWEY	__LC_RETURN_PSW,__LC_RETURN_LPSWE
292SYM_CODE_END(ret_from_fork)
293
294/*
295 * Program check handler routine
296 */
297
298SYM_CODE_START(pgm_check_handler)
299	STMG_LC	%r8,%r15,__LC_SAVE_AREA
300	GET_LC	%r13
301	stpt	__LC_SYS_ENTER_TIMER(%r13)
302	BPOFF
303	lmg	%r8,%r9,__LC_PGM_OLD_PSW(%r13)
304	xgr	%r10,%r10
305	tmhh	%r8,0x0001		# coming from user space?
306	jo	3f			# -> fault in user space
307#if IS_ENABLED(CONFIG_KVM)
308	lg	%r11,__LC_CURRENT(%r13)
309	tm	__TI_sie(%r11),0xff
310	jz	1f
311	BPENTER	__SF_SIE_FLAGS(%r15),_TIF_ISOLATE_BP_GUEST
312	SIEEXIT __SF_SIE_CONTROL(%r15),%r13
313	lghi	%r10,_PIF_GUEST_FAULT
314#endif
3151:	tmhh	%r8,0x4000		# PER bit set in old PSW ?
316	jnz	2f			# -> enabled, can't be a double fault
317	tm	__LC_PGM_ILC+3(%r13),0x80	# check for per exception
318	jnz	.Lpgm_svcper		# -> single stepped svc
3192:	aghi	%r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
320	# CHECK_VMAP_STACK branches to stack_invalid or 4f
321	CHECK_VMAP_STACK __LC_SAVE_AREA,%r13,4f
3223:	lg	%r15,__LC_KERNEL_STACK(%r13)
3234:	la	%r11,STACK_FRAME_OVERHEAD(%r15)
324	stg	%r10,__PT_FLAGS(%r11)
325	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
326	stmg	%r0,%r7,__PT_R0(%r11)
327	mvc	__PT_R8(64,%r11),__LC_SAVE_AREA(%r13)
328	mvc	__PT_LAST_BREAK(8,%r11),__LC_PGM_LAST_BREAK(%r13)
329	stmg	%r8,%r9,__PT_PSW(%r11)
330	# clear user controlled registers to prevent speculative use
331	xgr	%r0,%r0
332	xgr	%r1,%r1
333	xgr	%r3,%r3
334	xgr	%r4,%r4
335	xgr	%r5,%r5
336	xgr	%r6,%r6
337	xgr	%r7,%r7
338	xgr	%r12,%r12
339	lgr	%r2,%r11
340	brasl	%r14,__do_pgm_check
341	tmhh	%r8,0x0001		# returning to user space?
342	jno	.Lpgm_exit_kernel
343	STACKLEAK_ERASE
344	BPON
345	stpt	__LC_EXIT_TIMER(%r13)
346.Lpgm_exit_kernel:
347	mvc	__LC_RETURN_PSW(16,%r13),STACK_FRAME_OVERHEAD+__PT_PSW(%r15)
348	LBEAR	STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15)
349	lmg	%r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
350	LPSWEY	__LC_RETURN_PSW,__LC_RETURN_LPSWE
351
352#
353# single stepped system call
354#
355.Lpgm_svcper:
356	mvc	__LC_RETURN_PSW(8,%r13),__LC_SVC_NEW_PSW(%r13)
357	larl	%r14,.Lsysc_per
358	stg	%r14,__LC_RETURN_PSW+8(%r13)
359	lghi	%r14,1
360	LBEAR	__LC_PGM_LAST_BREAK(%r13)
361	LPSWEY	__LC_RETURN_PSW,__LC_RETURN_LPSWE # branch to .Lsysc_per
362SYM_CODE_END(pgm_check_handler)
363
364/*
365 * Interrupt handler macro used for external and IO interrupts.
366 */
367.macro INT_HANDLER name,lc_old_psw,handler
368SYM_CODE_START(\name)
369	STMG_LC	%r8,%r15,__LC_SAVE_AREA
370	GET_LC	%r13
371	stckf	__LC_INT_CLOCK(%r13)
372	stpt	__LC_SYS_ENTER_TIMER(%r13)
373	STBEAR	__LC_LAST_BREAK(%r13)
374	BPOFF
375	lmg	%r8,%r9,\lc_old_psw(%r13)
376	tmhh	%r8,0x0001			# interrupting from user ?
377	jnz	1f
378#if IS_ENABLED(CONFIG_KVM)
379	lg	%r10,__LC_CURRENT(%r13)
380	tm	__TI_sie(%r10),0xff
381	jz	0f
382	BPENTER	__SF_SIE_FLAGS(%r15),_TIF_ISOLATE_BP_GUEST
383	SIEEXIT __SF_SIE_CONTROL(%r15),%r13
384#endif
3850:	aghi	%r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
386	j	2f
3871:	lg	%r15,__LC_KERNEL_STACK(%r13)
3882:	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
389	la	%r11,STACK_FRAME_OVERHEAD(%r15)
390	stmg	%r0,%r7,__PT_R0(%r11)
391	# clear user controlled registers to prevent speculative use
392	xgr	%r0,%r0
393	xgr	%r1,%r1
394	xgr	%r3,%r3
395	xgr	%r4,%r4
396	xgr	%r5,%r5
397	xgr	%r6,%r6
398	xgr	%r7,%r7
399	xgr	%r10,%r10
400	xgr	%r12,%r12
401	xc	__PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
402	mvc	__PT_R8(64,%r11),__LC_SAVE_AREA(%r13)
403	MBEAR	%r11,%r13
404	stmg	%r8,%r9,__PT_PSW(%r11)
405	lgr	%r2,%r11		# pass pointer to pt_regs
406	brasl	%r14,\handler
407	mvc	__LC_RETURN_PSW(16,%r13),__PT_PSW(%r11)
408	tmhh	%r8,0x0001		# returning to user ?
409	jno	2f
410	STACKLEAK_ERASE
411	BPON
412	stpt	__LC_EXIT_TIMER(%r13)
4132:	LBEAR	__PT_LAST_BREAK(%r11)
414	lmg	%r0,%r15,__PT_R0(%r11)
415	LPSWEY	__LC_RETURN_PSW,__LC_RETURN_LPSWE
416SYM_CODE_END(\name)
417.endm
418
419	.section .irqentry.text, "ax"
420
421INT_HANDLER ext_int_handler,__LC_EXT_OLD_PSW,do_ext_irq
422INT_HANDLER io_int_handler,__LC_IO_OLD_PSW,do_io_irq
423
424	.section .kprobes.text, "ax"
425
426/*
427 * Machine check handler routines
428 */
429SYM_CODE_START(mcck_int_handler)
430	BPOFF
431	GET_LC	%r13
432	lmg	%r8,%r9,__LC_MCK_OLD_PSW(%r13)
433	TSTMSK	__LC_MCCK_CODE(%r13),MCCK_CODE_SYSTEM_DAMAGE
434	jo	.Lmcck_panic		# yes -> rest of mcck code invalid
435	TSTMSK	__LC_MCCK_CODE(%r13),MCCK_CODE_CR_VALID
436	jno	.Lmcck_panic		# control registers invalid -> panic
437	ptlb
438	lay	%r14,__LC_CPU_TIMER_SAVE_AREA(%r13)
439	mvc	__LC_MCCK_ENTER_TIMER(8,%r13),0(%r14)
440	TSTMSK	__LC_MCCK_CODE(%r13),MCCK_CODE_CPU_TIMER_VALID
441	jo	3f
442	la	%r14,__LC_SYS_ENTER_TIMER(%r13)
443	clc	0(8,%r14),__LC_EXIT_TIMER(%r13)
444	jl	1f
445	la	%r14,__LC_EXIT_TIMER(%r13)
4461:	clc	0(8,%r14),__LC_LAST_UPDATE_TIMER(%r13)
447	jl	2f
448	la	%r14,__LC_LAST_UPDATE_TIMER(%r13)
4492:	spt	0(%r14)
450	mvc	__LC_MCCK_ENTER_TIMER(8,%r13),0(%r14)
4513:	TSTMSK	__LC_MCCK_CODE(%r13),MCCK_CODE_PSW_MWP_VALID
452	jno	.Lmcck_panic
453	tmhh	%r8,0x0001		# interrupting from user ?
454	jnz	.Lmcck_user
455	TSTMSK	__LC_MCCK_CODE(%r13),MCCK_CODE_PSW_IA_VALID
456	jno	.Lmcck_panic
457#if IS_ENABLED(CONFIG_KVM)
458	lg	%r10,__LC_CURRENT(%r13)
459	tm	__TI_sie(%r10),0xff
460	jz	.Lmcck_user
461	# Need to compare the address instead of __TI_SIE flag.
462	# Otherwise there would be a race between setting the flag
463	# and entering SIE (or leaving and clearing the flag). This
464	# would cause machine checks targeted at the guest to be
465	# handled by the host.
466	larl	%r14,.Lsie_entry
467	clgrjl	%r9,%r14, 4f
468	larl	%r14,.Lsie_leave
469	clgrjhe	%r9,%r14, 4f
470	lg	%r10,__LC_PCPU(%r13)
471	oi	__PCPU_FLAGS+7(%r10), _CIF_MCCK_GUEST
4724:	BPENTER	__SF_SIE_FLAGS(%r15),_TIF_ISOLATE_BP_GUEST
473	SIEEXIT __SF_SIE_CONTROL(%r15),%r13
474#endif
475.Lmcck_user:
476	lg	%r15,__LC_MCCK_STACK(%r13)
477	la	%r11,STACK_FRAME_OVERHEAD(%r15)
478	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
479	lay	%r14,__LC_GPREGS_SAVE_AREA(%r13)
480	mvc	__PT_R0(128,%r11),0(%r14)
481	# clear user controlled registers to prevent speculative use
482	xgr	%r0,%r0
483	xgr	%r1,%r1
484	xgr	%r3,%r3
485	xgr	%r4,%r4
486	xgr	%r5,%r5
487	xgr	%r6,%r6
488	xgr	%r7,%r7
489	xgr	%r10,%r10
490	xgr	%r12,%r12
491	stmg	%r8,%r9,__PT_PSW(%r11)
492	xc	__PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
493	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
494	lgr	%r2,%r11		# pass pointer to pt_regs
495	brasl	%r14,s390_do_machine_check
496	lmg	%r0,%r10,__PT_R0(%r11)
497	mvc	__LC_RETURN_MCCK_PSW(16,%r13),__PT_PSW(%r11) # move return PSW
498	tm	__LC_RETURN_MCCK_PSW+1(%r13),0x01 # returning to user ?
499	jno	0f
500	BPON
501	stpt	__LC_EXIT_TIMER(%r13)
5020:	ALTERNATIVE "brcl 0,0", __stringify(lay %r12,__LC_LAST_BREAK_SAVE_AREA(%r13)),\
503		ALT_FACILITY(193)
504	LBEAR	0(%r12)
505	lmg	%r11,%r15,__PT_R11(%r11)
506	LPSWEY	__LC_RETURN_MCCK_PSW,__LC_RETURN_MCCK_LPSWE
507
508.Lmcck_panic:
509	/*
510	 * Iterate over all possible CPU addresses in the range 0..0xffff
511	 * and stop each CPU using signal processor. Use compare and swap
512	 * to allow just one CPU-stopper and prevent concurrent CPUs from
513	 * stopping each other while leaving the others running.
514	 */
515	lhi	%r5,0
516	lhi	%r6,1
517	larl	%r7,stop_lock
518	cs	%r5,%r6,0(%r7)		# single CPU-stopper only
519	jnz	4f
520	larl	%r7,this_cpu
521	stap	0(%r7)			# this CPU address
522	lh	%r4,0(%r7)
523	nilh	%r4,0
524	lhi	%r0,1
525	sll	%r0,16			# CPU counter
526	lhi	%r3,0			# next CPU address
5270:	cr	%r3,%r4
528	je	2f
5291:	sigp	%r1,%r3,SIGP_STOP	# stop next CPU
530	brc	SIGP_CC_BUSY,1b
5312:	ahi	%r3,1
532	brct	%r0,0b
5333:	sigp	%r1,%r4,SIGP_STOP	# stop this CPU
534	brc	SIGP_CC_BUSY,3b
5354:	j	4b
536SYM_CODE_END(mcck_int_handler)
537
538SYM_CODE_START(restart_int_handler)
539	ALTERNATIVE "nop", "lpp _LPP_OFFSET", ALT_FACILITY(40)
540	stg	%r15,__LC_SAVE_AREA_RESTART
541	TSTMSK	__LC_RESTART_FLAGS,RESTART_FLAG_CTLREGS,4
542	jz	0f
543	lctlg	%c0,%c15,__LC_CREGS_SAVE_AREA
5440:	larl	%r15,daton_psw
545	lpswe	0(%r15)				# turn dat on, keep irqs off
546.Ldaton:
547	GET_LC	%r15
548	lg	%r15,__LC_RESTART_STACK(%r15)
549	xc	STACK_FRAME_OVERHEAD(__PT_SIZE,%r15),STACK_FRAME_OVERHEAD(%r15)
550	stmg	%r0,%r14,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
551	GET_LC	%r13
552	mvc	STACK_FRAME_OVERHEAD+__PT_R15(8,%r15),__LC_SAVE_AREA_RESTART(%r13)
553	mvc	STACK_FRAME_OVERHEAD+__PT_PSW(16,%r15),__LC_RST_OLD_PSW(%r13)
554	xc	0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
555	lg	%r1,__LC_RESTART_FN(%r13)	# load fn, parm & source cpu
556	lg	%r2,__LC_RESTART_DATA(%r13)
557	lgf	%r3,__LC_RESTART_SOURCE(%r13)
558	ltgr	%r3,%r3				# test source cpu address
559	jm	1f				# negative -> skip source stop
5600:	sigp	%r4,%r3,SIGP_SENSE		# sigp sense to source cpu
561	brc	10,0b				# wait for status stored
5621:	basr	%r14,%r1			# call function
563	stap	__SF_EMPTY(%r15)		# store cpu address
564	llgh	%r3,__SF_EMPTY(%r15)
5652:	sigp	%r4,%r3,SIGP_STOP		# sigp stop to current cpu
566	brc	2,2b
5673:	j	3b
568SYM_CODE_END(restart_int_handler)
569
570	__INIT
571SYM_CODE_START(early_pgm_check_handler)
572	STMG_LC %r8,%r15,__LC_SAVE_AREA
573	GET_LC	%r13
574	aghi	%r15,-(STACK_FRAME_OVERHEAD+__PT_SIZE)
575	la	%r11,STACK_FRAME_OVERHEAD(%r15)
576	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
577	stmg	%r0,%r7,__PT_R0(%r11)
578	mvc	__PT_PSW(16,%r11),__LC_PGM_OLD_PSW(%r13)
579	mvc	__PT_R8(64,%r11),__LC_SAVE_AREA(%r13)
580	lgr	%r2,%r11
581	brasl	%r14,__do_early_pgm_check
582	mvc	__LC_RETURN_PSW(16,%r13),STACK_FRAME_OVERHEAD+__PT_PSW(%r15)
583	lmg	%r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
584	LPSWEY	__LC_RETURN_PSW,__LC_RETURN_LPSWE
585SYM_CODE_END(early_pgm_check_handler)
586	__FINIT
587
588	.section .kprobes.text, "ax"
589
590/*
591 * The synchronous or the asynchronous stack pointer is invalid. We are dead.
592 * No need to properly save the registers, we are going to panic anyway.
593 * Setup a pt_regs so that show_trace can provide a good call trace.
594 */
595SYM_CODE_START(stack_invalid)
596	GET_LC	%r15
597	lg	%r15,__LC_NODAT_STACK(%r15) # change to panic stack
598	la	%r11,STACK_FRAME_OVERHEAD(%r15)
599	stmg	%r0,%r7,__PT_R0(%r11)
600	stmg	%r8,%r9,__PT_PSW(%r11)
601	mvc	__PT_R8(64,%r11),0(%r14)
602	GET_LC	%r2
603	mvc	__PT_ORIG_GPR2(8,%r11),__LC_PGM_LAST_BREAK(%r2)
604	xc	__SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
605	lgr	%r2,%r11		# pass pointer to pt_regs
606	jg	kernel_stack_invalid
607SYM_CODE_END(stack_invalid)
608
609	.section .data, "aw"
610	.balign	4
611SYM_DATA_LOCAL(stop_lock,	.long 0)
612SYM_DATA_LOCAL(this_cpu,	.short 0)
613	.balign	8
614SYM_DATA_START_LOCAL(daton_psw)
615	.quad	PSW_KERNEL_BITS
616	.quad	.Ldaton
617SYM_DATA_END(daton_psw)