processor.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 *  S390 version
  4 *    Copyright IBM Corp. 1999
  5 *    Author(s): Hartmut Penner (hp@de.ibm.com),
  6 *               Martin Schwidefsky (schwidefsky@de.ibm.com)
  7 *
  8 *  Derived from "include/asm-i386/processor.h"
  9 *    Copyright (C) 1994, Linus Torvalds
 10 */
 11
 12#ifndef __ASM_S390_PROCESSOR_H
 13#define __ASM_S390_PROCESSOR_H
 14
 15#include <linux/bits.h>
 16
 17#define CIF_NOHZ_DELAY		2	/* delay HZ disable for a tick */
 18#define CIF_ENABLED_WAIT	5	/* in enabled wait state */
 19#define CIF_MCCK_GUEST		6	/* machine check happening in guest */
 20#define CIF_DEDICATED_CPU	7	/* this CPU is dedicated */
 21
 22#define _CIF_NOHZ_DELAY		BIT(CIF_NOHZ_DELAY)
 23#define _CIF_ENABLED_WAIT	BIT(CIF_ENABLED_WAIT)
 24#define _CIF_MCCK_GUEST		BIT(CIF_MCCK_GUEST)
 25#define _CIF_DEDICATED_CPU	BIT(CIF_DEDICATED_CPU)
 26
 27#define RESTART_FLAG_CTLREGS	_AC(1 << 0, U)
 28
 29#ifndef __ASSEMBLER__
 30
 31#include <linux/cpumask.h>
 32#include <linux/linkage.h>
 33#include <linux/irqflags.h>
 34#include <linux/bitops.h>
 35#include <asm/fpu-types.h>
 36#include <asm/cpu.h>
 37#include <asm/page.h>
 38#include <asm/ptrace.h>
 39#include <asm/setup.h>
 40#include <asm/runtime_instr.h>
 41#include <asm/irqflags.h>
 42#include <asm/alternative.h>
 43#include <asm/fault.h>
 44
 45struct pcpu {
 46	unsigned long ec_mask;		/* bit mask for ec_xxx functions */
 47	unsigned long ec_clk;		/* sigp timestamp for ec_xxx */
 48	unsigned long flags;		/* per CPU flags */
 49	unsigned long capacity;		/* cpu capacity for scheduler */
 50	signed char state;		/* physical cpu state */
 51	signed char polarization;	/* physical polarization */
 52	u16 address;			/* physical cpu address */
 53};
 54
 55DECLARE_PER_CPU(struct pcpu, pcpu_devices);
 56
 57typedef long (*sys_call_ptr_t)(struct pt_regs *regs);
 58
 59static __always_inline struct pcpu *this_pcpu(void)
 60{
 61	return (struct pcpu *)(get_lowcore()->pcpu);
 62}
 63
 64static __always_inline void set_cpu_flag(int flag)
 65{
 66	set_bit(flag, &this_pcpu()->flags);
 67}
 68
 69static __always_inline void clear_cpu_flag(int flag)
 70{
 71	clear_bit(flag, &this_pcpu()->flags);
 72}
 73
 74static __always_inline bool test_cpu_flag(int flag)
 75{
 76	return test_bit(flag, &this_pcpu()->flags);
 77}
 78
 79static __always_inline bool test_and_set_cpu_flag(int flag)
 80{
 81	return test_and_set_bit(flag, &this_pcpu()->flags);
 82}
 83
 84static __always_inline bool test_and_clear_cpu_flag(int flag)
 85{
 86	return test_and_clear_bit(flag, &this_pcpu()->flags);
 87}
 88
 89/*
 90 * Test CIF flag of another CPU. The caller needs to ensure that
 91 * CPU hotplug can not happen, e.g. by disabling preemption.
 92 */
 93static __always_inline bool test_cpu_flag_of(int flag, int cpu)
 94{
 95	return test_bit(flag, &per_cpu(pcpu_devices, cpu).flags);
 96}
 97
 98#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
 99
100static inline void get_cpu_id(struct cpuid *ptr)
101{
102	asm volatile("stidp %0" : "=Q" (*ptr));
103}
104
105static __always_inline unsigned long get_cpu_timer(void)
106{
107	unsigned long timer;
108
109	asm volatile("stpt	%[timer]" : [timer] "=Q" (timer));
110	return timer;
111}
112
113void s390_adjust_jiffies(void);
114void s390_update_cpu_mhz(void);
115void cpu_detect_mhz_feature(void);
116
117extern const struct seq_operations cpuinfo_op;
118extern void execve_tail(void);
119unsigned long vdso_text_size(void);
120unsigned long vdso_size(void);
121
122#define TASK_SIZE		(TASK_SIZE_MAX)
123#define TASK_UNMAPPED_BASE	(_REGION2_SIZE >> 1)
124#define TASK_SIZE_MAX		(-PAGE_SIZE)
125
126#define VDSO_BASE		(STACK_TOP + PAGE_SIZE)
127#define VDSO_LIMIT		(_REGION2_SIZE)
128#define STACK_TOP		(VDSO_LIMIT - vdso_size() - PAGE_SIZE)
129#define STACK_TOP_MAX		(_REGION2_SIZE - vdso_size() - PAGE_SIZE)
130
131#define HAVE_ARCH_PICK_MMAP_LAYOUT
132
133#define __stackleak_poison __stackleak_poison
134static __always_inline void __stackleak_poison(unsigned long erase_low,
135					       unsigned long erase_high,
136					       unsigned long poison)
137{
138	unsigned long tmp, count;
139
140	count = erase_high - erase_low;
141	if (!count)
142		return;
143	asm volatile(
144		"	cghi	%[count],8\n"
145		"	je	2f\n"
146		"	aghi	%[count],-(8+1)\n"
147		"	srlg	%[tmp],%[count],8\n"
148		"	ltgr	%[tmp],%[tmp]\n"
149		"	jz	1f\n"
150		"0:	stg	%[poison],0(%[addr])\n"
151		"	mvc	8(256-8,%[addr]),0(%[addr])\n"
152		"	la	%[addr],256(%[addr])\n"
153		"	brctg	%[tmp],0b\n"
154		"1:	stg	%[poison],0(%[addr])\n"
155		"	exrl	%[count],3f\n"
156		"	j	4f\n"
157		"2:	stg	%[poison],0(%[addr])\n"
158		"	j	4f\n"
159		"3:	mvc	8(1,%[addr]),0(%[addr])\n"
160		"4:"
161		: [addr] "+&a" (erase_low), [count] "+&a" (count), [tmp] "=&a" (tmp)
162		: [poison] "d" (poison)
163		: "memory", "cc"
164		);
165}
166
167/*
168 * Thread structure
169 */
170struct thread_struct {
171	unsigned int  acrs[NUM_ACRS];
172	unsigned long ksp;			/* kernel stack pointer */
173	unsigned long user_timer;		/* task cputime in user space */
174	unsigned long guest_timer;		/* task cputime in kvm guest */
175	unsigned long system_timer;		/* task cputime in kernel space */
176	unsigned long hardirq_timer;		/* task cputime in hardirq context */
177	unsigned long softirq_timer;		/* task cputime in softirq context */
178	union teid gmap_teid;			/* address and flags of last gmap fault */
179	unsigned int gmap_int_code;		/* int code of last gmap fault */
180	int ufpu_flags;				/* user fpu flags */
181	int kfpu_flags;				/* kernel fpu flags */
182
183	/* Per-thread information related to debugging */
184	struct per_regs per_user;		/* User specified PER registers */
185	struct per_event per_event;		/* Cause of the last PER trap */
186	unsigned long per_flags;		/* Flags to control debug behavior */
187	unsigned int system_call;		/* system call number in signal */
188	unsigned long last_break;		/* last breaking-event-address. */
189	/* pfault_wait is used to block the process on a pfault event */
190	unsigned long pfault_wait;
191	struct list_head list;
192	/* cpu runtime instrumentation */
193	struct runtime_instr_cb *ri_cb;
194	struct gs_cb *gs_cb;			/* Current guarded storage cb */
195	struct gs_cb *gs_bc_cb;			/* Broadcast guarded storage cb */
196	struct pgm_tdb trap_tdb;		/* Transaction abort diagnose block */
197	struct fpu ufpu;			/* User FP and VX register save area */
198	struct fpu kfpu;			/* Kernel FP and VX register save area */
199};
200
201/* Flag to disable transactions. */
202#define PER_FLAG_NO_TE			1UL
203/* Flag to enable random transaction aborts. */
204#define PER_FLAG_TE_ABORT_RAND		2UL
205/* Flag to specify random transaction abort mode:
206 * - abort each transaction at a random instruction before TEND if set.
207 * - abort random transactions at a random instruction if cleared.
208 */
209#define PER_FLAG_TE_ABORT_RAND_TEND	4UL
210
211typedef struct thread_struct thread_struct;
212
213#define ARCH_MIN_TASKALIGN	8
214
215#define INIT_THREAD {							\
216	.ksp = sizeof(init_stack) + (unsigned long) &init_stack,	\
217	.last_break = 1,						\
218}
219
220/*
221 * Do necessary setup to start up a new thread.
222 */
223#define start_thread(regs, new_psw, new_stackp) do {			\
224	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;	\
225	regs->psw.addr	= new_psw;					\
226	regs->gprs[15]	= new_stackp;					\
227	execve_tail();							\
228} while (0)
229
230#define start_thread31(regs, new_psw, new_stackp) do {			\
231	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_BA;			\
232	regs->psw.addr	= new_psw;					\
233	regs->gprs[15]	= new_stackp;					\
234	execve_tail();							\
235} while (0)
236
237struct task_struct;
238struct mm_struct;
239struct seq_file;
240struct pt_regs;
241
242void show_registers(struct pt_regs *regs);
243void show_cacheinfo(struct seq_file *m);
244
245/* Free guarded storage control block */
246void guarded_storage_release(struct task_struct *tsk);
247void gs_load_bc_cb(struct pt_regs *regs);
248
249unsigned long __get_wchan(struct task_struct *p);
250#define task_pt_regs(tsk) ((struct pt_regs *) \
251        (task_stack_page(tsk) + THREAD_SIZE) - 1)
252#define KSTK_EIP(tsk)	(task_pt_regs(tsk)->psw.addr)
253#define KSTK_ESP(tsk)	(task_pt_regs(tsk)->gprs[15])
254
255/* Has task runtime instrumentation enabled ? */
256#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
257
258/* avoid using global register due to gcc bug in versions < 8.4 */
259#define current_stack_pointer (__current_stack_pointer())
260
261static __always_inline unsigned long __current_stack_pointer(void)
262{
263	unsigned long sp;
264
265	asm volatile("lgr %0,15" : "=d" (sp));
266	return sp;
267}
268
269static __always_inline bool on_thread_stack(void)
270{
271	unsigned long ksp = get_lowcore()->kernel_stack;
272
273	return !((ksp ^ current_stack_pointer) & ~(THREAD_SIZE - 1));
274}
275
276static __always_inline unsigned short stap(void)
277{
278	unsigned short cpu_address;
279
280	asm volatile("stap %0" : "=Q" (cpu_address));
281	return cpu_address;
282}
283
284#define cpu_relax() barrier()
285
286#define ECAG_CACHE_ATTRIBUTE	0
287#define ECAG_CPU_ATTRIBUTE	1
288
289static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
290{
291	unsigned long val;
292
293	asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm));
294	return val;
295}
296
297static inline void psw_set_key(unsigned int key)
298{
299	asm volatile("spka 0(%0)" : : "d" (key));
300}
301
302/*
303 * Set PSW to specified value.
304 */
305static inline void __load_psw(psw_t psw)
306{
307	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
308}
309
310/*
311 * Set PSW mask to specified value, while leaving the
312 * PSW addr pointing to the next instruction.
313 */
314static __always_inline void __load_psw_mask(unsigned long mask)
315{
316	psw_t psw __uninitialized;
317	unsigned long addr;
318
319	psw.mask = mask;
320
321	asm volatile(
322		"	larl	%0,1f\n"
323		"	stg	%0,%1\n"
324		"	lpswe	%2\n"
325		"1:"
326		: "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");
327}
328
329/*
330 * Extract current PSW mask
331 */
332static inline unsigned long __extract_psw(void)
333{
334	unsigned int reg1, reg2;
335
336	asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
337	return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
338}
339
340static inline unsigned long __local_mcck_save(void)
341{
342	unsigned long mask = __extract_psw();
343
344	__load_psw_mask(mask & ~PSW_MASK_MCHECK);
345	return mask & PSW_MASK_MCHECK;
346}
347
348#define local_mcck_save(mflags)			\
349do {						\
350	typecheck(unsigned long, mflags);	\
351	mflags = __local_mcck_save();		\
352} while (0)
353
354static inline void local_mcck_restore(unsigned long mflags)
355{
356	unsigned long mask = __extract_psw();
357
358	mask &= ~PSW_MASK_MCHECK;
359	__load_psw_mask(mask | mflags);
360}
361
362static inline void local_mcck_disable(void)
363{
364	__local_mcck_save();
365}
366
367static inline void local_mcck_enable(void)
368{
369	__load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
370}
371
372/*
373 * Rewind PSW instruction address by specified number of bytes.
374 */
375static inline unsigned long __rewind_psw(psw_t psw, long ilen)
376{
377	unsigned long mask;
378
379	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
380	       (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
381					  (1UL << 24) - 1;
382	return (psw.addr - ilen) & mask;
383}
384
385static inline unsigned long __forward_psw(psw_t psw, long ilen)
386{
387	return __rewind_psw(psw, -ilen);
388}
389
390/*
391 * Function to drop a processor into disabled wait state
392 */
393static __always_inline void __noreturn disabled_wait(void)
394{
395	psw_t psw;
396
397	psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
398	psw.addr = _THIS_IP_;
399	__load_psw(psw);
400	while (1);
401}
402
403#define ARCH_LOW_ADDRESS_LIMIT	0x7fffffffUL
404
405static __always_inline bool regs_irqs_disabled(struct pt_regs *regs)
406{
407	return arch_irqs_disabled_flags(regs->psw.mask);
408}
409
410static __always_inline void bpon(void)
411{
412	asm_inline volatile(
413		ALTERNATIVE("	nop\n",
414			    "	.insn	rrf,0xb2e80000,0,0,13,0\n",
415			    ALT_SPEC(82))
416		);
417}
418
419#endif /* __ASSEMBLER__ */
420
421#endif /* __ASM_S390_PROCESSOR_H */