irq.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) 2012 Regents of the University of California
  4 * Copyright (C) 2017 SiFive
  5 * Copyright (C) 2018 Christoph Hellwig
  6 */
  7
  8#include <linux/interrupt.h>
  9#include <linux/irqchip.h>
 10#include <linux/irqdomain.h>
 11#include <linux/module.h>
 12#include <linux/scs.h>
 13#include <linux/seq_file.h>
 14#include <asm/sbi.h>
 15#include <asm/smp.h>
 16#include <asm/softirq_stack.h>
 17#include <asm/stacktrace.h>
 18
 19static struct fwnode_handle *(*__get_intc_node)(void);
 20
 21void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void))
 22{
 23	__get_intc_node = fn;
 24}
 25
 26struct fwnode_handle *riscv_get_intc_hwnode(void)
 27{
 28	if (__get_intc_node)
 29		return __get_intc_node();
 30
 31	return NULL;
 32}
 33EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode);
 34
 35/**
 36 * riscv_get_hart_index() - get hart index for interrupt delivery
 37 * @fwnode: interrupt controller node
 38 * @logical_index: index within the "interrupts-extended" property
 39 * @hart_index: filled with the hart index to use
 40 *
 41 * RISC-V uses term "hart index" for its interrupt controllers, for the
 42 * purpose of the interrupt routing to destination harts.
 43 * It may be arbitrary numbers assigned to each destination hart in context
 44 * of the particular interrupt domain.
 45 *
 46 * These numbers encoded in the optional property "riscv,hart-indexes"
 47 * that should contain hart index for each interrupt destination in the same
 48 * order as in the "interrupts-extended" property. If this property
 49 * not exist, it assumed equal to the logical index, i.e. index within the
 50 * "interrupts-extended" property.
 51 *
 52 * Return: error code
 53 */
 54int riscv_get_hart_index(struct fwnode_handle *fwnode, u32 logical_index,
 55			 u32 *hart_index)
 56{
 57	static const char *prop_hart_index = "riscv,hart-indexes";
 58	struct device_node *np = to_of_node(fwnode);
 59
 60	if (!np || !of_property_present(np, prop_hart_index)) {
 61		*hart_index = logical_index;
 62		return 0;
 63	}
 64
 65	return of_property_read_u32_index(np, prop_hart_index,
 66					  logical_index, hart_index);
 67}
 68
 69#ifdef CONFIG_IRQ_STACKS
 70#include <asm/irq_stack.h>
 71
 72DECLARE_PER_CPU(ulong *, irq_shadow_call_stack_ptr);
 73
 74#ifdef CONFIG_SHADOW_CALL_STACK
 75DEFINE_PER_CPU(ulong *, irq_shadow_call_stack_ptr);
 76#endif
 77
 78static void init_irq_scs(void)
 79{
 80	int cpu;
 81
 82	if (!scs_is_enabled())
 83		return;
 84
 85	for_each_possible_cpu(cpu)
 86		per_cpu(irq_shadow_call_stack_ptr, cpu) =
 87			scs_alloc(cpu_to_node(cpu));
 88}
 89
 90DEFINE_PER_CPU(ulong *, irq_stack_ptr);
 91
 92#ifdef CONFIG_VMAP_STACK
 93static void init_irq_stacks(void)
 94{
 95	int cpu;
 96	ulong *p;
 97
 98	for_each_possible_cpu(cpu) {
 99		p = arch_alloc_vmap_stack(IRQ_STACK_SIZE, cpu_to_node(cpu));
100		per_cpu(irq_stack_ptr, cpu) = p;
101	}
102}
103#else
104/* irq stack only needs to be 16 byte aligned - not IRQ_STACK_SIZE aligned. */
105DEFINE_PER_CPU_ALIGNED(ulong [IRQ_STACK_SIZE/sizeof(ulong)], irq_stack);
106
107static void init_irq_stacks(void)
108{
109	int cpu;
110
111	for_each_possible_cpu(cpu)
112		per_cpu(irq_stack_ptr, cpu) = per_cpu(irq_stack, cpu);
113}
114#endif /* CONFIG_VMAP_STACK */
115
116#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
117static void ___do_softirq(struct pt_regs *regs)
118{
119	__do_softirq();
120}
121
122void do_softirq_own_stack(void)
123{
124	if (on_thread_stack())
125		call_on_irq_stack(NULL, ___do_softirq);
126	else
127		__do_softirq();
128}
129#endif /* CONFIG_SOFTIRQ_ON_OWN_STACK */
130
131#else
132static void init_irq_scs(void) {}
133static void init_irq_stacks(void) {}
134#endif /* CONFIG_IRQ_STACKS */
135
136int arch_show_interrupts(struct seq_file *p, int prec)
137{
138	show_ipi_stats(p, prec);
139	return 0;
140}
141
142void __init init_IRQ(void)
143{
144	init_irq_scs();
145	init_irq_stacks();
146	irqchip_init();
147	if (!handle_arch_irq)
148		panic("No interrupt controller found.");
149	sbi_ipi_init();
150}