kvm.h

  1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
  2/*
  3 * Copyright (C) 2019 Western Digital Corporation or its affiliates.
  4 *
  5 * Authors:
  6 *     Anup Patel <anup.patel@wdc.com>
  7 */
  8
  9#ifndef __LINUX_KVM_RISCV_H
 10#define __LINUX_KVM_RISCV_H
 11
 12#ifndef __ASSEMBLER__
 13
 14#include <linux/types.h>
 15#include <asm/bitsperlong.h>
 16#include <asm/ptrace.h>
 17
 18#define __KVM_HAVE_IRQ_LINE
 19
 20#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
 21#define KVM_DIRTY_LOG_PAGE_OFFSET 64
 22
 23#define KVM_INTERRUPT_SET	-1U
 24#define KVM_INTERRUPT_UNSET	-2U
 25
 26#define KVM_EXIT_FAIL_ENTRY_NO_VSFILE	(1ULL << 0)
 27
 28/* for KVM_GET_REGS and KVM_SET_REGS */
 29struct kvm_regs {
 30};
 31
 32/* for KVM_GET_FPU and KVM_SET_FPU */
 33struct kvm_fpu {
 34};
 35
 36/* KVM Debug exit structure */
 37struct kvm_debug_exit_arch {
 38};
 39
 40/* for KVM_SET_GUEST_DEBUG */
 41struct kvm_guest_debug_arch {
 42};
 43
 44/* definition of registers in kvm_run */
 45struct kvm_sync_regs {
 46};
 47
 48/* for KVM_GET_SREGS and KVM_SET_SREGS */
 49struct kvm_sregs {
 50};
 51
 52/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
 53struct kvm_riscv_config {
 54	unsigned long isa;
 55	unsigned long zicbom_block_size;
 56	unsigned long mvendorid;
 57	unsigned long marchid;
 58	unsigned long mimpid;
 59	unsigned long zicboz_block_size;
 60	unsigned long satp_mode;
 61	unsigned long zicbop_block_size;
 62};
 63
 64/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
 65struct kvm_riscv_core {
 66	struct user_regs_struct regs;
 67	unsigned long mode;
 68};
 69
 70/* Possible privilege modes for kvm_riscv_core */
 71#define KVM_RISCV_MODE_S	1
 72#define KVM_RISCV_MODE_U	0
 73
 74/* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
 75struct kvm_riscv_csr {
 76	unsigned long sstatus;
 77	unsigned long sie;
 78	unsigned long stvec;
 79	unsigned long sscratch;
 80	unsigned long sepc;
 81	unsigned long scause;
 82	unsigned long stval;
 83	unsigned long sip;
 84	unsigned long satp;
 85	unsigned long scounteren;
 86	unsigned long senvcfg;
 87};
 88
 89/* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
 90struct kvm_riscv_aia_csr {
 91	unsigned long siselect;
 92	unsigned long iprio1;
 93	unsigned long iprio2;
 94	unsigned long sieh;
 95	unsigned long siph;
 96	unsigned long iprio1h;
 97	unsigned long iprio2h;
 98};
 99
100/* Smstateen CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
101struct kvm_riscv_smstateen_csr {
102	unsigned long sstateen0;
103};
104
105/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
106struct kvm_riscv_timer {
107	__u64 frequency;
108	__u64 time;
109	__u64 compare;
110	__u64 state;
111};
112
113/*
114 * ISA extension IDs specific to KVM. This is not the same as the host ISA
115 * extension IDs as that is internal to the host and should not be exposed
116 * to the guest. This should always be contiguous to keep the mapping simple
117 * in KVM implementation.
118 */
119enum KVM_RISCV_ISA_EXT_ID {
120	KVM_RISCV_ISA_EXT_A = 0,
121	KVM_RISCV_ISA_EXT_C,
122	KVM_RISCV_ISA_EXT_D,
123	KVM_RISCV_ISA_EXT_F,
124	KVM_RISCV_ISA_EXT_H,
125	KVM_RISCV_ISA_EXT_I,
126	KVM_RISCV_ISA_EXT_M,
127	KVM_RISCV_ISA_EXT_SVPBMT,
128	KVM_RISCV_ISA_EXT_SSTC,
129	KVM_RISCV_ISA_EXT_SVINVAL,
130	KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
131	KVM_RISCV_ISA_EXT_ZICBOM,
132	KVM_RISCV_ISA_EXT_ZICBOZ,
133	KVM_RISCV_ISA_EXT_ZBB,
134	KVM_RISCV_ISA_EXT_SSAIA,
135	KVM_RISCV_ISA_EXT_V,
136	KVM_RISCV_ISA_EXT_SVNAPOT,
137	KVM_RISCV_ISA_EXT_ZBA,
138	KVM_RISCV_ISA_EXT_ZBS,
139	KVM_RISCV_ISA_EXT_ZICNTR,
140	KVM_RISCV_ISA_EXT_ZICSR,
141	KVM_RISCV_ISA_EXT_ZIFENCEI,
142	KVM_RISCV_ISA_EXT_ZIHPM,
143	KVM_RISCV_ISA_EXT_SMSTATEEN,
144	KVM_RISCV_ISA_EXT_ZICOND,
145	KVM_RISCV_ISA_EXT_ZBC,
146	KVM_RISCV_ISA_EXT_ZBKB,
147	KVM_RISCV_ISA_EXT_ZBKC,
148	KVM_RISCV_ISA_EXT_ZBKX,
149	KVM_RISCV_ISA_EXT_ZKND,
150	KVM_RISCV_ISA_EXT_ZKNE,
151	KVM_RISCV_ISA_EXT_ZKNH,
152	KVM_RISCV_ISA_EXT_ZKR,
153	KVM_RISCV_ISA_EXT_ZKSED,
154	KVM_RISCV_ISA_EXT_ZKSH,
155	KVM_RISCV_ISA_EXT_ZKT,
156	KVM_RISCV_ISA_EXT_ZVBB,
157	KVM_RISCV_ISA_EXT_ZVBC,
158	KVM_RISCV_ISA_EXT_ZVKB,
159	KVM_RISCV_ISA_EXT_ZVKG,
160	KVM_RISCV_ISA_EXT_ZVKNED,
161	KVM_RISCV_ISA_EXT_ZVKNHA,
162	KVM_RISCV_ISA_EXT_ZVKNHB,
163	KVM_RISCV_ISA_EXT_ZVKSED,
164	KVM_RISCV_ISA_EXT_ZVKSH,
165	KVM_RISCV_ISA_EXT_ZVKT,
166	KVM_RISCV_ISA_EXT_ZFH,
167	KVM_RISCV_ISA_EXT_ZFHMIN,
168	KVM_RISCV_ISA_EXT_ZIHINTNTL,
169	KVM_RISCV_ISA_EXT_ZVFH,
170	KVM_RISCV_ISA_EXT_ZVFHMIN,
171	KVM_RISCV_ISA_EXT_ZFA,
172	KVM_RISCV_ISA_EXT_ZTSO,
173	KVM_RISCV_ISA_EXT_ZACAS,
174	KVM_RISCV_ISA_EXT_SSCOFPMF,
175	KVM_RISCV_ISA_EXT_ZIMOP,
176	KVM_RISCV_ISA_EXT_ZCA,
177	KVM_RISCV_ISA_EXT_ZCB,
178	KVM_RISCV_ISA_EXT_ZCD,
179	KVM_RISCV_ISA_EXT_ZCF,
180	KVM_RISCV_ISA_EXT_ZCMOP,
181	KVM_RISCV_ISA_EXT_ZAWRS,
182	KVM_RISCV_ISA_EXT_SMNPM,
183	KVM_RISCV_ISA_EXT_SSNPM,
184	KVM_RISCV_ISA_EXT_SVADE,
185	KVM_RISCV_ISA_EXT_SVADU,
186	KVM_RISCV_ISA_EXT_SVVPTC,
187	KVM_RISCV_ISA_EXT_ZABHA,
188	KVM_RISCV_ISA_EXT_ZICCRSE,
189	KVM_RISCV_ISA_EXT_ZAAMO,
190	KVM_RISCV_ISA_EXT_ZALRSC,
191	KVM_RISCV_ISA_EXT_ZICBOP,
192	KVM_RISCV_ISA_EXT_ZFBFMIN,
193	KVM_RISCV_ISA_EXT_ZVFBFMIN,
194	KVM_RISCV_ISA_EXT_ZVFBFWMA,
195	KVM_RISCV_ISA_EXT_MAX,
196};
197
198/*
199 * SBI extension IDs specific to KVM. This is not the same as the SBI
200 * extension IDs defined by the RISC-V SBI specification.
201 */
202enum KVM_RISCV_SBI_EXT_ID {
203	KVM_RISCV_SBI_EXT_V01 = 0,
204	KVM_RISCV_SBI_EXT_TIME,
205	KVM_RISCV_SBI_EXT_IPI,
206	KVM_RISCV_SBI_EXT_RFENCE,
207	KVM_RISCV_SBI_EXT_SRST,
208	KVM_RISCV_SBI_EXT_HSM,
209	KVM_RISCV_SBI_EXT_PMU,
210	KVM_RISCV_SBI_EXT_EXPERIMENTAL,
211	KVM_RISCV_SBI_EXT_VENDOR,
212	KVM_RISCV_SBI_EXT_DBCN,
213	KVM_RISCV_SBI_EXT_STA,
214	KVM_RISCV_SBI_EXT_SUSP,
215	KVM_RISCV_SBI_EXT_FWFT,
216	KVM_RISCV_SBI_EXT_MPXY,
217	KVM_RISCV_SBI_EXT_MAX,
218};
219
220/* SBI STA extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
221struct kvm_riscv_sbi_sta {
222	unsigned long shmem_lo;
223	unsigned long shmem_hi;
224};
225
226struct kvm_riscv_sbi_fwft_feature {
227	unsigned long enable;
228	unsigned long flags;
229	unsigned long value;
230};
231
232/* SBI FWFT extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
233struct kvm_riscv_sbi_fwft {
234	struct kvm_riscv_sbi_fwft_feature misaligned_deleg;
235	struct kvm_riscv_sbi_fwft_feature pointer_masking;
236};
237
238/* Possible states for kvm_riscv_timer */
239#define KVM_RISCV_TIMER_STATE_OFF	0
240#define KVM_RISCV_TIMER_STATE_ON	1
241
242/* If you need to interpret the index values, here is the key: */
243#define KVM_REG_RISCV_TYPE_MASK		0x00000000FF000000
244#define KVM_REG_RISCV_TYPE_SHIFT	24
245#define KVM_REG_RISCV_SUBTYPE_MASK	0x0000000000FF0000
246#define KVM_REG_RISCV_SUBTYPE_SHIFT	16
247
248/* Config registers are mapped as type 1 */
249#define KVM_REG_RISCV_CONFIG		(0x01 << KVM_REG_RISCV_TYPE_SHIFT)
250#define KVM_REG_RISCV_CONFIG_REG(name)	\
251	(offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
252
253/* Core registers are mapped as type 2 */
254#define KVM_REG_RISCV_CORE		(0x02 << KVM_REG_RISCV_TYPE_SHIFT)
255#define KVM_REG_RISCV_CORE_REG(name)	\
256		(offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
257
258/* Control and status registers are mapped as type 3 */
259#define KVM_REG_RISCV_CSR		(0x03 << KVM_REG_RISCV_TYPE_SHIFT)
260#define KVM_REG_RISCV_CSR_GENERAL	(0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
261#define KVM_REG_RISCV_CSR_AIA		(0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
262#define KVM_REG_RISCV_CSR_SMSTATEEN	(0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
263#define KVM_REG_RISCV_CSR_REG(name)	\
264		(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
265#define KVM_REG_RISCV_CSR_AIA_REG(name)	\
266	(offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long))
267#define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name)  \
268	(offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long))
269
270/* Timer registers are mapped as type 4 */
271#define KVM_REG_RISCV_TIMER		(0x04 << KVM_REG_RISCV_TYPE_SHIFT)
272#define KVM_REG_RISCV_TIMER_REG(name)	\
273		(offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
274
275/* F extension registers are mapped as type 5 */
276#define KVM_REG_RISCV_FP_F		(0x05 << KVM_REG_RISCV_TYPE_SHIFT)
277#define KVM_REG_RISCV_FP_F_REG(name)	\
278		(offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
279
280/* D extension registers are mapped as type 6 */
281#define KVM_REG_RISCV_FP_D		(0x06 << KVM_REG_RISCV_TYPE_SHIFT)
282#define KVM_REG_RISCV_FP_D_REG(name)	\
283		(offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
284
285/* ISA Extension registers are mapped as type 7 */
286#define KVM_REG_RISCV_ISA_EXT		(0x07 << KVM_REG_RISCV_TYPE_SHIFT)
287#define KVM_REG_RISCV_ISA_SINGLE	(0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
288#define KVM_REG_RISCV_ISA_MULTI_EN	(0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
289#define KVM_REG_RISCV_ISA_MULTI_DIS	(0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
290#define KVM_REG_RISCV_ISA_MULTI_REG(__ext_id)	\
291		((__ext_id) / __BITS_PER_LONG)
292#define KVM_REG_RISCV_ISA_MULTI_MASK(__ext_id)	\
293		(1UL << ((__ext_id) % __BITS_PER_LONG))
294#define KVM_REG_RISCV_ISA_MULTI_REG_LAST	\
295		KVM_REG_RISCV_ISA_MULTI_REG(KVM_RISCV_ISA_EXT_MAX - 1)
296
297/* SBI extension registers are mapped as type 8 */
298#define KVM_REG_RISCV_SBI_EXT		(0x08 << KVM_REG_RISCV_TYPE_SHIFT)
299#define KVM_REG_RISCV_SBI_SINGLE	(0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
300#define KVM_REG_RISCV_SBI_MULTI_EN	(0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
301#define KVM_REG_RISCV_SBI_MULTI_DIS	(0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
302#define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id)	\
303		((__ext_id) / __BITS_PER_LONG)
304#define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id)	\
305		(1UL << ((__ext_id) % __BITS_PER_LONG))
306#define KVM_REG_RISCV_SBI_MULTI_REG_LAST	\
307		KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1)
308
309/* V extension registers are mapped as type 9 */
310#define KVM_REG_RISCV_VECTOR		(0x09 << KVM_REG_RISCV_TYPE_SHIFT)
311#define KVM_REG_RISCV_VECTOR_CSR_REG(name)	\
312		(offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long))
313#define KVM_REG_RISCV_VECTOR_REG(n)	\
314		((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long))
315
316/* Registers for specific SBI extensions are mapped as type 10 */
317#define KVM_REG_RISCV_SBI_STATE		(0x0a << KVM_REG_RISCV_TYPE_SHIFT)
318#define KVM_REG_RISCV_SBI_STA		(0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
319#define KVM_REG_RISCV_SBI_STA_REG(name)		\
320		(offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long))
321#define KVM_REG_RISCV_SBI_FWFT		(0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
322#define KVM_REG_RISCV_SBI_FWFT_REG(name)	\
323		(offsetof(struct kvm_riscv_sbi_fwft, name) / sizeof(unsigned long))
324
325/* Device Control API: RISC-V AIA */
326#define KVM_DEV_RISCV_APLIC_ALIGN		0x1000
327#define KVM_DEV_RISCV_APLIC_SIZE		0x4000
328#define KVM_DEV_RISCV_APLIC_MAX_HARTS		0x4000
329#define KVM_DEV_RISCV_IMSIC_ALIGN		0x1000
330#define KVM_DEV_RISCV_IMSIC_SIZE		0x1000
331
332#define KVM_DEV_RISCV_AIA_GRP_CONFIG		0
333#define KVM_DEV_RISCV_AIA_CONFIG_MODE		0
334#define KVM_DEV_RISCV_AIA_CONFIG_IDS		1
335#define KVM_DEV_RISCV_AIA_CONFIG_SRCS		2
336#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS	3
337#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT	4
338#define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS	5
339#define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS	6
340
341/*
342 * Modes of RISC-V AIA device:
343 * 1) EMUL (aka Emulation): Trap-n-emulate IMSIC
344 * 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files
345 * 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever
346 *    available otherwise fallback to trap-n-emulation
347 */
348#define KVM_DEV_RISCV_AIA_MODE_EMUL		0
349#define KVM_DEV_RISCV_AIA_MODE_HWACCEL		1
350#define KVM_DEV_RISCV_AIA_MODE_AUTO		2
351
352#define KVM_DEV_RISCV_AIA_IDS_MIN		63
353#define KVM_DEV_RISCV_AIA_IDS_MAX		2048
354#define KVM_DEV_RISCV_AIA_SRCS_MAX		1024
355#define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX	8
356#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN	24
357#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX	56
358#define KVM_DEV_RISCV_AIA_HART_BITS_MAX		16
359#define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX	8
360
361#define KVM_DEV_RISCV_AIA_GRP_ADDR		1
362#define KVM_DEV_RISCV_AIA_ADDR_APLIC		0
363#define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu)	(1 + (__vcpu))
364#define KVM_DEV_RISCV_AIA_ADDR_MAX		\
365		(1 + KVM_DEV_RISCV_APLIC_MAX_HARTS)
366
367#define KVM_DEV_RISCV_AIA_GRP_CTRL		2
368#define KVM_DEV_RISCV_AIA_CTRL_INIT		0
369
370/*
371 * The device attribute type contains the memory mapped offset of the
372 * APLIC register (range 0x0000-0x3FFF) and it must be 4-byte aligned.
373 */
374#define KVM_DEV_RISCV_AIA_GRP_APLIC		3
375
376/*
377 * The lower 12-bits of the device attribute type contains the iselect
378 * value of the IMSIC register (range 0x70-0xFF) whereas the higher order
379 * bits contains the VCPU id.
380 */
381#define KVM_DEV_RISCV_AIA_GRP_IMSIC		4
382#define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS	12
383#define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK	\
384		((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1)
385#define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu, __isel)	\
386		(((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | \
387		 ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK))
388#define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr)	\
389		((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)
390#define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr)	\
391		((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS)
392
393/* One single KVM irqchip, ie. the AIA */
394#define KVM_NR_IRQCHIPS			1
395
396#endif
397
398#endif /* __LINUX_KVM_RISCV_H */