sbi.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) 2015 Regents of the University of California
  4 * Copyright (c) 2020 Western Digital Corporation or its affiliates.
  5 */
  6
  7#ifndef _ASM_RISCV_SBI_H
  8#define _ASM_RISCV_SBI_H
  9
 10#include <linux/types.h>
 11#include <linux/cpumask.h>
 12#include <linux/jump_label.h>
 13
 14#ifdef CONFIG_RISCV_SBI
 15enum sbi_ext_id {
 16#ifdef CONFIG_RISCV_SBI_V01
 17	SBI_EXT_0_1_SET_TIMER = 0x0,
 18	SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
 19	SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
 20	SBI_EXT_0_1_CLEAR_IPI = 0x3,
 21	SBI_EXT_0_1_SEND_IPI = 0x4,
 22	SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
 23	SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
 24	SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
 25	SBI_EXT_0_1_SHUTDOWN = 0x8,
 26#endif
 27	SBI_EXT_BASE = 0x10,
 28	SBI_EXT_TIME = 0x54494D45,
 29	SBI_EXT_IPI = 0x735049,
 30	SBI_EXT_RFENCE = 0x52464E43,
 31	SBI_EXT_HSM = 0x48534D,
 32	SBI_EXT_SRST = 0x53525354,
 33	SBI_EXT_SUSP = 0x53555350,
 34	SBI_EXT_PMU = 0x504D55,
 35	SBI_EXT_DBCN = 0x4442434E,
 36	SBI_EXT_STA = 0x535441,
 37	SBI_EXT_NACL = 0x4E41434C,
 38	SBI_EXT_FWFT = 0x46574654,
 39	SBI_EXT_MPXY = 0x4D505859,
 40	SBI_EXT_DBTR = 0x44425452,
 41
 42	/* Experimentals extensions must lie within this range */
 43	SBI_EXT_EXPERIMENTAL_START = 0x08000000,
 44	SBI_EXT_EXPERIMENTAL_END = 0x08FFFFFF,
 45
 46	/* Vendor extensions must lie within this range */
 47	SBI_EXT_VENDOR_START = 0x09000000,
 48	SBI_EXT_VENDOR_END = 0x09FFFFFF,
 49};
 50
 51enum sbi_ext_base_fid {
 52	SBI_EXT_BASE_GET_SPEC_VERSION = 0,
 53	SBI_EXT_BASE_GET_IMP_ID,
 54	SBI_EXT_BASE_GET_IMP_VERSION,
 55	SBI_EXT_BASE_PROBE_EXT,
 56	SBI_EXT_BASE_GET_MVENDORID,
 57	SBI_EXT_BASE_GET_MARCHID,
 58	SBI_EXT_BASE_GET_MIMPID,
 59};
 60
 61enum sbi_ext_time_fid {
 62	SBI_EXT_TIME_SET_TIMER = 0,
 63};
 64
 65enum sbi_ext_ipi_fid {
 66	SBI_EXT_IPI_SEND_IPI = 0,
 67};
 68
 69enum sbi_ext_rfence_fid {
 70	SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
 71	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
 72	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
 73	SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
 74	SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
 75	SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
 76	SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
 77};
 78
 79enum sbi_ext_hsm_fid {
 80	SBI_EXT_HSM_HART_START = 0,
 81	SBI_EXT_HSM_HART_STOP,
 82	SBI_EXT_HSM_HART_STATUS,
 83	SBI_EXT_HSM_HART_SUSPEND,
 84};
 85
 86enum sbi_hsm_hart_state {
 87	SBI_HSM_STATE_STARTED = 0,
 88	SBI_HSM_STATE_STOPPED,
 89	SBI_HSM_STATE_START_PENDING,
 90	SBI_HSM_STATE_STOP_PENDING,
 91	SBI_HSM_STATE_SUSPENDED,
 92	SBI_HSM_STATE_SUSPEND_PENDING,
 93	SBI_HSM_STATE_RESUME_PENDING,
 94};
 95
 96#define SBI_HSM_SUSP_BASE_MASK			0x7fffffff
 97#define SBI_HSM_SUSP_NON_RET_BIT		0x80000000
 98#define SBI_HSM_SUSP_PLAT_BASE			0x10000000
 99
100#define SBI_HSM_SUSPEND_RET_DEFAULT		0x00000000
101#define SBI_HSM_SUSPEND_RET_PLATFORM		SBI_HSM_SUSP_PLAT_BASE
102#define SBI_HSM_SUSPEND_RET_LAST		SBI_HSM_SUSP_BASE_MASK
103#define SBI_HSM_SUSPEND_NON_RET_DEFAULT		SBI_HSM_SUSP_NON_RET_BIT
104#define SBI_HSM_SUSPEND_NON_RET_PLATFORM	(SBI_HSM_SUSP_NON_RET_BIT | \
105						 SBI_HSM_SUSP_PLAT_BASE)
106#define SBI_HSM_SUSPEND_NON_RET_LAST		(SBI_HSM_SUSP_NON_RET_BIT | \
107						 SBI_HSM_SUSP_BASE_MASK)
108
109enum sbi_ext_srst_fid {
110	SBI_EXT_SRST_RESET = 0,
111};
112
113enum sbi_srst_reset_type {
114	SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
115	SBI_SRST_RESET_TYPE_COLD_REBOOT,
116	SBI_SRST_RESET_TYPE_WARM_REBOOT,
117};
118
119enum sbi_srst_reset_reason {
120	SBI_SRST_RESET_REASON_NONE = 0,
121	SBI_SRST_RESET_REASON_SYS_FAILURE,
122};
123
124enum sbi_ext_susp_fid {
125	SBI_EXT_SUSP_SYSTEM_SUSPEND = 0,
126};
127
128enum sbi_ext_susp_sleep_type {
129	SBI_SUSP_SLEEP_TYPE_SUSPEND_TO_RAM = 0,
130};
131
132enum sbi_ext_pmu_fid {
133	SBI_EXT_PMU_NUM_COUNTERS = 0,
134	SBI_EXT_PMU_COUNTER_GET_INFO,
135	SBI_EXT_PMU_COUNTER_CFG_MATCH,
136	SBI_EXT_PMU_COUNTER_START,
137	SBI_EXT_PMU_COUNTER_STOP,
138	SBI_EXT_PMU_COUNTER_FW_READ,
139	SBI_EXT_PMU_COUNTER_FW_READ_HI,
140	SBI_EXT_PMU_SNAPSHOT_SET_SHMEM,
141	SBI_EXT_PMU_EVENT_GET_INFO,
142};
143
144union sbi_pmu_ctr_info {
145	unsigned long value;
146	struct {
147		unsigned long csr:12;
148		unsigned long width:6;
149#if __riscv_xlen == 32
150		unsigned long reserved:13;
151#else
152		unsigned long reserved:45;
153#endif
154		unsigned long type:1;
155	};
156};
157
158/* Data structure to contain the pmu snapshot data */
159struct riscv_pmu_snapshot_data {
160	u64 ctr_overflow_mask;
161	u64 ctr_values[64];
162	u64 reserved[447];
163};
164
165struct riscv_pmu_event_info {
166	u32 event_idx;
167	u32 output;
168	u64 event_data;
169};
170
171#define RISCV_PMU_EVENT_INFO_OUTPUT_MASK 0x01
172
173#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0)
174#define RISCV_PMU_PLAT_FW_EVENT_MASK GENMASK_ULL(61, 0)
175/* SBI v3.0 allows extended hpmeventX width value */
176#define RISCV_PMU_RAW_EVENT_V2_MASK GENMASK_ULL(55, 0)
177#define RISCV_PMU_RAW_EVENT_IDX 0x20000
178#define RISCV_PMU_RAW_EVENT_V2_IDX 0x30000
179#define RISCV_PLAT_FW_EVENT	0xFFFF
180
181/** General pmu event codes specified in SBI PMU extension */
182enum sbi_pmu_hw_generic_events_t {
183	SBI_PMU_HW_NO_EVENT			= 0,
184	SBI_PMU_HW_CPU_CYCLES			= 1,
185	SBI_PMU_HW_INSTRUCTIONS			= 2,
186	SBI_PMU_HW_CACHE_REFERENCES		= 3,
187	SBI_PMU_HW_CACHE_MISSES			= 4,
188	SBI_PMU_HW_BRANCH_INSTRUCTIONS		= 5,
189	SBI_PMU_HW_BRANCH_MISSES		= 6,
190	SBI_PMU_HW_BUS_CYCLES			= 7,
191	SBI_PMU_HW_STALLED_CYCLES_FRONTEND	= 8,
192	SBI_PMU_HW_STALLED_CYCLES_BACKEND	= 9,
193	SBI_PMU_HW_REF_CPU_CYCLES		= 10,
194
195	SBI_PMU_HW_GENERAL_MAX,
196};
197
198/**
199 * Special "firmware" events provided by the firmware, even if the hardware
200 * does not support performance events. These events are encoded as a raw
201 * event type in Linux kernel perf framework.
202 */
203enum sbi_pmu_fw_generic_events_t {
204	SBI_PMU_FW_MISALIGNED_LOAD	= 0,
205	SBI_PMU_FW_MISALIGNED_STORE	= 1,
206	SBI_PMU_FW_ACCESS_LOAD		= 2,
207	SBI_PMU_FW_ACCESS_STORE		= 3,
208	SBI_PMU_FW_ILLEGAL_INSN		= 4,
209	SBI_PMU_FW_SET_TIMER		= 5,
210	SBI_PMU_FW_IPI_SENT		= 6,
211	SBI_PMU_FW_IPI_RCVD		= 7,
212	SBI_PMU_FW_FENCE_I_SENT		= 8,
213	SBI_PMU_FW_FENCE_I_RCVD		= 9,
214	SBI_PMU_FW_SFENCE_VMA_SENT	= 10,
215	SBI_PMU_FW_SFENCE_VMA_RCVD	= 11,
216	SBI_PMU_FW_SFENCE_VMA_ASID_SENT	= 12,
217	SBI_PMU_FW_SFENCE_VMA_ASID_RCVD	= 13,
218
219	SBI_PMU_FW_HFENCE_GVMA_SENT	= 14,
220	SBI_PMU_FW_HFENCE_GVMA_RCVD	= 15,
221	SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16,
222	SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17,
223
224	SBI_PMU_FW_HFENCE_VVMA_SENT	= 18,
225	SBI_PMU_FW_HFENCE_VVMA_RCVD	= 19,
226	SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20,
227	SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21,
228	SBI_PMU_FW_MAX,
229};
230
231/* SBI PMU event types */
232enum sbi_pmu_event_type {
233	SBI_PMU_EVENT_TYPE_HW = 0x0,
234	SBI_PMU_EVENT_TYPE_CACHE = 0x1,
235	SBI_PMU_EVENT_TYPE_RAW = 0x2,
236	SBI_PMU_EVENT_TYPE_RAW_V2 = 0x3,
237	SBI_PMU_EVENT_TYPE_FW = 0xf,
238};
239
240/* SBI PMU event types */
241enum sbi_pmu_ctr_type {
242	SBI_PMU_CTR_TYPE_HW = 0x0,
243	SBI_PMU_CTR_TYPE_FW,
244};
245
246/* Helper macros to decode event idx */
247#define SBI_PMU_EVENT_IDX_OFFSET 20
248#define SBI_PMU_EVENT_IDX_MASK 0xFFFFF
249#define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF
250#define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000
251#define SBI_PMU_EVENT_RAW_IDX 0x20000
252#define SBI_PMU_FIXED_CTR_MASK 0x07
253
254#define SBI_PMU_EVENT_CACHE_ID_CODE_MASK 0xFFF8
255#define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06
256#define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01
257
258#define SBI_PMU_EVENT_CACHE_ID_SHIFT 3
259#define SBI_PMU_EVENT_CACHE_OP_SHIFT 1
260
261#define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF
262
263/* Flags defined for config matching function */
264#define SBI_PMU_CFG_FLAG_SKIP_MATCH	BIT(0)
265#define SBI_PMU_CFG_FLAG_CLEAR_VALUE	BIT(1)
266#define SBI_PMU_CFG_FLAG_AUTO_START	BIT(2)
267#define SBI_PMU_CFG_FLAG_SET_VUINH	BIT(3)
268#define SBI_PMU_CFG_FLAG_SET_VSINH	BIT(4)
269#define SBI_PMU_CFG_FLAG_SET_UINH	BIT(5)
270#define SBI_PMU_CFG_FLAG_SET_SINH	BIT(6)
271#define SBI_PMU_CFG_FLAG_SET_MINH	BIT(7)
272
273/* Flags defined for counter start function */
274#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0)
275#define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1)
276
277/* Flags defined for counter stop function */
278#define SBI_PMU_STOP_FLAG_RESET BIT(0)
279#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1)
280
281enum sbi_ext_dbcn_fid {
282	SBI_EXT_DBCN_CONSOLE_WRITE = 0,
283	SBI_EXT_DBCN_CONSOLE_READ = 1,
284	SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2,
285};
286
287/* SBI STA (steal-time accounting) extension */
288enum sbi_ext_sta_fid {
289	SBI_EXT_STA_STEAL_TIME_SET_SHMEM = 0,
290};
291
292struct sbi_sta_struct {
293	__le32 sequence;
294	__le32 flags;
295	__le64 steal;
296	u8 preempted;
297	u8 pad[47];
298} __packed;
299
300#define SBI_SHMEM_DISABLE		-1
301
302enum sbi_ext_nacl_fid {
303	SBI_EXT_NACL_PROBE_FEATURE = 0x0,
304	SBI_EXT_NACL_SET_SHMEM = 0x1,
305	SBI_EXT_NACL_SYNC_CSR = 0x2,
306	SBI_EXT_NACL_SYNC_HFENCE = 0x3,
307	SBI_EXT_NACL_SYNC_SRET = 0x4,
308};
309
310enum sbi_ext_nacl_feature {
311	SBI_NACL_FEAT_SYNC_CSR = 0x0,
312	SBI_NACL_FEAT_SYNC_HFENCE = 0x1,
313	SBI_NACL_FEAT_SYNC_SRET = 0x2,
314	SBI_NACL_FEAT_AUTOSWAP_CSR = 0x3,
315};
316
317#define SBI_NACL_SHMEM_ADDR_SHIFT	12
318#define SBI_NACL_SHMEM_SCRATCH_OFFSET	0x0000
319#define SBI_NACL_SHMEM_SCRATCH_SIZE	0x1000
320#define SBI_NACL_SHMEM_SRET_OFFSET	0x0000
321#define SBI_NACL_SHMEM_SRET_SIZE	0x0200
322#define SBI_NACL_SHMEM_AUTOSWAP_OFFSET	(SBI_NACL_SHMEM_SRET_OFFSET + \
323					 SBI_NACL_SHMEM_SRET_SIZE)
324#define SBI_NACL_SHMEM_AUTOSWAP_SIZE	0x0080
325#define SBI_NACL_SHMEM_UNUSED_OFFSET	(SBI_NACL_SHMEM_AUTOSWAP_OFFSET + \
326					 SBI_NACL_SHMEM_AUTOSWAP_SIZE)
327#define SBI_NACL_SHMEM_UNUSED_SIZE	0x0580
328#define SBI_NACL_SHMEM_HFENCE_OFFSET	(SBI_NACL_SHMEM_UNUSED_OFFSET + \
329					 SBI_NACL_SHMEM_UNUSED_SIZE)
330#define SBI_NACL_SHMEM_HFENCE_SIZE	0x0780
331#define SBI_NACL_SHMEM_DBITMAP_OFFSET	(SBI_NACL_SHMEM_HFENCE_OFFSET + \
332					 SBI_NACL_SHMEM_HFENCE_SIZE)
333#define SBI_NACL_SHMEM_DBITMAP_SIZE	0x0080
334#define SBI_NACL_SHMEM_CSR_OFFSET	(SBI_NACL_SHMEM_DBITMAP_OFFSET + \
335					 SBI_NACL_SHMEM_DBITMAP_SIZE)
336#define SBI_NACL_SHMEM_CSR_SIZE		((__riscv_xlen / 8) * 1024)
337#define SBI_NACL_SHMEM_SIZE		(SBI_NACL_SHMEM_CSR_OFFSET + \
338					 SBI_NACL_SHMEM_CSR_SIZE)
339
340#define SBI_NACL_SHMEM_CSR_INDEX(__csr_num)	\
341		((((__csr_num) & 0xc00) >> 2) | ((__csr_num) & 0xff))
342
343#define SBI_NACL_SHMEM_HFENCE_ENTRY_SZ		((__riscv_xlen / 8) * 4)
344#define SBI_NACL_SHMEM_HFENCE_ENTRY_MAX		\
345		(SBI_NACL_SHMEM_HFENCE_SIZE /	\
346		 SBI_NACL_SHMEM_HFENCE_ENTRY_SZ)
347#define SBI_NACL_SHMEM_HFENCE_ENTRY(__num)	\
348		(SBI_NACL_SHMEM_HFENCE_OFFSET +	\
349		 (__num) * SBI_NACL_SHMEM_HFENCE_ENTRY_SZ)
350#define SBI_NACL_SHMEM_HFENCE_ENTRY_CONFIG(__num)	\
351		SBI_NACL_SHMEM_HFENCE_ENTRY(__num)
352#define SBI_NACL_SHMEM_HFENCE_ENTRY_PNUM(__num)\
353		(SBI_NACL_SHMEM_HFENCE_ENTRY(__num) + (__riscv_xlen / 8))
354#define SBI_NACL_SHMEM_HFENCE_ENTRY_PCOUNT(__num)\
355		(SBI_NACL_SHMEM_HFENCE_ENTRY(__num) + \
356		 ((__riscv_xlen / 8) * 3))
357
358#define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_BITS	1
359#define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_SHIFT	\
360		(__riscv_xlen - SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_BITS)
361#define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_MASK	\
362		((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_BITS) - 1)
363#define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND		\
364		(SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_MASK << \
365		 SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_SHIFT)
366
367#define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_BITS	3
368#define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_SHIFT \
369		(SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_SHIFT - \
370		 SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_BITS)
371
372#define SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_BITS	4
373#define SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_SHIFT	\
374		(SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_SHIFT - \
375		 SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_BITS)
376#define SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_MASK	\
377		((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_BITS) - 1)
378
379#define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA		0x0
380#define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_ALL	0x1
381#define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_VMID	0x2
382#define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_VMID_ALL 0x3
383#define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA		0x4
384#define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ALL	0x5
385#define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ASID	0x6
386#define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ASID_ALL 0x7
387
388#define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_BITS	1
389#define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_SHIFT \
390		(SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_SHIFT - \
391		 SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_BITS)
392
393#define SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_BITS	7
394#define SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_SHIFT \
395		(SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_SHIFT - \
396		 SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_BITS)
397#define SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_MASK	\
398		((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_BITS) - 1)
399#define SBI_NACL_SHMEM_HFENCE_ORDER_BASE	12
400
401#if __riscv_xlen == 32
402#define SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS	9
403#define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_BITS	7
404#else
405#define SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS	16
406#define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_BITS	14
407#endif
408#define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_SHIFT	\
409				SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS
410#define SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_MASK	\
411		((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS) - 1)
412#define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_MASK	\
413		((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_BITS) - 1)
414
415#define SBI_NACL_SHMEM_AUTOSWAP_FLAG_HSTATUS	BIT(0)
416#define SBI_NACL_SHMEM_AUTOSWAP_HSTATUS		((__riscv_xlen / 8) * 1)
417
418#define SBI_NACL_SHMEM_SRET_X(__i)		((__riscv_xlen / 8) * (__i))
419#define SBI_NACL_SHMEM_SRET_X_LAST		31
420
421/* SBI function IDs for FW feature extension */
422#define SBI_EXT_FWFT_SET		0x0
423#define SBI_EXT_FWFT_GET		0x1
424
425enum sbi_fwft_feature_t {
426	SBI_FWFT_MISALIGNED_EXC_DELEG		= 0x0,
427	SBI_FWFT_LANDING_PAD			= 0x1,
428	SBI_FWFT_SHADOW_STACK			= 0x2,
429	SBI_FWFT_DOUBLE_TRAP			= 0x3,
430	SBI_FWFT_PTE_AD_HW_UPDATING		= 0x4,
431	SBI_FWFT_POINTER_MASKING_PMLEN		= 0x5,
432	SBI_FWFT_LOCAL_RESERVED_START		= 0x6,
433	SBI_FWFT_LOCAL_RESERVED_END		= 0x3fffffff,
434	SBI_FWFT_LOCAL_PLATFORM_START		= 0x40000000,
435	SBI_FWFT_LOCAL_PLATFORM_END		= 0x7fffffff,
436
437	SBI_FWFT_GLOBAL_RESERVED_START		= 0x80000000,
438	SBI_FWFT_GLOBAL_RESERVED_END		= 0xbfffffff,
439	SBI_FWFT_GLOBAL_PLATFORM_START		= 0xc0000000,
440	SBI_FWFT_GLOBAL_PLATFORM_END		= 0xffffffff,
441};
442
443#define SBI_FWFT_PLATFORM_FEATURE_BIT		BIT(30)
444#define SBI_FWFT_GLOBAL_FEATURE_BIT		BIT(31)
445
446#define SBI_FWFT_SET_FLAG_LOCK			BIT(0)
447
448enum sbi_ext_mpxy_fid {
449	SBI_EXT_MPXY_GET_SHMEM_SIZE,
450	SBI_EXT_MPXY_SET_SHMEM,
451	SBI_EXT_MPXY_GET_CHANNEL_IDS,
452	SBI_EXT_MPXY_READ_ATTRS,
453	SBI_EXT_MPXY_WRITE_ATTRS,
454	SBI_EXT_MPXY_SEND_MSG_WITH_RESP,
455	SBI_EXT_MPXY_SEND_MSG_WITHOUT_RESP,
456	SBI_EXT_MPXY_GET_NOTIFICATION_EVENTS,
457};
458
459enum sbi_mpxy_attribute_id {
460	/* Standard channel attributes managed by MPXY framework */
461	SBI_MPXY_ATTR_MSG_PROT_ID		= 0x00000000,
462	SBI_MPXY_ATTR_MSG_PROT_VER		= 0x00000001,
463	SBI_MPXY_ATTR_MSG_MAX_LEN		= 0x00000002,
464	SBI_MPXY_ATTR_MSG_SEND_TIMEOUT		= 0x00000003,
465	SBI_MPXY_ATTR_MSG_COMPLETION_TIMEOUT	= 0x00000004,
466	SBI_MPXY_ATTR_CHANNEL_CAPABILITY	= 0x00000005,
467	SBI_MPXY_ATTR_SSE_EVENT_ID		= 0x00000006,
468	SBI_MPXY_ATTR_MSI_CONTROL		= 0x00000007,
469	SBI_MPXY_ATTR_MSI_ADDR_LO		= 0x00000008,
470	SBI_MPXY_ATTR_MSI_ADDR_HI		= 0x00000009,
471	SBI_MPXY_ATTR_MSI_DATA			= 0x0000000A,
472	SBI_MPXY_ATTR_EVENTS_STATE_CONTROL	= 0x0000000B,
473	SBI_MPXY_ATTR_STD_ATTR_MAX_IDX,
474	/*
475	 * Message protocol specific attributes, managed by
476	 * the message protocol specification.
477	 */
478	SBI_MPXY_ATTR_MSGPROTO_ATTR_START	= 0x80000000,
479	SBI_MPXY_ATTR_MSGPROTO_ATTR_END		= 0xffffffff
480};
481
482/* Possible values of MSG_PROT_ID attribute as-per SBI v3.0 (or higher) */
483enum sbi_mpxy_msgproto_id {
484	SBI_MPXY_MSGPROTO_RPMI_ID = 0x0,
485};
486
487/* RPMI message protocol specific MPXY attributes */
488enum sbi_mpxy_rpmi_attribute_id {
489	SBI_MPXY_RPMI_ATTR_SERVICEGROUP_ID = SBI_MPXY_ATTR_MSGPROTO_ATTR_START,
490	SBI_MPXY_RPMI_ATTR_SERVICEGROUP_VERSION,
491	SBI_MPXY_RPMI_ATTR_IMPL_ID,
492	SBI_MPXY_RPMI_ATTR_IMPL_VERSION,
493	SBI_MPXY_RPMI_ATTR_MAX_ID
494};
495
496/* Encoding of MSG_PROT_VER attribute */
497#define SBI_MPXY_MSG_PROT_VER_MAJOR(__ver)	upper_16_bits(__ver)
498#define SBI_MPXY_MSG_PROT_VER_MINOR(__ver)	lower_16_bits(__ver)
499#define SBI_MPXY_MSG_PROT_MKVER(__maj, __min)	(((u32)(__maj) << 16) | (u16)(__min))
500
501/* Capabilities available through CHANNEL_CAPABILITY attribute */
502#define SBI_MPXY_CHAN_CAP_MSI			BIT(0)
503#define SBI_MPXY_CHAN_CAP_SSE			BIT(1)
504#define SBI_MPXY_CHAN_CAP_EVENTS_STATE		BIT(2)
505#define SBI_MPXY_CHAN_CAP_SEND_WITH_RESP	BIT(3)
506#define SBI_MPXY_CHAN_CAP_SEND_WITHOUT_RESP	BIT(4)
507#define SBI_MPXY_CHAN_CAP_GET_NOTIFICATIONS	BIT(5)
508
509/* SBI debug triggers function IDs */
510enum sbi_ext_dbtr_fid {
511	SBI_EXT_DBTR_NUM_TRIGGERS = 0,
512	SBI_EXT_DBTR_SETUP_SHMEM,
513	SBI_EXT_DBTR_TRIG_READ,
514	SBI_EXT_DBTR_TRIG_INSTALL,
515	SBI_EXT_DBTR_TRIG_UPDATE,
516	SBI_EXT_DBTR_TRIG_UNINSTALL,
517	SBI_EXT_DBTR_TRIG_ENABLE,
518	SBI_EXT_DBTR_TRIG_DISABLE,
519};
520
521struct sbi_dbtr_data_msg {
522	unsigned long tstate;
523	unsigned long tdata1;
524	unsigned long tdata2;
525	unsigned long tdata3;
526};
527
528struct sbi_dbtr_id_msg {
529	unsigned long idx;
530};
531
532union sbi_dbtr_shmem_entry {
533	struct sbi_dbtr_data_msg data;
534	struct sbi_dbtr_id_msg id;
535};
536
537/* SBI spec version fields */
538#define SBI_SPEC_VERSION_DEFAULT	0x1
539#define SBI_SPEC_VERSION_MAJOR_SHIFT	24
540#define SBI_SPEC_VERSION_MAJOR_MASK	0x7f
541#define SBI_SPEC_VERSION_MINOR_MASK	0xffffff
542
543/* SBI return error codes */
544#define SBI_SUCCESS		0
545#define SBI_ERR_FAILURE		-1
546#define SBI_ERR_NOT_SUPPORTED	-2
547#define SBI_ERR_INVALID_PARAM	-3
548#define SBI_ERR_DENIED		-4
549#define SBI_ERR_INVALID_ADDRESS	-5
550#define SBI_ERR_ALREADY_AVAILABLE -6
551#define SBI_ERR_ALREADY_STARTED -7
552#define SBI_ERR_ALREADY_STOPPED -8
553#define SBI_ERR_NO_SHMEM	-9
554#define SBI_ERR_INVALID_STATE	-10
555#define SBI_ERR_BAD_RANGE	-11
556#define SBI_ERR_TIMEOUT		-12
557#define SBI_ERR_IO		-13
558#define SBI_ERR_DENIED_LOCKED	-14
559
560extern unsigned long sbi_spec_version;
561struct sbiret {
562	long error;
563	long value;
564};
565
566void sbi_init(void);
567long __sbi_base_ecall(int fid);
568struct sbiret __sbi_ecall(unsigned long arg0, unsigned long arg1,
569			  unsigned long arg2, unsigned long arg3,
570			  unsigned long arg4, unsigned long arg5,
571			  int fid, int ext);
572#define sbi_ecall(e, f, a0, a1, a2, a3, a4, a5)	\
573		__sbi_ecall(a0, a1, a2, a3, a4, a5, f, e)
574
575#ifdef CONFIG_RISCV_SBI_V01
576void sbi_console_putchar(int ch);
577int sbi_console_getchar(void);
578#else
579static inline void sbi_console_putchar(int ch) { }
580static inline int sbi_console_getchar(void) { return -ENOENT; }
581#endif
582long sbi_get_mvendorid(void);
583long sbi_get_marchid(void);
584long sbi_get_mimpid(void);
585void sbi_set_timer(uint64_t stime_value);
586void sbi_shutdown(void);
587void sbi_send_ipi(unsigned int cpu);
588int sbi_remote_fence_i(const struct cpumask *cpu_mask);
589
590int sbi_remote_sfence_vma_asid(const struct cpumask *cpu_mask,
591				unsigned long start,
592				unsigned long size,
593				unsigned long asid);
594int sbi_remote_hfence_gvma(const struct cpumask *cpu_mask,
595			   unsigned long start,
596			   unsigned long size);
597int sbi_remote_hfence_gvma_vmid(const struct cpumask *cpu_mask,
598				unsigned long start,
599				unsigned long size,
600				unsigned long vmid);
601int sbi_remote_hfence_vvma(const struct cpumask *cpu_mask,
602			   unsigned long start,
603			   unsigned long size);
604int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask,
605				unsigned long start,
606				unsigned long size,
607				unsigned long asid);
608long sbi_probe_extension(int ext);
609
610int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags);
611int sbi_fwft_set_cpumask(const cpumask_t *mask, u32 feature,
612			 unsigned long value, unsigned long flags);
613/**
614 * sbi_fwft_set_online_cpus() - Set a feature on all online cpus
615 * @feature: The feature to be set
616 * @value: The feature value to be set
617 * @flags: FWFT feature set flags
618 *
619 * Return: 0 on success, appropriate linux error code otherwise.
620 */
621static inline int sbi_fwft_set_online_cpus(u32 feature, unsigned long value,
622					   unsigned long flags)
623{
624	return sbi_fwft_set_cpumask(cpu_online_mask, feature, value, flags);
625}
626
627/* Check if current SBI specification version is 0.1 or not */
628static inline int sbi_spec_is_0_1(void)
629{
630	return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0;
631}
632
633/* Get the major version of SBI */
634static inline unsigned long sbi_major_version(void)
635{
636	return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_SHIFT) &
637		SBI_SPEC_VERSION_MAJOR_MASK;
638}
639
640/* Get the minor version of SBI */
641static inline unsigned long sbi_minor_version(void)
642{
643	return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK;
644}
645
646/* Make SBI version */
647static inline unsigned long sbi_mk_version(unsigned long major,
648					    unsigned long minor)
649{
650	return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << SBI_SPEC_VERSION_MAJOR_SHIFT)
651		| (minor & SBI_SPEC_VERSION_MINOR_MASK);
652}
653
654static inline int sbi_err_map_linux_errno(int err)
655{
656	switch (err) {
657	case SBI_SUCCESS:
658		return 0;
659	case SBI_ERR_DENIED:
660	case SBI_ERR_DENIED_LOCKED:
661		return -EPERM;
662	case SBI_ERR_INVALID_PARAM:
663	case SBI_ERR_INVALID_STATE:
664		return -EINVAL;
665	case SBI_ERR_BAD_RANGE:
666		return -ERANGE;
667	case SBI_ERR_INVALID_ADDRESS:
668		return -EFAULT;
669	case SBI_ERR_NO_SHMEM:
670		return -ENOMEM;
671	case SBI_ERR_TIMEOUT:
672		return -ETIMEDOUT;
673	case SBI_ERR_IO:
674		return -EIO;
675	case SBI_ERR_NOT_SUPPORTED:
676	case SBI_ERR_FAILURE:
677	default:
678		return -ENOTSUPP;
679	};
680}
681
682extern bool sbi_debug_console_available;
683int sbi_debug_console_write(const char *bytes, unsigned int num_bytes);
684int sbi_debug_console_read(char *bytes, unsigned int num_bytes);
685
686#else /* CONFIG_RISCV_SBI */
687static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1; }
688static inline void sbi_init(void) {}
689#endif /* CONFIG_RISCV_SBI */
690
691unsigned long riscv_get_mvendorid(void);
692unsigned long riscv_get_marchid(void);
693unsigned long riscv_cached_mvendorid(unsigned int cpu_id);
694unsigned long riscv_cached_marchid(unsigned int cpu_id);
695unsigned long riscv_cached_mimpid(unsigned int cpu_id);
696
697#if IS_ENABLED(CONFIG_SMP) && IS_ENABLED(CONFIG_RISCV_SBI)
698DECLARE_STATIC_KEY_FALSE(riscv_sbi_for_rfence);
699#define riscv_use_sbi_for_rfence() \
700	static_branch_unlikely(&riscv_sbi_for_rfence)
701void sbi_ipi_init(void);
702#else
703static inline bool riscv_use_sbi_for_rfence(void) { return false; }
704static inline void sbi_ipi_init(void) { }
705#endif
706
707#endif /* _ASM_RISCV_SBI_H */