FILE
insn-def.h

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linux-6.19.14/arch/riscv/include/asm/insn-def.h C
  1/* SPDX-License-Identifier: GPL-2.0-only */
  2
  3#ifndef __ASM_INSN_DEF_H
  4#define __ASM_INSN_DEF_H
  5
  6#include <asm/asm.h>
  7
  8#define INSN_R_FUNC7_SHIFT		25
  9#define INSN_R_RS2_SHIFT		20
 10#define INSN_R_RS1_SHIFT		15
 11#define INSN_R_FUNC3_SHIFT		12
 12#define INSN_R_RD_SHIFT			 7
 13#define INSN_R_OPCODE_SHIFT		 0
 14
 15#define INSN_I_SIMM12_SHIFT		20
 16#define INSN_I_RS1_SHIFT		15
 17#define INSN_I_FUNC3_SHIFT		12
 18#define INSN_I_RD_SHIFT			 7
 19#define INSN_I_OPCODE_SHIFT		 0
 20
 21#define INSN_S_SIMM7_SHIFT		25
 22#define INSN_S_RS2_SHIFT		20
 23#define INSN_S_RS1_SHIFT		15
 24#define INSN_S_FUNC3_SHIFT		12
 25#define INSN_S_SIMM5_SHIFT		 7
 26#define INSN_S_OPCODE_SHIFT		 0
 27
 28#ifdef __ASSEMBLER__
 29
 30#ifdef CONFIG_AS_HAS_INSN
 31
 32	.macro insn_r, opcode, func3, func7, rd, rs1, rs2
 33	.insn	r \opcode, \func3, \func7, \rd, \rs1, \rs2
 34	.endm
 35
 36	.macro insn_i, opcode, func3, rd, rs1, simm12
 37	.insn	i \opcode, \func3, \rd, \rs1, \simm12
 38	.endm
 39
 40	.macro insn_s, opcode, func3, rs2, simm12, rs1
 41	.insn	s \opcode, \func3, \rs2, \simm12(\rs1)
 42	.endm
 43
 44#else
 45
 46#include <asm/gpr-num.h>
 47
 48	.macro insn_r, opcode, func3, func7, rd, rs1, rs2
 49	.4byte	((\opcode << INSN_R_OPCODE_SHIFT) |		\
 50		 (\func3 << INSN_R_FUNC3_SHIFT) |		\
 51		 (\func7 << INSN_R_FUNC7_SHIFT) |		\
 52		 (.L__gpr_num_\rd << INSN_R_RD_SHIFT) |		\
 53		 (.L__gpr_num_\rs1 << INSN_R_RS1_SHIFT) |	\
 54		 (.L__gpr_num_\rs2 << INSN_R_RS2_SHIFT))
 55	.endm
 56
 57	.macro insn_i, opcode, func3, rd, rs1, simm12
 58	.4byte	((\opcode << INSN_I_OPCODE_SHIFT) |		\
 59		 (\func3 << INSN_I_FUNC3_SHIFT) |		\
 60		 (.L__gpr_num_\rd << INSN_I_RD_SHIFT) |		\
 61		 (.L__gpr_num_\rs1 << INSN_I_RS1_SHIFT) |	\
 62		 (\simm12 << INSN_I_SIMM12_SHIFT))
 63	.endm
 64
 65	.macro insn_s, opcode, func3, rs2, simm12, rs1
 66	.4byte	((\opcode << INSN_S_OPCODE_SHIFT) |		\
 67		 (\func3 << INSN_S_FUNC3_SHIFT) |		\
 68		 (.L__gpr_num_\rs2 << INSN_S_RS2_SHIFT) |	\
 69		 (.L__gpr_num_\rs1 << INSN_S_RS1_SHIFT) |	\
 70		 ((\simm12 & 0x1f) << INSN_S_SIMM5_SHIFT) |	\
 71		 (((\simm12 >> 5) & 0x7f) << INSN_S_SIMM7_SHIFT))
 72	.endm
 73
 74#endif
 75
 76#define __INSN_R(...)	insn_r __VA_ARGS__
 77#define __INSN_I(...)	insn_i __VA_ARGS__
 78#define __INSN_S(...)	insn_s __VA_ARGS__
 79
 80#else /* ! __ASSEMBLER__ */
 81
 82#ifdef CONFIG_AS_HAS_INSN
 83
 84#define __INSN_R(opcode, func3, func7, rd, rs1, rs2)	\
 85	".insn	r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n"
 86
 87#define __INSN_I(opcode, func3, rd, rs1, simm12)	\
 88	".insn	i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n"
 89
 90#define __INSN_S(opcode, func3, rs2, simm12, rs1)	\
 91	".insn	s " opcode ", " func3 ", " rs2 ", " simm12 "(" rs1 ")\n"
 92
 93#else
 94
 95#include <linux/stringify.h>
 96#include <asm/gpr-num.h>
 97
 98#define DEFINE_INSN_R							\
 99	__DEFINE_ASM_GPR_NUMS						\
100"	.macro insn_r, opcode, func3, func7, rd, rs1, rs2\n"		\
101"	.4byte	((\\opcode << " __stringify(INSN_R_OPCODE_SHIFT) ") |"	\
102"		 (\\func3 << " __stringify(INSN_R_FUNC3_SHIFT) ") |"	\
103"		 (\\func7 << " __stringify(INSN_R_FUNC7_SHIFT) ") |"	\
104"		 (.L__gpr_num_\\rd << " __stringify(INSN_R_RD_SHIFT) ") |"    \
105"		 (.L__gpr_num_\\rs1 << " __stringify(INSN_R_RS1_SHIFT) ") |"  \
106"		 (.L__gpr_num_\\rs2 << " __stringify(INSN_R_RS2_SHIFT) "))\n" \
107"	.endm\n"
108
109#define DEFINE_INSN_I							\
110	__DEFINE_ASM_GPR_NUMS						\
111"	.macro insn_i, opcode, func3, rd, rs1, simm12\n"		\
112"	.4byte	((\\opcode << " __stringify(INSN_I_OPCODE_SHIFT) ") |"	\
113"		 (\\func3 << " __stringify(INSN_I_FUNC3_SHIFT) ") |"	\
114"		 (.L__gpr_num_\\rd << " __stringify(INSN_I_RD_SHIFT) ") |"   \
115"		 (.L__gpr_num_\\rs1 << " __stringify(INSN_I_RS1_SHIFT) ") |" \
116"		 (\\simm12 << " __stringify(INSN_I_SIMM12_SHIFT) "))\n"	\
117"	.endm\n"
118
119#define DEFINE_INSN_S							\
120	__DEFINE_ASM_GPR_NUMS						\
121"	.macro insn_s, opcode, func3, rs2, simm12, rs1\n"		\
122"	.4byte	((\\opcode << " __stringify(INSN_S_OPCODE_SHIFT) ") |"	\
123"		 (\\func3 << " __stringify(INSN_S_FUNC3_SHIFT) ") |"	\
124"		 (.L__gpr_num_\\rs2 << " __stringify(INSN_S_RS2_SHIFT) ") |" \
125"		 (.L__gpr_num_\\rs1 << " __stringify(INSN_S_RS1_SHIFT) ") |" \
126"		 ((\\simm12 & 0x1f) << " __stringify(INSN_S_SIMM5_SHIFT) ") |" \
127"		 (((\\simm12 >> 5) & 0x7f) << " __stringify(INSN_S_SIMM7_SHIFT) "))\n" \
128"	.endm\n"
129
130#define UNDEFINE_INSN_R							\
131"	.purgem insn_r\n"
132
133#define UNDEFINE_INSN_I							\
134"	.purgem insn_i\n"
135
136#define UNDEFINE_INSN_S							\
137"	.purgem insn_s\n"
138
139#define __INSN_R(opcode, func3, func7, rd, rs1, rs2)			\
140	DEFINE_INSN_R							\
141	"insn_r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" \
142	UNDEFINE_INSN_R
143
144#define __INSN_I(opcode, func3, rd, rs1, simm12)			\
145	DEFINE_INSN_I							\
146	"insn_i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n" \
147	UNDEFINE_INSN_I
148
149#define __INSN_S(opcode, func3, rs2, simm12, rs1)			\
150	DEFINE_INSN_S							\
151	"insn_s " opcode ", " func3 ", " rs2 ", " simm12 ", " rs1 "\n"	\
152	UNDEFINE_INSN_S
153
154#endif
155
156#endif /* ! __ASSEMBLER__ */
157
158#define INSN_R(opcode, func3, func7, rd, rs1, rs2)		\
159	__INSN_R(RV_##opcode, RV_##func3, RV_##func7,		\
160		 RV_##rd, RV_##rs1, RV_##rs2)
161
162#define INSN_I(opcode, func3, rd, rs1, simm12)			\
163	__INSN_I(RV_##opcode, RV_##func3, RV_##rd,		\
164		 RV_##rs1, RV_##simm12)
165
166#define INSN_S(opcode, func3, rs2, simm12, rs1)			\
167	__INSN_S(RV_##opcode, RV_##func3, RV_##rs2,		\
168		 RV_##simm12, RV_##rs1)
169
170#define RV_OPCODE(v)		__ASM_STR(v)
171#define RV_FUNC3(v)		__ASM_STR(v)
172#define RV_FUNC7(v)		__ASM_STR(v)
173#define RV_SIMM12(v)		__ASM_STR(v)
174#define RV_RD(v)		__ASM_STR(v)
175#define RV_RS1(v)		__ASM_STR(v)
176#define RV_RS2(v)		__ASM_STR(v)
177#define __RV_REG(v)		__ASM_STR(x ## v)
178#define RV___RD(v)		__RV_REG(v)
179#define RV___RS1(v)		__RV_REG(v)
180#define RV___RS2(v)		__RV_REG(v)
181
182#define RV_OPCODE_AMO		RV_OPCODE(47)
183#define RV_OPCODE_MISC_MEM	RV_OPCODE(15)
184#define RV_OPCODE_OP_IMM	RV_OPCODE(19)
185#define RV_OPCODE_SYSTEM	RV_OPCODE(115)
186
187#define HFENCE_VVMA(vaddr, asid)				\
188	INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(17),		\
189	       __RD(0), RS1(vaddr), RS2(asid))
190
191#define HFENCE_GVMA(gaddr, vmid)				\
192	INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(49),		\
193	       __RD(0), RS1(gaddr), RS2(vmid))
194
195#define HLVX_HU(dest, addr)					\
196	INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(50),		\
197	       RD(dest), RS1(addr), __RS2(3))
198
199#define HLV_W(dest, addr)					\
200	INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(52),		\
201	       RD(dest), RS1(addr), __RS2(0))
202
203#ifdef CONFIG_64BIT
204#define HLV_D(dest, addr)					\
205	INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(54),		\
206	       RD(dest), RS1(addr), __RS2(0))
207#else
208#define HLV_D(dest, addr)					\
209	__ASM_STR(.error "hlv.d requires 64-bit support")
210#endif
211
212#define LB_AQ(dest, addr)					\
213	INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(26),			\
214	       RD(dest), RS1(addr), __RS2(0))
215
216#define LB_AQRL(dest, addr)					\
217	INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(27),			\
218	       RD(dest), RS1(addr), __RS2(0))
219
220#define LH_AQ(dest, addr)					\
221	INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(26),			\
222	       RD(dest), RS1(addr), __RS2(0))
223
224#define LH_AQRL(dest, addr)					\
225	INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(27),			\
226	       RD(dest), RS1(addr), __RS2(0))
227
228#define LW_AQ(dest, addr)					\
229	INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(26),			\
230	       RD(dest), RS1(addr), __RS2(0))
231
232#define LW_AQRL(dest, addr)					\
233	INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(27),			\
234	       RD(dest), RS1(addr), __RS2(0))
235
236#define SB_RL(src, addr)					\
237	INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(29),			\
238	       __RD(0), RS1(addr), RS2(src))
239
240#define SB_AQRL(src, addr)					\
241	INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(31),			\
242	       __RD(0), RS1(addr), RS2(src))
243
244#define SH_RL(src, addr)					\
245	INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(29),			\
246	       __RD(0), RS1(addr), RS2(src))
247
248#define SH_AQRL(src, addr)					\
249	INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(31),			\
250	       __RD(0), RS1(addr), RS2(src))
251
252#define SW_RL(src, addr)					\
253	INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(29),			\
254	       __RD(0), RS1(addr), RS2(src))
255
256#define SW_AQRL(src, addr)					\
257	INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(31),			\
258	       __RD(0), RS1(addr), RS2(src))
259
260#ifdef CONFIG_64BIT
261#define LD_AQ(dest, addr)					\
262	INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(26),			\
263	       RD(dest), RS1(addr), __RS2(0))
264
265#define LD_AQRL(dest, addr)					\
266	INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(27),			\
267	       RD(dest), RS1(addr), __RS2(0))
268
269#define SD_RL(src, addr)					\
270	INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(29),			\
271	       __RD(0), RS1(addr), RS2(src))
272
273#define SD_AQRL(src, addr)					\
274	INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(31),			\
275	       __RD(0), RS1(addr), RS2(src))
276#else
277#define LD_AQ(dest, addr)					\
278	__ASM_STR(.error "ld.aq requires 64-bit support")
279
280#define LD_AQRL(dest, addr)					\
281	__ASM_STR(.error "ld.aqrl requires 64-bit support")
282
283#define SD_RL(dest, addr)					\
284	__ASM_STR(.error "sd.rl requires 64-bit support")
285
286#define SD_AQRL(dest, addr)					\
287	__ASM_STR(.error "sd.aqrl requires 64-bit support")
288#endif
289
290#define SINVAL_VMA(vaddr, asid)					\
291	INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(11),		\
292	       __RD(0), RS1(vaddr), RS2(asid))
293
294#define SFENCE_W_INVAL()					\
295	INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(12),		\
296	       __RD(0), __RS1(0), __RS2(0))
297
298#define SFENCE_INVAL_IR()					\
299	INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(12),		\
300	       __RD(0), __RS1(0), __RS2(1))
301
302#define HINVAL_VVMA(vaddr, asid)				\
303	INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(19),		\
304	       __RD(0), RS1(vaddr), RS2(asid))
305
306#define HINVAL_GVMA(gaddr, vmid)				\
307	INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(51),		\
308	       __RD(0), RS1(gaddr), RS2(vmid))
309
310#define CBO_INVAL(base)						\
311	INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),		\
312	       RS1(base), SIMM12(0))
313
314#define CBO_CLEAN(base)						\
315	INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),		\
316	       RS1(base), SIMM12(1))
317
318#define CBO_FLUSH(base)						\
319	INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),		\
320	       RS1(base), SIMM12(2))
321
322#define CBO_ZERO(base)						\
323	INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),		\
324	       RS1(base), SIMM12(4))
325
326#define PREFETCH_I(base, offset)				\
327	INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(0),		\
328	       SIMM12((offset) & 0xfe0), RS1(base))
329
330#define PREFETCH_R(base, offset)				\
331	INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(1),		\
332	       SIMM12((offset) & 0xfe0), RS1(base))
333
334#define PREFETCH_W(base, offset)				\
335	INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(3),		\
336	       SIMM12((offset) & 0xfe0), RS1(base))
337
338#define RISCV_PAUSE	ASM_INSN_I("0x100000f")
339#define ZAWRS_WRS_NTO	ASM_INSN_I("0x00d00073")
340#define ZAWRS_WRS_STO	ASM_INSN_I("0x01d00073")
341#define RISCV_NOP4	ASM_INSN_I("0x00000013")
342
343#define RISCV_INSN_NOP4	_AC(0x00000013, U)
344
345#ifndef __ASSEMBLER__
346#define nop()           __asm__ __volatile__ ("nop")
347#define __nops(n)       ".rept  " #n "\nnop\n.endr\n"
348#define nops(n)         __asm__ __volatile__ (__nops(n))
349#endif
350
351#endif /* __ASM_INSN_DEF_H */
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