checksum.h

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Checksum routines
 4 *
 5 * Copyright (C) 2023 Rivos Inc.
 6 */
 7#ifndef __ASM_RISCV_CHECKSUM_H
 8#define __ASM_RISCV_CHECKSUM_H
 9
10#include <linux/in6.h>
11#include <linux/uaccess.h>
12
13#define ip_fast_csum ip_fast_csum
14
15extern unsigned int do_csum(const unsigned char *buff, int len);
16#define do_csum do_csum
17
18/* Default version is sufficient for 32 bit */
19#ifndef CONFIG_32BIT
20#define _HAVE_ARCH_IPV6_CSUM
21__sum16 csum_ipv6_magic(const struct in6_addr *saddr,
22			const struct in6_addr *daddr,
23			__u32 len, __u8 proto, __wsum sum);
24#endif
25
26/* Define riscv versions of functions before importing asm-generic/checksum.h */
27#include <asm-generic/checksum.h>
28
29/**
30 * Quickly compute an IP checksum with the assumption that IPv4 headers will
31 * always be in multiples of 32-bits, and have an ihl of at least 5.
32 *
33 * @ihl: the number of 32 bit segments and must be greater than or equal to 5.
34 * @iph: assumed to be word aligned given that NET_IP_ALIGN is set to 2 on
35 *  riscv, defining IP headers to be aligned.
36 */
37static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
38{
39	unsigned long csum = 0;
40	int pos = 0;
41
42	do {
43		csum += ((const unsigned int *)iph)[pos];
44		if (IS_ENABLED(CONFIG_32BIT))
45			csum += csum < ((const unsigned int *)iph)[pos];
46	} while (++pos < ihl);
47
48	/*
49	 * ZBB only saves three instructions on 32-bit and five on 64-bit so not
50	 * worth checking if supported without Alternatives.
51	 */
52	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&
53	    IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) &&
54	    riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) {
55		unsigned long fold_temp;
56
57		if (IS_ENABLED(CONFIG_32BIT)) {
58			asm(".option push				\n\
59			.option arch,+zbb				\n\
60				not	%[fold_temp], %[csum]		\n\
61				rori	%[csum], %[csum], 16		\n\
62				sub	%[csum], %[fold_temp], %[csum]	\n\
63			.option pop"
64			: [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp));
65		} else {
66			asm(".option push				\n\
67			.option arch,+zbb				\n\
68				rori	%[fold_temp], %[csum], 32	\n\
69				add	%[csum], %[fold_temp], %[csum]	\n\
70				srli	%[csum], %[csum], 32		\n\
71				not	%[fold_temp], %[csum]		\n\
72				roriw	%[csum], %[csum], 16		\n\
73				subw	%[csum], %[fold_temp], %[csum]	\n\
74			.option pop"
75			: [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp));
76		}
77		return (__force __sum16)(csum >> 16);
78	}
79
80#ifndef CONFIG_32BIT
81	csum += ror64(csum, 32);
82	csum >>= 32;
83#endif
84	return csum_fold((__force __wsum)csum);
85}
86
87#endif /* __ASM_RISCV_CHECKSUM_H */