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jh7110.dtsi
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linux-6.19.14/arch/riscv/boot/dts/starfive/jh7110.dtsi
1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2022 StarFive Technology Co., Ltd. 4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/starfive,jh7110-crg.h> 9#include <dt-bindings/power/starfive,jh7110-pmu.h> 10#include <dt-bindings/reset/starfive,jh7110-crg.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 compatible = "starfive,jh7110"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus: cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 S7_0: cpu@0 { 23 compatible = "sifive,s7", "riscv"; 24 reg = <0>; 25 device_type = "cpu"; 26 i-cache-block-size = <64>; 27 i-cache-sets = <64>; 28 i-cache-size = <16384>; 29 next-level-cache = <&ccache>; 30 riscv,isa = "rv64imac_zba_zbb"; 31 riscv,isa-base = "rv64i"; 32 riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr", 33 "zifencei", "zihpm"; 34 status = "disabled"; 35 36 cpu0_intc: interrupt-controller { 37 compatible = "riscv,cpu-intc"; 38 bootph-pre-ram; 39 interrupt-controller; 40 #interrupt-cells = <1>; 41 }; 42 }; 43 44 U74_1: cpu@1 { 45 compatible = "sifive,u74-mc", "riscv"; 46 reg = <1>; 47 d-cache-block-size = <64>; 48 d-cache-sets = <64>; 49 d-cache-size = <32768>; 50 d-tlb-sets = <1>; 51 d-tlb-size = <40>; 52 device_type = "cpu"; 53 i-cache-block-size = <64>; 54 i-cache-sets = <64>; 55 i-cache-size = <32768>; 56 i-tlb-sets = <1>; 57 i-tlb-size = <40>; 58 mmu-type = "riscv,sv39"; 59 next-level-cache = <&ccache>; 60 riscv,isa = "rv64imafdc_zba_zbb"; 61 riscv,isa-base = "rv64i"; 62 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", 63 "zicsr", "zifencei", "zihpm"; 64 tlb-split; 65 operating-points-v2 = <&cpu_opp>; 66 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; 67 clock-names = "cpu"; 68 #cooling-cells = <2>; 69 70 cpu1_intc: interrupt-controller { 71 compatible = "riscv,cpu-intc"; 72 bootph-pre-ram; 73 interrupt-controller; 74 #interrupt-cells = <1>; 75 }; 76 }; 77 78 U74_2: cpu@2 { 79 compatible = "sifive,u74-mc", "riscv"; 80 reg = <2>; 81 d-cache-block-size = <64>; 82 d-cache-sets = <64>; 83 d-cache-size = <32768>; 84 d-tlb-sets = <1>; 85 d-tlb-size = <40>; 86 device_type = "cpu"; 87 i-cache-block-size = <64>; 88 i-cache-sets = <64>; 89 i-cache-size = <32768>; 90 i-tlb-sets = <1>; 91 i-tlb-size = <40>; 92 mmu-type = "riscv,sv39"; 93 next-level-cache = <&ccache>; 94 riscv,isa = "rv64imafdc_zba_zbb"; 95 riscv,isa-base = "rv64i"; 96 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", 97 "zicsr", "zifencei", "zihpm"; 98 tlb-split; 99 operating-points-v2 = <&cpu_opp>; 100 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; 101 clock-names = "cpu"; 102 #cooling-cells = <2>; 103 104 cpu2_intc: interrupt-controller { 105 compatible = "riscv,cpu-intc"; 106 bootph-pre-ram; 107 interrupt-controller; 108 #interrupt-cells = <1>; 109 }; 110 }; 111 112 U74_3: cpu@3 { 113 compatible = "sifive,u74-mc", "riscv"; 114 reg = <3>; 115 d-cache-block-size = <64>; 116 d-cache-sets = <64>; 117 d-cache-size = <32768>; 118 d-tlb-sets = <1>; 119 d-tlb-size = <40>; 120 device_type = "cpu"; 121 i-cache-block-size = <64>; 122 i-cache-sets = <64>; 123 i-cache-size = <32768>; 124 i-tlb-sets = <1>; 125 i-tlb-size = <40>; 126 mmu-type = "riscv,sv39"; 127 next-level-cache = <&ccache>; 128 riscv,isa = "rv64imafdc_zba_zbb"; 129 riscv,isa-base = "rv64i"; 130 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", 131 "zicsr", "zifencei", "zihpm"; 132 tlb-split; 133 operating-points-v2 = <&cpu_opp>; 134 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; 135 clock-names = "cpu"; 136 #cooling-cells = <2>; 137 138 cpu3_intc: interrupt-controller { 139 compatible = "riscv,cpu-intc"; 140 bootph-pre-ram; 141 interrupt-controller; 142 #interrupt-cells = <1>; 143 }; 144 }; 145 146 U74_4: cpu@4 { 147 compatible = "sifive,u74-mc", "riscv"; 148 reg = <4>; 149 d-cache-block-size = <64>; 150 d-cache-sets = <64>; 151 d-cache-size = <32768>; 152 d-tlb-sets = <1>; 153 d-tlb-size = <40>; 154 device_type = "cpu"; 155 i-cache-block-size = <64>; 156 i-cache-sets = <64>; 157 i-cache-size = <32768>; 158 i-tlb-sets = <1>; 159 i-tlb-size = <40>; 160 mmu-type = "riscv,sv39"; 161 next-level-cache = <&ccache>; 162 riscv,isa = "rv64imafdc_zba_zbb"; 163 riscv,isa-base = "rv64i"; 164 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", 165 "zicsr", "zifencei", "zihpm"; 166 tlb-split; 167 operating-points-v2 = <&cpu_opp>; 168 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; 169 clock-names = "cpu"; 170 #cooling-cells = <2>; 171 172 cpu4_intc: interrupt-controller { 173 compatible = "riscv,cpu-intc"; 174 bootph-pre-ram; 175 interrupt-controller; 176 #interrupt-cells = <1>; 177 }; 178 }; 179 180 cpu-map { 181 cluster0 { 182 core0 { 183 cpu = <&S7_0>; 184 }; 185 186 core1 { 187 cpu = <&U74_1>; 188 }; 189 190 core2 { 191 cpu = <&U74_2>; 192 }; 193 194 core3 { 195 cpu = <&U74_3>; 196 }; 197 198 core4 { 199 cpu = <&U74_4>; 200 }; 201 }; 202 }; 203 }; 204 205 cpu_opp: opp-table-0 { 206 compatible = "operating-points-v2"; 207 opp-shared; 208 opp-375000000 { 209 opp-hz = /bits/ 64 <375000000>; 210 opp-microvolt = <800000>; 211 }; 212 opp-500000000 { 213 opp-hz = /bits/ 64 <500000000>; 214 opp-microvolt = <800000>; 215 }; 216 opp-750000000 { 217 opp-hz = /bits/ 64 <750000000>; 218 opp-microvolt = <800000>; 219 }; 220 opp-1500000000 { 221 opp-hz = /bits/ 64 <1500000000>; 222 opp-microvolt = <1040000>; 223 }; 224 }; 225 226 thermal-zones { 227 cpu-thermal { 228 polling-delay-passive = <250>; 229 polling-delay = <15000>; 230 231 thermal-sensors = <&sfctemp>; 232 233 cooling-maps { 234 map0 { 235 trip = <&cpu_alert0>; 236 cooling-device = 237 <&U74_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 238 <&U74_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 239 <&U74_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 240 <&U74_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 241 }; 242 }; 243 244 trips { 245 cpu_alert0: cpu-alert0 { 246 /* milliCelsius */ 247 temperature = <85000>; 248 hysteresis = <2000>; 249 type = "passive"; 250 }; 251 252 cpu-crit { 253 /* milliCelsius */ 254 temperature = <100000>; 255 hysteresis = <2000>; 256 type = "critical"; 257 }; 258 }; 259 }; 260 }; 261 262 dvp_clk: dvp-clock { 263 compatible = "fixed-clock"; 264 clock-output-names = "dvp_clk"; 265 #clock-cells = <0>; 266 }; 267 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { 268 compatible = "fixed-clock"; 269 clock-output-names = "gmac0_rgmii_rxin"; 270 #clock-cells = <0>; 271 }; 272 273 gmac0_rmii_refin: gmac0-rmii-refin-clock { 274 compatible = "fixed-clock"; 275 clock-output-names = "gmac0_rmii_refin"; 276 #clock-cells = <0>; 277 }; 278 279 gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { 280 compatible = "fixed-clock"; 281 bootph-pre-ram; 282 clock-output-names = "gmac1_rgmii_rxin"; 283 #clock-cells = <0>; 284 }; 285 286 gmac1_rmii_refin: gmac1-rmii-refin-clock { 287 compatible = "fixed-clock"; 288 bootph-pre-ram; 289 clock-output-names = "gmac1_rmii_refin"; 290 #clock-cells = <0>; 291 }; 292 293 hdmitx0_pixelclk: hdmitx0-pixel-clock { 294 compatible = "fixed-clock"; 295 clock-output-names = "hdmitx0_pixelclk"; 296 #clock-cells = <0>; 297 }; 298 299 i2srx_bclk_ext: i2srx-bclk-ext-clock { 300 compatible = "fixed-clock"; 301 clock-output-names = "i2srx_bclk_ext"; 302 #clock-cells = <0>; 303 }; 304 305 i2srx_lrck_ext: i2srx-lrck-ext-clock { 306 compatible = "fixed-clock"; 307 clock-output-names = "i2srx_lrck_ext"; 308 #clock-cells = <0>; 309 }; 310 311 i2stx_bclk_ext: i2stx-bclk-ext-clock { 312 compatible = "fixed-clock"; 313 clock-output-names = "i2stx_bclk_ext"; 314 #clock-cells = <0>; 315 }; 316 317 i2stx_lrck_ext: i2stx-lrck-ext-clock { 318 compatible = "fixed-clock"; 319 clock-output-names = "i2stx_lrck_ext"; 320 #clock-cells = <0>; 321 }; 322 323 mclk_ext: mclk-ext-clock { 324 compatible = "fixed-clock"; 325 clock-output-names = "mclk_ext"; 326 #clock-cells = <0>; 327 }; 328 329 osc: oscillator { 330 compatible = "fixed-clock"; 331 bootph-pre-ram; 332 clock-output-names = "osc"; 333 #clock-cells = <0>; 334 }; 335 336 rtc_osc: rtc-oscillator { 337 compatible = "fixed-clock"; 338 clock-output-names = "rtc_osc"; 339 #clock-cells = <0>; 340 }; 341 342 stmmac_axi_setup: stmmac-axi-config { 343 snps,lpi_en; 344 snps,wr_osr_lmt = <15>; 345 snps,rd_osr_lmt = <15>; 346 snps,blen = <256 128 64 32 0 0 0>; 347 }; 348 349 tdm_ext: tdm-ext-clock { 350 compatible = "fixed-clock"; 351 clock-output-names = "tdm_ext"; 352 #clock-cells = <0>; 353 }; 354 355 soc { 356 compatible = "simple-bus"; 357 interrupt-parent = <&plic>; 358 #address-cells = <2>; 359 #size-cells = <2>; 360 ranges; 361 362 clint: timer@2000000 { 363 compatible = "starfive,jh7110-clint", "sifive,clint0"; 364 reg = <0x0 0x2000000 0x0 0x10000>; 365 bootph-pre-ram; 366 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 367 <&cpu1_intc 3>, <&cpu1_intc 7>, 368 <&cpu2_intc 3>, <&cpu2_intc 7>, 369 <&cpu3_intc 3>, <&cpu3_intc 7>, 370 <&cpu4_intc 3>, <&cpu4_intc 7>; 371 }; 372 373 ccache: cache-controller@2010000 { 374 compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache"; 375 reg = <0x0 0x2010000 0x0 0x4000>; 376 interrupts = <1>, <3>, <4>, <2>; 377 cache-block-size = <64>; 378 cache-level = <2>; 379 cache-sets = <2048>; 380 cache-size = <2097152>; 381 cache-unified; 382 }; 383 384 plic: interrupt-controller@c000000 { 385 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; 386 reg = <0x0 0xc000000 0x0 0x4000000>; 387 interrupts-extended = <&cpu0_intc 11>, 388 <&cpu1_intc 11>, <&cpu1_intc 9>, 389 <&cpu2_intc 11>, <&cpu2_intc 9>, 390 <&cpu3_intc 11>, <&cpu3_intc 9>, 391 <&cpu4_intc 11>, <&cpu4_intc 9>; 392 interrupt-controller; 393 #interrupt-cells = <1>; 394 #address-cells = <0>; 395 riscv,ndev = <136>; 396 }; 397 398 uart0: serial@10000000 { 399 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart"; 400 reg = <0x0 0x10000000 0x0 0x10000>; 401 clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>, 402 <&syscrg JH7110_SYSCLK_UART0_APB>; 403 clock-names = "baudclk", "apb_pclk"; 404 resets = <&syscrg JH7110_SYSRST_UART0_APB>, 405 <&syscrg JH7110_SYSRST_UART0_CORE>; 406 interrupts = <32>; 407 reg-io-width = <4>; 408 reg-shift = <2>; 409 status = "disabled"; 410 }; 411 412 uart1: serial@10010000 { 413 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart"; 414 reg = <0x0 0x10010000 0x0 0x10000>; 415 clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>, 416 <&syscrg JH7110_SYSCLK_UART1_APB>; 417 clock-names = "baudclk", "apb_pclk"; 418 resets = <&syscrg JH7110_SYSRST_UART1_APB>, 419 <&syscrg JH7110_SYSRST_UART1_CORE>; 420 interrupts = <33>; 421 reg-io-width = <4>; 422 reg-shift = <2>; 423 status = "disabled"; 424 }; 425 426 uart2: serial@10020000 { 427 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart"; 428 reg = <0x0 0x10020000 0x0 0x10000>; 429 clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>, 430 <&syscrg JH7110_SYSCLK_UART2_APB>; 431 clock-names = "baudclk", "apb_pclk"; 432 resets = <&syscrg JH7110_SYSRST_UART2_APB>, 433 <&syscrg JH7110_SYSRST_UART2_CORE>; 434 interrupts = <34>; 435 reg-io-width = <4>; 436 reg-shift = <2>; 437 status = "disabled"; 438 }; 439 440 i2c0: i2c@10030000 { 441 compatible = "snps,designware-i2c"; 442 reg = <0x0 0x10030000 0x0 0x10000>; 443 clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>; 444 clock-names = "ref"; 445 resets = <&syscrg JH7110_SYSRST_I2C0_APB>; 446 interrupts = <35>; 447 #address-cells = <1>; 448 #size-cells = <0>; 449 status = "disabled"; 450 }; 451 452 i2c1: i2c@10040000 { 453 compatible = "snps,designware-i2c"; 454 reg = <0x0 0x10040000 0x0 0x10000>; 455 clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>; 456 clock-names = "ref"; 457 resets = <&syscrg JH7110_SYSRST_I2C1_APB>; 458 interrupts = <36>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 status = "disabled"; 462 }; 463 464 i2c2: i2c@10050000 { 465 compatible = "snps,designware-i2c"; 466 reg = <0x0 0x10050000 0x0 0x10000>; 467 clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>; 468 clock-names = "ref"; 469 resets = <&syscrg JH7110_SYSRST_I2C2_APB>; 470 interrupts = <37>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 status = "disabled"; 474 }; 475 476 spi0: spi@10060000 { 477 compatible = "arm,pl022", "arm,primecell"; 478 reg = <0x0 0x10060000 0x0 0x10000>; 479 clocks = <&syscrg JH7110_SYSCLK_SPI0_APB>, 480 <&syscrg JH7110_SYSCLK_SPI0_APB>; 481 clock-names = "sspclk", "apb_pclk"; 482 resets = <&syscrg JH7110_SYSRST_SPI0_APB>; 483 interrupts = <38>; 484 arm,primecell-periphid = <0x00041022>; 485 num-cs = <1>; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 status = "disabled"; 489 }; 490 491 spi1: spi@10070000 { 492 compatible = "arm,pl022", "arm,primecell"; 493 reg = <0x0 0x10070000 0x0 0x10000>; 494 clocks = <&syscrg JH7110_SYSCLK_SPI1_APB>, 495 <&syscrg JH7110_SYSCLK_SPI1_APB>; 496 clock-names = "sspclk", "apb_pclk"; 497 resets = <&syscrg JH7110_SYSRST_SPI1_APB>; 498 interrupts = <39>; 499 arm,primecell-periphid = <0x00041022>; 500 num-cs = <1>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 status = "disabled"; 504 }; 505 506 spi2: spi@10080000 { 507 compatible = "arm,pl022", "arm,primecell"; 508 reg = <0x0 0x10080000 0x0 0x10000>; 509 clocks = <&syscrg JH7110_SYSCLK_SPI2_APB>, 510 <&syscrg JH7110_SYSCLK_SPI2_APB>; 511 clock-names = "sspclk", "apb_pclk"; 512 resets = <&syscrg JH7110_SYSRST_SPI2_APB>; 513 interrupts = <40>; 514 arm,primecell-periphid = <0x00041022>; 515 num-cs = <1>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 status = "disabled"; 519 }; 520 521 tdm: tdm@10090000 { 522 compatible = "starfive,jh7110-tdm"; 523 reg = <0x0 0x10090000 0x0 0x1000>; 524 clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>, 525 <&syscrg JH7110_SYSCLK_TDM_APB>, 526 <&syscrg JH7110_SYSCLK_TDM_INTERNAL>, 527 <&syscrg JH7110_SYSCLK_TDM_TDM>, 528 <&syscrg JH7110_SYSCLK_MCLK_INNER>, 529 <&tdm_ext>; 530 clock-names = "tdm_ahb", "tdm_apb", 531 "tdm_internal", "tdm", 532 "mclk_inner", "tdm_ext"; 533 resets = <&syscrg JH7110_SYSRST_TDM_AHB>, 534 <&syscrg JH7110_SYSRST_TDM_APB>, 535 <&syscrg JH7110_SYSRST_TDM_CORE>; 536 dmas = <&dma 20>, <&dma 21>; 537 dma-names = "rx","tx"; 538 #sound-dai-cells = <0>; 539 status = "disabled"; 540 }; 541 542 i2srx: i2s@100e0000 { 543 compatible = "starfive,jh7110-i2srx"; 544 reg = <0x0 0x100e0000 0x0 0x1000>; 545 clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>, 546 <&syscrg JH7110_SYSCLK_I2SRX_APB>, 547 <&syscrg JH7110_SYSCLK_MCLK>, 548 <&syscrg JH7110_SYSCLK_MCLK_INNER>, 549 <&mclk_ext>, 550 <&syscrg JH7110_SYSCLK_I2SRX_BCLK>, 551 <&syscrg JH7110_SYSCLK_I2SRX_LRCK>, 552 <&i2srx_bclk_ext>, 553 <&i2srx_lrck_ext>; 554 clock-names = "i2sclk", "apb", "mclk", 555 "mclk_inner", "mclk_ext", "bclk", 556 "lrck", "bclk_ext", "lrck_ext"; 557 resets = <&syscrg JH7110_SYSRST_I2SRX_APB>, 558 <&syscrg JH7110_SYSRST_I2SRX_BCLK>; 559 dmas = <0>, <&dma 24>; 560 dma-names = "tx", "rx"; 561 starfive,syscon = <&sys_syscon 0x18 0x2>; 562 #sound-dai-cells = <0>; 563 status = "disabled"; 564 }; 565 566 pwmdac: pwmdac@100b0000 { 567 compatible = "starfive,jh7110-pwmdac"; 568 reg = <0x0 0x100b0000 0x0 0x1000>; 569 clocks = <&syscrg JH7110_SYSCLK_PWMDAC_APB>, 570 <&syscrg JH7110_SYSCLK_PWMDAC_CORE>; 571 clock-names = "apb", "core"; 572 resets = <&syscrg JH7110_SYSRST_PWMDAC_APB>; 573 dmas = <&dma 22>; 574 dma-names = "tx"; 575 #sound-dai-cells = <0>; 576 status = "disabled"; 577 }; 578 579 usb0: usb@10100000 { 580 compatible = "starfive,jh7110-usb"; 581 ranges = <0x0 0x0 0x10100000 0x100000>; 582 #address-cells = <1>; 583 #size-cells = <1>; 584 starfive,stg-syscon = <&stg_syscon 0x4>; 585 clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>, 586 <&stgcrg JH7110_STGCLK_USB0_STB>, 587 <&stgcrg JH7110_STGCLK_USB0_APB>, 588 <&stgcrg JH7110_STGCLK_USB0_AXI>, 589 <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>; 590 clock-names = "lpm", "stb", "apb", "axi", "utmi_apb"; 591 resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>, 592 <&stgcrg JH7110_STGRST_USB0_APB>, 593 <&stgcrg JH7110_STGRST_USB0_AXI>, 594 <&stgcrg JH7110_STGRST_USB0_UTMI_APB>; 595 reset-names = "pwrup", "apb", "axi", "utmi_apb"; 596 status = "disabled"; 597 598 usb_cdns3: usb@0 { 599 compatible = "cdns,usb3"; 600 reg = <0x0 0x10000>, 601 <0x10000 0x10000>, 602 <0x20000 0x10000>; 603 reg-names = "otg", "xhci", "dev"; 604 interrupts = <100>, <108>, <110>; 605 interrupt-names = "host", "peripheral", "otg"; 606 phys = <&usbphy0>; 607 phy-names = "cdns3,usb2-phy"; 608 }; 609 }; 610 611 usbphy0: phy@10200000 { 612 compatible = "starfive,jh7110-usb-phy"; 613 reg = <0x0 0x10200000 0x0 0x10000>; 614 clocks = <&syscrg JH7110_SYSCLK_USB_125M>, 615 <&stgcrg JH7110_STGCLK_USB0_APP_125>; 616 clock-names = "125m", "app_125m"; 617 #phy-cells = <0>; 618 }; 619 620 pciephy0: phy@10210000 { 621 compatible = "starfive,jh7110-pcie-phy"; 622 reg = <0x0 0x10210000 0x0 0x10000>; 623 starfive,sys-syscon = <&sys_syscon 0x18>; 624 starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>; 625 #phy-cells = <0>; 626 }; 627 628 pciephy1: phy@10220000 { 629 compatible = "starfive,jh7110-pcie-phy"; 630 reg = <0x0 0x10220000 0x0 0x10000>; 631 #phy-cells = <0>; 632 }; 633 634 stgcrg: clock-controller@10230000 { 635 compatible = "starfive,jh7110-stgcrg"; 636 reg = <0x0 0x10230000 0x0 0x10000>; 637 clocks = <&osc>, 638 <&syscrg JH7110_SYSCLK_HIFI4_CORE>, 639 <&syscrg JH7110_SYSCLK_STG_AXIAHB>, 640 <&syscrg JH7110_SYSCLK_USB_125M>, 641 <&syscrg JH7110_SYSCLK_CPU_BUS>, 642 <&syscrg JH7110_SYSCLK_HIFI4_AXI>, 643 <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, 644 <&syscrg JH7110_SYSCLK_APB_BUS>; 645 clock-names = "osc", "hifi4_core", 646 "stg_axiahb", "usb_125m", 647 "cpu_bus", "hifi4_axi", 648 "nocstg_bus", "apb_bus"; 649 #clock-cells = <1>; 650 #reset-cells = <1>; 651 }; 652 653 stg_syscon: syscon@10240000 { 654 compatible = "starfive,jh7110-stg-syscon", "syscon"; 655 reg = <0x0 0x10240000 0x0 0x1000>; 656 }; 657 658 uart3: serial@12000000 { 659 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart"; 660 reg = <0x0 0x12000000 0x0 0x10000>; 661 clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>, 662 <&syscrg JH7110_SYSCLK_UART3_APB>; 663 clock-names = "baudclk", "apb_pclk"; 664 resets = <&syscrg JH7110_SYSRST_UART3_APB>, 665 <&syscrg JH7110_SYSRST_UART3_CORE>; 666 interrupts = <45>; 667 reg-io-width = <4>; 668 reg-shift = <2>; 669 status = "disabled"; 670 }; 671 672 uart4: serial@12010000 { 673 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart"; 674 reg = <0x0 0x12010000 0x0 0x10000>; 675 clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>, 676 <&syscrg JH7110_SYSCLK_UART4_APB>; 677 clock-names = "baudclk", "apb_pclk"; 678 resets = <&syscrg JH7110_SYSRST_UART4_APB>, 679 <&syscrg JH7110_SYSRST_UART4_CORE>; 680 interrupts = <46>; 681 reg-io-width = <4>; 682 reg-shift = <2>; 683 status = "disabled"; 684 }; 685 686 uart5: serial@12020000 { 687 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart"; 688 reg = <0x0 0x12020000 0x0 0x10000>; 689 clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>, 690 <&syscrg JH7110_SYSCLK_UART5_APB>; 691 clock-names = "baudclk", "apb_pclk"; 692 resets = <&syscrg JH7110_SYSRST_UART5_APB>, 693 <&syscrg JH7110_SYSRST_UART5_CORE>; 694 interrupts = <47>; 695 reg-io-width = <4>; 696 reg-shift = <2>; 697 status = "disabled"; 698 }; 699 700 i2c3: i2c@12030000 { 701 compatible = "snps,designware-i2c"; 702 reg = <0x0 0x12030000 0x0 0x10000>; 703 clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>; 704 clock-names = "ref"; 705 resets = <&syscrg JH7110_SYSRST_I2C3_APB>; 706 interrupts = <48>; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 status = "disabled"; 710 }; 711 712 i2c4: i2c@12040000 { 713 compatible = "snps,designware-i2c"; 714 reg = <0x0 0x12040000 0x0 0x10000>; 715 clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>; 716 clock-names = "ref"; 717 resets = <&syscrg JH7110_SYSRST_I2C4_APB>; 718 interrupts = <49>; 719 #address-cells = <1>; 720 #size-cells = <0>; 721 status = "disabled"; 722 }; 723 724 i2c5: i2c@12050000 { 725 compatible = "snps,designware-i2c"; 726 reg = <0x0 0x12050000 0x0 0x10000>; 727 clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>; 728 clock-names = "ref"; 729 resets = <&syscrg JH7110_SYSRST_I2C5_APB>; 730 interrupts = <50>; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 status = "disabled"; 734 }; 735 736 i2c6: i2c@12060000 { 737 compatible = "snps,designware-i2c"; 738 reg = <0x0 0x12060000 0x0 0x10000>; 739 clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>; 740 clock-names = "ref"; 741 resets = <&syscrg JH7110_SYSRST_I2C6_APB>; 742 interrupts = <51>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 status = "disabled"; 746 }; 747 748 spi3: spi@12070000 { 749 compatible = "arm,pl022", "arm,primecell"; 750 reg = <0x0 0x12070000 0x0 0x10000>; 751 clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>, 752 <&syscrg JH7110_SYSCLK_SPI3_APB>; 753 clock-names = "sspclk", "apb_pclk"; 754 resets = <&syscrg JH7110_SYSRST_SPI3_APB>; 755 interrupts = <52>; 756 arm,primecell-periphid = <0x00041022>; 757 num-cs = <1>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 status = "disabled"; 761 }; 762 763 spi4: spi@12080000 { 764 compatible = "arm,pl022", "arm,primecell"; 765 reg = <0x0 0x12080000 0x0 0x10000>; 766 clocks = <&syscrg JH7110_SYSCLK_SPI4_APB>, 767 <&syscrg JH7110_SYSCLK_SPI4_APB>; 768 clock-names = "sspclk", "apb_pclk"; 769 resets = <&syscrg JH7110_SYSRST_SPI4_APB>; 770 interrupts = <53>; 771 arm,primecell-periphid = <0x00041022>; 772 num-cs = <1>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 status = "disabled"; 776 }; 777 778 spi5: spi@12090000 { 779 compatible = "arm,pl022", "arm,primecell"; 780 reg = <0x0 0x12090000 0x0 0x10000>; 781 clocks = <&syscrg JH7110_SYSCLK_SPI5_APB>, 782 <&syscrg JH7110_SYSCLK_SPI5_APB>; 783 clock-names = "sspclk", "apb_pclk"; 784 resets = <&syscrg JH7110_SYSRST_SPI5_APB>; 785 interrupts = <54>; 786 arm,primecell-periphid = <0x00041022>; 787 num-cs = <1>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 status = "disabled"; 791 }; 792 793 spi6: spi@120a0000 { 794 compatible = "arm,pl022", "arm,primecell"; 795 reg = <0x0 0x120A0000 0x0 0x10000>; 796 clocks = <&syscrg JH7110_SYSCLK_SPI6_APB>, 797 <&syscrg JH7110_SYSCLK_SPI6_APB>; 798 clock-names = "sspclk", "apb_pclk"; 799 resets = <&syscrg JH7110_SYSRST_SPI6_APB>; 800 interrupts = <55>; 801 arm,primecell-periphid = <0x00041022>; 802 num-cs = <1>; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 status = "disabled"; 806 }; 807 808 i2stx0: i2s@120b0000 { 809 compatible = "starfive,jh7110-i2stx0"; 810 reg = <0x0 0x120b0000 0x0 0x1000>; 811 clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>, 812 <&syscrg JH7110_SYSCLK_I2STX0_APB>, 813 <&syscrg JH7110_SYSCLK_MCLK>, 814 <&syscrg JH7110_SYSCLK_MCLK_INNER>, 815 <&mclk_ext>; 816 clock-names = "i2sclk", "apb", "mclk", 817 "mclk_inner","mclk_ext"; 818 resets = <&syscrg JH7110_SYSRST_I2STX0_APB>, 819 <&syscrg JH7110_SYSRST_I2STX0_BCLK>; 820 dmas = <&dma 47>; 821 dma-names = "tx"; 822 #sound-dai-cells = <0>; 823 status = "disabled"; 824 }; 825 826 i2stx1: i2s@120c0000 { 827 compatible = "starfive,jh7110-i2stx1"; 828 reg = <0x0 0x120c0000 0x0 0x1000>; 829 clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>, 830 <&syscrg JH7110_SYSCLK_I2STX1_APB>, 831 <&syscrg JH7110_SYSCLK_MCLK>, 832 <&syscrg JH7110_SYSCLK_MCLK_INNER>, 833 <&mclk_ext>, 834 <&syscrg JH7110_SYSCLK_I2STX1_BCLK>, 835 <&syscrg JH7110_SYSCLK_I2STX1_LRCK>, 836 <&i2stx_bclk_ext>, 837 <&i2stx_lrck_ext>; 838 clock-names = "i2sclk", "apb", "mclk", 839 "mclk_inner", "mclk_ext", "bclk", 840 "lrck", "bclk_ext", "lrck_ext"; 841 resets = <&syscrg JH7110_SYSRST_I2STX1_APB>, 842 <&syscrg JH7110_SYSRST_I2STX1_BCLK>; 843 dmas = <&dma 48>; 844 dma-names = "tx"; 845 #sound-dai-cells = <0>; 846 status = "disabled"; 847 }; 848 849 pwm: pwm@120d0000 { 850 compatible = "starfive,jh7110-pwm", "opencores,pwm-v1"; 851 reg = <0x0 0x120d0000 0x0 0x10000>; 852 clocks = <&syscrg JH7110_SYSCLK_PWM_APB>; 853 resets = <&syscrg JH7110_SYSRST_PWM_APB>; 854 #pwm-cells = <3>; 855 status = "disabled"; 856 }; 857 858 sfctemp: temperature-sensor@120e0000 { 859 compatible = "starfive,jh7110-temp"; 860 reg = <0x0 0x120e0000 0x0 0x10000>; 861 clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>, 862 <&syscrg JH7110_SYSCLK_TEMP_APB>; 863 clock-names = "sense", "bus"; 864 resets = <&syscrg JH7110_SYSRST_TEMP_CORE>, 865 <&syscrg JH7110_SYSRST_TEMP_APB>; 866 reset-names = "sense", "bus"; 867 #thermal-sensor-cells = <0>; 868 }; 869 870 qspi: spi@13010000 { 871 compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; 872 reg = <0x0 0x13010000 0x0 0x10000>, 873 <0x0 0x21000000 0x0 0x400000>; 874 interrupts = <25>; 875 clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>, 876 <&syscrg JH7110_SYSCLK_QSPI_AHB>, 877 <&syscrg JH7110_SYSCLK_QSPI_APB>; 878 clock-names = "ref", "ahb", "apb"; 879 resets = <&syscrg JH7110_SYSRST_QSPI_APB>, 880 <&syscrg JH7110_SYSRST_QSPI_AHB>, 881 <&syscrg JH7110_SYSRST_QSPI_REF>; 882 reset-names = "qspi", "qspi-ocp", "rstc_ref"; 883 cdns,fifo-depth = <256>; 884 cdns,fifo-width = <4>; 885 cdns,trigger-address = <0x0>; 886 status = "disabled"; 887 }; 888 889 syscrg: clock-controller@13020000 { 890 compatible = "starfive,jh7110-syscrg"; 891 reg = <0x0 0x13020000 0x0 0x10000>; 892 bootph-pre-ram; 893 clocks = <&osc>, <&gmac1_rmii_refin>, 894 <&gmac1_rgmii_rxin>, 895 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, 896 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, 897 <&tdm_ext>, <&mclk_ext>, 898 <&pllclk JH7110_PLLCLK_PLL0_OUT>, 899 <&pllclk JH7110_PLLCLK_PLL1_OUT>, 900 <&pllclk JH7110_PLLCLK_PLL2_OUT>; 901 clock-names = "osc", "gmac1_rmii_refin", 902 "gmac1_rgmii_rxin", 903 "i2stx_bclk_ext", "i2stx_lrck_ext", 904 "i2srx_bclk_ext", "i2srx_lrck_ext", 905 "tdm_ext", "mclk_ext", 906 "pll0_out", "pll1_out", "pll2_out"; 907 #clock-cells = <1>; 908 #reset-cells = <1>; 909 }; 910 911 sys_syscon: syscon@13030000 { 912 compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; 913 reg = <0x0 0x13030000 0x0 0x1000>; 914 915 pllclk: clock-controller { 916 compatible = "starfive,jh7110-pll"; 917 bootph-pre-ram; 918 clocks = <&osc>; 919 #clock-cells = <1>; 920 }; 921 }; 922 923 sysgpio: pinctrl@13040000 { 924 compatible = "starfive,jh7110-sys-pinctrl"; 925 reg = <0x0 0x13040000 0x0 0x10000>; 926 clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>; 927 resets = <&syscrg JH7110_SYSRST_IOMUX_APB>; 928 interrupts = <86>; 929 interrupt-controller; 930 #interrupt-cells = <2>; 931 gpio-controller; 932 #gpio-cells = <2>; 933 }; 934 935 watchdog@13070000 { 936 compatible = "starfive,jh7110-wdt"; 937 reg = <0x0 0x13070000 0x0 0x10000>; 938 clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, 939 <&syscrg JH7110_SYSCLK_WDT_CORE>; 940 clock-names = "apb", "core"; 941 resets = <&syscrg JH7110_SYSRST_WDT_APB>, 942 <&syscrg JH7110_SYSRST_WDT_CORE>; 943 }; 944 945 memory-controller@15700000 { 946 compatible = "starfive,jh7110-dmc"; 947 reg = <0x0 0x15700000 0x0 0x10000>, 948 <0x0 0x13000000 0x0 0x10000>; 949 bootph-pre-ram; 950 clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; 951 clock-names = "pll"; 952 resets = <&syscrg JH7110_SYSRST_DDR_AXI>, 953 <&syscrg JH7110_SYSRST_DDR_OSC>, 954 <&syscrg JH7110_SYSRST_DDR_APB>; 955 reset-names = "axi", "osc", "apb"; 956 }; 957 958 crypto: crypto@16000000 { 959 compatible = "starfive,jh7110-crypto"; 960 reg = <0x0 0x16000000 0x0 0x4000>; 961 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, 962 <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; 963 clock-names = "hclk", "ahb"; 964 interrupts = <28>; 965 resets = <&stgcrg JH7110_STGRST_SEC_AHB>; 966 dmas = <&sdma 1 2>, <&sdma 0 2>; 967 dma-names = "tx", "rx"; 968 }; 969 970 sdma: dma-controller@16008000 { 971 compatible = "arm,pl080", "arm,primecell"; 972 arm,primecell-periphid = <0x00041080>; 973 reg = <0x0 0x16008000 0x0 0x4000>; 974 interrupts = <29>; 975 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>; 976 clock-names = "apb_pclk"; 977 resets = <&stgcrg JH7110_STGRST_SEC_AHB>; 978 lli-bus-interface-ahb1; 979 mem-bus-interface-ahb1; 980 memcpy-burst-size = <256>; 981 memcpy-bus-width = <32>; 982 #dma-cells = <2>; 983 }; 984 985 rng: rng@1600c000 { 986 compatible = "starfive,jh7110-trng"; 987 reg = <0x0 0x1600C000 0x0 0x4000>; 988 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, 989 <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; 990 clock-names = "hclk", "ahb"; 991 resets = <&stgcrg JH7110_STGRST_SEC_AHB>; 992 interrupts = <30>; 993 }; 994 995 mmc0: mmc@16010000 { 996 compatible = "starfive,jh7110-mmc"; 997 reg = <0x0 0x16010000 0x0 0x10000>; 998 clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>, 999 <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; 1000 clock-names = "biu","ciu"; 1001 resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>; 1002 reset-names = "reset"; 1003 interrupts = <74>; 1004 fifo-depth = <32>; 1005 fifo-watermark-aligned; 1006 data-addr = <0>; 1007 starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>; 1008 status = "disabled"; 1009 }; 1010 1011 mmc1: mmc@16020000 { 1012 compatible = "starfive,jh7110-mmc"; 1013 reg = <0x0 0x16020000 0x0 0x10000>; 1014 clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>, 1015 <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; 1016 clock-names = "biu","ciu"; 1017 resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>; 1018 reset-names = "reset"; 1019 interrupts = <75>; 1020 fifo-depth = <32>; 1021 fifo-watermark-aligned; 1022 data-addr = <0>; 1023 starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>; 1024 status = "disabled"; 1025 }; 1026 1027 gmac0: ethernet@16030000 { 1028 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; 1029 reg = <0x0 0x16030000 0x0 0x10000>; 1030 clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, 1031 <&aoncrg JH7110_AONCLK_GMAC0_AHB>, 1032 <&syscrg JH7110_SYSCLK_GMAC0_PTP>, 1033 <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, 1034 <&syscrg JH7110_SYSCLK_GMAC0_GTXC>; 1035 clock-names = "stmmaceth", "pclk", "ptp_ref", 1036 "tx", "gtx"; 1037 resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, 1038 <&aoncrg JH7110_AONRST_GMAC0_AHB>; 1039 reset-names = "stmmaceth", "ahb"; 1040 interrupts = <7>, <6>, <5>; 1041 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 1042 rx-fifo-depth = <2048>; 1043 tx-fifo-depth = <2048>; 1044 snps,multicast-filter-bins = <64>; 1045 snps,perfect-filter-entries = <256>; 1046 snps,fixed-burst; 1047 snps,no-pbl-x8; 1048 snps,force_thresh_dma_mode; 1049 snps,axi-config = <&stmmac_axi_setup>; 1050 snps,tso; 1051 snps,txpbl = <16>; 1052 snps,rxpbl = <16>; 1053 starfive,syscon = <&aon_syscon 0xc 0x12>; 1054 status = "disabled"; 1055 }; 1056 1057 gmac1: ethernet@16040000 { 1058 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; 1059 reg = <0x0 0x16040000 0x0 0x10000>; 1060 clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, 1061 <&syscrg JH7110_SYSCLK_GMAC1_AHB>, 1062 <&syscrg JH7110_SYSCLK_GMAC1_PTP>, 1063 <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>, 1064 <&syscrg JH7110_SYSCLK_GMAC1_GTXC>; 1065 clock-names = "stmmaceth", "pclk", "ptp_ref", 1066 "tx", "gtx"; 1067 resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, 1068 <&syscrg JH7110_SYSRST_GMAC1_AHB>; 1069 reset-names = "stmmaceth", "ahb"; 1070 interrupts = <78>, <77>, <76>; 1071 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 1072 rx-fifo-depth = <2048>; 1073 tx-fifo-depth = <2048>; 1074 snps,multicast-filter-bins = <64>; 1075 snps,perfect-filter-entries = <256>; 1076 snps,fixed-burst; 1077 snps,no-pbl-x8; 1078 snps,force_thresh_dma_mode; 1079 snps,axi-config = <&stmmac_axi_setup>; 1080 snps,tso; 1081 snps,txpbl = <16>; 1082 snps,rxpbl = <16>; 1083 starfive,syscon = <&sys_syscon 0x90 0x2>; 1084 status = "disabled"; 1085 }; 1086 1087 dma: dma-controller@16050000 { 1088 compatible = "starfive,jh7110-axi-dma"; 1089 reg = <0x0 0x16050000 0x0 0x10000>; 1090 clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>, 1091 <&stgcrg JH7110_STGCLK_DMA1P_AHB>; 1092 clock-names = "core-clk", "cfgr-clk"; 1093 resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>, 1094 <&stgcrg JH7110_STGRST_DMA1P_AHB>; 1095 interrupts = <73>; 1096 #dma-cells = <1>; 1097 dma-channels = <4>; 1098 snps,dma-masters = <1>; 1099 snps,data-width = <3>; 1100 snps,block-size = <65536 65536 65536 65536>; 1101 snps,priority = <0 1 2 3>; 1102 snps,axi-max-burst-len = <16>; 1103 }; 1104 1105 aoncrg: clock-controller@17000000 { 1106 compatible = "starfive,jh7110-aoncrg"; 1107 reg = <0x0 0x17000000 0x0 0x10000>; 1108 clocks = <&osc>, <&gmac0_rmii_refin>, 1109 <&gmac0_rgmii_rxin>, 1110 <&syscrg JH7110_SYSCLK_STG_AXIAHB>, 1111 <&syscrg JH7110_SYSCLK_APB_BUS>, 1112 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>, 1113 <&rtc_osc>; 1114 clock-names = "osc", "gmac0_rmii_refin", 1115 "gmac0_rgmii_rxin", "stg_axiahb", 1116 "apb_bus", "gmac0_gtxclk", 1117 "rtc_osc"; 1118 #clock-cells = <1>; 1119 #reset-cells = <1>; 1120 }; 1121 1122 aon_syscon: syscon@17010000 { 1123 compatible = "starfive,jh7110-aon-syscon", "syscon"; 1124 reg = <0x0 0x17010000 0x0 0x1000>; 1125 #power-domain-cells = <1>; 1126 }; 1127 1128 aongpio: pinctrl@17020000 { 1129 compatible = "starfive,jh7110-aon-pinctrl"; 1130 reg = <0x0 0x17020000 0x0 0x10000>; 1131 resets = <&aoncrg JH7110_AONRST_IOMUX>; 1132 interrupts = <85>; 1133 interrupt-controller; 1134 #interrupt-cells = <2>; 1135 gpio-controller; 1136 #gpio-cells = <2>; 1137 }; 1138 1139 pwrc: power-controller@17030000 { 1140 compatible = "starfive,jh7110-pmu"; 1141 reg = <0x0 0x17030000 0x0 0x10000>; 1142 interrupts = <111>; 1143 #power-domain-cells = <1>; 1144 }; 1145 1146 csi2rx: csi@19800000 { 1147 compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx"; 1148 reg = <0x0 0x19800000 0x0 0x10000>; 1149 clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>, 1150 <&ispcrg JH7110_ISPCLK_VIN_APB>, 1151 <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF0>, 1152 <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF1>, 1153 <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF2>, 1154 <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF3>; 1155 clock-names = "sys_clk", "p_clk", 1156 "pixel_if0_clk", "pixel_if1_clk", 1157 "pixel_if2_clk", "pixel_if3_clk"; 1158 resets = <&ispcrg JH7110_ISPRST_VIN_SYS>, 1159 <&ispcrg JH7110_ISPRST_VIN_APB>, 1160 <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF0>, 1161 <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF1>, 1162 <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF2>, 1163 <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF3>; 1164 reset-names = "sys", "reg_bank", 1165 "pixel_if0", "pixel_if1", 1166 "pixel_if2", "pixel_if3"; 1167 phys = <&csi_phy>; 1168 phy-names = "dphy"; 1169 status = "disabled"; 1170 }; 1171 1172 ispcrg: clock-controller@19810000 { 1173 compatible = "starfive,jh7110-ispcrg"; 1174 reg = <0x0 0x19810000 0x0 0x10000>; 1175 clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, 1176 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, 1177 <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, 1178 <&dvp_clk>; 1179 clock-names = "isp_top_core", "isp_top_axi", 1180 "noc_bus_isp_axi", "dvp_clk"; 1181 resets = <&syscrg JH7110_SYSRST_ISP_TOP>, 1182 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, 1183 <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; 1184 #clock-cells = <1>; 1185 #reset-cells = <1>; 1186 power-domains = <&pwrc JH7110_PD_ISP>; 1187 }; 1188 1189 csi_phy: phy@19820000 { 1190 compatible = "starfive,jh7110-dphy-rx"; 1191 reg = <0x0 0x19820000 0x0 0x10000>; 1192 clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>, 1193 <&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>, 1194 <&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>; 1195 clock-names = "cfg", "ref", "tx"; 1196 resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>, 1197 <&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>; 1198 power-domains = <&aon_syscon JH7110_AON_PD_DPHY_RX>; 1199 #phy-cells = <0>; 1200 }; 1201 1202 camss: isp@19840000 { 1203 compatible = "starfive,jh7110-camss"; 1204 reg = <0x0 0x19840000 0x0 0x10000>, 1205 <0x0 0x19870000 0x0 0x30000>; 1206 reg-names = "syscon", "isp"; 1207 clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>, 1208 <&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>, 1209 <&ispcrg JH7110_ISPCLK_DVP_INV>, 1210 <&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>, 1211 <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>, 1212 <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, 1213 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>; 1214 clock-names = "apb_func", "wrapper_clk_c", "dvp_inv", 1215 "axiwr", "mipi_rx0_pxl", "ispcore_2x", 1216 "isp_axi"; 1217 resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>, 1218 <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>, 1219 <&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>, 1220 <&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>, 1221 <&syscrg JH7110_SYSRST_ISP_TOP>, 1222 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>; 1223 reset-names = "wrapper_p", "wrapper_c", "axird", 1224 "axiwr", "isp_top_n", "isp_top_axi"; 1225 power-domains = <&pwrc JH7110_PD_ISP>; 1226 interrupts = <92>, <87>, <90>, <88>; 1227 status = "disabled"; 1228 }; 1229 1230 voutcrg: clock-controller@295c0000 { 1231 compatible = "starfive,jh7110-voutcrg"; 1232 reg = <0x0 0x295c0000 0x0 0x10000>; 1233 clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, 1234 <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, 1235 <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, 1236 <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, 1237 <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, 1238 <&hdmitx0_pixelclk>; 1239 clock-names = "vout_src", "vout_top_ahb", 1240 "vout_top_axi", "vout_top_hdmitx0_mclk", 1241 "i2stx0_bclk", "hdmitx0_pixelclk"; 1242 resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; 1243 #clock-cells = <1>; 1244 #reset-cells = <1>; 1245 power-domains = <&pwrc JH7110_PD_VOUT>; 1246 }; 1247 1248 pcie0: pcie@940000000 { 1249 compatible = "starfive,jh7110-pcie"; 1250 reg = <0x9 0x40000000 0x0 0x1000000>, 1251 <0x0 0x2b000000 0x0 0x100000>; 1252 reg-names = "cfg", "apb"; 1253 linux,pci-domain = <0>; 1254 #address-cells = <3>; 1255 #size-cells = <2>; 1256 #interrupt-cells = <1>; 1257 ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, 1258 <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; 1259 interrupts = <56>; 1260 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 1261 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, 1262 <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, 1263 <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, 1264 <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; 1265 msi-controller; 1266 device_type = "pci"; 1267 starfive,stg-syscon = <&stg_syscon>; 1268 bus-range = <0x0 0xff>; 1269 clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, 1270 <&stgcrg JH7110_STGCLK_PCIE0_TL>, 1271 <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>, 1272 <&stgcrg JH7110_STGCLK_PCIE0_APB>; 1273 clock-names = "noc", "tl", "axi_mst0", "apb"; 1274 resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>, 1275 <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>, 1276 <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>, 1277 <&stgcrg JH7110_STGRST_PCIE0_BRG>, 1278 <&stgcrg JH7110_STGRST_PCIE0_CORE>, 1279 <&stgcrg JH7110_STGRST_PCIE0_APB>; 1280 reset-names = "mst0", "slv0", "slv", "brg", 1281 "core", "apb"; 1282 status = "disabled"; 1283 1284 pcie_intc0: interrupt-controller { 1285 #address-cells = <0>; 1286 #interrupt-cells = <1>; 1287 interrupt-controller; 1288 }; 1289 }; 1290 1291 pcie1: pcie@9c0000000 { 1292 compatible = "starfive,jh7110-pcie"; 1293 reg = <0x9 0xc0000000 0x0 0x1000000>, 1294 <0x0 0x2c000000 0x0 0x100000>; 1295 reg-names = "cfg", "apb"; 1296 linux,pci-domain = <1>; 1297 #address-cells = <3>; 1298 #size-cells = <2>; 1299 #interrupt-cells = <1>; 1300 ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, 1301 <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; 1302 interrupts = <57>; 1303 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 1304 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>, 1305 <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>, 1306 <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>, 1307 <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>; 1308 msi-controller; 1309 device_type = "pci"; 1310 starfive,stg-syscon = <&stg_syscon>; 1311 bus-range = <0x0 0xff>; 1312 clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, 1313 <&stgcrg JH7110_STGCLK_PCIE1_TL>, 1314 <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>, 1315 <&stgcrg JH7110_STGCLK_PCIE1_APB>; 1316 clock-names = "noc", "tl", "axi_mst0", "apb"; 1317 resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>, 1318 <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>, 1319 <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>, 1320 <&stgcrg JH7110_STGRST_PCIE1_BRG>, 1321 <&stgcrg JH7110_STGRST_PCIE1_CORE>, 1322 <&stgcrg JH7110_STGRST_PCIE1_APB>; 1323 reset-names = "mst0", "slv0", "slv", "brg", 1324 "core", "apb"; 1325 status = "disabled"; 1326 1327 pcie_intc1: interrupt-controller { 1328 #address-cells = <0>; 1329 #interrupt-cells = <1>; 1330 interrupt-controller; 1331 }; 1332 }; 1333 }; 1334};
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