sg2044-reset.h

  1/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
  2/*
  3 * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
  4 */
  5
  6#ifndef _SG2044_RESET_H
  7#define _SG2044_RESET_H
  8
  9#define RST_AP_SYS			0
 10#define RST_AP_SYS_CORE0		1
 11#define RST_AP_SYS_CORE1		2
 12#define RST_AP_SYS_CORE2		3
 13#define RST_AP_SYS_CORE3		4
 14#define RST_AP_PIC			5
 15#define RST_AP_TDT			6
 16#define RST_RP_PIC_TDT			7
 17#define RST_HSDMA			8
 18#define RST_SYSDMA			9
 19#define RST_EFUSE0			10
 20#define RST_EFUSE1			11
 21#define RST_RTC				12
 22#define RST_TIMER			13
 23#define RST_WDT				14
 24#define RST_AHB_ROM0			15
 25#define RST_AHB_ROM1			16
 26#define RST_I2C0			17
 27#define RST_I2C1			18
 28#define RST_I2C2			19
 29#define RST_I2C3			20
 30#define RST_GPIO0			21
 31#define RST_GPIO1			22
 32#define RST_GPIO2			23
 33#define RST_PWM				24
 34#define RST_AXI_SRAM0			25
 35#define RST_AXI_SRAM1			26
 36#define RST_SPIFMC0			27
 37#define RST_SPIFMC1			28
 38#define RST_MAILBOX			29
 39#define RST_ETH0			30
 40#define RST_EMMC			31
 41#define RST_SD				32
 42#define RST_UART0			33
 43#define RST_UART1			34
 44#define RST_UART2			35
 45#define RST_UART3			36
 46#define RST_SPI0			37
 47#define RST_SPI1			38
 48#define RST_MTLI			39
 49#define RST_DBG_I2C			40
 50#define RST_C2C0			41
 51#define RST_C2C1			42
 52#define RST_C2C2			43
 53#define RST_C2C3			44
 54#define RST_CXP				45
 55#define RST_DDR0			46
 56#define RST_DDR1			47
 57#define RST_DDR2			48
 58#define RST_DDR3			49
 59#define RST_DDR4			50
 60#define RST_DDR5			51
 61#define RST_DDR6			52
 62#define RST_DDR7			53
 63#define RST_DDR8			54
 64#define RST_DDR9			55
 65#define RST_DDR10			56
 66#define RST_DDR11			57
 67#define RST_DDR12			58
 68#define RST_DDR13			59
 69#define RST_DDR14			60
 70#define RST_DDR15			61
 71#define RST_BAR				62
 72#define RST_K2K				63
 73#define RST_CC_SYS_X1Y1			64
 74#define RST_CC_SYS_X1Y2			65
 75#define RST_CC_SYS_X1Y3			66
 76#define RST_CC_SYS_X1Y4			67
 77#define RST_CC_SYS_X0Y1			68
 78#define RST_CC_SYS_X0Y2			69
 79#define RST_CC_SYS_X0Y3			70
 80#define RST_CC_SYS_X0Y4			71
 81#define RST_SC_X1Y1			80
 82#define RST_SC_X1Y2			81
 83#define RST_SC_X1Y3			82
 84#define RST_SC_X1Y4			83
 85#define RST_SC_X0Y1			84
 86#define RST_SC_X0Y2			85
 87#define RST_SC_X0Y3			86
 88#define RST_SC_X0Y4			87
 89#define RST_RP_CLUSTER_X1Y1_S0		160
 90#define RST_RP_CLUSTER_X1Y1_S1		161
 91#define RST_RP_CLUSTER_X1Y2_S0		162
 92#define RST_RP_CLUSTER_X1Y2_S1		163
 93#define RST_RP_CLUSTER_X1Y3_S0		164
 94#define RST_RP_CLUSTER_X1Y3_S1		165
 95#define RST_RP_CLUSTER_X1Y4_S0		166
 96#define RST_RP_CLUSTER_X1Y4_S1		167
 97#define RST_RP_CLUSTER_X0Y1_W0		168
 98#define RST_RP_CLUSTER_X0Y1_W1		169
 99#define RST_RP_CLUSTER_X0Y2_W0		170
100#define RST_RP_CLUSTER_X0Y2_W1		171
101#define RST_RP_CLUSTER_X0Y3_W0		172
102#define RST_RP_CLUSTER_X0Y3_W1		173
103#define RST_RP_CLUSTER_X0Y4_W0		174
104#define RST_RP_CLUSTER_X0Y4_W1		175
105#define RST_TPSYS_X1Y1			180
106#define RST_TPSYS_X1Y2			181
107#define RST_TPSYS_X1Y3			182
108#define RST_TPSYS_X1Y4			183
109#define RST_TPSYS_X0Y1			184
110#define RST_TPSYS_X0Y2			185
111#define RST_TPSYS_X0Y3			186
112#define RST_TPSYS_X0Y4			187
113#define RST_SPACC			188
114#define RST_PKA				189
115#define RST_SE_TRNG			190
116#define RST_SE_DBG			191
117#define RST_SE_FAB_FW			192
118#define RST_SE_CTRL			193
119#define RST_MAILBOX0			194
120#define RST_MAILBOX1			195
121#define RST_MAILBOX2			196
122#define RST_MAILBOX3			197
123#define RST_INTC0			198
124#define RST_INTC1			199
125#define RST_INTC2			200
126#define RST_INTC3			201
127
128#endif /* _DT_BINDINGS_SG2044_RESET_H */