sg2042-cpus.dtsi

   1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2/*
   3 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
   4 */
   5
   6/ {
   7	cpus {
   8		#address-cells = <1>;
   9		#size-cells = <0>;
  10		timebase-frequency = <50000000>;
  11
  12		cpu-map {
  13			socket0 {
  14				cluster0 {
  15					 core0 {
  16						cpu = <&cpu0>;
  17					 };
  18					 core1 {
  19						cpu = <&cpu1>;
  20					 };
  21					 core2 {
  22						cpu = <&cpu2>;
  23					 };
  24					 core3 {
  25						cpu = <&cpu3>;
  26					 };
  27				};
  28
  29				cluster1 {
  30					 core0 {
  31						cpu = <&cpu4>;
  32					 };
  33					 core1 {
  34						cpu = <&cpu5>;
  35					 };
  36					 core2 {
  37						cpu = <&cpu6>;
  38					 };
  39					 core3 {
  40						cpu = <&cpu7>;
  41					 };
  42				};
  43
  44				cluster2 {
  45					 core0 {
  46						cpu = <&cpu16>;
  47					 };
  48					 core1 {
  49						cpu = <&cpu17>;
  50					 };
  51					 core2 {
  52						cpu = <&cpu18>;
  53					 };
  54					 core3 {
  55						cpu = <&cpu19>;
  56					 };
  57				};
  58
  59				cluster3 {
  60					 core0 {
  61						cpu = <&cpu20>;
  62					 };
  63					 core1 {
  64						cpu = <&cpu21>;
  65					 };
  66					 core2 {
  67						cpu = <&cpu22>;
  68					 };
  69					 core3 {
  70						cpu = <&cpu23>;
  71					 };
  72				};
  73
  74				cluster4 {
  75					 core0 {
  76						cpu = <&cpu8>;
  77					 };
  78					 core1 {
  79						cpu = <&cpu9>;
  80					 };
  81					 core2 {
  82						cpu = <&cpu10>;
  83					 };
  84					 core3 {
  85						cpu = <&cpu11>;
  86					 };
  87				};
  88
  89				cluster5 {
  90					 core0 {
  91						cpu = <&cpu12>;
  92					 };
  93					 core1 {
  94						cpu = <&cpu13>;
  95					 };
  96					 core2 {
  97						cpu = <&cpu14>;
  98					 };
  99					 core3 {
 100						cpu = <&cpu15>;
 101					 };
 102				};
 103
 104				cluster6 {
 105					 core0 {
 106						cpu = <&cpu24>;
 107					 };
 108					 core1 {
 109						cpu = <&cpu25>;
 110					 };
 111					 core2 {
 112						cpu = <&cpu26>;
 113					 };
 114					 core3 {
 115						cpu = <&cpu27>;
 116					 };
 117				};
 118
 119				cluster7 {
 120					 core0 {
 121						cpu = <&cpu28>;
 122					 };
 123					 core1 {
 124						cpu = <&cpu29>;
 125					 };
 126					 core2 {
 127						cpu = <&cpu30>;
 128					 };
 129					 core3 {
 130						cpu = <&cpu31>;
 131					 };
 132				};
 133
 134				cluster8 {
 135					 core0 {
 136						cpu = <&cpu32>;
 137					 };
 138					 core1 {
 139						cpu = <&cpu33>;
 140					 };
 141					 core2 {
 142						cpu = <&cpu34>;
 143					 };
 144					 core3 {
 145						cpu = <&cpu35>;
 146					 };
 147				};
 148
 149				cluster9 {
 150					 core0 {
 151						cpu = <&cpu36>;
 152					 };
 153					 core1 {
 154						cpu = <&cpu37>;
 155					 };
 156					 core2 {
 157						cpu = <&cpu38>;
 158					 };
 159					 core3 {
 160						cpu = <&cpu39>;
 161					 };
 162				};
 163
 164				cluster10 {
 165					 core0 {
 166						cpu = <&cpu48>;
 167					 };
 168					 core1 {
 169						cpu = <&cpu49>;
 170					 };
 171					 core2 {
 172						cpu = <&cpu50>;
 173					 };
 174					 core3 {
 175						cpu = <&cpu51>;
 176					 };
 177				};
 178
 179				cluster11 {
 180					 core0 {
 181						cpu = <&cpu52>;
 182					 };
 183					 core1 {
 184						cpu = <&cpu53>;
 185					 };
 186					 core2 {
 187						cpu = <&cpu54>;
 188					 };
 189					 core3 {
 190						cpu = <&cpu55>;
 191					 };
 192				};
 193
 194				cluster12 {
 195					 core0 {
 196						cpu = <&cpu40>;
 197					 };
 198					 core1 {
 199						cpu = <&cpu41>;
 200					 };
 201					 core2 {
 202						cpu = <&cpu42>;
 203					 };
 204					 core3 {
 205						cpu = <&cpu43>;
 206					 };
 207				};
 208
 209				cluster13 {
 210					 core0 {
 211						cpu = <&cpu44>;
 212					 };
 213					 core1 {
 214						cpu = <&cpu45>;
 215					 };
 216					 core2 {
 217						cpu = <&cpu46>;
 218					 };
 219					 core3 {
 220						cpu = <&cpu47>;
 221					 };
 222				};
 223
 224				cluster14 {
 225					 core0 {
 226						cpu = <&cpu56>;
 227					 };
 228					 core1 {
 229						cpu = <&cpu57>;
 230					 };
 231					 core2 {
 232						cpu = <&cpu58>;
 233					 };
 234					 core3 {
 235						cpu = <&cpu59>;
 236					 };
 237				};
 238
 239				cluster15 {
 240					 core0 {
 241						cpu = <&cpu60>;
 242					 };
 243					 core1 {
 244						cpu = <&cpu61>;
 245					 };
 246					 core2 {
 247						cpu = <&cpu62>;
 248					 };
 249					 core3 {
 250						cpu = <&cpu63>;
 251					 };
 252				};
 253			};
 254		};
 255
 256		cpu0: cpu@0 {
 257			compatible = "thead,c920", "riscv";
 258			device_type = "cpu";
 259			riscv,isa = "rv64imafdc";
 260			riscv,isa-base = "rv64i";
 261			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 262					       "ziccrse", "zicntr", "zicsr",
 263					       "zifencei", "zihpm", "zfh",
 264					       "xtheadvector";
 265			thead,vlenb = <16>;
 266			reg = <0>;
 267			i-cache-block-size = <64>;
 268			i-cache-size = <65536>;
 269			i-cache-sets = <512>;
 270			d-cache-block-size = <64>;
 271			d-cache-size = <65536>;
 272			d-cache-sets = <512>;
 273			next-level-cache = <&l2_cache0>;
 274			mmu-type = "riscv,sv39";
 275			numa-node-id = <0>;
 276
 277			cpu0_intc: interrupt-controller {
 278				compatible = "riscv,cpu-intc";
 279				interrupt-controller;
 280				#interrupt-cells = <1>;
 281			};
 282		};
 283
 284		cpu1: cpu@1 {
 285			compatible = "thead,c920", "riscv";
 286			device_type = "cpu";
 287			riscv,isa = "rv64imafdc";
 288			riscv,isa-base = "rv64i";
 289			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 290					       "ziccrse", "zicntr", "zicsr",
 291					       "zifencei", "zihpm", "zfh",
 292					       "xtheadvector";
 293			thead,vlenb = <16>;
 294			reg = <1>;
 295			i-cache-block-size = <64>;
 296			i-cache-size = <65536>;
 297			i-cache-sets = <512>;
 298			d-cache-block-size = <64>;
 299			d-cache-size = <65536>;
 300			d-cache-sets = <512>;
 301			next-level-cache = <&l2_cache0>;
 302			mmu-type = "riscv,sv39";
 303			numa-node-id = <0>;
 304
 305			cpu1_intc: interrupt-controller {
 306				compatible = "riscv,cpu-intc";
 307				interrupt-controller;
 308				#interrupt-cells = <1>;
 309			};
 310		};
 311
 312		cpu2: cpu@2 {
 313			compatible = "thead,c920", "riscv";
 314			device_type = "cpu";
 315			riscv,isa = "rv64imafdc";
 316			riscv,isa-base = "rv64i";
 317			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 318					       "ziccrse", "zicntr", "zicsr",
 319					       "zifencei", "zihpm", "zfh",
 320					       "xtheadvector";
 321			thead,vlenb = <16>;
 322			reg = <2>;
 323			i-cache-block-size = <64>;
 324			i-cache-size = <65536>;
 325			i-cache-sets = <512>;
 326			d-cache-block-size = <64>;
 327			d-cache-size = <65536>;
 328			d-cache-sets = <512>;
 329			next-level-cache = <&l2_cache0>;
 330			mmu-type = "riscv,sv39";
 331			numa-node-id = <0>;
 332
 333			cpu2_intc: interrupt-controller {
 334				compatible = "riscv,cpu-intc";
 335				interrupt-controller;
 336				#interrupt-cells = <1>;
 337			};
 338		};
 339
 340		cpu3: cpu@3 {
 341			compatible = "thead,c920", "riscv";
 342			device_type = "cpu";
 343			riscv,isa = "rv64imafdc";
 344			riscv,isa-base = "rv64i";
 345			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 346					       "ziccrse", "zicntr", "zicsr",
 347					       "zifencei", "zihpm", "zfh",
 348					       "xtheadvector";
 349			thead,vlenb = <16>;
 350			reg = <3>;
 351			i-cache-block-size = <64>;
 352			i-cache-size = <65536>;
 353			i-cache-sets = <512>;
 354			d-cache-block-size = <64>;
 355			d-cache-size = <65536>;
 356			d-cache-sets = <512>;
 357			next-level-cache = <&l2_cache0>;
 358			mmu-type = "riscv,sv39";
 359			numa-node-id = <0>;
 360
 361			cpu3_intc: interrupt-controller {
 362				compatible = "riscv,cpu-intc";
 363				interrupt-controller;
 364				#interrupt-cells = <1>;
 365			};
 366		};
 367
 368		cpu4: cpu@4 {
 369			compatible = "thead,c920", "riscv";
 370			device_type = "cpu";
 371			riscv,isa = "rv64imafdc";
 372			riscv,isa-base = "rv64i";
 373			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 374					       "ziccrse", "zicntr", "zicsr",
 375					       "zifencei", "zihpm", "zfh",
 376					       "xtheadvector";
 377			thead,vlenb = <16>;
 378			reg = <4>;
 379			i-cache-block-size = <64>;
 380			i-cache-size = <65536>;
 381			i-cache-sets = <512>;
 382			d-cache-block-size = <64>;
 383			d-cache-size = <65536>;
 384			d-cache-sets = <512>;
 385			next-level-cache = <&l2_cache1>;
 386			mmu-type = "riscv,sv39";
 387			numa-node-id = <0>;
 388
 389			cpu4_intc: interrupt-controller {
 390				compatible = "riscv,cpu-intc";
 391				interrupt-controller;
 392				#interrupt-cells = <1>;
 393			};
 394		};
 395
 396		cpu5: cpu@5 {
 397			compatible = "thead,c920", "riscv";
 398			device_type = "cpu";
 399			riscv,isa = "rv64imafdc";
 400			riscv,isa-base = "rv64i";
 401			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 402					       "ziccrse", "zicntr", "zicsr",
 403					       "zifencei", "zihpm", "zfh",
 404					       "xtheadvector";
 405			thead,vlenb = <16>;
 406			reg = <5>;
 407			i-cache-block-size = <64>;
 408			i-cache-size = <65536>;
 409			i-cache-sets = <512>;
 410			d-cache-block-size = <64>;
 411			d-cache-size = <65536>;
 412			d-cache-sets = <512>;
 413			next-level-cache = <&l2_cache1>;
 414			mmu-type = "riscv,sv39";
 415			numa-node-id = <0>;
 416
 417			cpu5_intc: interrupt-controller {
 418				compatible = "riscv,cpu-intc";
 419				interrupt-controller;
 420				#interrupt-cells = <1>;
 421			};
 422		};
 423
 424		cpu6: cpu@6 {
 425			compatible = "thead,c920", "riscv";
 426			device_type = "cpu";
 427			riscv,isa = "rv64imafdc";
 428			riscv,isa-base = "rv64i";
 429			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 430					       "ziccrse", "zicntr", "zicsr",
 431					       "zifencei", "zihpm", "zfh",
 432					       "xtheadvector";
 433			thead,vlenb = <16>;
 434			reg = <6>;
 435			i-cache-block-size = <64>;
 436			i-cache-size = <65536>;
 437			i-cache-sets = <512>;
 438			d-cache-block-size = <64>;
 439			d-cache-size = <65536>;
 440			d-cache-sets = <512>;
 441			next-level-cache = <&l2_cache1>;
 442			mmu-type = "riscv,sv39";
 443			numa-node-id = <0>;
 444
 445			cpu6_intc: interrupt-controller {
 446				compatible = "riscv,cpu-intc";
 447				interrupt-controller;
 448				#interrupt-cells = <1>;
 449			};
 450		};
 451
 452		cpu7: cpu@7 {
 453			compatible = "thead,c920", "riscv";
 454			device_type = "cpu";
 455			riscv,isa = "rv64imafdc";
 456			riscv,isa-base = "rv64i";
 457			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 458					       "ziccrse", "zicntr", "zicsr",
 459					       "zifencei", "zihpm", "zfh",
 460					       "xtheadvector";
 461			thead,vlenb = <16>;
 462			reg = <7>;
 463			i-cache-block-size = <64>;
 464			i-cache-size = <65536>;
 465			i-cache-sets = <512>;
 466			d-cache-block-size = <64>;
 467			d-cache-size = <65536>;
 468			d-cache-sets = <512>;
 469			next-level-cache = <&l2_cache1>;
 470			mmu-type = "riscv,sv39";
 471			numa-node-id = <0>;
 472
 473			cpu7_intc: interrupt-controller {
 474				compatible = "riscv,cpu-intc";
 475				interrupt-controller;
 476				#interrupt-cells = <1>;
 477			};
 478		};
 479
 480		cpu8: cpu@8 {
 481			compatible = "thead,c920", "riscv";
 482			device_type = "cpu";
 483			riscv,isa = "rv64imafdc";
 484			riscv,isa-base = "rv64i";
 485			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 486					       "ziccrse", "zicntr", "zicsr",
 487					       "zifencei", "zihpm", "zfh",
 488					       "xtheadvector";
 489			thead,vlenb = <16>;
 490			reg = <8>;
 491			i-cache-block-size = <64>;
 492			i-cache-size = <65536>;
 493			i-cache-sets = <512>;
 494			d-cache-block-size = <64>;
 495			d-cache-size = <65536>;
 496			d-cache-sets = <512>;
 497			next-level-cache = <&l2_cache4>;
 498			mmu-type = "riscv,sv39";
 499			numa-node-id = <1>;
 500
 501			cpu8_intc: interrupt-controller {
 502				compatible = "riscv,cpu-intc";
 503				interrupt-controller;
 504				#interrupt-cells = <1>;
 505			};
 506		};
 507
 508		cpu9: cpu@9 {
 509			compatible = "thead,c920", "riscv";
 510			device_type = "cpu";
 511			riscv,isa = "rv64imafdc";
 512			riscv,isa-base = "rv64i";
 513			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 514					       "ziccrse", "zicntr", "zicsr",
 515					       "zifencei", "zihpm", "zfh",
 516					       "xtheadvector";
 517			thead,vlenb = <16>;
 518			reg = <9>;
 519			i-cache-block-size = <64>;
 520			i-cache-size = <65536>;
 521			i-cache-sets = <512>;
 522			d-cache-block-size = <64>;
 523			d-cache-size = <65536>;
 524			d-cache-sets = <512>;
 525			next-level-cache = <&l2_cache4>;
 526			mmu-type = "riscv,sv39";
 527			numa-node-id = <1>;
 528
 529			cpu9_intc: interrupt-controller {
 530				compatible = "riscv,cpu-intc";
 531				interrupt-controller;
 532				#interrupt-cells = <1>;
 533			};
 534		};
 535
 536		cpu10: cpu@10 {
 537			compatible = "thead,c920", "riscv";
 538			device_type = "cpu";
 539			riscv,isa = "rv64imafdc";
 540			riscv,isa-base = "rv64i";
 541			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 542					       "ziccrse", "zicntr", "zicsr",
 543					       "zifencei", "zihpm", "zfh",
 544					       "xtheadvector";
 545			thead,vlenb = <16>;
 546			reg = <10>;
 547			i-cache-block-size = <64>;
 548			i-cache-size = <65536>;
 549			i-cache-sets = <512>;
 550			d-cache-block-size = <64>;
 551			d-cache-size = <65536>;
 552			d-cache-sets = <512>;
 553			next-level-cache = <&l2_cache4>;
 554			mmu-type = "riscv,sv39";
 555			numa-node-id = <1>;
 556
 557			cpu10_intc: interrupt-controller {
 558				compatible = "riscv,cpu-intc";
 559				interrupt-controller;
 560				#interrupt-cells = <1>;
 561			};
 562		};
 563
 564		cpu11: cpu@11 {
 565			compatible = "thead,c920", "riscv";
 566			device_type = "cpu";
 567			riscv,isa = "rv64imafdc";
 568			riscv,isa-base = "rv64i";
 569			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 570					       "ziccrse", "zicntr", "zicsr",
 571					       "zifencei", "zihpm", "zfh",
 572					       "xtheadvector";
 573			thead,vlenb = <16>;
 574			reg = <11>;
 575			i-cache-block-size = <64>;
 576			i-cache-size = <65536>;
 577			i-cache-sets = <512>;
 578			d-cache-block-size = <64>;
 579			d-cache-size = <65536>;
 580			d-cache-sets = <512>;
 581			next-level-cache = <&l2_cache4>;
 582			mmu-type = "riscv,sv39";
 583			numa-node-id = <1>;
 584
 585			cpu11_intc: interrupt-controller {
 586				compatible = "riscv,cpu-intc";
 587				interrupt-controller;
 588				#interrupt-cells = <1>;
 589			};
 590		};
 591
 592		cpu12: cpu@12 {
 593			compatible = "thead,c920", "riscv";
 594			device_type = "cpu";
 595			riscv,isa = "rv64imafdc";
 596			riscv,isa-base = "rv64i";
 597			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 598					       "ziccrse", "zicntr", "zicsr",
 599					       "zifencei", "zihpm", "zfh",
 600					       "xtheadvector";
 601			thead,vlenb = <16>;
 602			reg = <12>;
 603			i-cache-block-size = <64>;
 604			i-cache-size = <65536>;
 605			i-cache-sets = <512>;
 606			d-cache-block-size = <64>;
 607			d-cache-size = <65536>;
 608			d-cache-sets = <512>;
 609			next-level-cache = <&l2_cache5>;
 610			mmu-type = "riscv,sv39";
 611			numa-node-id = <1>;
 612
 613			cpu12_intc: interrupt-controller {
 614				compatible = "riscv,cpu-intc";
 615				interrupt-controller;
 616				#interrupt-cells = <1>;
 617			};
 618		};
 619
 620		cpu13: cpu@13 {
 621			compatible = "thead,c920", "riscv";
 622			device_type = "cpu";
 623			riscv,isa = "rv64imafdc";
 624			riscv,isa-base = "rv64i";
 625			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 626					       "ziccrse", "zicntr", "zicsr",
 627					       "zifencei", "zihpm", "zfh",
 628					       "xtheadvector";
 629			thead,vlenb = <16>;
 630			reg = <13>;
 631			i-cache-block-size = <64>;
 632			i-cache-size = <65536>;
 633			i-cache-sets = <512>;
 634			d-cache-block-size = <64>;
 635			d-cache-size = <65536>;
 636			d-cache-sets = <512>;
 637			next-level-cache = <&l2_cache5>;
 638			mmu-type = "riscv,sv39";
 639			numa-node-id = <1>;
 640
 641			cpu13_intc: interrupt-controller {
 642				compatible = "riscv,cpu-intc";
 643				interrupt-controller;
 644				#interrupt-cells = <1>;
 645			};
 646		};
 647
 648		cpu14: cpu@14 {
 649			compatible = "thead,c920", "riscv";
 650			device_type = "cpu";
 651			riscv,isa = "rv64imafdc";
 652			riscv,isa-base = "rv64i";
 653			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 654					       "ziccrse", "zicntr", "zicsr",
 655					       "zifencei", "zihpm", "zfh",
 656					       "xtheadvector";
 657			thead,vlenb = <16>;
 658			reg = <14>;
 659			i-cache-block-size = <64>;
 660			i-cache-size = <65536>;
 661			i-cache-sets = <512>;
 662			d-cache-block-size = <64>;
 663			d-cache-size = <65536>;
 664			d-cache-sets = <512>;
 665			next-level-cache = <&l2_cache5>;
 666			mmu-type = "riscv,sv39";
 667			numa-node-id = <1>;
 668
 669			cpu14_intc: interrupt-controller {
 670				compatible = "riscv,cpu-intc";
 671				interrupt-controller;
 672				#interrupt-cells = <1>;
 673			};
 674		};
 675
 676		cpu15: cpu@15 {
 677			compatible = "thead,c920", "riscv";
 678			device_type = "cpu";
 679			riscv,isa = "rv64imafdc";
 680			riscv,isa-base = "rv64i";
 681			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 682					       "ziccrse", "zicntr", "zicsr",
 683					       "zifencei", "zihpm", "zfh",
 684					       "xtheadvector";
 685			thead,vlenb = <16>;
 686			reg = <15>;
 687			i-cache-block-size = <64>;
 688			i-cache-size = <65536>;
 689			i-cache-sets = <512>;
 690			d-cache-block-size = <64>;
 691			d-cache-size = <65536>;
 692			d-cache-sets = <512>;
 693			next-level-cache = <&l2_cache5>;
 694			mmu-type = "riscv,sv39";
 695			numa-node-id = <1>;
 696
 697			cpu15_intc: interrupt-controller {
 698				compatible = "riscv,cpu-intc";
 699				interrupt-controller;
 700				#interrupt-cells = <1>;
 701			};
 702		};
 703
 704		cpu16: cpu@16 {
 705			compatible = "thead,c920", "riscv";
 706			device_type = "cpu";
 707			riscv,isa = "rv64imafdc";
 708			riscv,isa-base = "rv64i";
 709			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 710					       "ziccrse", "zicntr", "zicsr",
 711					       "zifencei", "zihpm", "zfh",
 712					       "xtheadvector";
 713			thead,vlenb = <16>;
 714			reg = <16>;
 715			i-cache-block-size = <64>;
 716			i-cache-size = <65536>;
 717			i-cache-sets = <512>;
 718			d-cache-block-size = <64>;
 719			d-cache-size = <65536>;
 720			d-cache-sets = <512>;
 721			next-level-cache = <&l2_cache2>;
 722			mmu-type = "riscv,sv39";
 723			numa-node-id = <0>;
 724
 725			cpu16_intc: interrupt-controller {
 726				compatible = "riscv,cpu-intc";
 727				interrupt-controller;
 728				#interrupt-cells = <1>;
 729			};
 730		};
 731
 732		cpu17: cpu@17 {
 733			compatible = "thead,c920", "riscv";
 734			device_type = "cpu";
 735			riscv,isa = "rv64imafdc";
 736			riscv,isa-base = "rv64i";
 737			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 738					       "ziccrse", "zicntr", "zicsr",
 739					       "zifencei", "zihpm", "zfh",
 740					       "xtheadvector";
 741			thead,vlenb = <16>;
 742			reg = <17>;
 743			i-cache-block-size = <64>;
 744			i-cache-size = <65536>;
 745			i-cache-sets = <512>;
 746			d-cache-block-size = <64>;
 747			d-cache-size = <65536>;
 748			d-cache-sets = <512>;
 749			next-level-cache = <&l2_cache2>;
 750			mmu-type = "riscv,sv39";
 751			numa-node-id = <0>;
 752
 753			cpu17_intc: interrupt-controller {
 754				compatible = "riscv,cpu-intc";
 755				interrupt-controller;
 756				#interrupt-cells = <1>;
 757			};
 758		};
 759
 760		cpu18: cpu@18 {
 761			compatible = "thead,c920", "riscv";
 762			device_type = "cpu";
 763			riscv,isa = "rv64imafdc";
 764			riscv,isa-base = "rv64i";
 765			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 766					       "ziccrse", "zicntr", "zicsr",
 767					       "zifencei", "zihpm", "zfh",
 768					       "xtheadvector";
 769			thead,vlenb = <16>;
 770			reg = <18>;
 771			i-cache-block-size = <64>;
 772			i-cache-size = <65536>;
 773			i-cache-sets = <512>;
 774			d-cache-block-size = <64>;
 775			d-cache-size = <65536>;
 776			d-cache-sets = <512>;
 777			next-level-cache = <&l2_cache2>;
 778			mmu-type = "riscv,sv39";
 779			numa-node-id = <0>;
 780
 781			cpu18_intc: interrupt-controller {
 782				compatible = "riscv,cpu-intc";
 783				interrupt-controller;
 784				#interrupt-cells = <1>;
 785			};
 786		};
 787
 788		cpu19: cpu@19 {
 789			compatible = "thead,c920", "riscv";
 790			device_type = "cpu";
 791			riscv,isa = "rv64imafdc";
 792			riscv,isa-base = "rv64i";
 793			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 794					       "ziccrse", "zicntr", "zicsr",
 795					       "zifencei", "zihpm", "zfh",
 796					       "xtheadvector";
 797			thead,vlenb = <16>;
 798			reg = <19>;
 799			i-cache-block-size = <64>;
 800			i-cache-size = <65536>;
 801			i-cache-sets = <512>;
 802			d-cache-block-size = <64>;
 803			d-cache-size = <65536>;
 804			d-cache-sets = <512>;
 805			next-level-cache = <&l2_cache2>;
 806			mmu-type = "riscv,sv39";
 807			numa-node-id = <0>;
 808
 809			cpu19_intc: interrupt-controller {
 810				compatible = "riscv,cpu-intc";
 811				interrupt-controller;
 812				#interrupt-cells = <1>;
 813			};
 814		};
 815
 816		cpu20: cpu@20 {
 817			compatible = "thead,c920", "riscv";
 818			device_type = "cpu";
 819			riscv,isa = "rv64imafdc";
 820			riscv,isa-base = "rv64i";
 821			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 822					       "ziccrse", "zicntr", "zicsr",
 823					       "zifencei", "zihpm", "zfh",
 824					       "xtheadvector";
 825			thead,vlenb = <16>;
 826			reg = <20>;
 827			i-cache-block-size = <64>;
 828			i-cache-size = <65536>;
 829			i-cache-sets = <512>;
 830			d-cache-block-size = <64>;
 831			d-cache-size = <65536>;
 832			d-cache-sets = <512>;
 833			next-level-cache = <&l2_cache3>;
 834			mmu-type = "riscv,sv39";
 835			numa-node-id = <0>;
 836
 837			cpu20_intc: interrupt-controller {
 838				compatible = "riscv,cpu-intc";
 839				interrupt-controller;
 840				#interrupt-cells = <1>;
 841			};
 842		};
 843
 844		cpu21: cpu@21 {
 845			compatible = "thead,c920", "riscv";
 846			device_type = "cpu";
 847			riscv,isa = "rv64imafdc";
 848			riscv,isa-base = "rv64i";
 849			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 850					       "ziccrse", "zicntr", "zicsr",
 851					       "zifencei", "zihpm", "zfh",
 852					       "xtheadvector";
 853			thead,vlenb = <16>;
 854			reg = <21>;
 855			i-cache-block-size = <64>;
 856			i-cache-size = <65536>;
 857			i-cache-sets = <512>;
 858			d-cache-block-size = <64>;
 859			d-cache-size = <65536>;
 860			d-cache-sets = <512>;
 861			next-level-cache = <&l2_cache3>;
 862			mmu-type = "riscv,sv39";
 863			numa-node-id = <0>;
 864
 865			cpu21_intc: interrupt-controller {
 866				compatible = "riscv,cpu-intc";
 867				interrupt-controller;
 868				#interrupt-cells = <1>;
 869			};
 870		};
 871
 872		cpu22: cpu@22 {
 873			compatible = "thead,c920", "riscv";
 874			device_type = "cpu";
 875			riscv,isa = "rv64imafdc";
 876			riscv,isa-base = "rv64i";
 877			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 878					       "ziccrse", "zicntr", "zicsr",
 879					       "zifencei", "zihpm", "zfh",
 880					       "xtheadvector";
 881			thead,vlenb = <16>;
 882			reg = <22>;
 883			i-cache-block-size = <64>;
 884			i-cache-size = <65536>;
 885			i-cache-sets = <512>;
 886			d-cache-block-size = <64>;
 887			d-cache-size = <65536>;
 888			d-cache-sets = <512>;
 889			next-level-cache = <&l2_cache3>;
 890			mmu-type = "riscv,sv39";
 891			numa-node-id = <0>;
 892
 893			cpu22_intc: interrupt-controller {
 894				compatible = "riscv,cpu-intc";
 895				interrupt-controller;
 896				#interrupt-cells = <1>;
 897			};
 898		};
 899
 900		cpu23: cpu@23 {
 901			compatible = "thead,c920", "riscv";
 902			device_type = "cpu";
 903			riscv,isa = "rv64imafdc";
 904			riscv,isa-base = "rv64i";
 905			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 906					       "ziccrse", "zicntr", "zicsr",
 907					       "zifencei", "zihpm", "zfh",
 908					       "xtheadvector";
 909			thead,vlenb = <16>;
 910			reg = <23>;
 911			i-cache-block-size = <64>;
 912			i-cache-size = <65536>;
 913			i-cache-sets = <512>;
 914			d-cache-block-size = <64>;
 915			d-cache-size = <65536>;
 916			d-cache-sets = <512>;
 917			next-level-cache = <&l2_cache3>;
 918			mmu-type = "riscv,sv39";
 919			numa-node-id = <0>;
 920
 921			cpu23_intc: interrupt-controller {
 922				compatible = "riscv,cpu-intc";
 923				interrupt-controller;
 924				#interrupt-cells = <1>;
 925			};
 926		};
 927
 928		cpu24: cpu@24 {
 929			compatible = "thead,c920", "riscv";
 930			device_type = "cpu";
 931			riscv,isa = "rv64imafdc";
 932			riscv,isa-base = "rv64i";
 933			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 934					       "ziccrse", "zicntr", "zicsr",
 935					       "zifencei", "zihpm", "zfh",
 936					       "xtheadvector";
 937			thead,vlenb = <16>;
 938			reg = <24>;
 939			i-cache-block-size = <64>;
 940			i-cache-size = <65536>;
 941			i-cache-sets = <512>;
 942			d-cache-block-size = <64>;
 943			d-cache-size = <65536>;
 944			d-cache-sets = <512>;
 945			next-level-cache = <&l2_cache6>;
 946			mmu-type = "riscv,sv39";
 947			numa-node-id = <1>;
 948
 949			cpu24_intc: interrupt-controller {
 950				compatible = "riscv,cpu-intc";
 951				interrupt-controller;
 952				#interrupt-cells = <1>;
 953			};
 954		};
 955
 956		cpu25: cpu@25 {
 957			compatible = "thead,c920", "riscv";
 958			device_type = "cpu";
 959			riscv,isa = "rv64imafdc";
 960			riscv,isa-base = "rv64i";
 961			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 962					       "ziccrse", "zicntr", "zicsr",
 963					       "zifencei", "zihpm", "zfh",
 964					       "xtheadvector";
 965			thead,vlenb = <16>;
 966			reg = <25>;
 967			i-cache-block-size = <64>;
 968			i-cache-size = <65536>;
 969			i-cache-sets = <512>;
 970			d-cache-block-size = <64>;
 971			d-cache-size = <65536>;
 972			d-cache-sets = <512>;
 973			next-level-cache = <&l2_cache6>;
 974			mmu-type = "riscv,sv39";
 975			numa-node-id = <1>;
 976
 977			cpu25_intc: interrupt-controller {
 978				compatible = "riscv,cpu-intc";
 979				interrupt-controller;
 980				#interrupt-cells = <1>;
 981			};
 982		};
 983
 984		cpu26: cpu@26 {
 985			compatible = "thead,c920", "riscv";
 986			device_type = "cpu";
 987			riscv,isa = "rv64imafdc";
 988			riscv,isa-base = "rv64i";
 989			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 990					       "ziccrse", "zicntr", "zicsr",
 991					       "zifencei", "zihpm", "zfh",
 992					       "xtheadvector";
 993			thead,vlenb = <16>;
 994			reg = <26>;
 995			i-cache-block-size = <64>;
 996			i-cache-size = <65536>;
 997			i-cache-sets = <512>;
 998			d-cache-block-size = <64>;
 999			d-cache-size = <65536>;
1000			d-cache-sets = <512>;
1001			next-level-cache = <&l2_cache6>;
1002			mmu-type = "riscv,sv39";
1003			numa-node-id = <1>;
1004
1005			cpu26_intc: interrupt-controller {
1006				compatible = "riscv,cpu-intc";
1007				interrupt-controller;
1008				#interrupt-cells = <1>;
1009			};
1010		};
1011
1012		cpu27: cpu@27 {
1013			compatible = "thead,c920", "riscv";
1014			device_type = "cpu";
1015			riscv,isa = "rv64imafdc";
1016			riscv,isa-base = "rv64i";
1017			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1018					       "ziccrse", "zicntr", "zicsr",
1019					       "zifencei", "zihpm", "zfh",
1020					       "xtheadvector";
1021			thead,vlenb = <16>;
1022			reg = <27>;
1023			i-cache-block-size = <64>;
1024			i-cache-size = <65536>;
1025			i-cache-sets = <512>;
1026			d-cache-block-size = <64>;
1027			d-cache-size = <65536>;
1028			d-cache-sets = <512>;
1029			next-level-cache = <&l2_cache6>;
1030			mmu-type = "riscv,sv39";
1031			numa-node-id = <1>;
1032
1033			cpu27_intc: interrupt-controller {
1034				compatible = "riscv,cpu-intc";
1035				interrupt-controller;
1036				#interrupt-cells = <1>;
1037			};
1038		};
1039
1040		cpu28: cpu@28 {
1041			compatible = "thead,c920", "riscv";
1042			device_type = "cpu";
1043			riscv,isa = "rv64imafdc";
1044			riscv,isa-base = "rv64i";
1045			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1046					       "ziccrse", "zicntr", "zicsr",
1047					       "zifencei", "zihpm", "zfh",
1048					       "xtheadvector";
1049			thead,vlenb = <16>;
1050			reg = <28>;
1051			i-cache-block-size = <64>;
1052			i-cache-size = <65536>;
1053			i-cache-sets = <512>;
1054			d-cache-block-size = <64>;
1055			d-cache-size = <65536>;
1056			d-cache-sets = <512>;
1057			next-level-cache = <&l2_cache7>;
1058			mmu-type = "riscv,sv39";
1059			numa-node-id = <1>;
1060
1061			cpu28_intc: interrupt-controller {
1062				compatible = "riscv,cpu-intc";
1063				interrupt-controller;
1064				#interrupt-cells = <1>;
1065			};
1066		};
1067
1068		cpu29: cpu@29 {
1069			compatible = "thead,c920", "riscv";
1070			device_type = "cpu";
1071			riscv,isa = "rv64imafdc";
1072			riscv,isa-base = "rv64i";
1073			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1074					       "ziccrse", "zicntr", "zicsr",
1075					       "zifencei", "zihpm", "zfh",
1076					       "xtheadvector";
1077			thead,vlenb = <16>;
1078			reg = <29>;
1079			i-cache-block-size = <64>;
1080			i-cache-size = <65536>;
1081			i-cache-sets = <512>;
1082			d-cache-block-size = <64>;
1083			d-cache-size = <65536>;
1084			d-cache-sets = <512>;
1085			next-level-cache = <&l2_cache7>;
1086			mmu-type = "riscv,sv39";
1087			numa-node-id = <1>;
1088
1089			cpu29_intc: interrupt-controller {
1090				compatible = "riscv,cpu-intc";
1091				interrupt-controller;
1092				#interrupt-cells = <1>;
1093			};
1094		};
1095
1096		cpu30: cpu@30 {
1097			compatible = "thead,c920", "riscv";
1098			device_type = "cpu";
1099			riscv,isa = "rv64imafdc";
1100			riscv,isa-base = "rv64i";
1101			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1102					       "ziccrse", "zicntr", "zicsr",
1103					       "zifencei", "zihpm", "zfh",
1104					       "xtheadvector";
1105			thead,vlenb = <16>;
1106			reg = <30>;
1107			i-cache-block-size = <64>;
1108			i-cache-size = <65536>;
1109			i-cache-sets = <512>;
1110			d-cache-block-size = <64>;
1111			d-cache-size = <65536>;
1112			d-cache-sets = <512>;
1113			next-level-cache = <&l2_cache7>;
1114			mmu-type = "riscv,sv39";
1115			numa-node-id = <1>;
1116
1117			cpu30_intc: interrupt-controller {
1118				compatible = "riscv,cpu-intc";
1119				interrupt-controller;
1120				#interrupt-cells = <1>;
1121			};
1122		};
1123
1124		cpu31: cpu@31 {
1125			compatible = "thead,c920", "riscv";
1126			device_type = "cpu";
1127			riscv,isa = "rv64imafdc";
1128			riscv,isa-base = "rv64i";
1129			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1130					       "ziccrse", "zicntr", "zicsr",
1131					       "zifencei", "zihpm", "zfh",
1132					       "xtheadvector";
1133			thead,vlenb = <16>;
1134			reg = <31>;
1135			i-cache-block-size = <64>;
1136			i-cache-size = <65536>;
1137			i-cache-sets = <512>;
1138			d-cache-block-size = <64>;
1139			d-cache-size = <65536>;
1140			d-cache-sets = <512>;
1141			next-level-cache = <&l2_cache7>;
1142			mmu-type = "riscv,sv39";
1143			numa-node-id = <1>;
1144
1145			cpu31_intc: interrupt-controller {
1146				compatible = "riscv,cpu-intc";
1147				interrupt-controller;
1148				#interrupt-cells = <1>;
1149			};
1150		};
1151
1152		cpu32: cpu@32 {
1153			compatible = "thead,c920", "riscv";
1154			device_type = "cpu";
1155			riscv,isa = "rv64imafdc";
1156			riscv,isa-base = "rv64i";
1157			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1158					       "ziccrse", "zicntr", "zicsr",
1159					       "zifencei", "zihpm", "zfh",
1160					       "xtheadvector";
1161			thead,vlenb = <16>;
1162			reg = <32>;
1163			i-cache-block-size = <64>;
1164			i-cache-size = <65536>;
1165			i-cache-sets = <512>;
1166			d-cache-block-size = <64>;
1167			d-cache-size = <65536>;
1168			d-cache-sets = <512>;
1169			next-level-cache = <&l2_cache8>;
1170			mmu-type = "riscv,sv39";
1171			numa-node-id = <2>;
1172
1173			cpu32_intc: interrupt-controller {
1174				compatible = "riscv,cpu-intc";
1175				interrupt-controller;
1176				#interrupt-cells = <1>;
1177			};
1178		};
1179
1180		cpu33: cpu@33 {
1181			compatible = "thead,c920", "riscv";
1182			device_type = "cpu";
1183			riscv,isa = "rv64imafdc";
1184			riscv,isa-base = "rv64i";
1185			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1186					       "ziccrse", "zicntr", "zicsr",
1187					       "zifencei", "zihpm", "zfh",
1188					       "xtheadvector";
1189			thead,vlenb = <16>;
1190			reg = <33>;
1191			i-cache-block-size = <64>;
1192			i-cache-size = <65536>;
1193			i-cache-sets = <512>;
1194			d-cache-block-size = <64>;
1195			d-cache-size = <65536>;
1196			d-cache-sets = <512>;
1197			next-level-cache = <&l2_cache8>;
1198			mmu-type = "riscv,sv39";
1199			numa-node-id = <2>;
1200
1201			cpu33_intc: interrupt-controller {
1202				compatible = "riscv,cpu-intc";
1203				interrupt-controller;
1204				#interrupt-cells = <1>;
1205			};
1206		};
1207
1208		cpu34: cpu@34 {
1209			compatible = "thead,c920", "riscv";
1210			device_type = "cpu";
1211			riscv,isa = "rv64imafdc";
1212			riscv,isa-base = "rv64i";
1213			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1214					       "ziccrse", "zicntr", "zicsr",
1215					       "zifencei", "zihpm", "zfh",
1216					       "xtheadvector";
1217			thead,vlenb = <16>;
1218			reg = <34>;
1219			i-cache-block-size = <64>;
1220			i-cache-size = <65536>;
1221			i-cache-sets = <512>;
1222			d-cache-block-size = <64>;
1223			d-cache-size = <65536>;
1224			d-cache-sets = <512>;
1225			next-level-cache = <&l2_cache8>;
1226			mmu-type = "riscv,sv39";
1227			numa-node-id = <2>;
1228
1229			cpu34_intc: interrupt-controller {
1230				compatible = "riscv,cpu-intc";
1231				interrupt-controller;
1232				#interrupt-cells = <1>;
1233			};
1234		};
1235
1236		cpu35: cpu@35 {
1237			compatible = "thead,c920", "riscv";
1238			device_type = "cpu";
1239			riscv,isa = "rv64imafdc";
1240			riscv,isa-base = "rv64i";
1241			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1242					       "ziccrse", "zicntr", "zicsr",
1243					       "zifencei", "zihpm", "zfh",
1244					       "xtheadvector";
1245			thead,vlenb = <16>;
1246			reg = <35>;
1247			i-cache-block-size = <64>;
1248			i-cache-size = <65536>;
1249			i-cache-sets = <512>;
1250			d-cache-block-size = <64>;
1251			d-cache-size = <65536>;
1252			d-cache-sets = <512>;
1253			next-level-cache = <&l2_cache8>;
1254			mmu-type = "riscv,sv39";
1255			numa-node-id = <2>;
1256
1257			cpu35_intc: interrupt-controller {
1258				compatible = "riscv,cpu-intc";
1259				interrupt-controller;
1260				#interrupt-cells = <1>;
1261			};
1262		};
1263
1264		cpu36: cpu@36 {
1265			compatible = "thead,c920", "riscv";
1266			device_type = "cpu";
1267			riscv,isa = "rv64imafdc";
1268			riscv,isa-base = "rv64i";
1269			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1270					       "ziccrse", "zicntr", "zicsr",
1271					       "zifencei", "zihpm", "zfh",
1272					       "xtheadvector";
1273			thead,vlenb = <16>;
1274			reg = <36>;
1275			i-cache-block-size = <64>;
1276			i-cache-size = <65536>;
1277			i-cache-sets = <512>;
1278			d-cache-block-size = <64>;
1279			d-cache-size = <65536>;
1280			d-cache-sets = <512>;
1281			next-level-cache = <&l2_cache9>;
1282			mmu-type = "riscv,sv39";
1283			numa-node-id = <2>;
1284
1285			cpu36_intc: interrupt-controller {
1286				compatible = "riscv,cpu-intc";
1287				interrupt-controller;
1288				#interrupt-cells = <1>;
1289			};
1290		};
1291
1292		cpu37: cpu@37 {
1293			compatible = "thead,c920", "riscv";
1294			device_type = "cpu";
1295			riscv,isa = "rv64imafdc";
1296			riscv,isa-base = "rv64i";
1297			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1298					       "ziccrse", "zicntr", "zicsr",
1299					       "zifencei", "zihpm", "zfh",
1300					       "xtheadvector";
1301			thead,vlenb = <16>;
1302			reg = <37>;
1303			i-cache-block-size = <64>;
1304			i-cache-size = <65536>;
1305			i-cache-sets = <512>;
1306			d-cache-block-size = <64>;
1307			d-cache-size = <65536>;
1308			d-cache-sets = <512>;
1309			next-level-cache = <&l2_cache9>;
1310			mmu-type = "riscv,sv39";
1311			numa-node-id = <2>;
1312
1313			cpu37_intc: interrupt-controller {
1314				compatible = "riscv,cpu-intc";
1315				interrupt-controller;
1316				#interrupt-cells = <1>;
1317			};
1318		};
1319
1320		cpu38: cpu@38 {
1321			compatible = "thead,c920", "riscv";
1322			device_type = "cpu";
1323			riscv,isa = "rv64imafdc";
1324			riscv,isa-base = "rv64i";
1325			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1326					       "ziccrse", "zicntr", "zicsr",
1327					       "zifencei", "zihpm", "zfh",
1328					       "xtheadvector";
1329			thead,vlenb = <16>;
1330			reg = <38>;
1331			i-cache-block-size = <64>;
1332			i-cache-size = <65536>;
1333			i-cache-sets = <512>;
1334			d-cache-block-size = <64>;
1335			d-cache-size = <65536>;
1336			d-cache-sets = <512>;
1337			next-level-cache = <&l2_cache9>;
1338			mmu-type = "riscv,sv39";
1339			numa-node-id = <2>;
1340
1341			cpu38_intc: interrupt-controller {
1342				compatible = "riscv,cpu-intc";
1343				interrupt-controller;
1344				#interrupt-cells = <1>;
1345			};
1346		};
1347
1348		cpu39: cpu@39 {
1349			compatible = "thead,c920", "riscv";
1350			device_type = "cpu";
1351			riscv,isa = "rv64imafdc";
1352			riscv,isa-base = "rv64i";
1353			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1354					       "ziccrse", "zicntr", "zicsr",
1355					       "zifencei", "zihpm", "zfh",
1356					       "xtheadvector";
1357			thead,vlenb = <16>;
1358			reg = <39>;
1359			i-cache-block-size = <64>;
1360			i-cache-size = <65536>;
1361			i-cache-sets = <512>;
1362			d-cache-block-size = <64>;
1363			d-cache-size = <65536>;
1364			d-cache-sets = <512>;
1365			next-level-cache = <&l2_cache9>;
1366			mmu-type = "riscv,sv39";
1367			numa-node-id = <2>;
1368
1369			cpu39_intc: interrupt-controller {
1370				compatible = "riscv,cpu-intc";
1371				interrupt-controller;
1372				#interrupt-cells = <1>;
1373			};
1374		};
1375
1376		cpu40: cpu@40 {
1377			compatible = "thead,c920", "riscv";
1378			device_type = "cpu";
1379			riscv,isa = "rv64imafdc";
1380			riscv,isa-base = "rv64i";
1381			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1382					       "ziccrse", "zicntr", "zicsr",
1383					       "zifencei", "zihpm", "zfh",
1384					       "xtheadvector";
1385			thead,vlenb = <16>;
1386			reg = <40>;
1387			i-cache-block-size = <64>;
1388			i-cache-size = <65536>;
1389			i-cache-sets = <512>;
1390			d-cache-block-size = <64>;
1391			d-cache-size = <65536>;
1392			d-cache-sets = <512>;
1393			next-level-cache = <&l2_cache12>;
1394			mmu-type = "riscv,sv39";
1395			numa-node-id = <3>;
1396
1397			cpu40_intc: interrupt-controller {
1398				compatible = "riscv,cpu-intc";
1399				interrupt-controller;
1400				#interrupt-cells = <1>;
1401			};
1402		};
1403
1404		cpu41: cpu@41 {
1405			compatible = "thead,c920", "riscv";
1406			device_type = "cpu";
1407			riscv,isa = "rv64imafdc";
1408			riscv,isa-base = "rv64i";
1409			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1410					       "ziccrse", "zicntr", "zicsr",
1411					       "zifencei", "zihpm", "zfh",
1412					       "xtheadvector";
1413			thead,vlenb = <16>;
1414			reg = <41>;
1415			i-cache-block-size = <64>;
1416			i-cache-size = <65536>;
1417			i-cache-sets = <512>;
1418			d-cache-block-size = <64>;
1419			d-cache-size = <65536>;
1420			d-cache-sets = <512>;
1421			next-level-cache = <&l2_cache12>;
1422			mmu-type = "riscv,sv39";
1423			numa-node-id = <3>;
1424
1425			cpu41_intc: interrupt-controller {
1426				compatible = "riscv,cpu-intc";
1427				interrupt-controller;
1428				#interrupt-cells = <1>;
1429			};
1430		};
1431
1432		cpu42: cpu@42 {
1433			compatible = "thead,c920", "riscv";
1434			device_type = "cpu";
1435			riscv,isa = "rv64imafdc";
1436			riscv,isa-base = "rv64i";
1437			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1438					       "ziccrse", "zicntr", "zicsr",
1439					       "zifencei", "zihpm", "zfh",
1440					       "xtheadvector";
1441			thead,vlenb = <16>;
1442			reg = <42>;
1443			i-cache-block-size = <64>;
1444			i-cache-size = <65536>;
1445			i-cache-sets = <512>;
1446			d-cache-block-size = <64>;
1447			d-cache-size = <65536>;
1448			d-cache-sets = <512>;
1449			next-level-cache = <&l2_cache12>;
1450			mmu-type = "riscv,sv39";
1451			numa-node-id = <3>;
1452
1453			cpu42_intc: interrupt-controller {
1454				compatible = "riscv,cpu-intc";
1455				interrupt-controller;
1456				#interrupt-cells = <1>;
1457			};
1458		};
1459
1460		cpu43: cpu@43 {
1461			compatible = "thead,c920", "riscv";
1462			device_type = "cpu";
1463			riscv,isa = "rv64imafdc";
1464			riscv,isa-base = "rv64i";
1465			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1466					       "ziccrse", "zicntr", "zicsr",
1467					       "zifencei", "zihpm", "zfh",
1468					       "xtheadvector";
1469			thead,vlenb = <16>;
1470			reg = <43>;
1471			i-cache-block-size = <64>;
1472			i-cache-size = <65536>;
1473			i-cache-sets = <512>;
1474			d-cache-block-size = <64>;
1475			d-cache-size = <65536>;
1476			d-cache-sets = <512>;
1477			next-level-cache = <&l2_cache12>;
1478			mmu-type = "riscv,sv39";
1479			numa-node-id = <3>;
1480
1481			cpu43_intc: interrupt-controller {
1482				compatible = "riscv,cpu-intc";
1483				interrupt-controller;
1484				#interrupt-cells = <1>;
1485			};
1486		};
1487
1488		cpu44: cpu@44 {
1489			compatible = "thead,c920", "riscv";
1490			device_type = "cpu";
1491			riscv,isa = "rv64imafdc";
1492			riscv,isa-base = "rv64i";
1493			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1494					       "ziccrse", "zicntr", "zicsr",
1495					       "zifencei", "zihpm", "zfh",
1496					       "xtheadvector";
1497			thead,vlenb = <16>;
1498			reg = <44>;
1499			i-cache-block-size = <64>;
1500			i-cache-size = <65536>;
1501			i-cache-sets = <512>;
1502			d-cache-block-size = <64>;
1503			d-cache-size = <65536>;
1504			d-cache-sets = <512>;
1505			next-level-cache = <&l2_cache13>;
1506			mmu-type = "riscv,sv39";
1507			numa-node-id = <3>;
1508
1509			cpu44_intc: interrupt-controller {
1510				compatible = "riscv,cpu-intc";
1511				interrupt-controller;
1512				#interrupt-cells = <1>;
1513			};
1514		};
1515
1516		cpu45: cpu@45 {
1517			compatible = "thead,c920", "riscv";
1518			device_type = "cpu";
1519			riscv,isa = "rv64imafdc";
1520			riscv,isa-base = "rv64i";
1521			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1522					       "ziccrse", "zicntr", "zicsr",
1523					       "zifencei", "zihpm", "zfh",
1524					       "xtheadvector";
1525			thead,vlenb = <16>;
1526			reg = <45>;
1527			i-cache-block-size = <64>;
1528			i-cache-size = <65536>;
1529			i-cache-sets = <512>;
1530			d-cache-block-size = <64>;
1531			d-cache-size = <65536>;
1532			d-cache-sets = <512>;
1533			next-level-cache = <&l2_cache13>;
1534			mmu-type = "riscv,sv39";
1535			numa-node-id = <3>;
1536
1537			cpu45_intc: interrupt-controller {
1538				compatible = "riscv,cpu-intc";
1539				interrupt-controller;
1540				#interrupt-cells = <1>;
1541			};
1542		};
1543
1544		cpu46: cpu@46 {
1545			compatible = "thead,c920", "riscv";
1546			device_type = "cpu";
1547			riscv,isa = "rv64imafdc";
1548			riscv,isa-base = "rv64i";
1549			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1550					       "ziccrse", "zicntr", "zicsr",
1551					       "zifencei", "zihpm", "zfh",
1552					       "xtheadvector";
1553			thead,vlenb = <16>;
1554			reg = <46>;
1555			i-cache-block-size = <64>;
1556			i-cache-size = <65536>;
1557			i-cache-sets = <512>;
1558			d-cache-block-size = <64>;
1559			d-cache-size = <65536>;
1560			d-cache-sets = <512>;
1561			next-level-cache = <&l2_cache13>;
1562			mmu-type = "riscv,sv39";
1563			numa-node-id = <3>;
1564
1565			cpu46_intc: interrupt-controller {
1566				compatible = "riscv,cpu-intc";
1567				interrupt-controller;
1568				#interrupt-cells = <1>;
1569			};
1570		};
1571
1572		cpu47: cpu@47 {
1573			compatible = "thead,c920", "riscv";
1574			device_type = "cpu";
1575			riscv,isa = "rv64imafdc";
1576			riscv,isa-base = "rv64i";
1577			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1578					       "ziccrse", "zicntr", "zicsr",
1579					       "zifencei", "zihpm", "zfh",
1580					       "xtheadvector";
1581			thead,vlenb = <16>;
1582			reg = <47>;
1583			i-cache-block-size = <64>;
1584			i-cache-size = <65536>;
1585			i-cache-sets = <512>;
1586			d-cache-block-size = <64>;
1587			d-cache-size = <65536>;
1588			d-cache-sets = <512>;
1589			next-level-cache = <&l2_cache13>;
1590			mmu-type = "riscv,sv39";
1591			numa-node-id = <3>;
1592
1593			cpu47_intc: interrupt-controller {
1594				compatible = "riscv,cpu-intc";
1595				interrupt-controller;
1596				#interrupt-cells = <1>;
1597			};
1598		};
1599
1600		cpu48: cpu@48 {
1601			compatible = "thead,c920", "riscv";
1602			device_type = "cpu";
1603			riscv,isa = "rv64imafdc";
1604			riscv,isa-base = "rv64i";
1605			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1606					       "ziccrse", "zicntr", "zicsr",
1607					       "zifencei", "zihpm", "zfh",
1608					       "xtheadvector";
1609			thead,vlenb = <16>;
1610			reg = <48>;
1611			i-cache-block-size = <64>;
1612			i-cache-size = <65536>;
1613			i-cache-sets = <512>;
1614			d-cache-block-size = <64>;
1615			d-cache-size = <65536>;
1616			d-cache-sets = <512>;
1617			next-level-cache = <&l2_cache10>;
1618			mmu-type = "riscv,sv39";
1619			numa-node-id = <2>;
1620
1621			cpu48_intc: interrupt-controller {
1622				compatible = "riscv,cpu-intc";
1623				interrupt-controller;
1624				#interrupt-cells = <1>;
1625			};
1626		};
1627
1628		cpu49: cpu@49 {
1629			compatible = "thead,c920", "riscv";
1630			device_type = "cpu";
1631			riscv,isa = "rv64imafdc";
1632			riscv,isa-base = "rv64i";
1633			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1634					       "ziccrse", "zicntr", "zicsr",
1635					       "zifencei", "zihpm", "zfh",
1636					       "xtheadvector";
1637			thead,vlenb = <16>;
1638			reg = <49>;
1639			i-cache-block-size = <64>;
1640			i-cache-size = <65536>;
1641			i-cache-sets = <512>;
1642			d-cache-block-size = <64>;
1643			d-cache-size = <65536>;
1644			d-cache-sets = <512>;
1645			next-level-cache = <&l2_cache10>;
1646			mmu-type = "riscv,sv39";
1647			numa-node-id = <2>;
1648
1649			cpu49_intc: interrupt-controller {
1650				compatible = "riscv,cpu-intc";
1651				interrupt-controller;
1652				#interrupt-cells = <1>;
1653			};
1654		};
1655
1656		cpu50: cpu@50 {
1657			compatible = "thead,c920", "riscv";
1658			device_type = "cpu";
1659			riscv,isa = "rv64imafdc";
1660			riscv,isa-base = "rv64i";
1661			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1662					       "ziccrse", "zicntr", "zicsr",
1663					       "zifencei", "zihpm", "zfh",
1664					       "xtheadvector";
1665			thead,vlenb = <16>;
1666			reg = <50>;
1667			i-cache-block-size = <64>;
1668			i-cache-size = <65536>;
1669			i-cache-sets = <512>;
1670			d-cache-block-size = <64>;
1671			d-cache-size = <65536>;
1672			d-cache-sets = <512>;
1673			next-level-cache = <&l2_cache10>;
1674			mmu-type = "riscv,sv39";
1675			numa-node-id = <2>;
1676
1677			cpu50_intc: interrupt-controller {
1678				compatible = "riscv,cpu-intc";
1679				interrupt-controller;
1680				#interrupt-cells = <1>;
1681			};
1682		};
1683
1684		cpu51: cpu@51 {
1685			compatible = "thead,c920", "riscv";
1686			device_type = "cpu";
1687			riscv,isa = "rv64imafdc";
1688			riscv,isa-base = "rv64i";
1689			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1690					       "ziccrse", "zicntr", "zicsr",
1691					       "zifencei", "zihpm", "zfh",
1692					       "xtheadvector";
1693			thead,vlenb = <16>;
1694			reg = <51>;
1695			i-cache-block-size = <64>;
1696			i-cache-size = <65536>;
1697			i-cache-sets = <512>;
1698			d-cache-block-size = <64>;
1699			d-cache-size = <65536>;
1700			d-cache-sets = <512>;
1701			next-level-cache = <&l2_cache10>;
1702			mmu-type = "riscv,sv39";
1703			numa-node-id = <2>;
1704
1705			cpu51_intc: interrupt-controller {
1706				compatible = "riscv,cpu-intc";
1707				interrupt-controller;
1708				#interrupt-cells = <1>;
1709			};
1710		};
1711
1712		cpu52: cpu@52 {
1713			compatible = "thead,c920", "riscv";
1714			device_type = "cpu";
1715			riscv,isa = "rv64imafdc";
1716			riscv,isa-base = "rv64i";
1717			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1718					       "ziccrse", "zicntr", "zicsr",
1719					       "zifencei", "zihpm", "zfh",
1720					       "xtheadvector";
1721			thead,vlenb = <16>;
1722			reg = <52>;
1723			i-cache-block-size = <64>;
1724			i-cache-size = <65536>;
1725			i-cache-sets = <512>;
1726			d-cache-block-size = <64>;
1727			d-cache-size = <65536>;
1728			d-cache-sets = <512>;
1729			next-level-cache = <&l2_cache11>;
1730			mmu-type = "riscv,sv39";
1731			numa-node-id = <2>;
1732
1733			cpu52_intc: interrupt-controller {
1734				compatible = "riscv,cpu-intc";
1735				interrupt-controller;
1736				#interrupt-cells = <1>;
1737			};
1738		};
1739
1740		cpu53: cpu@53 {
1741			compatible = "thead,c920", "riscv";
1742			device_type = "cpu";
1743			riscv,isa = "rv64imafdc";
1744			riscv,isa-base = "rv64i";
1745			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1746					       "ziccrse", "zicntr", "zicsr",
1747					       "zifencei", "zihpm", "zfh",
1748					       "xtheadvector";
1749			thead,vlenb = <16>;
1750			reg = <53>;
1751			i-cache-block-size = <64>;
1752			i-cache-size = <65536>;
1753			i-cache-sets = <512>;
1754			d-cache-block-size = <64>;
1755			d-cache-size = <65536>;
1756			d-cache-sets = <512>;
1757			next-level-cache = <&l2_cache11>;
1758			mmu-type = "riscv,sv39";
1759			numa-node-id = <2>;
1760
1761			cpu53_intc: interrupt-controller {
1762				compatible = "riscv,cpu-intc";
1763				interrupt-controller;
1764				#interrupt-cells = <1>;
1765			};
1766		};
1767
1768		cpu54: cpu@54 {
1769			compatible = "thead,c920", "riscv";
1770			device_type = "cpu";
1771			riscv,isa = "rv64imafdc";
1772			riscv,isa-base = "rv64i";
1773			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1774					       "ziccrse", "zicntr", "zicsr",
1775					       "zifencei", "zihpm", "zfh",
1776					       "xtheadvector";
1777			thead,vlenb = <16>;
1778			reg = <54>;
1779			i-cache-block-size = <64>;
1780			i-cache-size = <65536>;
1781			i-cache-sets = <512>;
1782			d-cache-block-size = <64>;
1783			d-cache-size = <65536>;
1784			d-cache-sets = <512>;
1785			next-level-cache = <&l2_cache11>;
1786			mmu-type = "riscv,sv39";
1787			numa-node-id = <2>;
1788
1789			cpu54_intc: interrupt-controller {
1790				compatible = "riscv,cpu-intc";
1791				interrupt-controller;
1792				#interrupt-cells = <1>;
1793			};
1794		};
1795
1796		cpu55: cpu@55 {
1797			compatible = "thead,c920", "riscv";
1798			device_type = "cpu";
1799			riscv,isa = "rv64imafdc";
1800			riscv,isa-base = "rv64i";
1801			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1802					       "ziccrse", "zicntr", "zicsr",
1803					       "zifencei", "zihpm", "zfh",
1804					       "xtheadvector";
1805			thead,vlenb = <16>;
1806			reg = <55>;
1807			i-cache-block-size = <64>;
1808			i-cache-size = <65536>;
1809			i-cache-sets = <512>;
1810			d-cache-block-size = <64>;
1811			d-cache-size = <65536>;
1812			d-cache-sets = <512>;
1813			next-level-cache = <&l2_cache11>;
1814			mmu-type = "riscv,sv39";
1815			numa-node-id = <2>;
1816
1817			cpu55_intc: interrupt-controller {
1818				compatible = "riscv,cpu-intc";
1819				interrupt-controller;
1820				#interrupt-cells = <1>;
1821			};
1822		};
1823
1824		cpu56: cpu@56 {
1825			compatible = "thead,c920", "riscv";
1826			device_type = "cpu";
1827			riscv,isa = "rv64imafdc";
1828			riscv,isa-base = "rv64i";
1829			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1830					       "ziccrse", "zicntr", "zicsr",
1831					       "zifencei", "zihpm", "zfh",
1832					       "xtheadvector";
1833			thead,vlenb = <16>;
1834			reg = <56>;
1835			i-cache-block-size = <64>;
1836			i-cache-size = <65536>;
1837			i-cache-sets = <512>;
1838			d-cache-block-size = <64>;
1839			d-cache-size = <65536>;
1840			d-cache-sets = <512>;
1841			next-level-cache = <&l2_cache14>;
1842			mmu-type = "riscv,sv39";
1843			numa-node-id = <3>;
1844
1845			cpu56_intc: interrupt-controller {
1846				compatible = "riscv,cpu-intc";
1847				interrupt-controller;
1848				#interrupt-cells = <1>;
1849			};
1850		};
1851
1852		cpu57: cpu@57 {
1853			compatible = "thead,c920", "riscv";
1854			device_type = "cpu";
1855			riscv,isa = "rv64imafdc";
1856			riscv,isa-base = "rv64i";
1857			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1858					       "ziccrse", "zicntr", "zicsr",
1859					       "zifencei", "zihpm", "zfh",
1860					       "xtheadvector";
1861			thead,vlenb = <16>;
1862			reg = <57>;
1863			i-cache-block-size = <64>;
1864			i-cache-size = <65536>;
1865			i-cache-sets = <512>;
1866			d-cache-block-size = <64>;
1867			d-cache-size = <65536>;
1868			d-cache-sets = <512>;
1869			next-level-cache = <&l2_cache14>;
1870			mmu-type = "riscv,sv39";
1871			numa-node-id = <3>;
1872
1873			cpu57_intc: interrupt-controller {
1874				compatible = "riscv,cpu-intc";
1875				interrupt-controller;
1876				#interrupt-cells = <1>;
1877			};
1878		};
1879
1880		cpu58: cpu@58 {
1881			compatible = "thead,c920", "riscv";
1882			device_type = "cpu";
1883			riscv,isa = "rv64imafdc";
1884			riscv,isa-base = "rv64i";
1885			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1886					       "ziccrse", "zicntr", "zicsr",
1887					       "zifencei", "zihpm", "zfh",
1888					       "xtheadvector";
1889			thead,vlenb = <16>;
1890			reg = <58>;
1891			i-cache-block-size = <64>;
1892			i-cache-size = <65536>;
1893			i-cache-sets = <512>;
1894			d-cache-block-size = <64>;
1895			d-cache-size = <65536>;
1896			d-cache-sets = <512>;
1897			next-level-cache = <&l2_cache14>;
1898			mmu-type = "riscv,sv39";
1899			numa-node-id = <3>;
1900
1901			cpu58_intc: interrupt-controller {
1902				compatible = "riscv,cpu-intc";
1903				interrupt-controller;
1904				#interrupt-cells = <1>;
1905			};
1906		};
1907
1908		cpu59: cpu@59 {
1909			compatible = "thead,c920", "riscv";
1910			device_type = "cpu";
1911			riscv,isa = "rv64imafdc";
1912			riscv,isa-base = "rv64i";
1913			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1914					       "ziccrse", "zicntr", "zicsr",
1915					       "zifencei", "zihpm", "zfh",
1916					       "xtheadvector";
1917			thead,vlenb = <16>;
1918			reg = <59>;
1919			i-cache-block-size = <64>;
1920			i-cache-size = <65536>;
1921			i-cache-sets = <512>;
1922			d-cache-block-size = <64>;
1923			d-cache-size = <65536>;
1924			d-cache-sets = <512>;
1925			next-level-cache = <&l2_cache14>;
1926			mmu-type = "riscv,sv39";
1927			numa-node-id = <3>;
1928
1929			cpu59_intc: interrupt-controller {
1930				compatible = "riscv,cpu-intc";
1931				interrupt-controller;
1932				#interrupt-cells = <1>;
1933			};
1934		};
1935
1936		cpu60: cpu@60 {
1937			compatible = "thead,c920", "riscv";
1938			device_type = "cpu";
1939			riscv,isa = "rv64imafdc";
1940			riscv,isa-base = "rv64i";
1941			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1942					       "ziccrse", "zicntr", "zicsr",
1943					       "zifencei", "zihpm", "zfh",
1944					       "xtheadvector";
1945			thead,vlenb = <16>;
1946			reg = <60>;
1947			i-cache-block-size = <64>;
1948			i-cache-size = <65536>;
1949			i-cache-sets = <512>;
1950			d-cache-block-size = <64>;
1951			d-cache-size = <65536>;
1952			d-cache-sets = <512>;
1953			next-level-cache = <&l2_cache15>;
1954			mmu-type = "riscv,sv39";
1955			numa-node-id = <3>;
1956
1957			cpu60_intc: interrupt-controller {
1958				compatible = "riscv,cpu-intc";
1959				interrupt-controller;
1960				#interrupt-cells = <1>;
1961			};
1962		};
1963
1964		cpu61: cpu@61 {
1965			compatible = "thead,c920", "riscv";
1966			device_type = "cpu";
1967			riscv,isa = "rv64imafdc";
1968			riscv,isa-base = "rv64i";
1969			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1970					       "ziccrse", "zicntr", "zicsr",
1971					       "zifencei", "zihpm", "zfh",
1972					       "xtheadvector";
1973			thead,vlenb = <16>;
1974			reg = <61>;
1975			i-cache-block-size = <64>;
1976			i-cache-size = <65536>;
1977			i-cache-sets = <512>;
1978			d-cache-block-size = <64>;
1979			d-cache-size = <65536>;
1980			d-cache-sets = <512>;
1981			next-level-cache = <&l2_cache15>;
1982			mmu-type = "riscv,sv39";
1983			numa-node-id = <3>;
1984
1985			cpu61_intc: interrupt-controller {
1986				compatible = "riscv,cpu-intc";
1987				interrupt-controller;
1988				#interrupt-cells = <1>;
1989			};
1990		};
1991
1992		cpu62: cpu@62 {
1993			compatible = "thead,c920", "riscv";
1994			device_type = "cpu";
1995			riscv,isa = "rv64imafdc";
1996			riscv,isa-base = "rv64i";
1997			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1998					       "ziccrse", "zicntr", "zicsr",
1999					       "zifencei", "zihpm", "zfh",
2000					       "xtheadvector";
2001			thead,vlenb = <16>;
2002			reg = <62>;
2003			i-cache-block-size = <64>;
2004			i-cache-size = <65536>;
2005			i-cache-sets = <512>;
2006			d-cache-block-size = <64>;
2007			d-cache-size = <65536>;
2008			d-cache-sets = <512>;
2009			next-level-cache = <&l2_cache15>;
2010			mmu-type = "riscv,sv39";
2011			numa-node-id = <3>;
2012
2013			cpu62_intc: interrupt-controller {
2014				compatible = "riscv,cpu-intc";
2015				interrupt-controller;
2016				#interrupt-cells = <1>;
2017			};
2018		};
2019
2020		cpu63: cpu@63 {
2021			compatible = "thead,c920", "riscv";
2022			device_type = "cpu";
2023			riscv,isa = "rv64imafdc";
2024			riscv,isa-base = "rv64i";
2025			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2026					       "ziccrse", "zicntr", "zicsr",
2027					       "zifencei", "zihpm", "zfh",
2028					       "xtheadvector";
2029			thead,vlenb = <16>;
2030			reg = <63>;
2031			i-cache-block-size = <64>;
2032			i-cache-size = <65536>;
2033			i-cache-sets = <512>;
2034			d-cache-block-size = <64>;
2035			d-cache-size = <65536>;
2036			d-cache-sets = <512>;
2037			next-level-cache = <&l2_cache15>;
2038			mmu-type = "riscv,sv39";
2039			numa-node-id = <3>;
2040
2041			cpu63_intc: interrupt-controller {
2042				compatible = "riscv,cpu-intc";
2043				interrupt-controller;
2044				#interrupt-cells = <1>;
2045			};
2046		};
2047
2048		l2_cache0: cache-controller-0 {
2049			compatible = "cache";
2050			cache-block-size = <64>;
2051			cache-level = <2>;
2052			cache-size = <1048576>;
2053			cache-sets = <1024>;
2054			cache-unified;
2055		};
2056
2057		l2_cache1: cache-controller-1 {
2058			compatible = "cache";
2059			cache-block-size = <64>;
2060			cache-level = <2>;
2061			cache-size = <1048576>;
2062			cache-sets = <1024>;
2063			cache-unified;
2064		};
2065
2066		l2_cache2: cache-controller-2 {
2067			compatible = "cache";
2068			cache-block-size = <64>;
2069			cache-level = <2>;
2070			cache-size = <1048576>;
2071			cache-sets = <1024>;
2072			cache-unified;
2073		};
2074
2075		l2_cache3: cache-controller-3 {
2076			compatible = "cache";
2077			cache-block-size = <64>;
2078			cache-level = <2>;
2079			cache-size = <1048576>;
2080			cache-sets = <1024>;
2081			cache-unified;
2082		};
2083
2084		l2_cache4: cache-controller-4 {
2085			compatible = "cache";
2086			cache-block-size = <64>;
2087			cache-level = <2>;
2088			cache-size = <1048576>;
2089			cache-sets = <1024>;
2090			cache-unified;
2091		};
2092
2093		l2_cache5: cache-controller-5 {
2094			compatible = "cache";
2095			cache-block-size = <64>;
2096			cache-level = <2>;
2097			cache-size = <1048576>;
2098			cache-sets = <1024>;
2099			cache-unified;
2100		};
2101
2102		l2_cache6: cache-controller-6 {
2103			compatible = "cache";
2104			cache-block-size = <64>;
2105			cache-level = <2>;
2106			cache-size = <1048576>;
2107			cache-sets = <1024>;
2108			cache-unified;
2109		};
2110
2111		l2_cache7: cache-controller-7 {
2112			compatible = "cache";
2113			cache-block-size = <64>;
2114			cache-level = <2>;
2115			cache-size = <1048576>;
2116			cache-sets = <1024>;
2117			cache-unified;
2118		};
2119
2120		l2_cache8: cache-controller-8 {
2121			compatible = "cache";
2122			cache-block-size = <64>;
2123			cache-level = <2>;
2124			cache-size = <1048576>;
2125			cache-sets = <1024>;
2126			cache-unified;
2127		};
2128
2129		l2_cache9: cache-controller-9 {
2130			compatible = "cache";
2131			cache-block-size = <64>;
2132			cache-level = <2>;
2133			cache-size = <1048576>;
2134			cache-sets = <1024>;
2135			cache-unified;
2136		};
2137
2138		l2_cache10: cache-controller-10 {
2139			compatible = "cache";
2140			cache-block-size = <64>;
2141			cache-level = <2>;
2142			cache-size = <1048576>;
2143			cache-sets = <1024>;
2144			cache-unified;
2145		};
2146
2147		l2_cache11: cache-controller-11 {
2148			compatible = "cache";
2149			cache-block-size = <64>;
2150			cache-level = <2>;
2151			cache-size = <1048576>;
2152			cache-sets = <1024>;
2153			cache-unified;
2154		};
2155
2156		l2_cache12: cache-controller-12 {
2157			compatible = "cache";
2158			cache-block-size = <64>;
2159			cache-level = <2>;
2160			cache-size = <1048576>;
2161			cache-sets = <1024>;
2162			cache-unified;
2163		};
2164
2165		l2_cache13: cache-controller-13 {
2166			compatible = "cache";
2167			cache-block-size = <64>;
2168			cache-level = <2>;
2169			cache-size = <1048576>;
2170			cache-sets = <1024>;
2171			cache-unified;
2172		};
2173
2174		l2_cache14: cache-controller-14 {
2175			compatible = "cache";
2176			cache-block-size = <64>;
2177			cache-level = <2>;
2178			cache-size = <1048576>;
2179			cache-sets = <1024>;
2180			cache-unified;
2181		};
2182
2183		l2_cache15: cache-controller-15 {
2184			compatible = "cache";
2185			cache-block-size = <64>;
2186			cache-level = <2>;
2187			cache-size = <1048576>;
2188			cache-sets = <1024>;
2189			cache-unified;
2190		};
2191	};
2192};