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cv180x.dtsi
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linux-6.19.14/arch/riscv/boot/dts/sophgo/cv180x.dtsi
1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 4 * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> 5 */ 6 7#include <dt-bindings/clock/sophgo,cv1800.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include "cv18xx-reset.h" 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 osc: oscillator { 17 compatible = "fixed-clock"; 18 clock-output-names = "osc_25m"; 19 #clock-cells = <0>; 20 }; 21 22 soc { 23 compatible = "simple-bus"; 24 #address-cells = <1>; 25 #size-cells = <1>; 26 ranges; 27 28 syscon: syscon@3000000 { 29 compatible = "sophgo,cv1800b-top-syscon", 30 "syscon", "simple-mfd"; 31 reg = <0x03000000 0x1000>; 32 #address-cells = <1>; 33 #size-cells = <1>; 34 35 usbphy: phy@48 { 36 compatible = "sophgo,cv1800b-usb2-phy"; 37 reg = <0x48 0x4>; 38 #phy-cells = <0>; 39 clocks = <&clk CLK_USB_125M>, 40 <&clk CLK_USB_33K>, 41 <&clk CLK_USB_12M>; 42 clock-names = "app", "stb", "lpm"; 43 resets = <&rst RST_COMBO_PHY0>; 44 }; 45 46 dmamux: dma-router@154 { 47 compatible = "sophgo,cv1800b-dmamux"; 48 reg = <0x154 0x8>, <0x298 0x4>; 49 #dma-cells = <2>; 50 dma-masters = <&dmac>; 51 }; 52 }; 53 54 rst: reset-controller@3003000 { 55 compatible = "sophgo,cv1800b-reset"; 56 reg = <0x3003000 0x1000>; 57 #reset-cells = <1>; 58 }; 59 60 mdio: mdio-mux@3009800 { 61 compatible = "mdio-mux-mmioreg", "mdio-mux"; 62 reg = <0x3009800 0x4>; 63 #address-cells = <1>; 64 #size-cells = <0>; 65 mdio-parent-bus = <&gmac0_mdio>; 66 mux-mask = <0x80>; 67 status = "disabled"; 68 69 internal_mdio: mdio@0 { 70 #address-cells = <1>; 71 #size-cells = <0>; 72 reg = <0>; 73 74 internal_ephy: phy@0 { 75 compatible = "ethernet-phy-ieee802.3-c22"; 76 reg = <1>; 77 }; 78 }; 79 80 external_mdio: mdio@80 { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 reg = <0x80>; 84 }; 85 }; 86 87 gpio0: gpio@3020000 { 88 compatible = "snps,dw-apb-gpio"; 89 reg = <0x3020000 0x1000>; 90 #address-cells = <1>; 91 #size-cells = <0>; 92 resets = <&rst RST_GPIO0>; 93 94 porta: gpio-controller@0 { 95 compatible = "snps,dw-apb-gpio-port"; 96 gpio-controller; 97 #gpio-cells = <2>; 98 ngpios = <32>; 99 reg = <0>; 100 interrupt-controller; 101 #interrupt-cells = <2>; 102 interrupts = <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>; 103 }; 104 }; 105 106 gpio1: gpio@3021000 { 107 compatible = "snps,dw-apb-gpio"; 108 reg = <0x3021000 0x1000>; 109 #address-cells = <1>; 110 #size-cells = <0>; 111 resets = <&rst RST_GPIO1>; 112 113 portb: gpio-controller@0 { 114 compatible = "snps,dw-apb-gpio-port"; 115 gpio-controller; 116 #gpio-cells = <2>; 117 ngpios = <32>; 118 reg = <0>; 119 interrupt-controller; 120 #interrupt-cells = <2>; 121 interrupts = <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>; 122 }; 123 }; 124 125 gpio2: gpio@3022000 { 126 compatible = "snps,dw-apb-gpio"; 127 reg = <0x3022000 0x1000>; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 resets = <&rst RST_GPIO2>; 131 132 portc: gpio-controller@0 { 133 compatible = "snps,dw-apb-gpio-port"; 134 gpio-controller; 135 #gpio-cells = <2>; 136 ngpios = <32>; 137 reg = <0>; 138 interrupt-controller; 139 #interrupt-cells = <2>; 140 interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>; 141 }; 142 }; 143 144 gpio3: gpio@3023000 { 145 compatible = "snps,dw-apb-gpio"; 146 reg = <0x3023000 0x1000>; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 resets = <&rst RST_GPIO3>; 150 151 portd: gpio-controller@0 { 152 compatible = "snps,dw-apb-gpio-port"; 153 gpio-controller; 154 #gpio-cells = <2>; 155 ngpios = <32>; 156 reg = <0>; 157 interrupt-controller; 158 #interrupt-cells = <2>; 159 interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_LEVEL_HIGH>; 160 }; 161 }; 162 163 saradc: adc@30f0000 { 164 compatible = "sophgo,cv1800b-saradc"; 165 reg = <0x030f0000 0x1000>; 166 clocks = <&clk CLK_SARADC>; 167 interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 status = "disabled"; 171 172 channel@0 { 173 reg = <0>; 174 }; 175 176 channel@1 { 177 reg = <1>; 178 }; 179 180 channel@2 { 181 reg = <2>; 182 }; 183 }; 184 185 i2c0: i2c@4000000 { 186 compatible = "snps,designware-i2c"; 187 reg = <0x04000000 0x10000>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; 191 clock-names = "ref", "pclk"; 192 interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>; 193 resets = <&rst RST_I2C0>; 194 status = "disabled"; 195 }; 196 197 i2c1: i2c@4010000 { 198 compatible = "snps,designware-i2c"; 199 reg = <0x04010000 0x10000>; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; 203 clock-names = "ref", "pclk"; 204 interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>; 205 resets = <&rst RST_I2C1>; 206 status = "disabled"; 207 }; 208 209 i2c2: i2c@4020000 { 210 compatible = "snps,designware-i2c"; 211 reg = <0x04020000 0x10000>; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; 215 clock-names = "ref", "pclk"; 216 interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>; 217 resets = <&rst RST_I2C2>; 218 status = "disabled"; 219 }; 220 221 i2c3: i2c@4030000 { 222 compatible = "snps,designware-i2c"; 223 reg = <0x04030000 0x10000>; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; 227 clock-names = "ref", "pclk"; 228 interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>; 229 resets = <&rst RST_I2C3>; 230 status = "disabled"; 231 }; 232 233 i2c4: i2c@4040000 { 234 compatible = "snps,designware-i2c"; 235 reg = <0x04040000 0x10000>; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; 239 clock-names = "ref", "pclk"; 240 interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>; 241 resets = <&rst RST_I2C4>; 242 status = "disabled"; 243 }; 244 245 gmac0: ethernet@4070000 { 246 compatible = "sophgo,cv1800b-dwmac", "snps,dwmac-3.70a"; 247 reg = <0x04070000 0x10000>; 248 clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>; 249 clock-names = "stmmaceth", "ptp_ref"; 250 interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>; 251 interrupt-names = "macirq"; 252 phy-handle = <&internal_ephy>; 253 phy-mode = "internal"; 254 resets = <&rst RST_ETH0>; 255 reset-names = "stmmaceth"; 256 rx-fifo-depth = <8192>; 257 tx-fifo-depth = <8192>; 258 snps,multicast-filter-bins = <0>; 259 snps,perfect-filter-entries = <1>; 260 snps,aal; 261 snps,txpbl = <8>; 262 snps,rxpbl = <8>; 263 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 264 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 265 snps,axi-config = <&gmac0_stmmac_axi_setup>; 266 status = "disabled"; 267 268 gmac0_mdio: mdio { 269 compatible = "snps,dwmac-mdio"; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 }; 273 274 gmac0_mtl_rx_setup: rx-queues-config { 275 snps,rx-queues-to-use = <1>; 276 queue0 {}; 277 }; 278 279 gmac0_mtl_tx_setup: tx-queues-config { 280 snps,tx-queues-to-use = <1>; 281 queue0 {}; 282 }; 283 284 gmac0_stmmac_axi_setup: stmmac-axi-config { 285 snps,blen = <16 8 4 0 0 0 0>; 286 snps,rd_osr_lmt = <2>; 287 snps,wr_osr_lmt = <1>; 288 }; 289 }; 290 291 uart0: serial@4140000 { 292 compatible = "snps,dw-apb-uart"; 293 reg = <0x04140000 0x100>; 294 interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; 296 clock-names = "baudclk", "apb_pclk"; 297 reg-shift = <2>; 298 reg-io-width = <4>; 299 resets = <&rst RST_UART0>; 300 status = "disabled"; 301 }; 302 303 uart1: serial@4150000 { 304 compatible = "snps,dw-apb-uart"; 305 reg = <0x04150000 0x100>; 306 interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>; 308 clock-names = "baudclk", "apb_pclk"; 309 reg-shift = <2>; 310 reg-io-width = <4>; 311 resets = <&rst RST_UART1>; 312 status = "disabled"; 313 }; 314 315 uart2: serial@4160000 { 316 compatible = "snps,dw-apb-uart"; 317 reg = <0x04160000 0x100>; 318 interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>; 320 clock-names = "baudclk", "apb_pclk"; 321 reg-shift = <2>; 322 reg-io-width = <4>; 323 resets = <&rst RST_UART2>; 324 status = "disabled"; 325 }; 326 327 uart3: serial@4170000 { 328 compatible = "snps,dw-apb-uart"; 329 reg = <0x04170000 0x100>; 330 interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>; 332 clock-names = "baudclk", "apb_pclk"; 333 reg-shift = <2>; 334 reg-io-width = <4>; 335 resets = <&rst RST_UART3>; 336 status = "disabled"; 337 }; 338 339 spi0: spi@4180000 { 340 compatible = "snps,dw-apb-ssi"; 341 reg = <0x04180000 0x10000>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; 345 clock-names = "ssi_clk", "pclk"; 346 interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>; 347 resets = <&rst RST_SPI0>; 348 status = "disabled"; 349 }; 350 351 spi1: spi@4190000 { 352 compatible = "snps,dw-apb-ssi"; 353 reg = <0x04190000 0x10000>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; 357 clock-names = "ssi_clk", "pclk"; 358 interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>; 359 resets = <&rst RST_SPI1>; 360 status = "disabled"; 361 }; 362 363 spi2: spi@41a0000 { 364 compatible = "snps,dw-apb-ssi"; 365 reg = <0x041a0000 0x10000>; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; 369 clock-names = "ssi_clk", "pclk"; 370 interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>; 371 resets = <&rst RST_SPI2>; 372 status = "disabled"; 373 }; 374 375 spi3: spi@41b0000 { 376 compatible = "snps,dw-apb-ssi"; 377 reg = <0x041b0000 0x10000>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; 381 clock-names = "ssi_clk", "pclk"; 382 interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>; 383 resets = <&rst RST_SPI3>; 384 status = "disabled"; 385 }; 386 387 uart4: serial@41c0000 { 388 compatible = "snps,dw-apb-uart"; 389 reg = <0x041c0000 0x100>; 390 interrupts = <SOC_PERIPHERAL_IRQ(32) IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; 392 clock-names = "baudclk", "apb_pclk"; 393 reg-shift = <2>; 394 reg-io-width = <4>; 395 resets = <&rst RST_UART4>; 396 status = "disabled"; 397 }; 398 399 sdhci0: mmc@4310000 { 400 compatible = "sophgo,cv1800b-dwcmshc"; 401 reg = <0x4310000 0x1000>; 402 interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&clk CLK_AXI4_SD0>, 404 <&clk CLK_SD0>; 405 clock-names = "core", "bus"; 406 status = "disabled"; 407 }; 408 409 sdhci1: mmc@4320000 { 410 compatible = "sophgo,cv1800b-dwcmshc"; 411 reg = <0x4320000 0x1000>; 412 interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&clk CLK_AXI4_SD1>, 414 <&clk CLK_SD1>; 415 clock-names = "core", "bus"; 416 status = "disabled"; 417 }; 418 419 dmac: dma-controller@4330000 { 420 compatible = "snps,axi-dma-1.01a"; 421 reg = <0x04330000 0x1000>; 422 interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>; 424 clock-names = "core-clk", "cfgr-clk"; 425 #dma-cells = <1>; 426 dma-channels = <8>; 427 snps,block-size = <1024 1024 1024 1024 428 1024 1024 1024 1024>; 429 snps,priority = <0 1 2 3 4 5 6 7>; 430 snps,dma-masters = <2>; 431 snps,data-width = <2>; 432 status = "disabled"; 433 }; 434 435 usb: usb@4340000 { 436 compatible = "sophgo,cv1800b-usb"; 437 reg = <0x04340000 0x10000>; 438 clocks = <&clk CLK_AXI4_USB>, <&clk CLK_APB_USB>; 439 clock-names = "otg", "utmi"; 440 g-np-tx-fifo-size = <32>; 441 g-rx-fifo-size = <1536>; 442 g-tx-fifo-size = <128 128 64 64 64 64 32 32>; 443 interrupts = <SOC_PERIPHERAL_IRQ(14) IRQ_TYPE_LEVEL_HIGH>; 444 phys = <&usbphy>; 445 phy-names = "usb2-phy"; 446 resets = <&rst RST_USB>; 447 reset-names = "dwc2"; 448 status = "disabled"; 449 }; 450 451 rtc@5025000 { 452 compatible = "sophgo,cv1800b-rtc", "syscon"; 453 reg = <0x5025000 0x2000>; 454 interrupts = <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>, 455 <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>, 456 <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>; 457 interrupt-names = "alarm", "longpress", "vbat"; 458 clocks = <&clk CLK_RTC_25M>, 459 <&clk CLK_SRC_RTC_SYS_0>; 460 clock-names = "rtc", "mcu"; 461 }; 462 }; 463};
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