cv180x-cpus.dtsi

 1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
 2/*
 3 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
 4 * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
 5 */
 6
 7/ {
 8	cpus: cpus {
 9		#address-cells = <1>;
10		#size-cells = <0>;
11		timebase-frequency = <25000000>;
12
13		cpu0: cpu@0 {
14			compatible = "thead,c906", "riscv";
15			device_type = "cpu";
16			reg = <0>;
17			d-cache-block-size = <64>;
18			d-cache-sets = <512>;
19			d-cache-size = <65536>;
20			i-cache-block-size = <64>;
21			i-cache-sets = <128>;
22			i-cache-size = <32768>;
23			mmu-type = "riscv,sv39";
24			riscv,isa = "rv64imafdc";
25			riscv,isa-base = "rv64i";
26			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
27					       "zifencei", "zihpm";
28
29			cpu0_intc: interrupt-controller {
30				compatible = "riscv,cpu-intc";
31				interrupt-controller;
32				#interrupt-cells = <1>;
33			};
34		};
35	};
36};