dr1v90.dtsi

  1// SPDX-License-Identifier: GPL-2.0 OR MIT
  2/*
  3 * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
  4 */
  5
  6/dts-v1/;
  7/ {
  8	#address-cells = <2>;
  9	#size-cells = <2>;
 10	model = "Anlogic DR1V90";
 11	compatible = "anlogic,dr1v90";
 12
 13	cpus {
 14		#address-cells = <1>;
 15		#size-cells = <0>;
 16		timebase-frequency = <800000000>;
 17
 18		cpu@0 {
 19			compatible = "nuclei,ux900", "riscv";
 20			d-cache-block-size = <64>;
 21			d-cache-sets = <256>;
 22			d-cache-size = <32768>;
 23			device_type = "cpu";
 24			i-cache-block-size = <64>;
 25			i-cache-sets = <256>;
 26			i-cache-size = <32768>;
 27			mmu-type = "riscv,sv39";
 28			reg = <0>;
 29			riscv,isa-base = "rv64i";
 30			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc",
 31					       "zbkc", "zbs", "zicntr", "zicsr", "zifencei",
 32					       "zihintpause", "zihpm";
 33
 34			cpu0_intc: interrupt-controller {
 35				compatible = "riscv,cpu-intc";
 36				#interrupt-cells = <1>;
 37				interrupt-controller;
 38			};
 39		};
 40	};
 41
 42	soc {
 43		compatible = "simple-bus";
 44		interrupt-parent = <&plic>;
 45		#address-cells = <2>;
 46		#size-cells = <2>;
 47		ranges;
 48
 49		aclint_mswi: interrupt-controller@68031000 {
 50			compatible = "anlogic,dr1v90-aclint-mswi", "nuclei,ux900-aclint-mswi";
 51			reg = <0x0 0x68031000 0x0 0x4000>;
 52			interrupts-extended = <&cpu0_intc 3>;
 53		};
 54
 55		aclint_mtimer: timer@68035000 {
 56			compatible = "anlogic,dr1v90-aclint-mtimer", "nuclei,ux900-aclint-mtimer";
 57			reg = <0x0 0x68035000 0x0 0x8000>;
 58			reg-names = "mtimecmp";
 59			interrupts-extended = <&cpu0_intc 7>;
 60		};
 61
 62		aclint_sswi: interrupt-controller@6803d000 {
 63			compatible = "anlogic,dr1v90-aclint-sswi", "nuclei,ux900-aclint-sswi";
 64			reg = <0x0 0x6803d000 0x0 0x3000>;
 65			#interrupt-cells = <0>;
 66			interrupt-controller;
 67			interrupts-extended = <&cpu0_intc 1>;
 68		};
 69
 70		plic: interrupt-controller@6c000000 {
 71			compatible = "anlogic,dr1v90-plic", "sifive,plic-1.0.0";
 72			reg = <0x0 0x6c000000 0x0 0x4000000>;
 73			#address-cells = <0>;
 74			#interrupt-cells = <1>;
 75			interrupt-controller;
 76			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
 77			riscv,ndev = <150>;
 78		};
 79
 80		uart0: serial@f8400000 {
 81			compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
 82			reg = <0x0 0xf8400000 0x0 0x1000>;
 83			clock-frequency = <50000000>;
 84			interrupts = <71>;
 85			reg-io-width = <4>;
 86			reg-shift = <2>;
 87			status = "disabled";
 88		};
 89
 90		uart1: serial@f8401000 {
 91			compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
 92			reg = <0x0 0xf8401000 0x0 0x1000>;
 93			clock-frequency = <50000000>;
 94			interrupts = <72>;
 95			reg-io-width = <4>;
 96			reg-shift = <2>;
 97			status = "disabled";
 98		};
 99	};
100};