sun20i-d1s.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
  3
  4#define SOC_PERIPHERAL_IRQ(nr)	(nr + 16)
  5
  6#include "sunxi-d1s-t113.dtsi"
  7
  8/ {
  9	cpus {
 10		timebase-frequency = <24000000>;
 11		#address-cells = <1>;
 12		#size-cells = <0>;
 13
 14		cpu0: cpu@0 {
 15			compatible = "thead,c906", "riscv";
 16			device_type = "cpu";
 17			reg = <0>;
 18			clocks = <&ccu CLK_RISCV>;
 19			d-cache-block-size = <64>;
 20			d-cache-sets = <256>;
 21			d-cache-size = <32768>;
 22			i-cache-block-size = <64>;
 23			i-cache-sets = <128>;
 24			i-cache-size = <32768>;
 25			mmu-type = "riscv,sv39";
 26			operating-points-v2 = <&opp_table_cpu>;
 27			riscv,isa = "rv64imafdc";
 28			riscv,isa-base = "rv64i";
 29			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
 30					       "zifencei", "zihpm", "xtheadvector";
 31			thead,vlenb = <16>;
 32			#cooling-cells = <2>;
 33
 34			cpu0_intc: interrupt-controller {
 35				compatible = "riscv,cpu-intc";
 36				interrupt-controller;
 37				#interrupt-cells = <1>;
 38			};
 39		};
 40	};
 41
 42	opp_table_cpu: opp-table-cpu {
 43		compatible = "operating-points-v2";
 44
 45		opp-408000000 {
 46			opp-hz = /bits/ 64 <408000000>;
 47			opp-microvolt = <900000 900000 1100000>;
 48		};
 49
 50		opp-1080000000 {
 51			opp-hz = /bits/ 64 <1008000000>;
 52			opp-microvolt = <900000 900000 1100000>;
 53		};
 54	};
 55
 56	soc {
 57		interrupt-parent = <&plic>;
 58
 59		riscv_wdt: watchdog@6011000 {
 60			compatible = "allwinner,sun20i-d1-wdt";
 61			reg = <0x6011000 0x20>;
 62			interrupts = <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
 63			clocks = <&dcxo>, <&rtc CLK_OSC32K>;
 64			clock-names = "hosc", "losc";
 65		};
 66
 67		plic: interrupt-controller@10000000 {
 68			compatible = "allwinner,sun20i-d1-plic",
 69				     "thead,c900-plic";
 70			reg = <0x10000000 0x4000000>;
 71			interrupts-extended = <&cpu0_intc 11>,
 72					      <&cpu0_intc 9>;
 73			interrupt-controller;
 74			riscv,ndev = <175>;
 75			#address-cells = <0>;
 76			#interrupt-cells = <2>;
 77		};
 78	};
 79
 80	pmu {
 81		compatible = "riscv,pmu";
 82		riscv,event-to-mhpmcounters =
 83			<0x00003 0x00003 0x00000008>,
 84			<0x00004 0x00004 0x00000010>,
 85			<0x00005 0x00005 0x00000200>,
 86			<0x00006 0x00006 0x00000100>,
 87			<0x10000 0x10000 0x00004000>,
 88			<0x10001 0x10001 0x00008000>,
 89			<0x10002 0x10002 0x00010000>,
 90			<0x10003 0x10003 0x00020000>,
 91			<0x10019 0x10019 0x00000040>,
 92			<0x10021 0x10021 0x00000020>;
 93		riscv,event-to-mhpmevent =
 94			<0x00003 0x00000000 0x00000001>,
 95			<0x00004 0x00000000 0x00000002>,
 96			<0x00005 0x00000000 0x00000007>,
 97			<0x00006 0x00000000 0x00000006>,
 98			<0x10000 0x00000000 0x0000000c>,
 99			<0x10001 0x00000000 0x0000000d>,
100			<0x10002 0x00000000 0x0000000e>,
101			<0x10003 0x00000000 0x0000000f>,
102			<0x10019 0x00000000 0x00000004>,
103			<0x10021 0x00000000 0x00000003>;
104		riscv,raw-event-to-mhpmcounters =
105			<0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
106			<0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
107			<0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
108			<0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
109			<0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
110			<0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
111			<0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
112			<0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
113			<0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
114			<0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
115			<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
116			<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
117	};
118};